Timing Issues in Digital Logic Circuits

Timing Hazards in Combinational Logic Circuits

• Hazards are undesirable changes in the output of a

combinational logic circuit caused by unequal gate
propagation delays.
• Static hazard (glitch) -- the output momentarily changes
from the correct or static state
• Static 1 hazard -- the output changes from 1 to 0 and back to 1
• Static 0 hazard -- the output changes from 0 to 1 and back to 0
• Dynamic hazard (bounce) -- the output changes multiple
times during a change of state
• Dynamic 0 to 1 hazard -- the output changes from 0 to 1 to 0 to 1
• Dynamic 1 to 0 hazard -- the output changes from 1 to 0 to 1 to 0
Figure (a)--(b) Illustration of a static hazard.

x1 y1 x1 y1
G1 G1
x2 x2
z(x1, x2, x3) z(x1, x2, x3)
G3 I1 G3
x1
x1
G2 G2
x3 y2 x3 y2

(a) (b)
Figure (c) Illustration of a static hazard (con’t)

x1

x2

x3

y1

y2

Dt Dt Dt
Time
t1 t2 t3 t4 t5 t6
(c)
Figure (d) Illustration of a static hazard (con’t).

x1

x2

x3

y1

y2

Dt2 Dt3 Dt2 Dt3

Time
Dt1 Dt3
t1 t2 t3 t4 t5 t6 t7 t8 t9
(d)
 Figure : Identifying hazards on a K-map.

x1 x1
z z

1 1

x3 1 1 1 x3 1 1 1

x2 x2
(a) (b)
Figure : Hazard-free network.

x1
G1
x2

x1 z(x1, x2, x3)

G2 G3
x3

x2
G4
x3
Figure (a)--(b) Example of a static-0 hazard.

A 0 0
G1
C
0 0 0 0
A z(A, B, C, D)
G2 G4 D
D
0 0
A C
B G3
C 0
(a)
B
(b)
Figure (c)--(d) Example of a static-0 hazard (con’t).

A
A
G1
C 0 0
A
G2 0 0 0 0
D z(A, B, C, D)
G4 D
A
B G3 0 0
C C
B 0
C G5
D
(c) B
(d)
Figure Dynamic hazards.

(a) (b)
◼ Timing in combinational circuits
❑ Propagation delay and contamination delay
❑ Glitches

◼ Timing in sequential circuits

❑ Setup time and hold time
❑ Determining how fast a circuit can operate

◼ Circuit Verification
❑ How to make sure a circuit works correctly
❑ Functional verification
❑ Timing verification

11
Tradeoffs in Circuit Design

12
Circuit Design is a Tradeoff Between:
◼ Area
❑ Circuit area is proportional to the cost of the device

◼ Speed / Throughput
❑ We want faster, more capable circuits

◼ Power / Energy
❑ Mobile devices need to work with a limited power supply
❑ High performance devices dissipate more than 100W/cm2

◼ Design Time
❑ Designers are expensive in time and money
❑ The competition will not wait for you
13
Requirements and Goals Depend On Application

14
Circuit Timing
◼ Until now, we investigated logical functionality

◼ What about timing?

❑ How fast is a circuit?
❑ How can we make a circuit faster?
❑ What happens if we run a circuit too fast?

◼ A design that is logically correct can still fail because of

real-world implementation issues!

15
 Part 1:
Combinational Circuit Timing

16
Digital Logic Abstraction
◼ “Digital logic” is a convenient abstraction
❑ Output changes immediately with the input

A 1 0

Y 0 1

17
Combinational Circuit Delay
◼ In reality, outputs are delayed from inputs
❑ Transistors take a finite amount of time to switch

A Y

delay

time
Time

18
Real Inverter Delay Example

Image source: Sandoval-Ibarra, F., and E. S. Hernández-Bernal. "Ring CMOS NOT-based oscillators:
Analysis and design." Journal of applied research and technology, 2008.
19
Circuit Delay and Its Variation
◼ Delay is fundamentally caused by
❑ Capacitance and resistance in a circuit
❑ Finite speed of light (not so fast on a nanosecond scale!)

◼ Anything affecting these quantities can change delay:

❑ Rising (i.e., 0 -> 1) vs. falling (i.e., 1 -> 0) inputs
❑ Different inputs have different delays
❑ Changes in environment (e.g., temperature)
❑ Aging of the circuit

◼ We have a range of possible delays from input to output

20
 Delays from Input to Output Y
◼ Contamination delay (tcd): delay until Y starts changing
◼ Propagation delay (tpd): delay until Y finishes changing

Example Circuit Effect of Changing Input ‘A’

Cross-hatching
means value is changing 21
Calculating Longest & Shortest Delay Paths
◼ We care about both the longest and shortest delay
paths in a circuit
Critical Path

A n1
B
n2
C
D Y

Short Path
◼ Critical (Longest) Path: tpd = 2 tpd_AND + tpd_OR
◼ Shortest Path: tcd = tcd_AND
22
Calculating Longest Delay Path (Critical Path)

◼ Critical (Longest) Path: tpd = 2 tpd_AND + tpd_OR

◼ Shortest Path: tcd = tcd_AND
23
Calculating Shortest Delay Path

◼ Critical (Longest) Path: tpd = 2 tpd_AND + tpd_OR

◼ Shortest Path: tcd = tcd_AND
24
Example tpd for a Real NAND-2 Gate

◼ Heavy dependence on voltage and temperature!

Source: Nexperia 2-input NAND (74HC00) Datasheet, Section 10 25
Example Worst-Case tpd
◼ Two different implementations of a 4:1 multiplexer
Gate Delays Implementation 1 Implementation 2

◼ Different designs lead to very different delays

26
Aside: A Third 4:1 MUX Implementation

27
Disclaimer: Calculating Long/Short Paths
◼ It’s not always this easy to determine the long/short paths!
❑ Not all input transitions affect the output
❑ Can have multiple different paths from an input to output

◼ In reality, circuits are not all built equally

❑ Different instances of the same gate have different delays
❑ Wires have nonzero delay (increasing with length)
❑ Temperature/voltage affect circuit speeds
◼ Not all circuit elements are affected the same way
◼ Can even change the critical path!

◼ Designers assume “worst-case” conditions and run many

statistical simulations to balance yield/performance

28
Combinational Timing Summary
◼ Circuit outputs change some time after the inputs change
❑ Caused by finite speed of light (not so fast on a ns scale!)
❑ Delay is dependent on inputs, environmental state, etc.

◼ The range of possible delays is characterized by:

❑ Contamination delay (tcd): minimum possible delay

❑ Propagation delay (tpd): maximum possible delay

◼ Delays change with:

❑ Circuit design (e.g., topology, materials)
❑ Operating conditions

29
Output Glitches

30
Glitches
◼ Glitch: one input transition causes multiple output transitions

Circuit initial state

0
0
1

31
Glitches
◼ Glitch: one input transition causes multiple output transitions

0
1 -> 0
1 -> ?

32
Glitches
◼ Glitch: one input transition causes multiple output transitions

Slow path (3 gates)

0
1 -> 0
1 -> ?

1
Fast path (2 gates)

33
Glitches
◼ Glitch: one input transition causes multiple output transitions

Slow path (3 gates)

0
1 -> 0
1 -> 0 -> 1

1
Fast path (2 gates)

34
Glitches
◼ Glitch: one input transition causes multiple output transitions
Slow path (3 gates)
0
(B) 1 -> 0 n1
(Y) 1 -> 0 -> 1
n2
1
Fast path (2 gates)

35
Optional: Avoiding Glitches Using K-Maps
◼ Glitches are visible in K-maps
❑ Recall: K-maps show the results of a change in a single input
❑ A glitch occurs when moving between prime implicants

(A) 0 AB
(B) 1 -> 0
(Y) 1 -> 0 -> 1

(C) 1
BC

36
Optional: Avoiding Glitches Using K-Maps
◼ We can fix the issue by adding in the consensus term
❑ Ensures no transition between different prime implicants

(A) 0 AB
(B) 1 -> 0
BC (Y) 1 -> 1

(C) 1 AB + A'C + BC = AB
consensus or reso
terms AB and A'C
conjunction of all th
AC of the terms, exclud
that appears unneg
and negated in the

No dependence on B
=> No glitch!

37
Avoiding Glitches
◼ Q: Do we always care about glitches?
❑ Fixing glitches is undesirable
◼ More chip area
◼ More power consumption
◼ More design effort
❑ The circuit is eventually guaranteed to converge to the right
value regardless of glitchiness

◼ A: No, not always!

❑ If we only care about the long-term steady state output,
we can safely ignore glitches
❑ Up to the designer to decide if glitches matter in their
application
◼ When examining simulation output, important to recognize glitches
38
 Part 2:
Sequential Circuit Timing

39
Recall: D Flip-Flop
◼ Flip-flop samples D at the active clock edge
❑ It outputs the sampled value to Q
❑ It “stores” the sampled value until the next active clock edge

CLK

D Q

◼ The D flip-flop is made from combinational elements

◼ D, Q, CLK all have timing requirements!
40
D Flip-Flop Input Timing Constraints
◼ D must be stable when sampled (i.e., at active clock edge)
CLK CLK

D
D Q
tsetup thold

ta

◼ Setup time (tsetup): time before the clock edge that data
must be stable (i.e. not changing)
◼ Hold time (thold): time after the clock edge that data must
be stable
◼ Aperture time (ta): time around clock edge that data
must be stable (ta = tsetup + thold)
41
Violating Input Timing: Metastability
◼ If D is changing when sampled, metastability can occur
❑ Flip-flop output is stuck somewhere between ‘1’ and ‘0’
❑ Output eventually settles non-deterministically
Example Timing Violations (NAND RS Latch)

CLK

Q Non-deterministic
Convergence
Metastability

Source: W. J. Dally, Lecture notes for EE108A, Lecture 13: Metastability and
Synchronization Failure (When Good Flip-Flops go Bad) 11/9/2005. 42
Flip-Flop Output Timing
CLK CLK

D Q
tccq
tpcq

◼ Contamination delay clock-to-q (tccq): earliest time after

the clock edge that Q starts to change (i.e., is unstable)

◼ Propagation delay clock-to-q (tpcq): latest time after the

clock edge that Q stops changing (i.e., is stable)

43
Recall: Sequential System Design

◼ Multiple flip-flops are connected with combinational logic

◼ Clock runs with period Tc (cycle time)

◼ Must meet timing requirements for both R1 and R2!

44
Ensuring Correct Sequential Operation
◼ Need to ensure correct input timing on R2

◼ Specifically, D2 must be stable:

❑ at least tsetup before the clock edge
❑ at least until thold after the clock edge

CLK

tsetup thold

ta

45
Ensuring Correct Sequential Operation
◼ This means there is both a minimum and maximum
delay between two flip-flops
Potential
CL too fast -> R2 thold violation
R2 tHOLD
❑

❑ CL too slow -> R2 tsetup violation

VIOLATION!
CLK CLK
Q1 CL D2 Potential
R1 R2
R2 tSETUP
VIOLATION!
(a)
Tc
CLK

Q1

D2
(b) tHOLD tSETUP
46
Setup Time Constraint
◼ Safe timing depends on the maximum delay from R1 to R2
◼ The input to R2 must be stable at least tsetup before the clock edge.

CLK CLK
Q1 CL D2 Tc
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup

47
Setup Time Constraint
◼ Safe timing depends on the maximum delay from R1 to R2
◼ The input to R2 must be stable at least tsetup before the clock edge.

CLK CLK
Q1 CL D2 Tc > tpcq
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup

48
Setup Time Constraint
◼ Safe timing depends on the maximum delay from R1 to R2
◼ The input to R2 must be stable at least tsetup before the clock edge.

CLK CLK
Q1 CL D2 Tc > tpcq + tpd
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup

49
Setup Time Constraint
◼ Safe timing depends on the maximum delay from R1 to R2
◼ The input to R2 must be stable at least tsetup before the clock edge.

CLK CLK
Q1 CL D2 Tc > tpcq + tpd + tsetup
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup

50
Setup Time Constraint
◼ Safe timing depends on the maximum delay from R1 to R2
◼ The input to R2 must be stable at least tsetup before the clock edge.

Wasted work
CLK CLK
Q1 CL D2 Tc > tpcq + tpd + tsetup
R1 R2 Useful work
Tc
CLK

Q1 Sequencing overhead:
D2
amount of time wasted
tpcq tpd tsetup
each cycle due to sequencing
element timing requirements

51
tsetup Constraint and Design Performance

◼ Critical path: path with the longest tpd

Tc > tpcq + tpd + tsetup
◼ Overall design performance is determined by the critical path tpd
❑ Determines the minimum clock period (i.e., max operating frequency)
❑ If the critical path is too long, the design will run slowly
❑ If critical path is too short, each cycle will do very little useful work
◼ i.e., most of the cycle will be wasted in sequencing overhead

52
Hold Time Constraint
◼ Safe timing depends on the minimum delay from R1 to R2
◼ D2 (i.e., R2 input) must be stable for at least thold after the clock edge
Must not change until
thold after the clock
CLK CLK
Q1 CL D2 tccq
R1 R2

CLK

Q1

D2
tccq tcd
thold

53
Hold Time Constraint
◼ Safe timing depends on the minimum delay from R1 to R2
◼ D2 (i.e., R2 input) must be stable for at least thold after the clock edge

CLK CLK
Q1 CL D2 tccq + tcd
R1 R2

CLK

Q1

D2
tccq tcd
thold

54
Hold Time Constraint
◼ Safe timing depends on the minimum delay from R1 to R2
◼ D2 (i.e., R2 input) must be stable for at least thold after the clock edge

CLK CLK
Q1 CL D2 tccq + tcd > thold
R1 R2

CLK

Q1

D2
tccq tcd
thold

55
Hold Time Constraint
◼ Safe timing depends on the minimum delay from R1 to R2
◼ D2 (i.e., R2 input) must be stable for at least thold after the clock edge

CLK CLK
Q1 CL D2 tccq + tcd > thold
R1 R2
tcd > thold - tccq
CLK

Q1
We need to have a minimum
D2
combinational delay!
tccq tcd
thold

56
Hold Time Constraint
◼ Safe timing depends on the minimum delay from R1 to R2
◼ D2 (i.e., R2 input) must be stable for at least thold after the clock edge

CLK CLK
Q1 CL D2 tccq + tcd > thold
R1 R2
tcd > thold - tccq
CLK

Q1
Does NOT depend on Tc!
D2
tccq tcd
Very hard to fix thold violations after
thold
manufacturing- must modify circuits!
57
Sequential Timing Summary
tccq / tpcq clock-to-q delay (contamination/propagation)
tcd / tpd combinational logic delay (contamination/propagation)
tsetup time that FF inputs must be stable before next clock edge
thold time that FF inputs must be stable after a clock edge
Tc clock period

CLK CLK CLK CLK

Q1 D2 Q1 CL D2
CL

R1 R2 R1 R2
Tc

CLK CLK

Q1 Q1

D2 D2
tccq tcd tpcq tpd tsetup

thold

58
Example: Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
tpcq = 50 ps
X' X
C tsetup = 60 ps

D
Y' Y thold = 70 ps

per gate
tpd = 35 ps
tpd =
tcd = 25 ps
tcd =
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc >
fmax = 1/Tc =
59
Example: Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
tpcq = 50 ps
X' X
C tsetup = 60 ps

D
Y' Y thold = 70 ps

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd =
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc >
fmax = 1/Tc =
60
Example: Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
tpcq = 50 ps
X' X
C tsetup = 60 ps

D
Y' Y thold = 70 ps

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 25 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc >
fmax = 1/Tc =
61
Example: Timing Analysis
tpcq CLKA CLK
Timing Characteristics
tccq = 30 ps
B tpd
tpcq = 50 ps
X' X
C tsetup = 60 ps

D
Y' Y thold = 70 ps
tsetup

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 25 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps
fmax = 1/Tc = 4.65 GHz
62
Example: Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
tccq tpcq = 50 ps
X' X
C tsetup = 60 ps

D
tcd Y' Y thold = 70 ps

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 25 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps (30 + 25) ps > 70 ps ?
fmax = 1/Tc = 4.65 GHz
63
Example: Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
tpcq = 50 ps
X' X
C tsetup = 60 ps

D
Y' Y thold = 70 ps

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 25 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps (30 + 25) ps > 70 ps ?
fmax = 1/Tc = 4.65 GHz 64
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
A tccq = 30 ps

B tpcq = 50 ps

X' X tsetup = 60 ps
C
thold = 70 ps
Y' Y
D

per gate
tpd = 35 ps
tpd =
tcd = 25 ps
tcd =
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc >
fc =
65
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
A tccq = 30 ps

B tpcq = 50 ps

X' X tsetup = 60 ps
C
thold = 70 ps
Y' Y
D

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc >
fc =
66
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
tpcq A tccq = 30 ps

B tpd tpcq = 50 ps

X' X tsetup = 60 ps
C
thold = 70 ps
Y' Y
D

per gate
tsetup tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps
fc = 1/Tc = 4.65 GHz
67
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
A tccq = 30 ps

B tpcq = 50 ps

X' X tsetup = 60 ps
C
thold = 70 ps
Y' Y
D

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps
Note: no change
fc = 1/Tc = 4.65 GHz
to max frequency!
68
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
A tccq = 30 ps

B tpcq = 50 ps
tccq X' X tsetup = 60 ps
C

tcd Y' Y
thold = 70 ps
D

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps (30 + 50) ps > 70 ps ?
fc = 1/Tc = 4.65 GHz
69
Example: Fixing Hold Time Violation
Add buffers to the short paths:
CLK CLK
Timing Characteristics
A tccq = 30 ps

B tpcq = 50 ps

X' X tsetup = 60 ps
C
thold = 70 ps
Y' Y
D

per gate
tpd = 35 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Check setup time constraints: Check hold time constraints:
Tc > tpcq + tpd + tsetup tccq + tcd > thold ?
Tc > (50 + 105 + 60) ps = 215 ps (30 + 50) ps > 70 ps ?
fc = 1/Tc = 4.65 GHz
70
Clock Skew
◼ To make matters worse, clocks have delay too!
❑ The clock does not reach all parts of the chip at the same time!
◼ Clock skew: time difference between two clock edges

CLOCK A
SOURCE

Long, slow B
clock path

Clock Source
Point A
Point B

clock skew

71
Clock Skew Example
◼ Example of the Alpha 21264 clock skew spatial distribution

P. E. Gronowski+, "High-performance Microprocessor Design," JSSC’98. 72

Clock Skew: Setup Time Revisited
◼ Safe timing requires considering the worst-case skew
❑ Clock arrives at R2 before R1
❑ Leaves as little time as possible for the combinational logic

Signal must arrive at D2 earlier!

This effectively increases tsetup:

Tc > tpcq + tpd + tsetup + tskew

Tc > tpcq + tpd + tsetup, effective

73
Clock Skew: Hold Time Revisited
◼ Safe timing requires considering the worst-case skew
❑ Clock arrives at R2 after R1
❑ Increases the minimum required delay for the combinational logic

Signal must arrive at D2 later!

This effectively increases thold:

tcd + tccq > thold + tskew
tccq tcd

tcd + tccq > thold, effective

tskew thold
74
Clock Skew: Summary
◼ Skew effectively increases both tsetup and thold
❑ Increased sequencing overhead
❑ i.e., less useful work done per cycle

◼ Designers must keep skew to a minimum

❑ Requires intelligent “clock network” across a chip
❑ Goal: clock arrives at all locations at roughly the same time

Source: Abdelhadi, Ameer, et al. "Timing-driven variation-aware nonuniform clock mesh synthesis." GLSVLSI’10.

75
Review:Synchronous Timing Basics
R1 R2
In Combinational
D Q D Q
logic

tclk1 tclk2
clk
tc-q, tsu, tplogic, t cdlogic
thold, tcdreg
❑ Under ideal conditions (i.e., when tclk1 = tclk2)
T  tc-q + tplogic + tsu
thold ≤ tcdlogic + tcdreg
❑ Under real conditions, the clock signal can have both
spatial (clock skew) and temporal (clock jitter) variations
⚫ skew is constant from cycle to cycle (by definition); skew can be
positive (clock and data flowing in the same direction) or negative
(clock and data flowing in opposite directions)
⚫ jitter causes T to change on a cycle-by-cycle basis
Sources of Clock Skew and Jitter in Clock
Network
power supply4
interconnect 3
clock capacitive load 6
1
generation
7 capacitive
PLL coupling
2 clock drivers

5 temperature

❑ Skew ❑ Jitter
⚫ manufacturing device ⚫ clock generation
variations in clock drivers
⚫ capacitive loading and
⚫ interconnect variations coupling
⚫ environmental variations ⚫ environmental variations
(power supply and (power supply and
temperature) temperature)
Positive Clock Skew
❑ Clock and R1 R2
data flow in In D Q
Combinational
D Q
the same logic
direction tclk1 tclk2
clk
delay
T
T+
1 3
>0

2 4

 + thold
T: T +   tc-q + tplogic + tsu so T  tc-q + tplogic + tsu - 
thold : thold +  ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - 
❑  > 0: Improves performance, but makes thold harder to
meet. If thold is not met (race conditions), the circuit
malfunctions independent of the clock period!
Negative Clock Skew
❑ Clock and R1 R2
data flow in In D Q
Combinational
D Q
opposite logic
directions tclk1 tclk2
clk
delay
T
T+
1 3

2 4
<0

T: T +   tc-q + tplogic + tsu so T  tc-q + tplogic + tsu - 

thold : thold +  ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - 

❑  < 0: Degrades performance, but thold is easier to meet

(eliminating race conditions)
•In the following circuit, find out whether there is any setup and hold violation if the
clock period is 15ns?

80
81
82
Clock Jitter
❑ Jitter causes T to R1
Combinational
vary on a cycle-by- In logic
cycle basis
tclk
clk
T

-tjitter +tjitter

T : T - 2tjitter  tc-q + tplogic + tsu so T  tc-q + tplogic + tsu + 2tjitter

❑ Jitter directly reduces the performance of a sequential

circuit
 Combined Impact of Skew and Jitter
❑ Constraints R1 R2
on the In D Q
Combinational
D Q
minimum logic
clock period tclk1 tclk2
( > 0) T
T+
1
>0

6 12
-tjitter

T  tc-q + tplogic + tsu -  + 2tjitter thold ≤ tcdlogic + tcdreg –  –2tjitter

❑  > 0 with jitter: Degrades performance, and makes thold
even harder to meet. (The acceptable skew is reduced by
jitter.)
 Part 3:
Circuit Verification

85
How Do You Know That A Circuit Works?
◼ You have designed a circuit
❑ Is it functionally correct?
❑ Even if it is logically correct, does the hardware meet all
timing constraints?

◼ How can you test for:

❑ Functionality?
❑ Timing?

◼ Answer: simulation tools!

❑ Formal verification tools (e.g., SAT solvers)
❑ HDL timing simulation (e.g., Vivado)
❑ Circuit simulation (e.g., SPICE)

86
Testing Large Digital Designs
◼ Testing can be the most time consuming design stage
❑ Functional correctness of all logic paths
❑ Timing, power, etc. of all circuit elements

◼ Unfortunately, low-level (e.g., circuit) simulation is much

slower than high-level (e.g., HDL, C) simulation

◼ Solution: we split responsibilities:

❑ 1) Check only functionality at a high level (e.g., C, HDL)
◼ (Relatively) fast simulation time allows high code coverage
◼ Easy to write and run tests
❑ 2) Check only timing, power, etc. at low level (e.g., circuit)
◼ No functional testing of low-level model
◼ Instead, test functional equivalence to high-level model
❑ Hard, but easier than testing logical functionality at this level
Adapted from ”CMOS VLSI Design 4e”, Neil H. E. Weste and David Money Harris ©2011 Pearson 87
Testing Large Digital Designs
◼ We have tools to handle different levels of verification
❑ Logic synthesis tools guarantee equivalence of high-level logic
and synthesized circuit-level description
❑ Timing verification tools check all circuit timings
❑ Design rule checks ensure that physical circuits are buildable

◼ The task of a logic designer is to:

❑ Provide functional tests for logical correctness of the design
❑ Provide timing constraints (e.g., desired operating frequency)

◼ Tools and/or circuit engineers will decide if it can be built!

Adapted from ”CMOS VLSI Design 4e”, Neil H. E. Weste and David Money Harris ©2011 Pearson 88
 Part 4:
Functional Verification

89
Functional Verification
◼ Goal: check logical correctness of the design

◼ Physical circuit timing (e.g., tsetup/thold) is typically ignored

❑ May implement simple checks to catch obvious bugs
❑ We’ll discuss timing verification later in this lecture

◼ There are two primary approaches

❑ Logic simulation (e.g., C/C++/Verilog test routines)
❑ Formal verification techniques

◼ In this course, we will use Verilog for functional verification

90
Testbench-Based Functional Testing
◼ Testbench: a module created specifically to test a design
❑ Tested design is called the “device under test (DUT)”

Outputs
Inputs
Test Output
Pattern Checking
Generator Logic
DUT

Testbench

◼ Testbench provides inputs (test patterns) to the DUT

❑ Hand-crafted values
❑ Automatically generated (e.g., sequential or random values)
◼ Testbench checks outputs of the DUT against:
❑ Hand-crafted values
❑ A “golden design” that is known to be bug-free
91
Testbench-Based Functional Testing
◼ A testbench can be:
❑ HDL code written to test other HDL modules
❑ Circuit schematic used to test other circuit designs

◼ The testbench is not designed for hardware synthesis!

❑ Runs in simulation only
◼ HDL simulator (e.g., Vivado simulator)
◼ SPICE circuit simulation
❑ Testbench uses simulation-only constructs
◼ E.g., “wait 10ns”
◼ E.g., ideal voltage/current source
◼ Not suitable to be physically built!

92
Common Verilog Testbench Types

Input/Output
Testbench Error Checking
Generation
Simple Manual Manual
Self-Checking Manual Automatic
Automatic Automatic Automatic

93
Example DUT
◼ We will walk through different types of testbenches to test
a module that implements the logic function:
y = (b ∙ c) + (a ∙ b)
// performs y = ~b & ~c | a & ~b
module sillyfunction(input a, b, c,
output y);
wire b_n, c_n;
wire m1, m2;

not not_b(b_n, b);

not not_c(c_n, c);

and minterm1(m1, b_n, c_n);

and minterm2(m2, a, b_n);
or out_func(y, m1, m2);
endmodule
94
Useful Verilog Syntax for Testbenching
module example_syntax();
reg a;

// like “always” block, but runs only once at sim start

initial
begin
a = 0; // set value of reg: use blocking assignments
#10; // wait (do nothing) for 10 ns
a = 1;
$display(“printf() style message!"); // print message
end
endmodule

95
Simple Testbench

96
Simple Testbench
module testbench1(); // No inputs, outputs
reg a, b, c; // Manually assigned
wire y; // Manually checked

// instantiate device under test

sillyfunction dut (.a(a), .b(b), .c(c), .y(y) );

// apply hardcoded inputs one at a time

initial begin
a = 0; b = 0; c = 0; #10; // apply inputs, wait 10ns
c = 1; #10; // apply inputs, wait 10ns
b = 1; c = 0; #10; // etc .. etc..
c = 1; #10;
a = 1; b = 0; c = 0; #10;
end
endmodule

97
Simple Testbench: Output Checking
◼ Most common method is to look at waveform diagrams
❑ Thousands of signals over millions of clock cycles

❑ Too many to just printf()!

time
◼ Manually check that output is correct at all times

98
Simple Testbench
◼ Pros:
❑ Easy to design
❑ Can easily test a few, specific inputs (e.g., corner cases)

◼ Cons:
❑ Not scalable to many test cases
❑ Outputs must be checked manually outside of the simulation
◼ E.g., inspecting dumped waveform signals
◼ E.g., printf() style debugging

99
 Part 5:
Timing Verification

100
Timing Verification Approaches
◼ High-level simulation (e.g., C, Verilog)
❑ Can model timing using “#x” statements in the DUT
❑ Useful for hierarchical modeling
◼ Insert delays in FF’s, basic gates, memories, etc.
◼ High level design will have some notion of timing
❑ Usually not as accurate as real circuit timing

◼ Circuit-level timing verification

❑ Need to first synthesize your design to actual circuits
◼ No one general approach- very design flow specific
◼ Your FPGA/ASIC/etc. technology has special tool(s) for this
❑ E.g., Xilinx Vivado (what you’re using in lab)
❑ E.g., Synopsys/Cadence Tools (for VLSI design)

101
The Good News
◼ Tools will try to meet timing for you!
❑ Setup times, hold times
❑ Clock skews
❑ …

◼ They usually provide a ‘timing report’ or ‘timing summary’

❑ Worst-case delay paths
❑ Maximum operation frequency
❑ Any timing errors that were found

102
The Bad News
◼ The tool can fail to find a solution
❑ Desired clock frequency is too aggressive
◼ Can result in setup time violation on a particularly long path
❑ Too much logic on clock paths
◼ Introduces excessive clock skew
❑ Timing issues with asynchronous logic

◼ The tool will provide (hopefully) helpful errors

❑ Reports will contain paths that failed to meet timing
❑ Gives a place from where to start debugging

◼ Q: How can we fix timing errors?

103
Meeting Timing Constraints
◼ Unfortunately, this is often a manual, iterative process
❑ Meeting strict timing constraints (e.g., high performance
designs) can be tedious

◼ Can try synthesis/place-and-route with different options

❑ Different random seeds
❑ Manually provided hints for place-and-route

◼ Can manually optimize the reported problem paths

❑ Simplify complicated logic
❑ Split up long combinational logic paths
❑ Recall: fix hold time violations by adding more logic!

104
Meeting Timing Constraints: Principles
◼ Let’s go back to the fundamentals

◼ Clock cycle time is determined by the maximum logic delay

we can accommodate without violating timing constraints

◼ Good design principles

❑ Critical path design: Minimize the maximum logic delay
→ Maximizes performance
❑ Balanced design: Balance maximum logic delays across different
parts of a system (i.e., between different pairs of flip flops)
→ No bottlenecks + minimizes wasted time
❑ Bread and butter design: Optimize for the common case, but
make sure non-common-cases do not overwhelm the design
→ Maximizes performance for realistic cases
105