Analog Integrated Circuits and Signal Processing (2024) 119:43–55

https://doi.org/10.1007/s10470-024-02252-5

A design approach for class‑AB operational amplifier using the ­gm/ID

methodology
Chen Chen1 · Jinxing Cheng2 · Hongyi Wang1 · Youyou Fan3 · Kaikai Wu1 · Tao Tao1 · Qingbo Wang1 · Ai Yu2 ·
Weiwei Wen2 · Youpeng Wu2 · Yue Zhang2

Received: 27 March 2023 / Revised: 29 December 2023 / Accepted: 4 January 2024 / Published online: 11 February 2024
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024

Abstract
The primary contribution of this paper is the extension of the ­gm/ID design methodology to two-stage operational amplifiers
with class-AB output stages. First, the circuit is analyzed from the perspective of the ­gm/ID methodology, with a focus on
its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit
sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary
solution automatically. Benefiting from the ­gm/ID methodology, the gap between analytical equations and circuit simulation
is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize
the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using
the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm
and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that
it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics.

Keywords Class-AB output stage · Two-stage op-amp design · The ­gm/ID methodology · Analog integrated circuit
optimization

1 Introduction in various industrial products due to its high current drive

capability, such as low-dropout regulators, active-matrix dis-
The operational amplifier (op-amp) is an essential com- play drivers, etc [1–3]. In addition, this operational ampli-
ponent of analog integrated circuits, playing a critical and fier has excellent scalability. The circuit performance can
indispensable role in a wide range of circuit systems. The be improved by adding some small-scale function blocks
two-stage op-amp with class-AB output stage is widely used or components, such as [4, 5]. Manual circuit sizing can
be a time-consuming and tedious task due to the high-
dimensional design space and the sophisticated trade-offs
Chen Chen and Jinxing Cheng have contributed equally to this among various performance metrics. Therefore, it is crucial
work. to establish a design approach for the operational amplifier
* Jinxing Cheng to achieve optimal performance.
[email protected] In order to overcome the challenge arising from manual
* Hongyi Wang circuit sizing, various automatic sizing techniques have
[email protected] been developed. These techniques can be classified into
Chen Chen equation-based method [6, 7], simulation-based method
[email protected] [8] and simulation & equation-based method [9]. However,
none of these can be directly used to solve the class-AB op-
1
School of Microelectronics, Xi’an Jiaotong Univeristy, amp sizing problem. In the case of existing equation-based
Xi’an 710049, Shaanxi, China
method, the analytical equations are built on the simple
2
Beijing New-High Technology Academy, Beijing 100094, square law model, which creates a big gap between the ana-
China
lytical equations and SPICE simulation. Consequently, the
3
Beijing Microelectronics Technology Institute, sizing result may differ significantly from expectations. The
Beijing 100076, China

Vol.:(0123456789)

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44 Analog Integrated Circuits and Signal Processing (2024) 119:43–55

simulation-based method uses optimization algorithms that and SMIC 180nm technologies, and compared with the
suffer from several problems, such as the curse of dimen- equation-based method using the square-law model, two
sionality [10], huge computational resource overhead, ina- simulation-based methods, and a commercial tool Cadence
bility to handle equality constraints, etc. Furthermore, the ADE GXL. Our proposed approach achieves the best results
designer is completely detached from the circuit design, as with minimal time overhead.
the optimizer does not provide any insights into the circuit The rest of this paper is organized as follows. In Sect. 2,
behavior, the achievable design metrics, or the trade-offs we present the basic circuit topology and analytical
between different specifications. The simulation & equation- equations of the circuit behavior. In Sect. 3, we present the
based methods encounter challenges when dealing with proposed design procedure. The experimental results are
amplifiers that have a class-AB output stage, as these meth- presented in Sect. 4 to verify the efficiency of the proposed
ods rely on specific problem constraints and require addi- approach. Finally, we conclude the paper in Sect. 5.
tional knowledge to guide the algorithm. Previous works,
such as [9, 11], have only focused on class-A op-amp.
The ­gm/ID design methodology is a promising approach
2 Basic topology and analysis
that aims to overcome the limitations of existing equation-
based methods. This methodology bridges the gap between
As one of the typical class-AB implementations, the circuit
analytical equations and simulations, and it was first
architecture presented in [21, 22] is shown in Fig. 1, and it
proposed in [12]. It has been extended to optimize the noise
includes three stages: the input stage, gain stage, and output
performance of OTA [13, 14], minimize power consumption
stage. The input stage consists of the differential pairs M1
[15] and design various analog circuit [16–19]. The
and M2 , the gain stage is a folded cascode structure, and
methodology is based on a series of look-up tables (LUTs)
the output stage is a class-AB structure that introduces two
used to describe the transistor behavior more accurately
translinear loops to precisely control the quiescent current.
than the square law model. The LUTs are generated from
The PMOS translinear loop is formed by M14 , M16 , M17 ,
DC-analysis using the SPICE model provided by the silicon
and M22 , and the NMOS translinear loop is formed by M15,
foundry and thus can accurately depict the actual behavior of
M20 , M21, and M23.
transistors. The LUTs describe various parameters (include
By setting VGS14 = VGS17 and VGS15 = VGS20, the quiescent
transit frequency, fT , intrinsic gain, gm ro , current density,
current of the output stage can be controlled by the size ratio
ID/W, intrinsic capacitance ratio, CGD/CGG and CDD/CGG ,
of M16 and M22(M21 and M23). The output stage’s quiescent
saturation voltage, Vdsat , etc.) as a function of the inversion
current is determined by the ratio of the bias current source
level, which is represented by the transconductance
and the transistor size, which reduces the influence of
efficiency (i.e. gm/ID) [20].
process, power supply, and temperature.
To enable the application of the gm/ID methodology for
To reduce the influence of the channel length modulation
class-AB op-amp, the main contribution of this paper are
effect on output stage current, M18 and M19 are added. By
summarized as follows: (1) Overall, this paper extends the
setting VGS18 = VGS23 and VGS19 = VGS22 , VD17 = VD14 and
gm/ID methodology to design class-AB op-amp. The design
VD15 = VD20 , the channel length modulation effect can be
variables are the gm/ID value, the length of each transistor,
suppressed.
and branch current. The results show only a small deviation
The Miller compensation network, which consists of CC1,
between the design values and simulation result, especially
CC2 , R1, and R2 , is used for loop stability compensation.
for DC operating point. (2) This paper analyzes the large-
The operational amplifier structure discussed in this paper
signal performance, small-signal performance, class-AB
has extensive commercial applications. Key performance
stage output current, and constraints of the class-AB op-amp
metrics that must be considered when designing operational
specifically in the gm/ID space. After that, the sizing task is
amplifiers include power consumption, noise, gain,
formulated as a single-objective optimization problem, and
bandwidth, and slew rate. These metrics are critical for
the temporary sizing is automatically obtained by SLSQP
achieving optimal operational amplifier performance and
(Sequential Least Squares Programming) optimizer. (3)
hold significant importance. Therefore, this paper focuses
Although the gm/ID methodology reduces the gap between
on analyzing the aforementioned metrics.
analytical equations and simulations, some deviation still
exists due to high-order effects. Therefore, if temporary
solution fails to meet the required specifications a rule- 2.1 Power consumption
guided fine-tuning method is adopted to improve the circuit
performance. (4) To verify the efficiency of the proposed By investigating the DC analysis of the circuit shown in
approach, this approach is verified by using SMIC 55nm Fig. 1, it becomes apparent that the power consumption is

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 45

VDD

Ib2
Ib1
M9 M10
M16 M19

M7 M8 M17 Ib2
Vb1
P V1
M1 M2 M22
Vin-

Cc1 Rc1 Vout

Vin+ M14
M13 Cc2 Rc2
V2 M15
M23
Vb2
M5 M6
Ib2
M20
Ib2

M3 M4 M18 M21
Ib2
M0
VSS

Fig. 1  The basic topology of class-AB op-amp

the product of the power supply voltage and the current variables. Additionally, Vb1 and Vb2 represent cascode bias,
flowing through each branch. Taking symmetry into which is implemented by diode-connected transistors in our
consideration, we set IM3 = IM4 = Ib1. Therefore, the power case.
consumption is expressed by Eq. (1).
2.2 Gain and bandwidth
Pdiss = VDD (2Ib1 + 5Ib2 + Isc ) (1)
where Isc is the quiescent current of the output stage. In Considering the AC parameters, the small-signal equivalent
this paper, Ib2 is a constant, while Ib1 and Isc are two design circuit of the class-AB op-amp has been built in Fig. 2. The
Co1, Ro1 are the parasitic capacitor and the resistor of node

Fig. 2  The small-signal equiva- Cc1 Rc1

lent circuit of the op-amp
Ro1 Co1
Vin- P V1 Vout
-gm1 -gm10 -gm22

1/gm9 CP RL CL
gm15V2 gm14V1

Vin+ V2
-gm2 -gm23

Ro2 Co2

Cc2 Rc2

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46 Analog Integrated Circuits and Signal Processing (2024) 119:43–55

V1 respectively. The Co2 , Ro2 are the parasitic capacitor and However, taking into account PVT variations, the errors
the resistor of node V2 respectively. The CP is the parasitic in the above equations, and the current consumption, we
capacitor of node P, and the resistance seen in node P is opt to set the 𝜔z slightly larger than 𝜔u to improve the
1/gm9. stability. In the default case, 𝜔z is set as 1.2 times 𝜔u , as
In general, we can assume that gm1 ≈ gm2 , gm9 ≈ gm10 , shown in Eq. (4).
Ro1 ≈ Ro2 , Co1 ≈ Co2 , Cc1 = Cc2 , Rc1 = Rc2 . Neglecting the
1 2
pole determined by the gate of M9 (which is approximately Rc = − (4)
0.6gm1 gm22 + gm23
at −gm9 ∕CP and in the high frequency range), the transfer
function of the class-AB op-amp is shown in Eq. (2).
gm1 Ro1 (gm22 + gm23 )RL A 2.3 Slew rate
H(s) = (2)
2(Bs3 + Cs2 + Ds + 1)
In the class-AB op-amp, the push and pull currents can be
where A = 1 + Cc1 Rc1 s −
2Cc1 s
, B = CL Cc1 Co1 RL Rc1 Ro1, very large and are primarily determined by the aspect ratio
gm22 +gm23
, of M22 and M23. On the other hand, the slew rate is mainly
C = CL Cc1 RL Rc1 + CL Cc1 RL Ro1 + CL Co1 RL Ro1 + 2Cc1 Co1 RL Ro1 + Cc1 Co1 Rc1 Ro1
. depends on the quiescent current of first stage Ib1, and the
D = Cc1 RL Ro1 (gm22 + gm23) + CL RL + 2Cc1 RL + Cc1 Rc + Cc1 Ro1 + Co Ro
Thus, the DC gain, the unity-gain frequency, the Miller capacitor Cc . The slew rate can be given by Eq. (5).
dominant pole(assuming (gm22 + gm23 )RL ≫ 2 ), the second Ib1
pole, and the third pole can be expressed as equations SR ≈ (5)
2Cc1
(3a)–(3f) respectively. The pole 𝜔p3 generated by the
Miller compensation structure is also at high frequency,
and can be safely neglected. 2.4 Noise
gm1 Ro1 (gm22 + gm23 )RL
Av = H(s) ∣s=0 ≈ (3a) In this class-AB op-amp, generally, the first stage is the
2 primary contributor to noise, whereas the noise generated
by the second stage is negligible. The dominant sources
gm1
𝜔u ≈ (3b) of noise are the input transistor and the common-source
2Cc1 transistor of the gain stage, and the input-referred noise can
be determined using Eq. 6.
gm22 + gm23
𝜔z = (3c)
[
Cc1 [2 − Rc1 (gm22 + gm23 )] 2 8kT𝛾 2 KP
Vn,in ≈ 2 (gm1 + gm3 + gm9 ) +
gm1 Cox (WL)1
2 2
] (6)
1 K g KN gm9 1
𝜔p1 ≈ −
(gm22 + gm23 )RL Cc1 Ro1 (3d) + N m3 +
(WL)3 g2m1 (WL)9 g2m1 f

gm22 + gm23 where k is the Boltzmann constant, and 𝛾 , Cox , KP , and KN

𝜔p2 ≈ −
CL (3e) are four process-dependent constants that can be extracted
by simulation. T is temperature in Kelvin.
1
𝜔p3 ≈ −
Co1 Rc1 (3f)
3 The proposed design approach
Note that the equations above are based on
approximations that may lead to significant deviations in The proposed design approach aims to use the gm/ID method-
certain scenarios. Therefore, these equations are treated as ology to optimize the design parameters illustrated in Fig. 1.
constraint terms or used to estimate the search bound of By employing this lookup table approach, the simulation
design variables. To obtain accurate estimations of Av , wu , result is expected to more closely align with our expecta-
and phase margin, we directly solve Eq. (2). tions, thereby enhancing optimization efficiency and effec-
According to Eq. (3c), Rc can control the position of tiveness. Figure 3 provides an overview of the proposed
zero. There are several ways to design the value of Rc , method. The sizing task is formulated into a single objec-
such as shifting the zero into the left half plane to cancel tive optimization problem using the equation in Sects. 2
the second pole, moving the 𝜔z to infinity, or solely using and 3.2. SLSQP (Sequential Least Squares Programming)
Cc and setting wz > Nwu (where N is 10, for example). is then employed to find the temporary solution while con-
sidering the aforementioned constraints and search bounds.

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 47

Design Variables Constraints Table 1  Design variables and suggested search bounds
(Section3.1) (Section3.3) Design variables Suggested search bounds Matching

Design Cc [Cc (min) = 4pF ,

Vairbles Cc (max) = 10pF ]
Multi-Start SLSQP Circuit Evaluation
Ib1 [SR ⋅ Cc (min),
Optimizer (Section 3.4 ) (Section 2 & 3.2 )
Performance N ⋅ SR ⋅ Cc (max)]
Evaluation
Ib2 10𝜇A
SPICE verification Isc [100𝜇A, 300𝜇A]
gm1 [Cc (min) ⋅ wu, gm2
N ⋅ Cc (max) ⋅ wu]
No Fine-tuning gm ∕ID3 [6mS/mA, 18mS/mA] gm ∕ID4
Meet the specs
(Section 3.5) gm ∕ID5 [6mS/mA, 18mS/mA] gm ∕ID6
Yes gm ∕ID7 [6mS/mA, 18mS/mA] gm ∕ID8
gm ∕ID9 [6mS/mA, 18mS/mA] gm ∕ID10
Optimized
Circuit gm ∕ID13 [6mS/mA, 18mS/mA] gm ∕ID14,15,17,20
gm ∕ID22 [6mS/mA, 18mS/mA] gm ∕ID16,19
gm ∕ID23 [6mS/mA, 18mS/mA] gm ∕ID18,21
Fig. 3  Overview of the proposed approach
L1 [1.08𝜇, 1.8𝜇] L2
L3 [1.80𝜇, 3.60𝜇] L0,4
Under the given design variables in gm/ID space (Sect. 3.1) L5 [0.36𝜇, 1.08𝜇] L6
and constraints (Sect. 3.3), the SLSQP algorithm automati- L7 [0.36𝜇, 1.08𝜇] L8
cally and swiftly generates an temporary solution. Finally, L9 [1.08𝜇, 3.60𝜇] L10
to address small deviations between the analytical equation L13 [0.36𝜇, 1.08𝜇] L14,15,17,20
and SPICE simulation that remain even with the use of the L23 [0.36𝜇, 1.08𝜇] L18,21
gm/ID methodology, if the temporary solution fail to meet the L22 [0.36𝜇, 1.08𝜇] L16,19
required specifications, a rule-guided fine-tuning method is Vb1 [VDD ∕2, VDD-Vthp]
proposed by leveraging valuable design knowledge to ensure Vb2 [Vthn, VDD ∕2]
all the specifications are met.

clip method is used to ensure that gm ∕ID1 remains within

3.1 Design variables and search bound reasonable bounds. The remaining transistors’ design vari-
ables are their gm/ID values.
In the proposed approach, the design variables are gm/ID In terms of search bounds, a reasonable search bound
(or gm ), the channel length of each transistor, as well as can aid in finding a good solution. From the mathematical
the current value of each branch. The width of a transistor optimization point of view, wide search bounds may increase
can be obtained through the look-up table operation, as the searching difficulty in certain cases, while narrow
demonstrated in Eq. (7). search bounds have risk to miss the optimum solution.
Therefore, to determine reasonable search bounds, the
W = ID ∕fLUT (gm ∕ID , L) (7) following considerations apply: (1) The lower bound of
where fLUT (⋅) is lookup table operation to get the current Ib1 is determined by Eq. (5). (2) The lower bound of gm1
density. is determined by Eq. (3b). (3) The search bound of Cc is
Table 1 presents the design variables and their cor- determined by the 𝜔u , 𝜔p1, and load. (4) The search bound
responding reference search bounds, where “matching” of gm ∕ID value is [6, 18], allowing transistors to work in
denotes that these variables have the same value. A total of strong inversion and moderate inversion regions. (5) The
21 design variables are considered. VDD refers to the supply search bound of L1 mainly considers the noise and parasitic
voltage, Vthp refers to the PMOS threshold voltage, and Vthn effect. (6) The search bound of L3, and L9 mainly consider
refers to the NMOS threshold voltage. The Vb1 and Vb2 are the noise, intrinsic gain and channel length modulation
implemented by a diode-connected transistor structure, and effect. (7) The search bound of L5, L7, L13, L22 and L23 mainly
their width can be calculated according to LUT. The default consider the parasitic effect.
value of N is 3. For M1, since gm1 has a direct relationship Additionally, searching for the transistor’s gm/ID rather
between unity gain frequency and noise, the design variable than width offers several benefits. (1) The value range
is gm1. Its gm ∕ID value is the ratio of gm1 and Ib1 ∕2, and the of gm/ID is around 2–25 S/A (depending on the process),
which means the search bound is bounded and naturally

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48 Analog Integrated Circuits and Signal Processing (2024) 119:43–55

normalized, making it more friendly to the optimization 3.3.1 Constraints of translinear loop in the gm/ID space
algorithm. (2) Since the relationship between circuit
performance metric and width is highly nonlinear and vague, In a circuit with a translinear loop, the quiescent current
it can be challenging to set a reasonable search bound for is determined by the size ratio of transistors if the VGS of
width. transistors match. For the circuit shown in Fig. 1, if the
circuit can satisfy the following constraints, the quiescent
3.2 The output current estimation of class‑AB stage current of output stage is determined by the aspect ratio
of M16 , M22 and M21, M23.
Class-AB output stages are known for their ability to
deliver high output current while consuming a small
VGS,20 =VGS,15 (9)
quiescent current. Concretely, the maximum of push
current (the current through M22 ) and pull current (the VGS,14 =VGS,17 (10)
current through M23 ) can be much greater than the
quiescent current Isc . When the in-phase signal current Benefit from the gm/ID methodology, the above constraints
are pushed into class-AB output stage, the current through can be efficiently implemented directly from the
M14 increase while the current through M15 decrease, constraints of the design variables: gm ∕ID15 = gm ∕ID20 ,
causing M23 to pull current from the Vout node. Even after gm ∕ID21 = gm ∕ID23, gm ∕ID14 = gm ∕ID17, gm ∕ID16 = gm ∕ID22 .
the current through M14 equal that of M8 , the pull current For simplicity, gm ∕ID15 = gm ∕ID14 = gm ∕ID15 . Since
of M23 can continue to increase until M23 operate in linear VGS22 = VGS9, we have gm ∕ID22 = gm ∕ID9.
region. A similar behavior can be observed when the input
signals are pulled into the class-AB stage. 3.3.2 Constraints of operating point
The existing gm / ID methodology design circuit to
operate in a steady state. However, if the size of transistor Constraints on the transistor guarantee that the transistors
is determined, the gm /ID value changed as the current operate normally. The constraints include:
changes. In our case, the gm/ID of M22 and M23 operating VDD − (Vb1 + VSG7 ) > vdsat9 + M (11)
on steady state is bigger than the value when deliver a
heavy output current. As the LUTs of current density is
(Vb1 + VSG7 ) − (VDD − VSG22 ) > vdsat7 + M (12)
monotonically decreasing with the gm /ID value, in our
paper, the maximum push and pull current are given using
Eqs. (8a) and (8b). Vb2 − VGS5 > vdsat3 + M (13)

Ipull,max = W23 ⋅ fLUT ((gm ∕ID )∗ , L23) (8a) VGS23 − (Vb2 − VGS5 ) > vdsat5 + M (14)

Ipush,max = W22 ⋅ fLUT ((gm ∕ID )∗ , L22) (8b) vdsat15 + M < VDD − VGS22 − VGS23 (15)
where W22 and W23 are the width calculated according to
Eq. (7). The (gm ∕ID )∗ is a small value, indicating that the vdsat14 + M < VDD − VGS22 − VGS23 (16)
transistor operates near the linear region, and in our case, it where M is a design margin. M ensures that transistors
is 2. The Eqs. (8a) and (8b) can be considered as constraint operate in the saturation region under process variations. It
terms or optimization targets. should be a trade-off between the transistor’s intrinsic gain
and swing. In our case, we have chosen 0.15 V for M. The
3.3 Constraints vdsat is the minimum drain-source voltage for a transistor to
operate in the saturation region. The vdsat and VGS values for
To make sure the circuit operates normally, suitable the transistors can be obtained from lookup tables.
equality and inequality constraints must be established.
Three types of constraints are considered, including 3.3.3 Constraints of performance
translinear loop, transistor operating point, and circuit
performance. The translinear loop constraints ensure that In order to meet the circuit specs, it is necessary to ensure that
the quiescent current of the class-AB stage is set normally. some basic constraints related to circuit performance metrics
The transistor operating point constraints ensure that are met. Equation (17) defines the constraints on phase mar-
transistors work in saturation region. The performance gin, where N is set to 3 by default. Equation (18) defines the
constraints are the basic constraints related to circuit
performances.

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 49

constraints on unity gain frequency. Equation (19) defines the of the objective function approaching zero [23, 24]. To use
constraints on slew rate. SLSQP, only the objective function, constraint function, and
optimization variables need to be provided. In our problem,
𝜔p2 ≥ N𝜔p1 (17) the objective is to meet circuit specifications, which is
transformed into a single objective optimization through
gm1 ≥ 2Cc1 𝜔u_spec (18) Eq. (20). The search bounds are described in Sect. 3.1 and
the constraints are described in Sect. 3.3.
To avoid being stuck at a local optimum, a multi-start
Ib1 ≥ 2SRspec Cc (19)
local search strategy is used. Firstly, a number of points
The Eq. (17) is represents constraint term in the proposed are selected as starting points. Multiple SLSQP local
approach. The Eqs. (18) and (19) constrain the search bound searches are performed starting from these points. The
of corresponding design variables. final solution is chosen as as the best result obtained from
these searches. The optimizer may require a few minutes
3.4 Solving the sizing problem by single objective to find the temporary solution for the circuit. The results
optimization are further improved by the fine-tuning strategy, which
will be described below.
Once the design variables and search bounds are determined,
the circuit analytic equations presented in Sect. 2 and the
constraints presented in Sect. 3.3 are used to optimize the 3.5 Fine tuning the temporary solution
circuit. Due to the abundance of equations and constraints
involved, formulating the circuit optimization problem as Due to the presence of parasitic and second-order effects in
a single-objective problem is advisable. This allows for the circuit, there will inevitably be some deviation between
automation of the handling of search bounds and constraints. the analytical equations and the simulation results. Although
The optimization objective can be defined as: the gm/ID methodology can reduce this deviation, it cannot
completely eliminate it. The temporary solution produced
N1 ) N2
specj by the SLSQP algorithm requires further validation
( ( )
∑ yi (x) ∑
f (x) = min ,1 + min ,1 (20) through electrical simulations. To prevent the failure to
i=1
speci j=1
yj (x)
meet specifications resulting from such deviations, various
where yi is the circuit performance equation described in potential solutions are available: (1) Setting some margins
Sect. 2, speci is specification for i-th performance metric, for specs before running the SLSQP optimization algorithm;
and x is the design variables described in Sect. 3.1. N1 (2) Adopting a simulation-based algorithm to achieve full
and N2 represent the number of performance metrics to be accuracy [25]; (3) Fine-tuning the temporary solution based
maximized and minimized, respectively. on design knowledge. To achieve interpretability and avoid
With the sizing problem now in the form of a single- detaching the designer from the circuit design, a rule-guided
objective optimization task, the objective function given fine-tuning method is proposed to modify the temporary
by Eq. (20) is passed to a suitable solver. In this work, we solution obtained from SLSQP.
use SLSQP, a modified Sequential Quadratic Programming
(SQP) algorithm that is well-suited to solve nonlinear Algorithm 1: Fine Tuning Rules
programming (NLP) problems. The SLSQP algorithm Input: The temporary solution of class-AB op-amp
starts from an starting point, constructing a quadratic While (performance not satisfied or not reach iteration limit)
approximation of the objective function and constraints near If Phase margin is too small
this point, thereby forming a Quadratic Programming (QP) 1) Sweep RC to adjust zero
subproblem. This step transforms the complex optimization 2) Increase gm22 and gm23
problem into a more manageable quadratic subproblem. else if Noise is too big
Subsequently, the algorithm employ BFGS quasi-Newton if thermal noise dominant
method to update the approximation of the Hessian matrix Increase the gm1
of the objective function, enhancing the search direction if 1/f noise dominant
and step size. With each iteration, the algorithm updates the Increase the of length of M1 / M3 / M9 that
current solution using the determined step length and then contribute most of the noise
re-evaluates the quadratic approximation of the objective else if Gain is too small
function and constraints. This process is repeated until pre- 1) Increase the length of M3 and M9
set convergence criteria are met, such as the change in the 2) Increase the length of M22 and M23
solution falling below a specific threshold or the gradient

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50 Analog Integrated Circuits and Signal Processing (2024) 119:43–55

Algorithm 1: Fine Tuning Rules Table 2  Performance specifications for class-AB OPAMP

else if SR is too small Performance Specification Condition

1) Increase the Ib1
GAIN (dB) ≥ 80 CL = 10pF, RL = 1kΩ
else if Unity gain frequency is too small
UGB (MHz) ≥ 10 CL = 10pF, RL = 1kΩ
1) Decrease Cc
SR (V/µs) ≥9 CL = 50pF, RL = 1kΩ,
2) Increase gm1 1–2 V(10–90%)
Endwhile PM (°) ≥ 60 CL = 10pF
Output: The optimized sizing Iq (µA) ≤ 600 CL = 10pF
≤ 20 @(10kHz)
√
No (nV/ Hz)
After acquiring the temporary solution via SLSQP Iout (mA) ≥ 2 mA @Vout = 1.65
optimization, a recursive, rule-guided method is employed
for fine-tuning. This method is organized as a series of
’if-else if’ rules that adjust various design parameters.
The process is repeated in a while loop, with each
Table 3  The DC Operating point of temporary solution (180 nm)
iteration refining the parameters until all specifications
are satisfactorily met or the iteration limit is reached. In Design variables Design value Simulation result Error (%)
the while loop, the rules are arranged sequentially, and
Iq 566.8 µA 572.0 µA 0.92
subsequent optimizations should not negatively impact the
Isc 241.7 µA 243.5 µA 0.74
performance already optimized. Stability is a fundamental
ID,M14 34.38 µA 33.2 µA 3.4
requirement for circuit operation; therefore, the phase margin
ID,M15 34.38 µA 37.3 µA 8.56
is the first parameter to be optimized. When optimizing
gm1 987.9 µS 967.1 µS 2.11
for noise, some transistor lengths and gm values may be
gm ∕ID,1 14.4 mS/mA 14.1 mS/mA 2.1
changed, making it necessary to prioritize noise optimization
gm ∕ID,3 14.0 mS/mA 13.4 mS/mA 4.29
before gain and unity-gain bandwidth. When optimizing for
gm ∕ID,5 8.5 mS/mA 8.1 mS/mA 4.71
slew rate, the gm1 value may be modified, and therefore, the
gm ∕ID,7 6.7 mS/mA 6.1 mS/mA 8.96
optimization of slew rate should precede that of unity gain
gm ∕ID,9 8.8 mS/mA 8.1 mS/mA 7.95
bandwidth.
gm ∕ID,14 11.3 mS/mA 11.1 mS/mA 1.77
The gm/ID methodology provides direct constraint on the gm ∕ID,15 11.3 mS/mA 10.9 mS/mA 3.5
branch current through search bounds and allows for precise gm ∕ID,22 8.5 mS/mA 8.0 mS/mA 5.88
control of circuit current, thereby generally meeting power gm ∕ID,23 11.4 mS/mA 10.9 mS/mA 4.39
consumption requirements. Therefore, we did not consider VGS15 – 0.94 –
it in the fine-tuning process. VGS20 – 0.93 –
VGS14 – 0.99 –
VGS17 – 0.92 –
4 Simulation result

The proposed approach is implemented in Python and the

CADENCE simulator is used to validate the sizing outcomes.
simulation-based methods, including evolution algorithm
Two different technologies are used to demonstrate the
(EA) [27], Bayesian Optimization (BO) [28], and a com-
efficiency of the proposed approach, including SMIC 55nm
mercial tool Cadence ADE GXL. To ensure a fair com-
and SMIC 180nm CMOS technology. The experiments
parison, the search space, which involves the transistor
are conducted on a Sugon I620-C20 workstation with two
width and length, is kept identical to that of the proposed
Intel E5-2643 CPUs and 128GB memory. In this work, the
approach. The Eqs. (9) and (10) represent the constraint
SLSQP optimizer is leveraged from the SciPy library [26].
terms, which are added to Eq. (20) using a quadratic pen-
To our knowledge, regarding equation-based
alty function. For BO, the initial point is 20, and the num-
methods,there is a scarcity in the literature specifically
ber of iterations is 200; the Gpytorch is used to handle
focusing on optimizing Class-AB circuits. Therefore,
the Gaussian process; the acquisition function is expected
we chose to construct analytical equations for compari-
improvement(EI); the kernel of the Gaussian process is
son using the method described in [6]. The matching
RBF kernel. For EA, the population size and iterations
relationship of the translinear loop is given by [22]. In
are 25 and 40 respectively; the hyper-parameters of EA
addition, We compared the proposed approach to several
are the same as the default value of [29]. For ADE GXL,

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 51

we use the global optimization method, and the maximum constraints described in Sect. 3.3.1 rather than the SLSQP
iteration is 400. optimizer.
With 3.3V supply, the circuit specs are shown in The temporary solution performance under various
Table 2. GAIN denotes the DC gain. UGB denotes the unit corners is shown in Table 4. A maximum deviation of only
gain bandwidth. PM denotes the phase margin. SR denotes 1.3% is observed in terms of quiescent current. It is common
the slew rate, which is the minimum value of rising SR+ for the simulation value of UGB and SR to be smaller than
and falling SR-. Iq denotes quiescent current. No denotes the design value. The remaining metrics exhibit reasonable
the input referred noise. Iout is the minimum value of Ipush fluctuations under different corners. The gain deviation
and Ipull when the gm/ID value is 2. Several typical PVT is found to be higher than that of other metrics due to the
corners are taken into account, including TT, SS, FF, strong dependence of the intrinsic gain gm ro of a transistor
FNSP, SNFP, and the optimization target is the worst case. on VDS.
Table 5 presents the performance comparison between
4.1 Simulation result on 55 nm process the proposed approach and other methods. The worst-case
for each metric under different corners are listed in the table.
The DC operating point of temporary solution generated by In this experiment, since the temporary solution can meet
SLSQP under TT corner is presented in Table 3. Overall, the the specs, fine-tuning is unnecessary. The simulation-based
gm/ID methodology benefits the design by resulting in only methods BO and EA are run 10 times, and the best results
a small deviation between the design value and simulation are reported in the table. ADE GXL is the commercial sizing
result. For transistors that suffer from the body effect, the tool Cadence ADE GXL. The average running time of each
deviation is much bigger than other transistors. Fortunately, method is recorded in the “Time” column.
since the body effect simultaneously affects M15 and M20 In terms of equation-based methods, there is a consider-
( M14 and M17 ), the VGS of these two transistors are basi- able deviation in performance metrics, which is also men-
cally the same, which behave in the same way as expected tioned in [6]. Since the square-law model cannot encompass
in translinear loop design. This property is caused by the the variations in mobility, even considering translinear loop
matching, it still cannot bias the currents of the class AB

Table 4  Performance metrics Performance Modela TT SS FF FNSP SNFP

on different corners (180 nm)
GAIN (dB) 105.3 89.7 85.0 91.0 87.7 89.5
UGB (MHz) 14.1 12.2 11.7 12.4 12.1 12.1
SR (V/µs) 12.7 11.4 11.2 11.3 11.5 11.3
PM ( ◦) 101.6 82.9 82.4 83.2 82.9 82.8
Iq (µA) 566.8 572.0 574.2 569.9 571.5 572.5
11.5 15.9 16.0 15.9 16.2 15.7
√
No (nV/ Hz)
Iout (mA) 3.6 3.2 3.0 3.3 3.1 3.1
a
The results calculated based on the analytical equations utilized in this study

Table 5  Performance Performance [6] BO EA ADE GXL

TSa FTb Model in [6] c
comparison of class-AB OPA
(180 nm) GAIN (dB) 85.0 – 123.4 76.5 95.9 87.0 73.1
UGB (MHz) 11.7 – 11.3 9.1 11.0 13.6 15.3
SR (V/µs) 11.2 – 9.53 8.0 12.3 12.4 10.6
PM ( ◦) 82.4 – 97.1 76.9 77.6 65.3 30.9
Iq (µA) 574.2 – 548.9 456.2 715.3 580.0 594.7
16.2 – 11.05 12.9 25.1 19.98 15.1
√
No (nV/ Hz)
Iout (mA) 3.0 – – 1.4 6.7 6.1 2.6
Time (s) 257.5 – – 1.1 4157.5 9286.8 8244.0
a
The simulation results of the temporary solution
b
The simulation results of the temporary solution that has undergone fine-tuning
c
The results calculated based on the analytical equations utilized in [6]
The metrics that do not meet the specs are bold

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52 Analog Integrated Circuits and Signal Processing (2024) 119:43–55

Table 6  The DC operating point of temporary solution output stage. Moreover, the square-law model fails to con-
Design variables Design value Simulation result Error (%) sider the constraints of vdsat. The time cost of square-law
model only took one second, which is because, on the one
Iq 475.1 µA 472.9 µA 0.46 hand, there is no need for lookup table operations and solv-
Isc 232.8 µA 235.1 µA 0.98 ing transfer functions, and on the other hand, due to the
ID,M14 24.1 µA 23.2 µA 3.7 severe overestimation in the analytical equation, SLSQP
ID,M15 24.1 µA 22.6 µA 6.2 quickly exited the loop iteration.
gm1 850.0 mS 854.4 mS 0.52 In terms of simulation-based methods, it can be observed
gm ∕ID,1 17.7 mS/mA 17.8 mS/mA 0.56 that only the proposed approach and EA satisfy the hard
gm ∕ID,3 14.1 mS/mA 14.2 mS/mA 0.71 constraints. However, EA has a significantly longer average
gm ∕ID,5 12.9 mS/mA 13.3 mS/mA 3.10 running time. Simulation-based algorithms treat the circuit
gm ∕ID,7 7.7 mS/mA 7.8 mS/mA 1.30 as a black box and do not leverage any circuit design
gm ∕ID,9 9.5 mS/mA 9.6 mS/mA 1.05 knowledge. These methods completely detach designers
gm ∕ID,14 6.0 mS/mA 6.0 mS/mA 0.16 from circuit design and fail to provide insights into circuit
gm ∕ID,15 6.0 mS/mA 6.3 mS/mA 5.00 behavior. Moreover, simulation-based algorithms incur a
gm ∕ID,22 8.65 mS/mA 8.65 mS/mA 0.03 high computational overhead, whereas our method takes
gm ∕ID,23 9.63 mS/mA 9.64 mS/mA 0.03 less than 10 min to complete.
VGS15 – 1.42 V –
VGS20 – 1.43 V – 4.2 Simulation result on 180 nm Process
VGS14 – 1.38 V –
VGS17 – 1.38 V – To further verify the proposed approach, an additional
experiment was conducted using SMIC 180 nm process.
The DC operating point of temporary solution is presented
in Table 6, and the performance metrics under various cor-
ners are provided in Table 7. The results confirm that the

Table 7  Performance on Performance TT SS FF FNSP SNFP

Model a
different corners
GAIN (dB) 112.4 102.2 93.9 104.7 100.0 102.5
UGB (MHz) 12.1 11.3 10.9 11.6 11.2 11.4
SR (V/µs) 9.5 8.5 8.4 8.6 8.5 8.6
PM ( ◦) 101.6 80.1 79.6 80.2 79.8 80.3
Iq (µA) 475.1 472.9 479.6 467.2 468.8 477.3
11.44 16.5 16.0 16.8 17.0 16.0
√
No (nV/ Hz)
Iout (mA) 3.4 3.4 3.3 3.6 3.4 3.5
a
The results calculated based on the analytical equations utilized in this study

Table 8  Performance metrics Performance [6] BO EA ADE GXL

TS a FT b Model in [6] c
comparison of class-AB OPA
GAIN (dB) 93.9 92.1 129.2 117.5 104.3 102.5 90.4
UGB (MHz) 10.9 10.3 20.1 10.7 17.7 16.2 9.8
SR (V/µs) 8.4 8.6 13.0 9.9 9.7 8.57 17.1
PM ( ◦) 79.6 85.08 105.8 76.2 90.3 75.6 58.1
Iq (µA) 479.3 506.4 557.8 988.7 847.6 623.9 516
17.0 19.1 10.7 18.7 25.3 17.82 14.9
√
No (nV/ Hz)
Iout (mA) 3.3 3.3 – 5.0 3.5 7.9 4.0
Time (s) 343.6 – – 1.1 3328.2 5541.9 4949.0
a
The simulation results of the temporary solution
b
The simulation results of the temporary solution that has undergone fine-tuning
c
The results calculated based on the analytical equations utilized in [6]
The metrics that do not meet the specs are bold

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 53

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Publisher's Note Springer Nature remains neutral with regard to November 2016. His research
jurisdictional claims in published maps and institutional affiliations. area includes DC-DC converters,
high-precision digital-to-analog
Springer Nature or its licensor (e.g. a society or other partner) holds converters (ADC), high-precision low-noise operational amplifiers,
exclusive rights to this article under a publishing agreement with the high-speed operational amplifiers, analog front-end circuits, power
author(s) or other rightsholder(s); author self-archiving of the accepted management chips, Li-ion battery protection circuits, and optical on-
manuscript version of this article is solely governed by the terms of chip sensor.
such publishing agreement and applicable law.

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Analog Integrated Circuits and Signal Processing (2024) 119:43–55 55

Youyou Fan received the B.S. and Ai Yu received a Ph.D. degree in

Ph.D. degrees in microelectron- Environmental Science. Since
ics from Xi’an Jiaotong Univer- completing her doctoral studies,
sity, Xi’an, China, in 2013 and she has been actively engaged in
2020. He joined the Beijing the field of radiation detection
Microelectronics Technology and measurement. Currently, she
Institute (BMTI), Beijing, China, is working in Beijing New-High
in 2020. He served as a co-cul- Technology Academy. Her
ture postdoc at Peking University research interests include radia-
and BMTI from 2020 to 2023. tion detectors and on-line moni-
His research interests include toring technology.
digital–analog hybrid integrated
circuits design.

Kaikai Wu received his B.S. and Weiwei Wen received a Ph.D.

M.S. degrees in electronic sci- degree in nuclear technology and
ence and technology from applications. Since completing
Chang’an University in 2014 and his doctoral studies, he has been
2017, respectively. Since 2017, actively engaged in the field of
he has been with Chengdu radiation detection and measure-
Zhenxin Technology Co., Ltd, as ment. Currently, he is working in
an analog design engineer. He is Beijing New-High Technology
currently studying for a Ph.D. in Academy. His research interests
electronic science and technol- include radiation detectors and
ogy at Xi’an Jiaotong University. n o n d e s t r u c t i ve d e t e c t i o n
His research areas include Li-ion technology.
battery protection circuits, high-
speed CMOS continuous-time
Sigma-Delta modulators, and
phase-locked loop (PLL) design.
Youpeng Wu received a Ph.D.
Tao Tao received his B.S. and degree in material chemistry.
M.S. degrees in electronic sci- Since completing his doctoral
ence and technology from Xi’an studies, he has been actively
Jiaotong University (Xi’an, engaged in the field of radiation
Shaanxi) in 2010 and 2013, detection and measurement. Cur-
respectively. Since 2013, he has rently, he is working in Beijing
been with the Dalian Institute of New-High Technology Acad-
Chemical Physics, Chinese emy. His research interests
Academy of Sciences. He is cur- include radiation detectors and
rently pursuing his Ph.D. in elec- applications of low-energy X/γ
tronic science and technology at spectrometry.
Xi’an Jiaotong University. His
research areas include Li-ion bat-
tery protection circuits, DC-DC
converter design, and power
management system design.
Yue Zhang received a M.S.
degree in Environmental Sci-
ence. Since completing her mas-
Qingbo Wang received a Ph.D. ter's studies, she has been
degree in nuclear science and actively engaged in the field of
technology. Since completing his radiation detection and measure-
doctoral studies, he has been ment. Currently, she is working
actively engaged in the field of in Beijing New-High Technol-
radiation detection and measure- ogy Academy. Her research
ment. Currently, he is working in interests include radiation detec-
Beijing New-High Technology tors and on-line monitoring
Academy. His research interests technology.
include radiation detectors and
nuclear electronics.

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