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2.5 LogicSim Parallel

The document discusses logic simulation techniques, including compiled code, event-driven, and parallel simulation, highlighting the benefits of parallelism in bit-wise operations. It addresses the complexity of logic simulation, asserting it operates in polynomial time, and introduces improved encoding methods for handling unknown values in ternary logic. The document concludes with insights into the challenges and considerations of logic simulations.

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Krish Shah
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2 views11 pages

2.5 LogicSim Parallel

The document discusses logic simulation techniques, including compiled code, event-driven, and parallel simulation, highlighting the benefits of parallelism in bit-wise operations. It addresses the complexity of logic simulation, asserting it operates in polynomial time, and introduces improved encoding methods for handling unknown values in ternary logic. The document concludes with insights into the challenges and considerations of logic simulations.

Uploaded by

Krish Shah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Logic Simulation

 Introduction
 Simulation Models
 Logic Simulation Techniques
Compiled code simulation
 Event driven simulation
 Parallel Simulation
 Issues of Logic Simulations
 Conclusions

1 VLSI Test 2.5 © National Taiwan University


Parallel Simulation
 Pack W patterns into a single word (W = word size)
Simultaneously evaluate a gate with W patterns
 Exploit parallelism of bit-wise logic operation
 Example: W = 4 (WWW Fig 3.8)
 Consider only binary logic (no u or z)

1 0 0 1 1 0 0 1 1 0 0 0

1 1 1 0
0 1 1 0

0 0 1 0 1 1 1 0 0 0 0 1

2 VLSI Test 2.5 © National Taiwan University


Quiz
Q: what is the speedup of parallel simulation? (W = CPU size)
A. W
B. W2
C. No speedup

1 0 0 1 1 0 0 1 1 0 0 0

1 1 1 0
0 1 1 0

0 0 1 0 1 1 1 0 0 0 0 1

3 VLSI Test 2.5 © National Taiwan University


How about Ternary Logic?
 Simple idea: use 2 bits to represent ternary logic
 Simple encoding method

Logic one=11, Logic zero=00, Unknown =10
 Works fine with OR/AND …. but wrong with inversion
1 1 1 1 1 1 1 1 1 1 1 0

1 1 1 0
0 0 0 0

0 0 1 0 1 1 1 0
wrong!
0 0 0 1

 Can we use both 10 and 01 as u? No


4 VLSI Test 2.5 © National Taiwan University
Sol: Improved Encoding Method
 Two words to encode single A: A1, A0
A1=1 means logic one. A0=1 means logic zero.
 A1=0 A0=0 means unknown.
 Example W=4, four patterns
 C = {0, 0, u, 1}
 C1 = (0, 0, 0, 1)
 C0 = (1, 1, 0, 0)

B1 0 1 0 1

B0 1 0 1 0

C1 0 0 0 1 0 1 0 1

C0 1 1 0 0 1 0 0 0
5 VLSI Test 2.5 © National Taiwan University
Parallel Gate Evaluation
a
c Gate Bitwise Operations
b c1 = a1․b1
AND
c0 = a0 + b0
c1 = a0 + b0
NAND
c0 = a1․b1
c1 = a1 + b1
OR
c0 = a0․b0
c1 = a0․b0
NOR
c0 = a1 + b1
‧= bitwise AND c1 = a0
INV
+ = bitwise OR c0 = a1

Quiz: what are equations for XOR?


A:

6 VLSI Test 2.5 © National Taiwan University


Example
 Apply four patterns
 A={1,1,1,0 }; B={0,1,0,1 }; C={0,0,u,1 }
 K={0,0,u,1 }

A1 1 1 1 0 0 1 0 0

A0 0 0 0 1 1 0 0 1
0 0 0 1

1 1 0 0
B1 0 1 0 1

B0 1 0 1 0

C1 0 0 0 1 0 1 0 1 1 0 0 0

C0 1 1 0 0 1 0 0 0 0 1 0 1

7 VLSI Test 2.5 © National Taiwan University


What is Complexity of LogicSim?
 Suppose P patterns, G gates
 Compiled-code, parallel simulation = (PxG)
 Event-driven simulation = (PxE)
 E: number of events in each pattern
 Assume E = O(G)
 O(PxG)

 Logic simulation is polynomial time complexity

Logic Simulation is Polynomial Time


8 VLSI Test 2.5 © National Taiwan University
Summary
 Introduction
 Simulation Models
 Logic Simulation Techniques
Compiled code simulation
 Event driven simulation
 Parallel Simulation
 Exploits bitwise operation to gain linear speed up
 Improved encoding for unknowns
 Logic simulation is polynomial time
 Issues of Logic Simulations
 Conclusions

9 VLSI Test 2.5 © National Taiwan University


Parallel Version of Compiled-code/Event-driven

1001 1001 1000

1110
0110

0010 1110 0001

while{true} do
read(A,B,C);
E OR(B,C);
H AND(A,E);
J NOT(E);
K NOR(H,J);
end
compiled-code one-pass event-driven
(zero-delay)
10 VLSI Test 2.5 © National Taiwan University
FFT
 Q1: Can we swap bit pairs after inverter?
 Q2: If we can, what are advantages/disadvantages of 1-word
encoding method compared with the 2-word encoding method ?

1 1 1 1 1 1 1 1 1 1 1 0

1 1 1 0
0 0 0 1

0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0

0 0 1 0

11 VLSI Test 2.5 © National Taiwan University

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