/* Prog10_Pixel RGB:

Neste projeto elaboraremos o software necessário para acionar um led RGB. Ele contém 3
emissores de luz: vermelho (red), verde (green) e azul (blue).

A combinação das três cores, em intensidades variadas, permite criar todas as cores do
espectro visível.

Adotaremos a técnica de PWM para variar a intensidade luminosa de cada cor. Para tal
utilizaremos o Timer_A e as 3 saídas dos seus blocos de comparação TA0, TA1 e TA2.
Esta situação nos levará trará limitações na seleção dos de contagem e de saída o Ti‐
mer_A, mas é factível.

Seremos obrigados a utilizar o modo de contagem contínuo (MC=2) e o modo de saída Set
(OUTMOD = 1).

A intenção é utilizar uma configuração mínima de hardware. O próprio oscilador interno

cadenciará o contador do Timer_A. Neste sentido, será necessário aumentar a frequência
de clock da CPU para o valor máximo.

Para padronizar os programas, adotaremos as seguintes conexões de saída dos blocos CCR
e os leds:
RED = TA0 = P1.1
GREEN = TA1 = P1.2
BLUE = TA2 = P1.3

Prog10_a: CLOCK
Etapa inicial na qual vamos geral um programa simples que apenas configura o clock da
CPU para o seu valor máximo.
A verificação do resultado pode ser feita configurando o pino P1.4 como função espe‐
cial e saída. Neste caso e exteriorizará o sinal do SMCLK.

Prog10_b: Timer_A
Tomando por base a versão Prog10_a, vamos adicionar configuração do Timer_A:
‐ Bloco contador: o modo de contagem MC = 2; TAIF gerando interrupção ao final da
contagem.
‐ Para cada um dos blocos CCR0, 1 e 2: o modo de saída sendo OUTMOD = 1.
‐ A RTI gerada pelo TAIFG deve se encarregar de zerar as saídas TAO, 1 e 2. Isto pode
ser feito alterado o modo de saída para OUTMOD = 0 e depois retornando para OUTMOD =
1.
O teste de funcionamento pode ser feito atribuindo valores fixos para TACCR0, 1 e 2.

*/
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − OCTOBER 2002 − REVISED MARCH 2011

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK 20 I/O General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
P2.6/ADC12CLK/ 26 I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger
DMAE0
P2.7/TA0 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0 28 I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
P3.1/SIMO0/SDA 29 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I2C data − USART0/I2C mode
P3.2/SOMI0 30 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0/SCL 31 I/O General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output –
USART0/SPI mode, I2C clock − USART0/I2C mode
P3.4/UTXD0 32 I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode
P3.5/URXD0 33 I/O General-purpose digital I/O pin/receive data in – USART0/UART mode
P3.6/UTXD1† 34 I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode
P3.7/URXD1† 35 I/O General-purpose digital I/O pin/receive data in – USART1/UART mode
P4.0/TB0 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3† 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4† 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5† 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6† 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/STE1† 44 I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode
P5.1/SIMO1† 45 I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
P5.2/SOMI1† 46 I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
P5.3/UCLK1† 47 I/O General-purpose digital I/O pin/external clock input – USART1/UART or SPI mode, clock output –
USART1/SPI mode
† 16x, 161x devices only

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − OCTOBER 2002 − REVISED MARCH 2011

USART0
The MSP430F15x and the MSP430F16x(x) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered
transmit and receive channels.
The I2C support is compliant with the Philips I2C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported,
as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two
dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C
mode.
USART1 (MSP430F16x/161x only)
The MSP430F16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels. With the exception of I2C support, operation of USART1 is identical to USART0.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN
MODULE BLOCK
NUMBER SIGNAL NAME SIGNAL NUMBER
12 - P1.0 TACLK TACLK
ACLK ACLK
Timer NA
SMCLK SMCLK
21 - P2.1 TAINCLK INCLK
13 - P1.1 TA0 CCI0A 13 - P1.1
22 - P2.2 TA0 CCI0B 17 - P1.5
CCR0 TA0
DVSS GND 27 - P2.7
DVCC VCC
14 - P1.2 TA1 CCI1A 14 - P1.2
CAOUT (internal) CCI1B 18 - P1.6
CCR1 TA1
DVSS GND 23 - P2.3
DVCC VCC ADC12 (internal)
15 - P1.3 TA2 CCI2A 15 - P1.3
ACLK (internal) CCI2B 19 - P1.7
CCR2 TA2
DVSS GND 24 - P2.4
DVCC VCC

Timer_B3 (MSP430F15x only)

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 Basic Clock Module Introduction

Figure 4−1. Basic Clock Block Diagram

DIVAx

LFXT1CLK Divider
/1/2/4/8
XTS ACLK
OSCOFF
Auxillary Clock
0V
XIN
12pF
LF XT
LFOff XT1Off
12pF
XOUT 0V
SELMx
LFXT1 Oscillator DIVMx
CPUOFF
00
01 Divider
XT2CLK 0
10 /1/2/4/8
1
11 MCLK
XT2OFF
XT2IN Main System Clock

XT

XT2OUT XT2 Oscillator

MODx

VCC
Modulator
DCOR SCG0 RSELx DCOx
SELS DIVSx
SCG1
off n
0 DC 0 DCOCLK
DCO 0 Divider
1 Generator 1 0
n+1 /1/2/4/8
1
P2.5/Rosc 1
SMCLK

Sub System Clock

Note: XT2 Oscillator

The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx
devices. The LFXT1CLK is used in place of XT2CLK.

Basic Clock Module 4-3

 MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − OCTOBER 2002 − REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
DCO (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 0.08 0.12 0.15
f(DCO03) Rsel = 0
0, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 0.08 0.13 0.16
2.2 V 0.14 0.19 0.23
f(DCO13) Rsel = 1
1, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 0.14 0.18 0.22
2.2 V 0.22 0.30 0.36
f(DCO23) Rsel = 2
2, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 0.22 0.28 0.34
2.2 V 0.37 0.49 0.59
f(DCO33) Rsel = 3
3, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 0.37 0.47 0.56
2.2 V 0.61 0.77 0.93
f(DCO43) Rsel = 4
4, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 0.61 0.75 0.90
2.2 V 1 1.2 1.5
f(DCO53) Rsel = 5
5, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 1 1.3 1.5
2.2 V 1.6 1.9 2.2
f(DCO63) Rsel = 6
6, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 1.69 2.0 2.29
2.2 V 2.4 2.9 3.4
f(DCO73) Rsel = 7
7, DCO = 3
3, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 2.7 3.2 3.65
fDCO40 fDCO40 fDCO40
f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 2.2 V/3 V MHz
× 1.7 × 2.1 × 2.5
2.2 V 4 4.5 4.9
f(DCO77) Rsel = 7
7, DCO = 7
7, MOD = 0
0, DCOR = 0
0, TA = 25°C MHz
3V 4.4 4.9 5.4
SRsel SR = fRsel+1 / fRsel 2.2 V/3 V 1.35 1.65 2
SDCO SDCO = f(DCO+1) / f(DCO) 2.2 V/3 V 1.07 1.12 1.16
2.2 V −0.31 −0.36 −0.40
Dt Temperature drift,
drift Rsel = 4
4, DCO = 3
3, MOD = 0 (see Note 2) %/°C
3V −0.33 −0.38 −0.43
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
DV 2.2 V/3 V 0 5 10 %/V
(see Note 2)
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System).
2. This parameter is not production tested.

ÎÎÎÎÎÎÎ
1
f DCOCLK

ÎÎÎÎÎÎÎ
Max
f DCO_7
Frequency Variance

Min

f DCO_0
Max

Min
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
0 1 2 3 4 5 6 7 DCO
2.2 3 VCC − V

Figure 15. DCO Characteristics

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

 Basic Clock Module Registers

DCOCTL, DCO Control Register

7 6 5 4 3 2 1 0

DCOx MODx

rw−0 rw−1 rw−1 rw−0 rw−0 rw−0 rw−0 rw−0

DCOx Bits DCO frequency select. These bits select which of the eight discrete DCO
7-5 frequencies of the RSELx setting is selected.
MODx Bits Modulator selection. These bits define how often the fDCO+1 frequency is
4-0 used within a period of 32 DCOCLK cycles. During the remaining clock
cycles (32−MOD) the fDCO frequency is used. Not useable when DCOx=7.

BCSCTL1, Basic Clock System Control Register 1

7 6 5 4 3 2 1 0

XT2OFF XTS DIVAx XT5V RSELx

rw−(1) rw−(0) rw−(0) rw−(0) rw−0 rw−1 rw−0 rw−0

XT2OFF Bit 7 XT2 off. This bit turns off the XT2 oscillator
0 XT2 is on
1 XT2 is off if it is not used for MCLK or SMCLK.
XTS Bit 6 LFXT1 mode select.
0 Low frequency mode
1 High frequency mode
DIVAx Bits Divider for ACLK
5-4 00 /1
01 /2
10 /4
11 /8
XT5V Bit 3 Unused. XT5V should always be reset.
RSELx Bits Resistor Select. The internal resistor is selected in eight different steps.
2-0 The value of the resistor defines the nominal frequency. The lowest
nominal frequency is selected by setting RSELx=0.

Basic Clock Module 4-15

Basic Clock Module Registers

BCSCTL2, Basic Clock System Control Register 2

7 6 5 4 3 2 1 0

SELMx DIVMx SELS DIVSx DCOR

rw−(0) rw−(0) rw−(0) rw−(0) rw−0 rw−0 rw−0 rw−0

SELMx Bits Select MCLK. These bits select the MCLK source.
7-6 00 DCOCLK
01 DCOCLK
10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2
oscillator not present on-chip.
11 LFXT1CLK
DIVMx BitS Divider for MCLK
5-4 00 /1
01 /2
10 /4
11 /8
SELS Bit 3 Select SMCLK. This bit selects the SMCLK source.
0 DCOCLK
1 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2
oscillator not present on-chip.
DIVSx BitS Divider for SMCLK
2-1 00 /1
01 /2
10 /4
11 /8
DCOR Bit 0 DCO resistor select
0 Internal resistor
1 External resistor

4-16 Basic Clock Module

 Basic Clock Module Registers

IE1, Interrupt Enable Register 1

7 6 5 4 3 2 1 0

OFIE

rw−0

Bits These bits may be used by other modules. See device-specific datasheet.
7-2
OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.
Because other bits in IE1 may be used for other modules, it is recommended
to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B
or CLR.B instructions.
0 Interrupt not enabled
1 Interrupt enabled

Bits 0 This bit may be used by other modules. See device-specific datasheet.

IFG1, Interrupt Flag Register 1

7 6 5 4 3 2 1 0

OFIFG

rw−1

Bits These bits may be used by other modules. See device-specific datasheet.
7-2
OFIFG Bit 1 Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other
modules, it is recommended to set or clear this bit using BIS.B or BIC.B
instructions, rather than MOV.B or CLR.B instructions.
0 No interrupt pending
1 Interrupt pending
Bits 0 This bit may be used by other modules. See device-specific datasheet.

Basic Clock Module 4-17

 Timer_A Introduction

Figure 11−1. Timer_A Block Diagram

Timer Clock Timer Block

TASSELx IDx MCx
15 0

TACLK 00 16−bit Timer

Divider Count
TAR EQU0
ACLK 01 1/2/4/8 Mode
Clear RC
SMCLK 10
INCLK 11 Set TAIFG
TACLR
CCR0
CCR1
CCR2

CCISx CMx logic COV

SCS
CCI2A 00 Capture
Mode 15 0
CCI2B 01
0
GND 10 TACCR2
Timer Clock Sync 1
VCC 11

Comparator 2
CCI
EQU2
CAP

A
SCCI Y
EN 0
Set TACCR2
1 CCIFG

OUT
Output
Unit2 D Set Q OUT2 Signal
EQU0
Timer Clock
Reset

POR
OUTMODx

Timer_A 11-3
 Timer_A Operation

Continuous Mode
In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts
from zero as shown in Figure 11−4. The capture/compare register TACCR0
works the same way as the other capture/compare registers.

Figure 11−4. Continuous Mode

0FFFFh

0h

The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.
Figure 11−5 shows the flag set cycle.

Figure 11−5. Continuous Mode Flag Setting

Timer Clock

Timer FFFEh FFFFh 0h 1h FFFEh FFFFh 0h

Set TAIFG

Timer_A 11-7
 Timer_A Operation

11.2.5 Output Unit

Each capture/compare block contains an output unit. The output unit is used
to generate output signals such as PWM signals. Each output unit has eight
operating modes that generate signals based on the EQU0 and EQUx signals.

Output Modes
The output modes are defined by the OUTMODx bits and are described in
Table 11−2. The OUTx signal is changed with the rising edge of the timer clock
for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for
output unit 0 because EQUx = EQU0.

Table 11−2. Output Modes

OUTMODx Mode Description

000 Output The output signal OUTx is defined by the
OUTx bit. The OUTx signal updates
immediately when OUTx is updated.
001 Set The output is set when the timer counts
to the TACCRx value. It remains set until
a reset of the timer, or until another
output mode is selected and affects the
output.
010 Toggle/Reset The output is toggled when the timer
counts to the TACCRx value. It is reset
when the timer counts to the TACCR0
value.
011 Set/Reset The output is set when the timer counts
to the TACCRx value. It is reset when the
timer counts to the TACCR0 value.
100 Toggle The output is toggled when the timer
counts to the TACCRx value. The output
period is double the timer period.
101 Reset The output is reset when the timer counts
to the TACCRx value. It remains reset
until another output mode is selected and
affects the output.
110 Toggle/Set The output is toggled when the timer
counts to the TACCRx value. It is set
when the timer counts to the TACCR0
value.
111 Reset/Set The output is reset when the timer counts
to the TACCRx value. It is set when the
timer counts to the TACCR0 value.

Timer_A 11-13
 Timer_A Operation

Output Example—Timer in Continuous Mode

The OUTx signal is changed when the timer reaches the TACCRx and
TACCR0 values, depending on the output mode. An example is shown in
Figure 11−13 using TACCR0 and TACCR1.

Figure 11−13.Output Example—Timer in Continuous Mode

0FFFFh

TACCR0
Quando o TAR retornar a zero,
TACCR1
uma INT será gerada. Forçar as
saídas TA0, TA1 e TA2 para nível
0h
zero dentro da RTI.
Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events

Timer_A 11-15