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Lab 4 - VDP

This document outlines the instructions for Lab Work 4 on CMOS Analog Circuits, requiring a group report submission in IEEE format with specific sections on task contributions, schematics, and post-laboratory questions. It details the tasks for building NMOS and PMOS transistors with guard rings and conducting design rule checks using Electric VLSI. Additionally, it includes a section on common centroid layout for PMOS differential pairs and poses questions regarding the benefits of guard rings, dummy devices, and common-centroid layouts.

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Glenn Virrey
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12 views4 pages

Lab 4 - VDP

This document outlines the instructions for Lab Work 4 on CMOS Analog Circuits, requiring a group report submission in IEEE format with specific sections on task contributions, schematics, and post-laboratory questions. It details the tasks for building NMOS and PMOS transistors with guard rings and conducting design rule checks using Electric VLSI. Additionally, it includes a section on common centroid layout for PMOS differential pairs and poses questions regarding the benefits of guard rings, dummy devices, and common-centroid layouts.

Uploaded by

Glenn Virrey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB WORK 4

Layout of CMOS Analog Circuits (Part 2)


Prepared by:
Engr. Angelito A. Silverio, Ph.D.
Directions:

1. Submit a softcopy of your group report in IEEE conference paper format into the Laboratory
Work 4 Submission bin in Blackboard.
2. Submit this group report individually.
3. Include a section on your report mentioning the task partitions/ contributions by each group
member.
4. Include in your report snapshots of the schematics as well as the relevant plots which are
asked in each procedure.
5. Provide a section in the report which answers the post-laboratory questions.
6. Do not forget to include references whenever you cited some relevant literature.

Grading:
SO5.4 – Task Partitions (10pts)
SO6.1 – Data Completeness (10pts)
SO6.2 – Discussion of Results (10pts)
SO6.3 - Conclusion and Post-Lab Questions (10pts)
For sensitive circuits, and to avoid latch up, implement your bulk connection using a guard ring.
Part 1. The Guard Ring and the use of Dummy Transistors

1. Using Electric VLSI, build the schematic and layout of an NMOS and PMOS transistor with
an aspect ratio of 5u/5u m=4 and 10u/5u m=4, respectively. Implement the respective
bulks of the NMOS and PMOS transistors using guard rings. Provide labels. Show a
snapshot of both the schematic and layout views.
2. Ensure that there are no layout Design Rule violations by running the DRC. Show a
snapshot of the Electric Messages Tab upon running the DRC.
3. Ensure that the layout and schematic are the same by running the Network Compliance
Check (NCC). Show a snapshot of the Electric Messages Tab upon running the DRC.

Part 2. Common Centroid Layout


1. Using Electric VLSI, build the schematic and layout of a PMOS differential pair with both
having an aspect ratio of 5u/5u m=8. Implement using interdigitation pattern, common-
centroid layout and guard ring. Show a snapshot of both the schematic and layout views.
Do not forget to put labels onto the layouts. Consider the following differential pair
circuit.

2. Ensure that there are no layout Design Rule violations by running the DRC. Show a
snapshot of the Electric Messages Tab upon running the DRC.
3. Ensure that the layout and schematic are the same by running the Network Compliance
Check (NCC). Show a snapshot of the Electric Messages Tab upon running the DRC.

Post Lab Questions


1. What is the benefit of using guard rings for sensitive transistor circuits?
2. What is the benefit of using dummy devices (e.g. dummy MOS)?
3. What is the benefit of using common-centroid layout?

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