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Lec 3

The document discusses control hazards in pipelined processors, particularly in the MIPS architecture, where branch outcomes affect instruction fetching. It covers techniques such as stalling, branch prediction, and forwarding to mitigate these hazards and improve performance. Additionally, it outlines the importance of pipeline registers and control signals in managing instruction flow and resolving data hazards.

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Abdalrhman Mohamed
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7 views30 pages

Lec 3

The document discusses control hazards in pipelined processors, particularly in the MIPS architecture, where branch outcomes affect instruction fetching. It covers techniques such as stalling, branch prediction, and forwarding to mitigate these hazards and improve performance. Additionally, it outlines the importance of pipeline registers and control signals in managing instruction flow and resolving data hazards.

Uploaded by

Abdalrhman Mohamed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Control hazard

Control Hazards
• Branch determines flow of control
– Fetching next instruction depends on branch
outcome
– Pipeline can’t always fetch correct instruction
• Still working on ID stage of branch
• In MIPS pipeline
– Need to compare registers and compute target
early in the pipeline
– Add hardware to do it in ID stage

Chapter 4 — The Processor


—2
Stall on Branch
• Wait until branch outcome determined before
fetching next instruction Before adding hardware to ID
beq IF--ID--EX--MEM--WB
stall
stall
or IF--ID--EX--MEM--WB

after adding hardware to ID

Chapter 4 — The Processor


—3
Branch Prediction
• Longer pipelines can’t readily determine
branch outcome early
– Stall penalty becomes unacceptable
• Predict outcome of branch
– Only stall if prediction is wrong
• In MIPS pipeline
– Can predict branches not taken
– Fetch instruction after branch, with no delay

Chapter 4 — The Processor


—4
MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

Chapter 4 — The Processor


—5
More-Realistic Branch Prediction
• Static branch prediction
– Based on typical branch behavior
– Example: loop and if-statement branches
• Predict backward branches taken
• Predict forward branches not taken
• Dynamic branch prediction
– Hardware measures actual branch behavior
• e.g., record recent history of each branch
– Assume future behavior will continue the trend
• When wrong, stall while re-fetching, and update history

Chapter 4 — The Processor


—6
Pipeline Summary
The BIG Picture

• Pipelining improves performance by increasing


instruction throughput
– Executes multiple instructions in parallel
– Each instruction has the same latency
• Subject to hazards
– Structure, data, control
• Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor
—7
MIPS Pipelined Datapath

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor


—8
Pipeline registers
• Need registers between stages
– To hold information produced in previous cycle

Chapter 4 — The Processor


—9
Pipeline Operation
• Cycle-by-cycle flow of instructions through the
pipelined datapath
– “Single-clock-cycle” pipeline diagram
• Shows pipeline usage in a single cycle
• Highlight resources used
– c.f. “multi-clock-cycle” diagram
• Graph of operation over time
• We’ll look at “single-clock-cycle” diagrams for
load & store
Chapter 4 — The Processor
— 10
IF for Load, Store, …

Chapter 4 — The Processor


— 11
ID for Load, Store, …

Chapter 4 — The Processor


— 12
EX for Load

Chapter 4 — The Processor


— 13
MEM for Load

Chapter 4 — The Processor


— 14
WB for Load

Wrong
register
number

Chapter 4 — The Processor


— 15
Corrected Datapath for Load

Chapter 4 — The Processor


— 16
EX for Store

Chapter 4 — The Processor


— 17
MEM for Store

Chapter 4 — The Processor


— 18
WB for Store

Chapter 4 — The Processor


— 19
Multi-Cycle Pipeline Diagram
• Form showing resource usage

there is a typo,
so swap them

Chapter 4 — The Processor


— 20
Multi-Cycle Pipeline Diagram
• Traditional form

Chapter 4 — The Processor


— 21
Single-Cycle Pipeline Diagram
• State of pipeline in a given cycle

Chapter 4 — The Processor


— 22
Pipelined Control (Simplified)

Chapter 4 — The Processor


— 23
Pipelined Control
• Control signals derived from instruction

Chapter 4 — The Processor


— 24
Pipelined Control

Important note:
see the control signals well

Chapter 4 — The Processor


— 25
§4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions

• Consider this sequence:


sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)
• We can resolve hazards with forwarding
– How do we detect when to forward?

Chapter 4 — The Processor


— 26
Dependencies & Forwarding

Chapter 4 — The Processor


— 27
Detecting the Need to Forward
• Pass register numbers along pipeline
– e.g., ID/EX.RegisterRs = register number for Rs sitting in
ID/EX pipeline register
• ALU operand register numbers in EX stage are
given by
– ID/EX.RegisterRs, ID/EX.RegisterRt
• Data hazards when
Fwd from
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt pipeline reg
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs Fwd from
MEM/WB
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
pipeline reg

Chapter 4 — The Processor


— 28
Detecting the Need to Forward
• But only if forwarding instruction will write to
a register!
– EX/MEM.RegWrite, MEM/WB.RegWrite
• And only if Rd for that instruction is not $zero
– EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0

So we do forwarding only if forwarding instruction will write to


a register

Chapter 4 — The Processor


— 29
Forwarding Paths

Chapter 4 — The Processor


— 30

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