Unit 4

A computer Architecture
structure and behaviour of the computer
3 aspects 1 Computer hardware circuits displays storage etc
2 Instruction set registers memory instruction set etc
3 computer organization design
of internal CPU
bus structure memory sys
2 approaches 1 ISC complex instruction set comp
2 RISC reduced instruction set comp

Functional Units
5 June units
of a comp
hfffory
4 output
s control units

Itt Iliffe an

output Network control

units

operation The comp accepts programs from an

input unit
and stores it in the
memory
stored in is fetched to the A L V
InfoC Us
and when
memory
it is processed
Processed leaves the comp through an output
info
unit All activities in the comp are directedby the c out
 An instruction consists to 2 parts
1 OPCODE OPERATION CODES
2 OPERANDS

The data operants is stored in the

memory
The individual instruction is brought from the memory
to the processor
Then processor performs the specific operation
A Typical instruction
ADD LOCA RO
It is addition operation
an
To execute this instruction
step1 Fetch the instruction from main memory to processor
step2 Fetch the operand at locationLOCAfrom main memory into the
processor
step3 add memory operandto the contents of register Ro
step4 store the result Sum in Ro register
LOAD R2 LOL

step1 same as above

step 2 operation to be performed is determined
the control unit by
step3 operant atis COC is fetched2 on
step4 operand stored in aug
steps arithmatic logic operations can be performed
ADD RH R2 R3

adds contents of ores 2 and 3

Essence REM ionisation by the sum

They can be transferred to memory using

STORE R 4 LOC
copies operand in R4 to memory location LOC
contents LOC are overwritten
original
those in R4 are
of
preserved
 list steps to Load R2 LOC in terms b w
oftransfers
the processor and control unit assume that the addressof hm location
containing this instruction is initially in register P C
Transfor contentsof of orgPC toMAR
Issue a command to the memory until MDRis loaded
read
Transfer the instruction from MDR to IR
instruction org to decode it
Transfer the address LOCA from IR to MAR
issue read command until MDR is loaded
Transfer all contents of MDR to ALU
Transfer contents of Ro to the A L U
perform addition of the 2 operants in A L U
transfer result to Ro
Transfer contentsin of PC to ACU
add 1 to operand ALU transfer incremented addresstop

Mm Add RH R2 R3 in towns
of
transfers b w
components
ofprocessor Me PC

ÉFÉFnsfa
the contentsof R1 R2 to ALU
perform add in me

IF PTO

Main Parts of Processor Basic Operational

concepts
ALU
general purpose registers from Ro Rn
IR holds the instruction
into org to be executed
Control unit generatessignals op to be performed
PC program counter mem add
of next instruction to be em
MAR mem access reg holds add
of location tobeaccessed
MDR mem data reg datato be written into readinto 9 location
MAR MD R facilitates communication with the memory
General steps to execute an instruction to
all
address of 1st instruction is loaded to PC questions
Contents ofPC is transferred to MAR
control unit issues a read signal
1st instruction is placed into MDR
contents of MDR is transferred to IR to be
decoded and executed
To fetch an operand it's address is placed in MAR
controlunit issues read signal
operand is transferred to MDR
and then it is in
from MDR to ALU
ALU performs the specific I Zoration
result is stored
contents PC is incremented to point to the next
of
instruction in the program

Connection b w main
processor memory

main memory

Mosso meminterface

12
Er

sea 1

Processor
 Performance
of a process

1 How fast the instructions can be executed

2 Bestperformance at lowest cost
3 How quickly machine instructions are brought into the processor
4 Design
of hardware of processon influences its performance
WCSI very large scale integration technology is crucial as
it fabricates electronic circuits on a single chip
Everyyearthe size of transistors are madesmaller and shows
better computation The speed switching b w the states 0 and 1 in
circuits is largely determined ofthe size transistors smaller transistors
by of
switchfaster Moretransistorscan beplacedon a chip Instructions canbe executedfaster
More
memory capacity
5 The 0 s and the application software impacts the processor's performance
6 A compilertranslates H L L into maeline level language A proficient
compiller can generate
efficient machinecode enhancing the
Execution speed

Parallism
The performance can also be increased performing many operations in
by 1Mel
i e parallelism Parallelism can be implemented on many difflevels
Instruction level Parallelism
Multicore Processors

Multiprocessorscomputersystem

aka pipelining multiple processingunits are in

tegeratedinto one chip
fyhzffffggdpfhhfftqgfffffpfgfae e each unit is termed as a ere
The complete chipis termedas
execution time Traditional a processor
mentioning
new gouramyle dual core 2

msn.fi iii iiiiiiaii

operation isunderway the next instant 9d.IE f
can be fetchedfrom the loses on a singerchip share
memory
It keeps variousparts of theprocessor resources like cache memory elf
busy with diff instructions simultaneously Offeringimproved performance
multitaskingcapabilities
 multiprocessors
Systems thathave more than one processor
systemswith multiprocessors each containing multiple cores akamultiprocessors
These systems execute numerous applicationtasks inparallel or
perform subtasks of a single largetaskconcurrently
shared memory b w all processors data sharing goodcommunication
enhanced scalibility
efficient utilization of resources f
Basic Performance eqn
T N 5 R no Ofclockcyclespersecond clockerate
no basic stepsneededtoexecute one machineinstant
of
no of machinelong instructions
processortime
reqto execute a program that is in
high level language

Questions
A program contains 100 of that 501 instructions req 4
instructions out
clockcycles and remaining aug 3 clockcycles for execution Find the total
time req to execute the program running on a 1 MHzmachine
501of instructions need 4 clockcycles 50 4 2004
501of instructionsneed3 dockcycles
3 a you

4a men s I 1558Itoseconds
A perg contains 1000 instructions 251 aug 4 In cycles 401
instruction req 5 In cycles and remaining req 3 Clk cyclesto
execution find the total time meg to execute the pegrunning
on a 1 GHz machine
25 94 250 4 10004

44 of 5
0
400 5 20004
4 I fifhd ff.fm

351.93 150 3

q_
Computer Performance
using Bench mark Programs
Computer performenace does not just dependon the N S T asseen
previously
Benchmark Standard Program used to measure the performance
a computer
of
Performance measure isthe timeit takes to executethe bending
program
non profitorganization EC sysperformance evaluationcompany
SPEC

t s.int
uses benchmark programs to check the comp performance
and to represent various domains rangingfromgaming
computing

test results
its.im i
for diff commercially available computers
a

j.FIpagsoun
3The running time is measuredfor each prg
on the ref comp
SPEC is then calculated by running time on refcomp SPEC
running time on testcomp orating
For ed for
sec of compis Y f wfE
h

process
rating is 50 that means that the comp under
If 4
mes as fast as the
ref comp

Instruction set Architecture

4 aspects Memoryorganization
Byte addressability
Endianness
Wordalignment

Memory organization

Instructions data are storedin the memory in binaryform

memory is organized into groups of n'bits called words
word lengthsbeing 16,32 64,128bits n word length
E 32 bit wordlengthconnpcanstore a 32 bit no in asinglewordAsciicharacter
 Es E
1stword
2ndword tfff.it Asignedinteger

iii iiiiii
man

Temaywords lastword

Byterdressabilty
memory is made of 1 Bit memory cells organizedintobytes words
uniqueaddress is req to access thebyte 8bits
each memorylocation representing 1byte has givenone unique address
This is known as byteaddressability
addresses range from 0 to n 1 n total no mem locations bytes
of
based on address lines providedby the processor
address lines
If M no
of
2M tot no of addlines perorbyprocessor
2 1 kilobytes
220 1 Megabyte
23 1 Gigan
240 1 Tera
ÉÉm
Indianness

Itdetermines the bytes within a word in memory

There are 2 ways

f thatched
adddshf
Ñft Iffff
f
af y s
htdgff
bytfhaffffrdff.ee
Word alignment
wordsaresaidtobealigned in memory
iftheystart at addressesthatisamultipleofthe noOf
8s In a bitsys natural word boundaries occur at addresses0 4,8ets
alignedmemoryfess improves performance for operations
efficiency
 Memory Operations
RAM has 2 operations Read reads data stored at location
White writes data
Machine Lang perg 2 operations store write operation
load read operations

TTanstersacopyfthontentsf v
Transfers an itemofinfofrom

TmtRdÑh n thdthdm.deotoaspeciticme
www
the IAdTestroys
contents

Assembly language Notation

Types of instructions supported by the processor
Zero address instruction
One address instruction
Two address instruction
Three address instruction.fr

Zero
addest
These instructions tjᵗYany operands
dont spec
They operate directly on
goals stored in registers or mem

Fp pops a wae fromthe top of a stack

HALT stops the processor
PUSH pushes a nal to the stack

QQ.hs.im
aftomi Operationdestination
These have one operand explicitly specified
The operation is performed b w the smiend
location A'tothe andgaffhfh.dk
t
add contents contents
of mem ofreg
d copies contents men location intotheaccumulator
of
ftp.sinafesfoam Operation source destination
Thesehave 2 operands explicitly specified
 performs B A B Sum is storedin'B
HEFFETTI performs e Cos contentsof B'is unchanged
a

Qfsfm.to
dts operation source 1 some 2 destination
3 operands are
explicitly specified
They perform an operation b w the first 2 operandsEestoresthe result in
the 3rd operand
be Addff addsA GB result is sent to loc c

Questions
What is register transfer notation explainthe assemblylongnotations
symbolic2
RTN is a language used to describe the transfer
of data b w
registers in a digital computer
The contents of location are denoted byplacing
square brackets around the name of the location
R3
of reap
What are the 4 types of operations performedby comp
instructions
whts
Efffff ththffffly.mg
If transfers
hffffffmkms
24 2x 6
y Write an ALP code to implement this

Faddress
using X Y and no easiest method

his 3 5 4 S.ie
MUL X X X X2 X2 24 X x containe 24
ADD X Y Y 4 22 7
ADD 6 Y Y 24 Zat Y

usingzaddressinstfi MY goingtodisturbcontents
tyz f www.go ofx
MOL X X 4 Cahasse4
MUL Z Y 2 2x Y Ycontains k 2 n 2n storein Y

1B EE xp
using one address instm we use an accumulator
initially accumulator is empty
KIMOV X X Accumulator a is moved to accumulator

In I is E
IE
STOREY
iEEi Eau
Acc Y whatever is there in the ace is storedin4

Condition Codes
while performing any operation in the processor arithmetic
4tags flip flops are set
ofinto that representtheoutcome
tmall.IT
of ffhfhffhd
certain operations peerformedb porocess

es
2
or tags
zero
AT if
NCregetine tag setto 1 if resultie
1 result
0 or 0
ne or set too

V overflow flag 1 ifarithmatic overflow or feng o

C carry flag 1 carry out results orgacy
if of

Addressing Modes linkedlistsagainanenes

programmers use various datasutions to updateusing in computations
The diffways in which location of an operand is specified in an instant
are referred to as addressing modes
Fffmmediate
addressin
distantaddressing
in direct add
add
Register Reginaired

Indexed add
relative add
Auto increment
Auto decrement w r
 Immedidende ADD S X

operandis specifiedin the instant itself

bused
smiI.fm
effectiveaddress no address so the operand value
MOU s copies 3 into accumulator
acc
sp
Direct mode absolutemode LMOVX

instant includes address as an operand

effective address address of the mem location
Syntax LOC
MOVS 5 is the memorylocationinstantreadsdatafrom mem location 5
If the toe has the value to's 10 is storedin acy

Register mode
reg address
instant includes as an operandi e instantgets
data from that reg
effective address address of register
Syntax Ri
ble MOVR1 Ro more contents of myRy to Rego

FLESHINESS memaddress as an operand But the address

specified in the instant is not the add of the operand It is
the add of a memorylocation that containsthe addof theoperand
Syntax LOC
effective address contents of LOC Look pophand
WEADDCAD Ro contains B then contentsfrom'B is fetched
IfandA added to RO
I
Fly
Register indirectmode
instantincludes reg add as an operand But the add specified
is not the add of the operand It is the add of a rig that contains
the add of the operand
Syntax Ri
WEADDCRD.RO RD B operand

Indenteddisplacement mode
instant includes 2 vials addressA indenregister asoperand
variants ofindex mode Inden mode Syntax CRIS
Base index Syntax Ri Rj
Base with index andoffset Syntax X Ri RI
allative mode Syntax PCT
effectiveaddress contents
of indenregister Ri
Eg ADD 20CRT R2

effective add sum of Zags rid Rj

reg Tseng
Tinder
Gf MOV RO RD Rz
contents
of Ro Re are movedto R2

offer add sum of contentsof 2 regs and a constantlopset

Af Mor Ro RI R2
contents Roth R2
of
effee add sum of offset ual contents
ofPe next instm address
Of JMP 100 jumpto mem add 100already currentinstin

Auto increment mode

Cffec add contents in the inston
of a only specifiedthe
afteraccessing the operand contents of are
org automating
incremented to valuenext
Syntax Ri
ARISE t.ro

R s instant reads add reg R

5 10 instr reads data from mem loc
A in ace
tons

thy for decrement mode READ R

8 1 3O
aces
Assembly language Bogram
complete set of symbolic names Erule constituteto form a prog
language Eassemblytry
Assembly language programs can be translatedinto a sequence of
machine instructions a program called an assembler
by
when an assembler program is executed it reads the userprogram
If
and analyzes it and generates the machine Langprogram
the userpay in original text is k as SEP 09
the makine long
in OBJECTS
Assembler Directives
assembly tospecify otherinfoneeded to
long allows the programmer Directives
translatethe sourcepeg to objpeg Kommandt

i i
D write an ALPpegto add N'numbers storedin the memory
ORIGIN 100
MOVE N R1 mom set ofN nos R1
MOVE ANUMI R2 move 1st no R2
MOVE 0 Ro CLRRo clear Ro
ADD R2 Ro
ᵈᵈ
ÉrÉÉn'Tr1

ff
LOOP or BUT
more um i
ORIGIN 200
SUM RESERVE4
N DATA
WORD150
NUMI RESERVE600
END
ii EEE
 A write ALPprogram to compute the test scores
and store in
sum
of all
mem forN'students
ORIGIN 100 N total noofstudent
MOVE LIST RO studentI'D
CLEARA
CLEAR R2
CLEAR R 3
NOV N R4 MoveN'tory
3tests
AABB
for
FEIEEEI.EEIFs16bis.Cinorement
LOOP

ORIGIN 200
4
s
IEsEEii tests 15
List DREESE
END
A
A
Ls F
on the display screenusing
fdhhffffha
program
agree
controlled o
a producesaction output
I
Flags forcommb w www.magifuaaonfgmd ham
FIffffhhhhhhhaphthyister
idata inDatan
stored

datahastobedisplayedonthescreensend
when datatoDATAUT
deviceitwrites
datatoanoutput

I mail.ES sina.im iisi t i.nnon

Bus connection to processor keyboard display

keyboard
t.at
d
 Read input line
continuouslycheck SIN inputstatus until it indicatesthat a char is available
in the DATAINregister
Once SIN is set transfer the charfrom to 11
DEAL
Displayingitin
continuouslycheck SOUT outputstatus until it indicates that thedisplay is
readyto relieve thechar
once sout is set char fromRI istransferred to DIVE
Looping waiting
use a loop to check status tags asseenabove
ensures synchronization b w processor I odevices
CISC style instructions
useinstructions likeTestBit to checkstatusof Ilo flags
MoreBytetotransferinstructions bwbufferregisters
Implementate
readSINthey
If SIN is set morecharfromDATAINSRs If not branchbackto READWAIT
readSoutHey
If SOUTis set morecharfrom R1 DATAOUT Ifnot we WRITEWAID

Implementation
of Stacks
Astackis a datastructure and i.at oftest
iheefgyg.ggmhmm
elementsarepushedandroped gt thing
variousoperationson stacksare
Push addinganele to the top thestack
Pop removing an ele from top of
the thestack
of
display todisplay thecontents
ofstarch
IT If is usedto keeptrack of the address ofthede
fgfgfffzt.at
It pointtothe
marathon wherethe taste waspassedontothe
wheman all itpushedontothe stack stackpointer is incremented
when all ispopped we decremented

0
É stack is full
if full branch to FULLERII
opened if not NEWITE
INI
stack

43 Bottomelement
SAFES
check stack is
a if empty
htEm.EMteEmor
Implement gauer
Data in queues are stored in 0
basis
new data is added to the back ofqueue andretrieved from
thefront
Two pointers are used to manage the queue

8sep
mom
It tt saaises
addresses from beginning toend is assigned tothe queue
Afstentry CTgher
addresses

A circular and is used toprevent the queuefrom exceeding the allocated

memory
By the time the backof the queue reaches the end space will
becreated at beginning if some items are removed from the queued
proper care must be taken to check if a queueis emptyor tale

Subroutine

hasto seemed manyam

IIEEE.fragkfyikfg the subroutine
execution
of calling program continues immediately afterthe callford
the callingprogram
2c sfstsmf.gs That
simplest method to handle call and return is storing the return
astonam
k
EE ii IffiiEE gis
Subroutine
nesting
subroutine nesting is when one subroutine calls another subroutine
each time a subroutine is called its RETURN address is storedin
the LI
each time mn the peren return add is overned
How to handle subroutine nesting
By saving the contents of LI before calling another subroutine
subroutines can call other subroutines andform a nested steady
LEO order is managed to return addressesusinga processed state It is a
specialstackwhere returnaddresses are stored duringsubroutinecalls
 Many processors do this automaticallybyhandling the stack operations
with CALL ErRETURN instructions
CALL pushes the PS into the proesostach loadssubroutineaddress to P.C
RETURN pops the retromaddestfrom the processor stack into
P.LA
Subroutine Parameter Passing

It is the change of info

bw a
callington and a subroutine
methods
registers efficientmethod
memlocations
processor stack flexiblemethod
Paramethpassing can be done
by value and byreference
In passingthe value the
actual tothe
value ofparameter is passed subsidy
In passingthe oaf theactual valueis notpassedbut itsmereaddofparameter ispassed
The calling pay pushesthe parametersinto the stack the stateposter is decremented
each parameter takes up a certain space in the stack
once the parameters are pushed into the stack thecalligg program
executes the CALLIN to involve the subroutine
Once the outward is pushed onto the stack S P is further
decremented.toaccommodate this additional data

Subroutine Completion
Local variables are removed from stack
Processor register's contents are stored
old value of FPrestored

is created.eepushed onto the call stack

Nestedframes are built as more stackframes subroutines
Are called
Stack frames serve as a container for all the info related
to subroutines execution
once the subroutine completes its task stack frame is popped
out of the call stack control retrom to the calling fun
p
 If Ét source dest

Sean
2 address sourcedist

mEEE.EE's oh

13 s
D
Iaddress dist f

Accumulator each
step

IIIIIE EEEE EI son

ADDSUMMULIMOVLoadstored
j hg
MULT
MOV X Y Y
in EfEEI
fi
mut xxx
XY X x 23

SUB 45
s