 2CP05: COMPUTER ORGANIZATION AND ARCHITECTURE

CREDITS - 4 (LTP:3,0,1)

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 instruction

 An instruction is a command to the microprocessor to

perform a given task on specified data
 Each instruction has two parts : one is the task to be
performed called the operation code (op code) and the
second is the data to be operated on called the operand
 The way by which operand specify in instruction is called
addressing mode
 1. immediate
 2. register
 3. direct
 4. register indirect
 5. implicit

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 Addressing mode

Immediate Addressing Mode

 In immediate addressing mode the source operand is always
data. If the data is 8-bit, then the instruction will be of 2
bytes, if the data is of 16-bit then the instruction will be of
3 bytes.
 Examples:
MVI B ,45 (move the data 45H immediately to register B)
LXI H, 3050 (load the H-L pair with the operand 3050H
immediately)

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Register Addressing Mode –
In register addressing mode, the data to be operated is available inside
the register(s) and register(s) is(are) operands. Therefore the operation is
performed within various registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register
A)
INR A (increment the contents of register A by one)

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Direct Addressing Mode –
In direct addressing mode, the data to be operated is available inside a
memory location and that memory location is directly specified as an
operand.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register
pair)
IN 35 (read the data from port whose address is 35)
LHLD 2500H 2500 32 > L
2501 25 > H

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 Register Indirect Addressing Mode –
In register indirect addressing mode, the data to be
operated is available inside a memory location and that
memory location is indirectly specified by a register
pair. Examples:
MOV A, M (move the contents of the memory location
pointed by the H-L pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
 STAXB
 LDAXD STAXD

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Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is hidden and the
data to be operated is available in the instruction itself. Examples:
CMA (finds and stores the 1’s complement of the contains of
accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

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 Addressing mode

 Some microprocessor has additional addressing modes:

Relative addressing mode
 PC (program counter) Relative addressing mode
 Index addressing mode
 Base register addressing mode

Advantages
Code become relocatable
No of byte in instruction reduced

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Which of the following addressing modes
are suitable for program relocation at run
time?
1.Absolute addressing
2.Based addressing
3.Relative addressing
4.Indirect addressing
A I and IV
B I and II
C II and III
D I, II and IV

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Which is the most appropriate match for the items in the first
column with the items in the second column?
X. Indirect Addressing
Y. Indexed Addressing
Z. Base Register Addressing
I.Array implementation
II.Writing relocatable code
III.Passing array as parameter

A) (X, III) (Y, I) (Z, II)

(B) (X, II) (Y, III) (Z, I)
(C) (X, III) (Y, II) (Z, I)
(D) (X, I) (Y, III) (Z, II)

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 Instruction word size

 According to word size three categories

 1. 1 byte instruction
 E.g. MOV A,B ADD B CMA
 2. 2 byte
 MVI A,32H ADI 50H
 3. 3 byte
 LDA 2500H
 JMP 2040H
 LXI H,2500H

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 Opcode format

 Registers register pair

 000 B 00 BC
 001 C 01 DE
 010 D 10 HL
 011 E 11 AF or SP
 100 H
 101 L
 111 A
 110 reserved for memory related operation

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 Opcode format

 MOV
 01DDDSSS
 E.g. MOV C,A 01001111 4FH
 ADD
 10000SSS
 ADD B
 10000000 80H
 MVI A,35H
 3E 35
 00DDD110
 LXI Rp,16bit LXI H,2500H
 00DD0001 00100001 21 00 25

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A computer uses a memory unit with 256K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one of
64 registers, and an address part.
1. How many bits are there in operation code, the register code part, and the
address part?
2. How many total operation codes are possible?
3. How many bits are there in the data and address inputs of the memory?

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6 bit for register, 1bit for indirect, 18bit address so 7 bit for opcode
Total 128 operation codes are possible
32 bit for data and 18 bit for address

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A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit
instruction word has an opcode, two register operands and an immediate operand. The
number of bits available for the immediate operand field is __________ .

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one
of the following is a legal program counter (all values in decimal)?
A 400 B 500 C 600 D 700

A processor has 64 registers and uses 16-bit instruction format. It has two types of
instructions: I-type and R-type. Each I-type instruction contains an opcode, a register
name, and a 4-bit immediate value. Each R-type instruction contains an opcode and
two register names. If there are 8 distinct I-type opcodes, then the maximum number of
distinct R-type opcodes is _______.

A processor has 16 integer registers (R0, R1, … , R15) and 64 floating point registers
(F0, F1, … , F63). It uses a 2-byte instruction format. There are four categories of
instructions: Type-1, Type-2, Type-3, and Type 4. Type-1 category consists of four
instructions, each with 3 integer register operands (3Rs). Type-2 category consists of
eight instructions, each with 2 floating point register operands (2Fs). Type-3 category
consists of fourteen instructions, each with one integer register operand and one
floating point register operand (1R+1F). Type-4 category consists of N instructions,
each with a floating point register operand (1F).
The maximum value of N is _______ .
 Instruction cycle & Machine cycle

 Time required to complete the execution of an instruciton is

known as instruction cycle
 To execute an instruction 8085 required to perform various
operations such s memory read/write and I/O red/write
known as machine cycle
 Machine cycles are divided into precise system clock periods
know as T-state

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25
 Draw instruction cycle of MVI A,32H

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27
28
29
30
 Draw insteuciton cycle of STA 8000H

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32
33
 Draw instruction cycle of MOV M,reg

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35
 Draw instruction cycle of MOV reg,M

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 Find out no of bytes, machine cycles, addressing mode
 Draw instruction cycle of LDAXB instruction
 Draw instruction cycle of LXI H,2500H
 Draw instruction cycle of INR M
 Draw instruction cycle of LHLD 2600H
 Draw instruction cycle of MVI M,25H

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Instruction No of bytes No of machine Addresing mode
cycles
LDAXB 1 2 (7 Tstates) Indirect
LXI H,2500H 3 3 (10 Tstates) immediate

INR M 1 3(10 Tstates) Indirect

2 3 (10 Tstates) immediate
MVI M,25H Indirect

LHLD 2600H 3 5 (16 Tstates) direct

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 Memory

 Memory stores instruction and data

 RAM and ROM

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Memory

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44
 RAM
 6116 or 6132….
 ROM
 2716,2732,….

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 Memory map

 8085 is capable of identifying 2 16 (64k) memory registers

 so entire address range from 0000 to FFFFH
 Range of addresses for given memory chip known as memory
map

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50
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 How many address lines required for an 8Kbyte memory chip

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 Interface 8Kbyte RAM and 8Kbyte EPROM with 8085
 EPROM starting address 0000 and RAM starting address
 RAM starting address 2000H

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60
In a system where some address lines are not decoded resulting
multiple addresses, is called partial decoding. Used in small system
Advantage is cost saving

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Absolute or exhaustive decoding

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63
 Interface 4 kbyte EPROM with starting address 0000 and
2kbyte RAM with starting address 2000H

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The chip select logic for a certain DRAM chip in a memory system design
is shown below. Assume that the memory system has 16 address lines
denoted by A15 to A0. What is the range of addresses (in hexadecimal) of
the memory system that can get enabled by the chip select (CS) signal?
(assume active high chip select)

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 Interface 4Kbyte EPROM using 2Kbyte chip starting at
0000 and 8Kbyte RAM using 2Kbye chip starting at 2000H

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77
 Interface 2Kbyte EPROM using 2KX4 chip starting address
0000H

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A processor can support a maximum memory of 4GB where the memory is
word-addressable (a word consists of two bytes). What is the size of the
address bus of the processor?

80
One byte instruction
81
Two byte instruction
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84
85
3 byte instruction, register pair can be H/B/D/SP
LXI B,2300H

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5 machine cycle and 16 T-state

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88
B or D can be used

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90
One machine cycle and four T-states

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 Data transfer between 8085 and memory

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 Data transfer between Microprocessor and I/O

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98
99
100
101
102
103
104
Peripheral I/o or IO mapped IO

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107
108
109
IN FAH
OUT F8H

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Memory Mapped I/O

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113
114
115
116
8085 based system

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ADD M one byte, two machine cycle, 7 T states
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119
What are the states of the Auxiliary Carry (AC) and
Carry Flag (dCY) after executing the following 8085
program?

MVI L, 5DH
MVI H, 6BH
MOV A, H
ADD L
(A) AC = 0 and CY = 0
(B) AC = 1 and CY = 1
(C) AC = 1 and CY = 0
(D) AC = 0 and CY = 0

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121
2 byte, 2 Machine cycle and 7 States

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123
 Add two 8 bit data

 MVI A,93H
 MVI C,B7H
 ADD C
 MOV B,A
 MVI A,00H
 ACI 00
 HLT

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 Add two 16 bit data
 LXI H,2500H
 LXI D,2600H
 MOV A,L
 ADD E
 MOV C,A or STA 2700H
 MOV A,H
 ADC D
 MOV B,A or STA 2701H
 MVI A,00
 ACI 00 STA 2702H

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Register pair can be B, D, H,SP
It is one byte instruction and required 3 machine cycle and 10 T states
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 Opcode fetch
 Second machine cycle
 T1 rpl->A
 T2 L->Tmp
 A+TMP->ALU
 T3 ALU->L
 Third Machine cycle
 T1 rpH->A
 T2 H->Tmp
 A+TMP->ALU
 T3 ALU->H

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 DAD H
 Suppose H is 0242H then it become 0484H so multiply by 2
 Bring SP into HL pair
 LXI H,0000
 DAD SP

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129
 subtraction

 Perform following step

 Convert subtrahend into 1’s complement
 Add 1 to 1’s complement to obtain 2’s complement
 Add 2’s complement to minuend(contet of accumulator)
 Complement carry flag

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S, Z,P and AC are modified to reflect the result of operation but CY is
not modified
INR M one byte, 3 Machine cycles and 10T states 138
 Register D contains FF. what is the content of register
after increment
 D become zero so zero flag become 1 but cy flag is not
affected

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1 byte instruction and required one machine cycle but 6 T state
required. No flags are affected
Pair can be B,D,H and SP

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 HL consists of 9FFFH what is after INX H
 Hl becomes A000H

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S, Z,P and AC are modified to reflect the result of operation
but CY is not modified
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 B is zero what is B after DCR B

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 Find flag after execution of following instructions
 A B S Z CY

SUB A
MOV B, A
DCR B
INR B
SUI 01H
HLT

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145
1 byte instruction and required one machine cycle but 6 T state
required. No flags are affected
Pair can be B,D,H and SP

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 ANA R
 ANA M
 ANI 8bit
 S, Z and P are modifies to reflect the operation .CY is reset
and AC flag is set
 APPLICATION
 Masking bit
 E..g separate lower nibble form 8 bit
 ANI 0FH

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Assume on-off switches are connected to input port 00.
turn on A.C. if switch s7 is on ignore all other switches

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 Assume on-off switches are connected to input port 00. turn
on A.C. if switch s7 is on ignore all other switches
 IN 00H
 ANI 80H
 OUT 01H
 HLT

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153
 ORA R
 ORA M
 ORI 8bit
 Z, S and P are modified to reflect the result of the
operation , AC and CY are reset
 ORA A clear carry flag
 Application : set bits
 E.g. A=03H
 B=50H
 ORA B

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Radio is connected on D4 line of out put port. Keep radio on
irrespective of switches pressed

Turn off a.c. without affecting other devices given that ac is

connected with D7

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 Radio is connected on D4 line of out put port. Keep radio on
irrespective of switches pressed
 IN 00
 ORI 10H
 OUT 01H
 HLT
Turn off a.c. without affecting other devices given that ac is
connected with D7
IN 00
ANI 7FH
Out 01

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TWO input port and one output port. Turn on devices form any
port
IN 00H
MOV B,A
IN 01H
ORA B
Out 02h
HLT

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158
 XRA Reg
 XRA M
 XRI 8 bit
 Z,S and P are modified to reflect the result, CY and AC are
reset
 XRA A single instruction clear Accumulator and carry flag

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Comparison is done using subtraction but source and destination
are not changed. S,P,AC are modified in addition to Z and CY flag

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

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 Unpacked to packed BCD e.g. 03 and 05 should 35H
 MVIA,03H
 MVI B,05H
 RLC
 RLC
 RLC
 RLC
 ORA B
 HLT

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 Write an alp two unpacked 8 bit BCD data
 E.g. 35H converted to 03 and 05
 MVI A,35H
 MOV B,A
 ANI 0FOH
 RLC
 RLC
 RLC
 RLC
 MOV C,A
 MOV A,B
 ANI oFH

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 Applications
 Rotate is used for multiplication and division
 E.g A=08
 RAL become 16H multiplication
 RAR become 04 division
 But it become invalid in case of E.g. 80H become 01 when
RLC is sued
 Two bring carry into register
 MVI A,00
 RAL

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 Rotate 16bit number

175
 16bit rotation without carry

 LHLD 2500H
 XRA A
 MOV A,L
 RAL
 MOV L,A
 MOV A,H
 RAL
 MOV H,A
 JNC ok
 INR L
 OK: HLT

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8085 program to reverse 16 bit number

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 Logical Shift
 • A Left Logical Shift of one position moves each bit to
the left by one. The vacant least significant bit (LSB) is
filled with zero and the most significant bit (MSB) is
discarded.
 • A Right Logical Shift of one position moves each bit to
the right by one. The least significant bit is discarded and
the vacant MSB is filled with zero.


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Arithmetic Shift
•A Left Arithmetic Shift of one position moves each bit to the left by
one. The vacant least significant bit (LSB) is filled with zero and the
most significant bit (MSB) is discarded. It is identical to Left Logical
Shift.
•A Right Arithmetic Shift of one position moves each bit to the right
by one. The least significant bit is discarded and the vacant MSB is
filled with the value of the previous (now shifted one position to the
right) MSB.

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180
Arithmetic Shift operations can be used for dividing or multiplying an
integer variable
For unsigned representation, when the first “1” is shifted out of the left
edge, the operation has overflowed. The result of the multiplication is
larger than the largest possible.
Shifting left on signed values also works, but overflow occurs when the
most significant bit changes values (from 0 to 1, or 1 to 0).
If we have the binary number 01110101 (117 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 00111010 (58 decimal). So we have divided the original
number by 2.
If we have the binary number 1010 (-6 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 1101 (-3 decimal). So we have divided the original negative
number by 2.

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3 byte instruction, 3machine cycle and 10 Tstates
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187
 It take only 2 machine cycle and 7 T-states when condition
is not true but condition is true then 3 machine cycle and 10
t state

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 Compare two 16 bit numbers

189
 LXI H,2345H
 LXI D,3456H
 MOV A,H
 CMP D
 JC seocnd
 Jnz first
 MOV A,L
 CMP E
 JC second
 Jnz first
 MOV B,00
Jmp last
 SECOND: Mov B,02
 Jmp last
 FIRST:MOV B,01
 Last: HLT
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 Multibyte data addition (64bit data addition)
 MVI B,8
 LXI H,2500H
 LXI D,2600H
 XRA A
 CONTI:LDAXD
 ADC M
 STAXD
 INXH
 INXD
 DCR B
 JNZ CONTI
 hlt

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 A SET OF 10 READING IS STORED AT MEMEORY
LOCATIONS STARTING AT 2500h. ADD ALL POSITVE
DATA

192
 MVI B,00
 MVI D,0Ah
 MVI C,00H
 LXI H,2500H
 NEXT:MOV A,M
 RAL
 JC REJECT
 RAR
 ADD C
 JNC X
 INR B
 X: MOV C,A
 REJECT: INXH
 DCR D
JNZ NEXT
193

 A set of 10 reading is stored memory locations staring at
2600H. Write an 8085 alp to Count odd number and even
number

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 Write an ALP program to sort given array in ascending order

Bubble sort

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 MVI C,05
 Again:LXI H,2000H
 DCR C
 JZ LAST
 MOV B,C
 LOOP: MOV A,M
 INXH
 CMP M
 JC NEXT
 MOV D,M
 MOV M,A
 DCXH
 MOV M,D
 INXH
 Next:DCR B
 JNZ LOOP
 JMP again
 LAST:HLT 196
 BCD addititon

 DAA : decimal adjust accumulator

 1 Byte instruction, 1 machine cycle and 4 T state
 After addition of two bcd data , if you want answer also BCD
then use DAA instruction. After addition, if we use this
instruction then change the contain of accumulator from
binary to BCD. It operate on 8 bit data
 Flags : S,Z,AC,P and CY flags are altered to reflect the
result of the operation
 It convert binary answer of accumulator to BCD as follows
 1. if the value of lower nibble(D0-D3) in the accumulator is
greater than 9 or if AC flag is set , the instruction add 6 to
the lower four bits
 2. if the value of higher-order bits(D4-D7) in the
accumulator is greater than 9 or if the carry flag is set the
instruction adds 6 to the higher order four bits
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198
199
A SET OF 10 BCD READING IS STORED AT MEMEORY
LOCATIONS STARTING AT 2500h. ADD ALL DATA and
answer must be BCD

200
MVI B,00
MVI D,0Ah
XRA A
LXI H,2500H
NEXT:ADD M
DAA
JNC X
MOV C,A
MOV A,B
ADI 01
DAA
MOV B,A
MOV A,C
X: INXH
DCR D
JNZ NEXT

201
 ADD TWO 16BIT bcd DTATA
 LXI H,2546h
 LXI D,2345h
 MOV A,L
 ADD E
 DAA
 MOV C,A
 MOV A,H
 ADC D
 DAA
 MOV B,A
 MVI A ,00
 ACI 00
 DAA
HLT
202

 An array of six data byte is stored starting from memory
location 2050H. Write a program to eliminate zero from the
array
 Assume an array of sorted 10 byte. Insert given element at
appropriate position

203
LXI H, 2500H
MVI C,05H
MVI B,28
AGAIN: MOV A,M
CMP B
JC NEXT
MOV A,L
ADD C
MOV L,A
CONT: DCX H
MOV A,M
INX H
MOV M,A
DCX H
DCR C
JNZ CONT
MOV M,B
HLT
NEXT: INX H
DCR C
JNZ AGAIN
MOV M,B
HLT 204