TIMER/COUNTER

8051 has two 16 bit timer.counter registers

•Timer 0
•Timer 1
Both can work either as timers or event
counters
Four different operating modes to select
Timer/Counter
9ch….. ff

9Ch
 Interfacing Peripheral Devices
BUZZER
#include<reg51.h>
#include<stdio.h>

void delay();
int i;

void main()
{

while(1)
{

P2=0xEF;

delay();

P2=0xff;
delay();
}
 Program:
#include <reg51.h>
INTERFACING LED #include <stdio.h>
unsigned long int i;
void delay()
{
for (i=0; i<2500; i++);
}
void main()
{
while (1)
{
P1 = 0x00;
delay();
P1 = 0xff;
delay();
}}
REG51.Hhttps://www.keil.com/dd/docs/c51/reg51.h

Header file for generic 80C51 and 80C31 microcontroller.

Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/

#ifndef __REG51_H__ sfr TL1 = 0x8B;

#define __REG51_H__ sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
/* BYTE Register */ sfr IE = 0xA8;
sfr P0 = 0x80; sfr IP = 0xB8;
sfr P1 = 0x90; sfr SCON = 0x98;
sfr P2 = 0xA0;
sfr SBUF = 0x99;
sfr P3 = 0xB0;
sfr PSW = 0xD0; /* BIT Register */
sfr ACC = 0xE0;
sfr B = 0xF0;
/* PSW */
sfr SP = 0x81; sbit CY = 0xD7;
sfr DPL = 0x82; sbit AC = 0xD6;
sfr DPH = 0x83; sbit F0 = 0xD5;
sfr PCON = 0x87; sbit RS1 = 0xD4;
sfr TCON = 0x88; sbit RS0 = 0xD3;
sfr TMOD = 0x89; sbit OV = 0xD2;
sfr TL0 = 0x8A; sbit P = 0xD0;
 https://developer.arm.com/documentation/10
1655/0961/Cx51-User-s-Guide/Library-Referen
ce/Include-Files/stdio-h
stdio.h
The stdio.h include file contains prototypes and
definitions for stream I/O routines. They are:
_getkey
getchar
gets
printf
putchar
puts
scanf
sprintf
sscanf
ungetchar
vprintf
vsprintf
The stdio.h include file also defines the EOF and
NULL manifest constants.
 Serial Communication
SCON REGISTER
MODE 0 : SHIFT REGISTER TXD serves as the clock
while RXD is used for
both receiving and
transmitting data. In
mode 0, the serial port is
only half duplex; it
cannot transmit and
receive data at the same
time because the same
line (RXD) is being used
for both transmit and
receive.
• The serial port in mode 0 is an example of synchronous
communication;
• the clock signal is sent with the data on the TXD line.
• TXD pulses at the same frequency as the machine
cycle.
• In other words, TXD runs at 1/12th the frequency of
the system clock.
• If we are using a 12MHz system clock, then the
frequency of TXD is 1MHz, which implies its cycle
length is 1us.
• Therefore, each bit is active on the RXD line for 1us.
• To shift the entire 8-bit word along RXD takes 8us.
MODE 1

The serial port in mode 1 operates as an 8-bit UART

(Universal Asynchronous Receive/Transmit). This is
asynchronous communication, therefore no clock
signal is sent with the data. Instead, a single start bit
(always logic 0) and a single stop bit (always logic 1)
encapsulate the data (8 bits). Therefore, in total, ten
bits are sent per byte of data.
Data is transmitted on TXD. Transmission is initiated by a write to the serial
buffer (eg; MOV SBUF, R0). Once the stop bit is transmitted TI is set,
alerting the processor to the fact that the entire byte has been transmitted.

When no data is being transmitted the TXD line is constantly held HIGH (ie;
a constant stream of stop bits).

Received data arrives on RXD. When the stop bit is received the RI flag is
set, alerting the processor to the fact that an byte has been received.

If no data is being received RXD will be a constant HIGH (because the

transmitter, working off the same protocol, will hold its TXD line HIGH when
not transmitting data).
Therefore, the receiver waits for a 1 to 0 transition. This signals the arrival
of a start bit, which indicates a data byte is following. The start bit is
skipped and the eight data bits are fed into the serial port shift register.
When all eight bits have been shifted into the register the following occur:
•The stop bit is copied to RB8 in SCON.
•The data in the shift register is moved (in parallel) into SBUF (read-only).
•RI is set.
Mode 2
 Mode 3

Mode 3 is identical to mode 2 except that the baud

rate is determined exactly as in model 1 using Timer 1
to generate communication frequencies
• 8051 serial communication has TTL voltage level which are 0 v
for logic 0 and 5 v for logic 1.
• In computers and most of the old devices for serial
communication, RS232 protocol with DB9 connector is used.
RS232 serial communication has different voltage levels than
8051 serial communication. i.e. +3 v to +25 v for logic zero and
-3 v to -25 v for logic 1.
• So to communicate with RS232 protocol, we need to use a
voltage level converter like MAX232 IC.
• Although there are 9 pins in the DB9 connector, we don’t need
to use all the pins. Only 2nd Tx(Transmit), 3rd Rx(Receive), and
5th GND pin need to be connected.
8051 interfacing with RS232

RxD and TxD pins in the 8051

The 8051 has two pins that are used specifically for transferring and receiving data serially.
These two pins are called TxD and RxD and are part of the port 3 group (P3.0 and P3.1). Pin
11 of the 8051 (P3.1) is assigned to TxD and pin 10 (P3.0) is designated as RxD. These pins
are TTL compatible; therefore, they require a line driver to make them RS232 compatible.
One such line driver is the MAX232 chip.

MAX232

Since the RS232 is not compatible with today’s microprocessors and microcontrollers, we
need a line driver (voltage converter) to convert the RS232′s signals to TTL voltage levels
that will be acceptable to the 8051 ‘s TxD and RxD pins. One example of such a converter is
MAX232 from Maxim Corp. (www.maxim-ic.com). The MAX232 converts from RS232
voltage levels to TTL voltage levels, and vice versa. One advantage of the MAX232 chip is
that it uses a +5 V power source which, is the same as the source voltage for the 8051. In
other words, with a single +5 V power supply we can power both the 8051 and MAX232,
with no need for the dual power supplies that are common in many older systems.
INTERFACING 7 SEGMENT LED WITH 8051
7 SEGMENT LEDS ARE CONNECTED IN COMMON CATHODE CONFIGURATION
Common anode configuration

DECI h g f e d c b a Hex
MAL value
NO
0 1 1 0 0 0 0 0 0 0xc0
1 1 1 1 1 1 0 0 1 0xf9
2 1 0 1 0 0 1 0 0 0xa4
3 1 0 1 1 0 0 0 0 oxb0
4 1 0 0 1 1 0 0 1 0x99
5…9
A…f
 #include<reg51.h>
#include<stdio.h> void main()
#include<string.h> {

#define HIGH 1; while(1)

#define LOW 0;
#define ONE 1; { key=123;
#define ZERO 0; DISPSEVSEG();

sbit seg0 = P2^0; }

sbit seg1=P2^1; }
sbit seg2=P2^2;
sbit seg3=P2^3;
unsigned int d4;
int key=0;
void delay();
void DISPSEVSEG();
int a[5]={0xc0,0xF9,0xA4,0xB0,0x99,
…..0x};
void DISPSEVSEG()
{
int d2,d1,d0;

d2= key /100; d2=1

key= key%100; key =23 void delay()
d1= key/10; d1=23/10 =2 {
d0=key%10; d0=3 long int i;
P1=a[d0]; for(i=0;i<100;i++);
seg0=0;
delay(); }
seg0=1;
P1=a[d1];
seg1=0; delay();
seg1=1;
P1=a[d2];
seg2=0; delay();
seg2=1;
P1=a[0];
seg3=0; delay();
seg3=1; }
 8051 INTERRUPTS
• Interrupts vs. polling
– on receiving interrupt, the microcontroller
interrupts whatever it is doing and
executes interrupt service routine (ISR)
– microcontroller can serve many devices
– each device gets attention based on the
priority
– polling wastes time

55
 8051 INTERRUPTS
• Interrupt service routine
– for each interrupt there must be ISR
– for every interrupt, there is a fixed location in
memory that holds the address of its ISR
– interrupt vector table

56
 8051 INTERRUPTS

Table Interrupt Vector Table for the 8051

57
 8051 INTERRUPTS
• Steps in executing an interrupt
1. μC finishes the instruction it is executing and saves
the address of the next instruction (PC) on the stack
2. it saves the current status of all the interrupts
internally
3. it jumps to a fixed location in memory called the
interrupt vector table
4. the microcontroller gets the address of the ISR from
the interrupt vector table and jumps to it and starts
to execute the ISR until it reaches the last instruction
RETI
5. the microcontroller returns to the place where it was
interrupted, it gets the PC address from the stack by
popping the top two bytes of the stack into the PC
and then it starts to execute from that address 58
 8051 INTERRUPTS
• Six interrupts in the 8051
– 1 reset interrupt, when the reset pin is activated, the
8051 jumps to address location 0000
– 2 timer interrupts
– 2 external hardware interrupts
– pin 12 (P3.2) and 13 (P3.3) in port 3 are for the
external hardware interrupts
– 1 serial communication interrupt that belongs to
both receive and transmit
– a limited number of bytes is set aside for each
interrupt

59
 8051 INTERRUPTS
• Enabling and disabling an interrupt
– upon reset all interrupts are disabled
– interrupts must be enabled by software
– IE register (interrupt enable) is responsible for
enabling and disabling the interrupts
– IE is a bit-addressable register

60
 8051 INTERRUPTS
• Steps in enabling an interrupt
1. EA must be set to 1
2. set the relevant bits in IE register to high

– EA = 0, no interrupt will be responded to,

even if the relevant bit in the IE register is
high

61
IE (Interrupt Enable) Register

62
Show the instructions to
(a) enable the serial interrupt, Timer 0 interrupt,
and external hardware interrupt 1 (EX1),

(b) disable (mask) the Timer 0 interrupt,

then
(c) show how to disable all the interrupts with a
single instruction.

1 0 0 1 0 1 1 0 = 0x96 MOV IE, #96

2 MOV IE,#00 OR MOV IE.7,#00
 PROGRAMMING TIMER INTERRUPTS

• Roll-over timer flag and interrupt

Figure 1 TF Interrupt
– if the timer interrupt is enabled, whenever TF=1, the microcontroller is interrupted in
whatever it is doing, and jumps to the interrupt vector table to service the ISR
– In this way, the microcontroller can do other things until it is notified that the timer
has rolled over

64
 PROGRAMMING EXTERNAL HARDWARE
INTERRUPTS
• External interrupts INT0 and INT1

Figure Activation of INT0 and INT1 65

 PROGRAMMING EXTERNAL HARDWARE
INTERRUPTS
• Level-triggered interrupt
– INT0 and INT1 pins are normally high
– if low-level signal is applied, it triggers the interrupt
– microcontroller stops whatever it is doing and jumps
to the interrupt vector table to service the interrupt
– the low-level signal must be removed before the
execution of the last instruction of the interrupt
service routine, RETI
– otherwise, another interrupt will be generated

66
 INTERRUPT PRIORITY IN THE 8051

• Interrupt priority upon reset

Table 11–3 8051/52 Interrupt Priority Upon Reset 67

• Setting interrupt priority with the IP
register

68
 Program the IP register to assign the highest priority to INTI,
then (b) discuss what happens if INT0, INT1, and TF0are
activated at the same time. Assume that the interrupts are
both edge-triggered.

• (a) MOV IP,#00000100B or "SETB IP.2“

• (b) when INT0, INT1, and TF0 interrupts are

activated at the same time, the 8051 services INT1
first, then it services INT0, then TF0

69
 Inter-Integrated Circuit
• I²C is a serial computer bus, which is invented by NXP semiconductors
previously it is named as Philips semiconductors.
• The I²C bus is used to attach low-speed peripheral integrated circuits to
microcontrollers and processors.
• I²C bus uses two bidirectional open-drain lines such as SDA (serial data
line) and SCl (serial clock line) and these are pulled up with resistors.
• I²C bus permits a master device to start communication with a slave
device.
• Data is interchanged between these two devices.
• Typical voltages used are +3.3V or +5V although systems with extra
voltages are allowed.
• Nowadays new microcontrollers have inbuilt I²C Registers. But in 8051
there is no such registers.
• So we have to achieve I²C in 8051. So in this tutorial, we will see how to
achieve that.
Analog to Digital Interfacing with 8051
•ADC – analog to digital conversion
• It converts the given analog value to a digital value
•There are lot of digital ICs available to convert analog to digital
• In microcontroller interfacing the frequently used ICs are 0804 and 0808
•Different types- flash, successive approximation, integral type

•ADC0808 :
•ADC0808 is a commonly used External 8 bit ADC and it has 28 pins.
•It can measure up to eight ADC values from 0 to 5 volt since it has eight channels.
•when voltage reference is +5V, its Step size will be 19.53mV. That is, for every
increase of 19.53mV on the input side there will be an increase of 1 bit at the
output side.

Step size= full scale voltage /2^8

WORKING OF ADC
SUCESSIVE APPROXIMATION
ADC0808 needs an external clock to operate. The ADC needs some specific control
signals for its operations like start conversion and bring data to output pins. When the
conversion is complete the EOC pins go low to indicate the end of a conversion and that
the data is ready to be picked up.

Features

Easy interface to all microprocessors

Operates ratio metrically or with 5 V DC or analog span adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to 5V input range with single 5V power supply
Outputs meet TTL voltage level specifications
Standard hermetic or molded 28-pin DIP package
28-pin molded chip carrier package
Channel Selection :
We can select any input channel by using the Address lines ADD A, ADD B and ADD C. As
you can see in the below table, We can select the input line IN0 by keeping all three
address lines ADD A, ADD B and ADD C Low.
Steps to be followed to interface ADC (ADC0808) with 8051
Start
Select the channel using Address pins.
A Low – High transition on ALE to latch in the address.
A Low – High transition on Start to reset the ADC’s SAR.
A High – Low transition on ALE.
A High – Low transition on start to start the conversion.
Wait for End of cycle (EOC) pin to become high.
Make Output Enable pin High.
Take Data from the ADC’s output
Make Output Enable pin Low.
Stop
INTERFACING ADC WITH 8051
Steps to calculate voltage.
Voltage value for each increase of bit can be found using the equation :
Step Size = (Vref+ – Vref-)/256
Step size can be multiplied with ADC output to get the voltage.
Example :
If Vref+ is connected to 5v and Vref- is connected to ground the equation
becomes :
Step size = (5 – 0)/256= 19.53 mv

In such a case if the output value is 01101110 = 110

The voltage value will be : 110 x 19.53 mV = 2.14 V .
The Digital to Analog converter (DAC) is a device, that is widely used for converting digital
pulses to analog signals.
There are two methods of converting digital signals to analog signals.
These two methods are binary weighted method and R/2R ladder method.

MC1408 (DAC0808) Digital to Analog Converter.

This chip uses R/2R ladder method. This method can achieve a much higher degree of
precision. DACs are judged by its resolution.

The resolution is a function of the number of binary inputs.

The most common input counts are 8, 10, 12 etc.
Number of data inputs decides the resolution of DAC. So if there are n digital input pin,
there are 2n analog levels. So 8 input DAC has 256 discrete voltage levels.
 The MC1408 DAC (or DAC0808)
In this chip the digital inputs are converted to current. The output current is known
as Iout by connecting a resistor to the output to convert into voltage. The total current
provided by the Iout pin is basically a function of the binary numbers at the input pins D0 -
D7 (D0 is the LSB and D7 is the MSB) of DAC0808 and the reference current Iref. The
following formula is showing the function of Iout

The Iref is the input current. This must be provided into the pin 14. Generally 2.0mA is used as
Iref
We connect the Iout pin to the resistor to convert the current to voltage. But in real life it may
cause inaccuracy since the input resistance of the load will also affect the output voltage. So
practically Iref current input is isolated by connecting it to an Op-Amp with Rf = 5KΩ as
feedback resistor. The feedback resistor value can be changed as per requirement.
Weighted Resistor DAC
A weighted resistor DAC produces an analog output, which is almost equal to the
digital (binary) input by using binary weighted resistors in the inverting adder circuit.
In short, a binary weighted resistor DAC is called as weighted resistor DAC.

circuit diagram of a 3-bit binary weighted resistor DAC

The bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0.
Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal
to ‘0’. Similarly, the digital switches shown in the above figure will be connected to the negative reference
voltage, −VR when the corresponding input bits are equal to ‘1’.
In the above circuit, the non-inverting input terminal of an op-amp is connected to ground. That means zero volts is
applied at the non-inverting input terminal of op-amp.

We can write the generalized output voltage equation of an N-bit binary weighted resistor
DAC as shown below based on the output voltage equation of a 3-bit binary weighted resistor
DAC.

The disadvantages of a binary weighted resistor DAC are as follows −

The difference between the resistance values corresponding to LSB & MSB will increase as
the number of bits present in the digital input increases.
It is difficult to design more accurate resistors as the number of bits present in the digital
input increases.
R-2R Ladder DAC
The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As
the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal
to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit.
The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure −
Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1.

Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least
Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are
equal to ‘0’. Similarly, the digital switches shown in above figure will be connected to the negative reference
voltage, −VR−VR when the corresponding input bits are equal to ‘1’.
It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But, we can find the analog output
voltage values of R-2R Ladder DAC for individual binary input combinations easily.

The advantages of a R-2R Ladder DAC are as follows −

•R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to select and design more accurate
resistors.
•If more number of bits are present in the digital input, then we have to include required number of R-2R sections
additionally.
Due to the above advantages, R-2R Ladder DAC is preferable over binary weighted resistor DAC.
 Introduction of SPI Communication Protocol

•SPI stands for the serial peripheral interface.

•It is a Synchronous serial communication protocol that is based on master and slave.
• In the SPI protocol, communication is always started by the master to put the
slave-select line low.

•The SPI Interface was developed by Motorola in late 1980 and it is the most popular
serial synchronous bus protocol for short-distance communication.

•Sometimes, SPI is called a four-wire serial bus and each bus has a specific role and
importance. SPI works in full-duplex mode, which means it can receive and send data at
a time.
SPI is a single master full-duplex communication protocol that means communication
always starts by the master. In SPI communication multi-slave can be attached with a
single master and slave cannot change its role to master.
Each slave has its own slave select pin which is controlled by the master. In the case of
multi-slave, the master selects the slave by pulling down its slave select line (ss). There
is four-wire is used in communication these are MOSI, MISO, SCLK, and SS.
SCLK: Serial Clock (It is produced by the master to start the communication)
MOSI: Master Out, Slave In (This line is used to carry data from the master to the
slave)
MISO: Master in, Slave out (This line is used to carry the data from the slave to the
master)
SS: Slave Select (This line is used to select the slave in case of the multi-slave
communication)
Steps for the SPI communication

Step1: Master pulling down the slave select line of a slave that it
wants to communicate.

Step2: After selecting the slave master start to generates the clock
signal which is shared by the slave. The clock configuration
(polarity and phase) of the master and slave should be the same.

Step3: Now master generates information on the MOSI line and

samples the received data at the MISO line at the same time.
How SPI Works?
Each time the master drives a pulse on the clock line and one
bit is transferred in each direction. The MOSI line sends out a
bit, while the MISO line receives a bit. While this means that
the amount of data sent and the amount of data received must
be equal, it’s trivial to provide dummy data when you don’t
have anything interesting to send.
I2C stands for Inter-Integrated Circuit. It is a bus interface connection
protocol incorporated into devices for serial communication. It was originally
designed by Philips Semiconductor in 1982. Recently, it is a widely used
protocol for short-distance communication. It is also known as Two Wired
Interface(TWI).
Working of I2C Communication Protocol :
It uses only 2 bi-directional open-drain lines for data communication called
SDA and SCL. Both these lines are pulled high.
Serial Data (SDA) – Transfer of data takes place through this pin.
Serial Clock (SCL) – It carries the clock signal.
I2C operates in 2 modes –
•Master mode
•Slave mode
Each data bit transferred on SDA line is synchronized by a high to the low
pulse of each clock on the SCL line.
 According to I2C protocols, the data line can not change when
the clock line is high, it can change only when the clock line is
low. The 2 lines are open drain, hence a pull-up resistor is
required so that the lines are high since the devices on the I2C
bus are active low. The data is transmitted in the form of
packets which comprises 9 bits. The sequence of these bits are
–
1.Start Condition – 1 bit
2.Slave Address – 8 bit
3.Acknowledge – 1 bit
Start and Stop Conditions :

START and STOP can be generated by keeping the SCL line

high and changing the level of SDA. To generate START
condition the SDA is changed from high to low while keeping
the SCL high. To generate STOP condition SDA goes from low
to high while keeping the SCL high, as shown in the figure
below.
Read/Write Bit :
A high Read/Write bit indicates that the master is sending the data to the slave, whereas a
low Read/Write bit indicates that the master is receiving data from the slave.

ACK/NACK Bit :
After every data frame, follows an ACK/NACK bit. If the data frame is received successfully
then ACK bit is sent to the sender by the receiver.
Addressing :
The address frame is the first frame after the start bit. The address of the slave with which
the master wants to communicate is sent by the master to every slave connected with it.
The slave then compares its own address with this address and sends ACK.
I2C Packet Format :
In the I2C communication protocol, the data is transmitted in the form of packets. These
packets are 9 bits long, out of which the first 8 bits are put in SDA line and the 9th bit is
reserved for ACK/NACK i.e. Acknowledge or Not Acknowledge by the receiver.
START condition plus address packet plus one more data packet plus STOP
condition collectively form a complete Data transfer.
 Interfacing EEPROM with 8051 using I2C

EEPROM
Electrically Erasable Programmable ROM (EEPROM) is a user-modifiable ROM that can be
removed and reprogrammed frequently through the application of higher than the normal
electrical voltage. An EEPROM is a kind of non-volatile memory used in electronic devices
like computers to store small quantities of data that should be saved when power is
detached.
Write Mode
Send the START command from the Master.
Send Device (EEPROM) Address with write mode.
Send Register address in Device (EEPROM), Where we have to access.
Send the Data to the Device (EEPROM).
If you want to send more than one byte, keep sending that byte.
Finally, Send the STOP command.
Read Mode
Send the START command from the Master.
Send Device (EEPROM) Address with write mode.
Send Register address in Device (EEPROM), Where we have to access.
Send again START command or Repeated START command.
Send Device address with Reading mode.
Read the data from Device (EEPROM).
Finally, Send the STOP command.
 START Command
1. Initially, SDA and SCL are High.
2.SDA first goes to Zero.
3.Then SCL goes to Zero.

STOP Command
When SCL is High, We have to toggle the SDA Low to High.
Send Data
Sending Data and addresses are the same
procedure. Here we have to send bit by bit to
the SDA based on the SCL.

Read Data
Reading also the same as write
data. We have to read bit by bit
from the SDA line based on
SCL.
Features I2C Communication Protocol SPI Communication Protocol

Number of wires 2 (SDA and SCL) 4 (MOSI, MISO, SCK, and SS)

Communication type Half-duplex Full-duplex

Maximum number of Limited by number of chip select

Limited by addressing scheme
devices (SS) lines

Data transfer speed Slower Faster

Error handling Improved due to ACK/NACK feature Not as robust

More expensive due to additional

Cost Cost-efficient due to fewer wires
wires
•Zigbee Technology is specially built for control and sensor networks on IEEE 802.15.4
standard for Wireless Personal Area Networks(WPANs), and it is the product from
Zigbee alliance.
•This communication standard defines physical and Media Access Control
(MAC) layers to handle many devices at low-data rates.
•These Zigbee’s WPANs operate at 868 MHz, 902-928MHz and 2.4 GHz frequencies.
•The data rate of 250 kbps is best suited for periodic as well as intermediate two way
transmission of data between sensors and controllers.

Zigbee is particularly designed locally for networks in home environment, and it does
not directly communicate with the servers on the internet.
Zigbee devices are needed to send and collect the data back to the managing server
on the internet with an additional mechanism.
For example, a gateway can be placed to connect a ZigBee network to the Internet.
In a ZigBee network, end devices collect data and send data to the gateway, which then
translates the data from the ZigBee protocol format to Internet Protocol format, and vice
versa.
This allows ZigBee devices to communicate with the servers on the Internet.
•ZigBee is a popularly adopted communication technology in smart-grid systems.
•There are three types of devices in a ZigBee network: coordinator, routers, and end devices.
A coordinator is responsible for establishing, maintaining, and controlling a ZigBee network.
•It allocates network addresses to other nodes that join the network successively. Routers,
sometimes called as Relay nodes, take care of data transmission and have the capability to
extend the scope of a ZigBee network.
•End devices collect data and transmit it to routers or coordinators.
HC-05 is a Bluetooth device used for wireless communication. It works on serial
communication (UART).
It is a 6 pin module.
The device can be used in 2 modes; data mode and command mode.
The data mode is used for data transfer between devices whereas command mode is used
for changing the settings of the Bluetooth module.
AT commands are required in command mode.
The module works on 5V or 3.3V. It has an onboard 5V to 3.3V regulator.
As the HC-05 Bluetooth module has a 3.3 V level for RX/TX and the microcontroller can
detect 3.3 V level, so, no need to shift the transmit level of the HC-05 module. But we need
to shift the transmit voltage level from the microcontroller to RX of the HC-05 module.