INTRODUCTION TO ARM

(32bit RISC PROCESSOR)

1
 Salient Features of ARM

• Developed by Acorn Computers in 1980s –

Acorn RISC Machine

• Renamed as Advanced RISC Machine in

1990

• Used in commercial appliances and

embedded systems

2
 Salient Features of ARM

1. 32 bit Microcontroller
2. 32 bit ALU
3. 32 bit data bus
0000
0100
1000
1100

Aligned data starting with even addressing

3
Salient Features of ARM

• 32 bit address bus

• All instructions are 32 bit

long- perform 32 bit
operations
• All registers are of 32 bit

4
 Salient Features of
ARM
• Harvard model

• Load- Store instruction set

5
 RECAP
• 32 bit microcontroller
• 32 bit ALU
• 32 bit data bus
• 32 bit address bus
• 32 bit long instructions
• HARVARD Model
• 5 stage pipeline
• 7 operating modes
6
ARM ARCHITECTURE
 Salient Features of
ARM
• 5 stage Pipelining

User
Fast
Interrupt (FIQ)
• 7 operating
Interrupt (IRQ)
Modes Supervisor
Abort mode
System 10
MAIN FUNCTION OF PROCESSOR/MICROCONTROLLER

Fetches data/ instruction

from memory
FETCH

PC, Address bus, data bus

Analyse the instruction

DECODE opcode

Control unit and

instruction decoder

ALU, Register, MLA,

EXECUTE Data bus, address bus,
memory,
Fetching an instruction:

Control
unit

• PC is incremented
• Address bus holds the address of memory
• Opcode /data is fetched from memory
after appropriate control signal
• Instruction enters into instruction decoder
and data into
Register
DECODING AN INSTRUCTION

• Analysis the opcode

• Each instruction has binary form of

representation called opcode

• Every instruction has different opcode

• Data enters into register – can be byte,

half word, word

• 16 registers in ARM
 REGISTER
Importance of SIGN EXTEND

EXAMPLE:
+7 in binary 0000 0111
-7 in binary 1111 1001

+7 in 32 bit form – 0000 0000 0000 0000 0000

0000 0000 0111

-7 in 32 bit form – 1111 1111 1111 1111 1111

1111 1111 1001

Look sign bit (MSB) and extend

Note: 8 and 16 bit needs sign extend
• ARM supports TRIADIC
operations

ADD R0,R1,R2

R0=R1+R2

Why Not ??? ADD

R1,R2
• Shifter

SHIFT 0: y0,y1,y2,y3
SHIFT 1: Y1,Y2,Y3,Y0
 • MAC – Multiply and
Accumulate

Multiplier

Multiplicant
• If we need to access subsequent memory

location- address register - base index

addressing

• No ALU involvement

• ARM 7 does not work on floating point

numbers – No division
RECAP
Instruction Decoder

Sign extend

Register
Multiplier
ALU with shifter Multiplica
nt

MAC

Address register
 ARM 9 REGISTERS
Programmers Model
&
OPERATING MODES
OPERATING MODES

(ON SUPERVISOR
RESET)
ort ABORT
Ab
SWI ta
fetch / da
m
Pre gra
IRQ pro

USER MODE

UNDEF
FIQ
System
Calls
SYSTEM
 SUPERVISOR MODE:
On reset (when u switch on ARM) - processor enters into supervisor mode
Example: In Mobile phone BIOS – loads OS from Secondary memory to primary memory
then ICONs then control comes to u (USER MODE)

SYSTEM MODE:
• Protection should be there in processor similar to protection in mobile phone
• System program access system data or user data
• User program cannot access system data/program - changing the APP- not permitted
• When ARM is in supervisor mode, we can access system mode and not in user mode

USER MODE:
• 90% of its life time, ARM is in user mode

• Rearranging icon in mobile phone – go to supervisor and then come back to user mode
• Install an app from play store (SWI – ARM goes to supervisor)
• FIQ and IRQ mode - when appropriate interrupt
comes

• Abort mode – when user access system program

/ data; shut down APP and come back to user
mode

• Undef- when the instructions are not belong to

ARM
7 MODES

SUPERVISOR
USER
SYSTEM
ABORT
IRQ
FIQ
UNDEF
ARM REGISTERS – PROGRAMMING MODEL
 ARM REGISTERS

• 37 registers
• User mode has 17 registers –
r0 to r15, CPSR
Remaining 20 registers-
• 5 register in FIQ
• 5 new SP
• 5 new LR
• 5 new SPSR
 ARM REGISTERS

• 90% of its life time, ARM will be in user

mode
• User and System mode use same
register
• No interrupt is required when
switching between user and system
mode.
 ARM REGISTERS

• 5 modes- FIQ, IRQ, SUPERVISOR, ABORT, UNDEF

• To enter these five modes, we need interrupt
• In ARM, when interrupts come…not only goes to ISR and but
also enters into one of five modes
• When the interrupt occurs, PC have next instruction address
called return address.
• Intel push PC address into stack and when coming back from
ISR return address is popped into pc
 ARM REGISTERS
• In ARM, not using stack
• Arm uses only registers, stack is in memory.
• We need register to store the return
address- Link register
• For example, we get an interrupts IRQ
 CPSR and SPSR
• Suppose an interrupt FIQ occurs before checking the status of
flag in User mode
• The User mode flag status is stored in SPSR (Saved Program
Stack Register) of FIQ mode
• Different mode have its own SPSR register
 Stack operation

Normal operation of
stack

Stack when interrupts occurs when

stack is common
Importance of dedicated SP for
each mode
 IRQ AND FIQ MODE
• In normal interrupt, we need to store the register
value in memory and after interrupt, load data from
memory.

• Storing and loading from memory takes time- affects

pipelining

• Normal interrupt is slow (for normal situation) -IRQ

• In FIQ, we have dedicated r8-r12 ( new set of registers)

– for critical situation
 Recap

• User and system mode uses same set of

register -17 Register

• 5 new SP, LR, SPSR

• Waste time in load and store -5 in FIQ

(r8-r15)
Current Program
Status Register –
Flag register
CPSR - FORMAT
32 bit register
 CPSR -FLAGS
• Gives status of current register
• V, N, Z,C – condition flags

Overflow occurs when range is more than signed number

Range for 8 bit signed number:

-80 +7f
 Negative Flag
When overflow happens, positive number looks like
negative number and vice versa

+40 0100 0000 +23 0010 0011

+42 0100 0010 +32 0011 0010
+82 1000 0010
+54 0101 0100
Note: OVERFLOW =1
N=0 (inversion of Note: Overflow =0
MSB) N=0
 Zero and Carry Flag
• Zero flag – set when ALU result is zero
• Example: 1011+
1000
--------
10011
XOR operation of 25 and 25
C=1
N=0
V=0
Z=0

• Carry flag – set when ALU results in extra bit

 I ,F T

• 2 hardware interrupts- IRQ and FIQ

• Both Interrupts are maskable - can be disabled

when flag =1

• By default, both interrupt flag is 1

• T- thumb state
 Different states of ARM
• Two states in ARM processor – Thumb and Normal

• In normal state- instructions are of 32 bits.

• In thumb -16 bit wide (miniature version of Normal

instruction)

• More bits to express the register operations – Normal

state is powerful eg., mobile phone, laptops

• Cost, space is important than performance – remote control
• For 1KB memory
• Load 256 instruction in ARM
• Load 512 instructions in THUMB
• So if we need to load 512 instructions we need to only one
memory . In normal state we need 2 memory
• When the program is running, program should be in RAM
• Less No. of RAM– power consumption is less

256 1KB
instruction MEMO 512
RY instructions
Normal Vs Thumb State

More code density

Less Cost
Low power
consumption

THUMB

More powerful
More cost
More power
consumption
NORMAL
MODES
 RECAP

• CPSR is a 32 bit flag register

• SPSR –same as CPSR
• 4 flags- C,Z, V, N
• Provision to disable the interrupts- IRQ and FIQ
• T=1 for Thumb state
• Provision to select mode
PIPELINING IN ARM
MAIN FUNCTION OF PROCESSOR/MICROCONTROLLER

Fetches data/ instruction

from memory
FETCH

PC, Address bus, data bus

Analyse the instruction

DECODE opcode

Control unit and

instruction decoder

ALU, Register, MLA,

EXECUTE Data bus, address bus,
memory,
SEQUENTIAL EXECUTION
 Decomposing
sequential
process into
sub operations
with each sub
operations
executing in
dedicated
segments
EXECUTION TIME

No of machine cycle required = K* N

= 3*3 =9

No of machine cycle required = K+(N-1)

= 3*2 =6
NOTE: K= no of stages
N= no of instructions
RISC processor has 5 stage instruction pipeline to execute all the instructions in the RISC
instruction set. Following are the 5 stages of RISC pipeline with their respective operations:
Stage 1 (Instruction Fetch)
In this stage the CPU reads instructions from the address in the memory whose value is
present in the program counter.
Stage 2 (Instruction Decode)
In this stage, instruction is decoded and the register file is accessed to get the values from
the registers used in the instruction.
Stage 3 (Instruction Execute)
In this stage, ALU operations are performed.
Stage 4 (Memory Access)
In this stage, memory operands are read and written from/to the memory that is present in
the instruction.
Stage 5 (Write Back)
In this stage, computed/fetched value is written back to the register present in the
instructions.
Justify only 1 cycle required for each stage in ARM

• Fetch requires 1 cycle – ALL instruction is 32 bit,

data bus is 32 bit and ALU is 32 bit
• Decoding - Simple instruction uses hardwired
control unit – 1 cycle (Hardwired faster than
microprogrammed control)

• Execution - all operation with register, LOAD and

STORE -1 cycle
PIPELINE Hazards
STRUCTURAL No hardware
support

DATA FLOW Instruction

depends on
results of previous

CONTROL
Branch and other
instructions
STRUCTUAL HAZARDS

SOLVE
USING
STALL
DATA HAZARDS

TO
SOLVE
CONTROL/BRANCH HAZARDS

SOLVE USING
STALL
Summarize

• 3 Stage Pipeline in ARM

• No of machine cycle- decreases

• Pipeline Hazards
ARM 9 INSTRUCTION SET
 BRANCH INSTRUCTIONS

Branch Descriptions
Instructio
ns
BAL Branch Always (Unconditional
Jump)
BNV Branch Never (NOP) BRANCH
BCS Branch if carry flag is set Instruction sees
the previous
BCC Branch if carry flag is cleared instructions and
Jumps
BVS Brach if overflow flag is set accordingly
BVC Brach if overflow flag is cleared
BMI Branch if MINUS
BPL Branch if POSITIVE
BEQ Branch if equal
BNE Branch if not equal
Branch Descriptions
Instructions
BHI Branch if higher
Compare first with second number. If first number
is greater then jumps
BHS Branch if higher or same
Compare first with second number. If first number
is greater/same then jumps For Signed
BLO Branch if lower numbers
Compare first with second number. If first number
is lesser then jumps
BLS Branch if lower or same
Compare first with second number. If first number
is lesser/same then jumps
BGT Branch if greater
BGE Branch if greater or equal Unsigned
BLT Branch if lesser numbers
BLE Branch if lesser or equal
DATA MOVEMENT/DATA TRANSFER INSTRUCTIONS
INSTRUCTIONS DESCRIPTIONS OPERATIONS
MOV R0,R1 Move the content of R1 to R0. Here R1 R0 R1
and R0 is 32 bit data

MOV R0, #25H OR Move immediate data 25h to R0.Here R0 25h

MOV R0, #0X25 immediate data is always 8 bit data
MOVS R0,R1 Move content of R1 to R0 and also affects S stands for status register
the flag
MOVEQ R0,R1 Move the content of R1 to R0 if the R0 R1
previous instruction is equal
MOVEQS R0,R1 Move the content of R1 to R0 if the
previous instruction is equal and also
affects the flag after transfer
MOVCS R0,R1 Move the content of R1 to R0 if the carry FLAGS are affected
flag is set by the previous instruction.
MVN R0,R1 Mov NOT R0 (NOT R1)
MVNHIS R0,R1 Mov NOT R0 (NOT R1) carry affected
LOAD/STORE INSTRUCTIONS

INSTRUCTIONS DESCRIPTIONS OPERATIONS

LDR R0, [R1] R0 gets the data from location R0 [R1]
pointed by R1
LDRB R0,[R1] R0 gets the BYTE (8 bit) from location R0 [R1]
pointed by R1
LDRH R0,[R1] R0 gets the half word (16 bit) from R0 [R1]
location pointed by R1
LDRSB R0,[R1] R0 gets the byte from location R0 [R1]
pointed by R1 (for signed number)
LDRSH R0,[R1] R0 gets the half word from location R0 [R1]
pointed by R1 (for signed number)
LDRT R0,[R1] R0 gets the data from location T STANDS PROTECTION
pointed by R1 using this instruction, we
are giving protection that R1
will not point to system data
LOAD/STORE INSTRUCTIONS
INSTRUCTIONS DESCRIPTIONS OPERATIONS
STR R0, [R1] R0 data is stored in location pointed R0 [R1]
by R1
STRB R0,[R1] Byte available in R0 is stored in R0 [R1]
location pointed by R1
STRH R0,[R1] Half word in R0 is stored in location R0 [R1]
pointed by R1
STRSB R0,[R1] Signed byte in R0 is stored in R0 [R1]
location pointed by R1
STRSH R0,[R1] Signed half word R0 is stored in R0 [R1]
location pointed by R1
 ARITHMETIC INSTRUCTIONS
INSTRUCTIONS DESCRIPTIONS OPERATIONS

ADD R0,R1,R2 Add R1 and R2 and store the result in R0. R0=R1+R2
Here R1,R2,R0 are32 bit . No flags are
affected
ADDS R0,R1,R2 Add R1 and R2 and store the result in R0.
Here R1,R2,R0 are32 bit . Flags are affected

ADC R0,R1,R2 Add R1 and R2 along with carry and store 12 ff

the result in R0. Here R1,R2,R0 are 32 bit . 00 01
--------
13 00

SUB R0,R1,R2 Sub R1 and R2 and store the result in R0.

Here R1,R2,R0 are32 bit . No flags are
affected

SUBS R0,R1,R2 Sub R1 and R2 and store the result in R0.

Here R1,R2,R0 are32 bit . flags are affected
INSTRUCTIONS DESCRIPTIONS OPERATIONS
SBC R0,R1,R2 Sub R1, R2 , and borrow .store the result in R0. R0= R1-R2-carry
Here R1,R2,R0 are32 bit . No flags are affected

RSB R0,R1,R2 Reverse subtract R0=R2-R1

RSC R0,R1,R2 Reverse subtract with carry

RSCEQS R0,R1,R2 Reverse subtract with carry if carry flag is set in Affects the flag
previous instruction
MUL R0,R1,R2 Multiply R1 and R2 and store in R0 R0=R1*R2 result will be 32 bit

MLA R0,R1,R2, R3 Multiply R1 and R2 and add R3 then store in R0 R0=(R1*R2)+R3 result will be 32 bit

UMULL R0,R1,R2,R3 Unsigned multiplication long Result will be 64 bit

Multiply R2 and R3 and store in (R0, R1)

SMULL R0,R1,R2,R3 signed multiplication long For signed numbers

Multiply R2 and R3 and store in (R0, R1)

UMLAL R0,R1,R2,R3 Unsigned multiplication and accumulation long (R0, R1)=(R2*R3)+(R0,R1) result will
be 64 bit
SMLAL R0,R1,R2,R3 signed multiplication and accumulation long For signed numbers
 LOGICAL INSTRUCTIONS
INSTRUCTIONS DESCRIPTIONS OPERATIONS

AND R0,R1,R2 Logically AND R1 and R2 and store the result in R0=R1 AND R2
R0
ORR R0,R1,R2 Logically OR R1 and R2 and store the result in R0=R1 OR R2
R0
EOR R0,R1,R2 Logically EOR R1 and R2 and store the result in R0=R1 EOR R2
R0

CMP R0,R1 Compare R0 and R1. the content of R0 and R1 Only flags are affected
are not changed . do R0-R1
CMN R0,R1 Compare negate Only flags are affected
Compare R0 and R1. the content of R0 and R1
are not changed . Do R0+R1

TST R0,R1 TEST Only flags are affected

Do R0^R1
TEQ R0,R1 TEST IF EQUAL Only flags are affected
 STACK OPERATIONS –PUSH AND POP
INSTRUCTIONS DESCRIPTIONS OPERATIONS

STMFA sp!, {R0-R4} M refers to multiple STORE R0 to R4 in stack

STMFA 13!, {R0-R4} F- Full; E-empty Initially SP points to full location
A- ascending; D-descending For ascending, SP get increments
and store R0
So SP+1 =R0
SP+2 =R1
SP+3=R2
SP+4= R4
SMFD 13!, {R0-R4} M refers to multiple STORE R0 to R4 in stack
F- Full; E-empty Initially SP points to full location
A- ascending; D-descending For descending, SP get decrements
and store
STMEA 13!, {R0-R4} M refers to multiple Initially SP points to empty location
F- Full; E-empty
A- ascending; D-descending

STMED 13!, {R0-R4} M refers to multiple Initially SP points to empty location

F- Full; E-empty
A- ascending; D-descending
LDMFA sp!, {R0-R4} M refers to multiple Load R0 to R4 in stack
STMFA 13!, {R0-R4} F- Full; E-empty Initially SP points to full location
A- ascending; D-descending For ascending, SP get value and
decrements
So R0 =SP
R1=SP-1
R2=SP-2
R3=SP-3
LDMFD 13!, {R0-R4} M refers to multiple STORE R0 to R4 in stack
F- Full; E-empty Initially SP points to full location
A- ascending; D-descending For descending, SP get value and
increments
LDMEA 13!, {R0-R4} M refers to multiple Initially SP points to empty location
F- Full; E-empty
A- ascending; D-descending
LDMED 13!, {R0-R4} M refers to multiple Initially SP points to empty location
F- Full; E-empty
A- ascending; D-descending
STACK OPERATION
 HIGH

LO
W
STACK OPERATION
RECAP

• DATA TRANSFER INSTRUCTION

• ARITHMETIC INSTRUCTIONS

• LOGICAL INSTRUCTIONS

• BRANCH INSTRUCTIONS

• STACK INSTRUCTIONS
 ARM
ADDRESSING MODES
ADDRESSING MODES OF ARM

ADDRESSING
MODES

Base
Immedi Register Base with
Register Direct Indirect Relative
ate index scaled
index
ADDRESSING MODE: Manner in which
operand is given in the instruction

IMMEDIATE ADDRESSING MODE

• Operand/ Data is given in the instruction

MOV R0, #25h

Note:
ADD R0, R1, #45h
DATA should be
Opcode+Specified Reg+8 bit = 32 bit 8 bit
REGISTER ADDRESSING MODE

Operand is in Register

MOV R0, R1
ADD R0, R1, R2

DIRECT ADDRESSING MODE

Address is given in the instruction

LDR R0, Amount

STR R0, Amount

AMOUNT is 12 bit
OFFSET (Variable)
INDIRECT ADDRESSING MODE

LDR R0, [R1]

ADDRESS is given using a
STR R0, [R1]
Register

• Acess one/two
location – Direct int arr[5] = {1,2,3,4,5};
X=arr[3];
• Access series of if (i=0; i<4; i++)
location - Indirect Y=arr[i];
i++;
REGISTER RELATIVE ADDRESSING MODE
Normal
LDR R0, [R1,#04H]
ADDRESS is given by the
Let R1=2000; register and
R0= [R1+04] but R1 =2000 displacement
then r0<=(r1)+4
Pre Index

LDR R0, [R1,#04H]!

Let R1=2000;
R0= [R1+04] but R1 =2004

Post Index
LDR R0, [R1],#04H]
Load the content of 2000 and then R1 become
2004
then r0<=(r1)+4
Let R1=2000;
R0= [R1] then R1 =2004
BASE INDEXED ADDRESSING MODE
ADDRESS is given
Normal by SUM of two
LDR R0, [R1,R2] registers
Let R1=2000; R2=1000;
R0= [R1+R2] but R1 =2000; R2=1000;

Pre Index

LDR R0, [R1,R2]!

Let R1=2000; R2=1000;
R0= [R1+R2] but R1 =3000

Post Index
LDR R0, [R1], R2

Let R1=2000; R2=1000;

R0= [R1] but R1 =3000 ; [R1]= 2000;
 BASE WITH SCALED INDEXED ADDRESSING MODE
Normal R2<<02 = 1200
LDR R0, [R1,R2, LSL#02H] ADDRESS is given
R0=[1234] by SUM of two
Let R1=0034; R2=12; registers where
R0= [R1+R2] but R1 =0034; one register is
scaled
Pre Index

LDR R0, [R1,R2, LSL #02H]!

Let R1=0034; R2=12; R2<<02 = 1200
R0= [R1+(R2 <<02)] R1=1234

Post Index
LDR R0, [R1], R2, LSL#02H
R0=[0034]
Let R1=0034; R2=12;
R2<<02 = 1200
R0= [R1] then R1=R1+R2<<2
R1=1234
RECAP

ADDRESSING
MODES

Base
Immedi Register Base with
Register Direct Indirect Relative
ate index scaled
index