CHAPTER 1

INTRODUCTION
1.1 CRYPTOGRAPHY AND AES:
Cryptography—most of us just call it encryption, right. It’s all about keeping our info
safe and sound. Think of it like having a super secure digital vault that only trusted folks can
access. The main goal? Keeping sensitive stuff under wraps, especially when it’s zooming
around online.

At the core of it all is this cool thing called a cryptosystem. Picture it as a secret code that only
a select few can crack. When you take a message and run it through the encryption process,
you end up with something called ciphertext. Basically, just a messy jumble of letters and
numbers that looks like total nonsense to anyone who doesn’t have the right key to decode it.

Looking back, the classic encryption method was called the Data Encryption Standard (DES).
But as tech advanced, DES started feeling pretty old school. It just wasn’t cutting it for
security anymore. That’s when the experts at the National Institute of Standards and
Technology (NIST) came in to create something way stronger.

NIST checked out five different encryption algorithms and picked one created by two
awesome Belgian cryptographers, Joan Daemen and Vincent Rijmen. They originally came
up with a fun name—Pipelined, which was a mash-up of their names—but eventually, it got a
makeover to what we know today as the Advanced Encryption Standard, or AES for short.

AES officially became part of the federal standard back in 2000 (that’s FIPS-197 for those
keeping score), and since then, it’s built up a solid reputation as the gold standard in
encryption. Nowadays, you’ll find AES everywhere—in software and hardware—because it’s
not only fast and effective, but also super secure.

So, AES works as a block cipher. This means it takes data and processes it in fixed-size
chunks—usually 128 bits, or 16 bytes, at a time. When encrypting, the data is scrambled over
multiple rounds—anywhere from 10 to 14 rounds, depending on your key length. Each round
adds another layer of security, making it even harder for anyone to crack the code.
The AES algorithm isn't a piece of software or source code—it's actually a mathematical way
to obscure data. Various people, including the original inventors, have created code that
implements AES encryption. AES relies on a single key for the entire encryption process,
which can come in different sizes—either 128 bits (16 bytes), 192 bits (24 bytes), or 256 bits
(32 bytes). When we mention 128-bit encryption, we're talking about using a 128-bit key. An
encryption key is just a binary string that guides the encryption process. It's important to
protect this key and choose one that's hard to guess since the same key works for both
encoding and decoding. Some keys are generated by dedicated software, whereas others
might come from a passphrase. Reliable encryption systems don’t solely rely on a passphrase
for generating encryption keys.

To effectively guard against side channel attacks, various strategies can be used.
 Avoid using arrays. Compute the values of SBOX and RCon to lessen the chances of
timing attacks.
 Design algorithms and devices to operate with consistent timing intervals, regardless of
the key and plaintext employed. It is essential to comprehend device specifications and
obtain accurate performance data. For example, determining which operation—XOR or
shift—has a slower execution time is important.
 Ensure consistent memory usage; keep in mind that cache is faster than DRAM.
 Perform Key Expansion dynamically rather than storing it in advance and retrieving it
from memory.
 Utilize pipelining to stabilize power consumption within the CPU.
 When possible, leverage specialized chips, as they currently offer significantly better
performance than CPUs and require advanced equipment to address external channel
attacks.

NIST acknowledged the threat posed by side channel attacks when evaluating all the finalists.
In assessing the security of the Pipelined algorithm against side channel attacks compared to
the other four finalists considered by NIST, they concluded:

 Both Pipelined and Serpent depend solely on Boolean operations, table lookups, and
fixed shifts/rotations, making these operations relatively easy to defend against attacks.
 Two fish include addition, which introduces a slightly greater difficulty in terms of
defence against attacks.
  MARS and RC6 employ multiplication/division/squaring and/or variable shift/rotation,
which present significant challenges for defence mechanisms.

1.2 UNDERSTANDING AES CRYPTOGRAPHY (For Text & Images)

AES, or Advanced Encryption Standard, is like having a super-secure lock that keeps
your personal information safe. Whenever you send a quick message to a friend or share a
beloved photo online, AES is silently working behind the scenes to protect your privacy. It
takes your data, cuts it into tidy little pieces—usually 128 bits each—and scrambles those
pieces through a series of steps that change it into a completely unreadable code. The best
part? Only someone with the special key can release it and make it understandable again.
Text Data:
So, how does AES handle your text? It starts by taking your message, known as
plaintext, and breaking it down into those bite-sized chunks. Each chunk gets a complete
makeover with a secret key, undergoing several rounds of transformation—about 10 rounds
for a 128-bit key.
This transformation involves a series of operations: SubBytes, ShiftRows, MixColumns, and
AddRoundKey. Each step adds another layer of complexity, making sure that the final result
is totally nonsensical. What you’re left with is ciphertext, which is essentially a jumbled mess
of characters that would seem like gibberish to anyone not in the loop. But don’t worry—if
you need to get your original message back, AES simply retraces its steps in reverse, using
the same key.
Image Data:
AES works its encryption magic on images in much the same way. Just as your
favorite photos consist of countless pixels—each represented by numbers—it starts by
grouping these pixel values into blocks. These blocks then follow the same AES encryption
process as the text data. Once it’s finished, the image might look odd, almost like a screen full
of static. But there’s no need to panic! When you use the right key to decrypt it, the image
returns to its original, beautiful form. AES treats all data the same; whether it’s text, pictures,
or any other kind of data, it handles everything securely, bit by bit.
1.3 THE POWER OF AES IN DATA SECURITY
So, imagine you’ve got some really important stuff on your computer—like photos,
documents, private messages, you name it. You don’t want just anyone poking around in
there, right? That’s where AES steps in. It’s kind of like having a super high-tech safe for
your files.

 when your info is easily readable, that’s called plaintext. But AES takes that data and
scrambles it into what’s known as ciphertext—basically a jumble of characters that
looks like total gibberish to anyone trying to peek.
 Now, check this out: you need a special key to release that mess and switch it back to
your original info. Without the key, it’s just a bunch of nonsense. It’s kind of like
locking up your diary with a secret code—only you (or someone you trust) knows how
to crack it.
 AES is a big player in the security game. Banks, governments, and all sorts of
organizations that handle sensitive info trust it.
 You don’t need to be a cybersecurity whiz to use it—this tech is built into tons of
devices and apps already.
 And here’s the kicker: it comes in different strengths—like 128, 192, or 256-bit keys—
so you can choose just how secure you want your data to be.
 Even with all that security, it’s super-fast and efficient, which is why it works great on
everything from huge computer systems to tiny gadgets like your phone or smart
devices.
 AES is a really handy way to keep all sorts of digital files safe, whether you're dealing
with text documents, photos, or pretty much anything else you can think of. It takes
your data, chops it up into little pieces, and scrambles everything so that it’s locked up
tight from prying eyes.
 To keep everything secure, AES uses a secret key that messes with the original data.
The readable version of the data is called 'plaintext,' and once it’s all mixed up, it turns
into 'ciphertext,' which is just a fancy way of saying it looks like total gibberish to
anyone trying to sneak a peek.
1.4 OBJECTIVE:

 Lightweight Architecture: I created a super-efficient AES setup that works well with 8-
bit data paths, making it perfect for low-resource IP devices.
 Optimized Register Usage: I added two special register banks to keep plaintext, keys,
and intermediate results close at hand, which really boosts memory efficiency.
 Logic Reduction: I managed to fit the Shift-Rows operation right into the State-Register,
which brought down the overall logic and resource use.
 Pipelining for Delay Reduction: Applied pipelining techniques within the AES design to
reduce processing delay, improving throughput and overall performance.

CHAPTER 2
LITERATURE SURVEY:
2.1 J. Zhou and M. Yung, Eds, “AES against first and second-order differential power
analysis Applied Cryptography and Network Security”, vol. 6123, Springer-Verlag, pp.
168–185. Berlin, Germany, April,2012
Differential Power Analysis (DPA) is a handy and effective way to attack cryptographic
implementations, especially when you're working with limited resources. In this paper, we
show how you can take advantage of certain intermediate values from the internal rounds. By
fixing certain bytes of plaintext or ciphertext, you can really get into how the encryption
works. We break down five key principles about the DPA weaknesses we found in
unprotected AES implementations, plus a few guidelines for protected AES versions too. This
helps determine which AES operations can be at risk for both first and second-order DPA
attacks. To put this into perspective, we look at two AES implementations that have different
countermeasures to boost their resistance against power analysis. Despite their defenses, we
found they’re still not entirely safe from DPA. In the end, our conclusion is clear: to keep a
software implementation of AES secure against first and second-order DPA attacks, you
really need to protect at least the first two and a half rounds and the last three rounds of AES.

2.2 Hossein Kouzehgar, Meisam Nesary Moghadam and Pooya Torkzadeh,” : A High
Data Rate Pipelined Architecture of AES Encryption/Decryption in Storage Area
Networks”, 26th Iranian Conference on Electrical Engineering (ICEE2018), May, 2018
AES is one of the most popular encryption algorithms out there. When you implement AES
on an FPGA, it can vary based on what you need it for and how complex the internal parts
are. In our research, we took a close look at the different blocks in the AES algorithm and
proposed a model for both the encryption and decryption components on FPGA. We used a
pipelined structure to crank out high throughput while keeping the area minimal. To hit the
target throughput rate for AES in a data storage network, we combined memory usage with
GF(2^4). We also created a specialized multiplexer-based architecture for the S-Box block
that uses the fewest slices possible. Our results from the encryption and decryption
implementation on the Xilinx Virtex5 were impressive, hitting a throughput of 60 Gb/s and
running at a frequency of 460 MHz, which beats previous works by a long shot.

2.3 Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong and
Bah-Hwee Gwee, "A High Throughput and Secure Authentication-Encryption AES-
CCM Algorithm on Asynchronous Multicore Processor", IEEE Transactions on
Information Forensics and Security, June, 2018
In this paper, we’re really excited to share a new way of authenticating and encrypting
data, using something we call an asynchronous Multicore Processor (AMP-MP). What’s our
endgame? To speed things up while keeping everything secure with the Advanced Encryption
Standard in Counter and Chaining Mode (AES-CCM). So, what’s neat about our AMP-MP?
It’s based on four key ideas. First off, we’re using matrix multiplication in GF(28) to combine
16 pieces of plaintext into one, which boosts the authentication speed by a huge 32 times for
both the sender and receiver. Next, we designed a system where three AES encryptions
happen on three different cores. This balances their energy use and cuts down the link
between data processing and any physical leaks by over three times. Then, we share some
AES-CCM results between cores to keep things random and tough for side-channel attacks to
grab anything, which ups our security another three times. Finally, we’ve got this clever trick
to throw off pattern attackers by adjusting the keys using S-Box byte-key transformation. We
put our AMP-MP through its paces on an 8-bit asynchronous 9-core processor made with a
65nm CMOS process. Results? An authentication speed of 13.54 Gbps, and with encryption,
we’re hitting 8.32 Gbps—faster than anything we’ve seen so far by 17 and 70 times,
respectively. Plus, when it comes to power usage and electromagnetic side-channel attacks,
our secret key stays strong even after 5×10^5 traces, making it about 17 times more secure
than regular ASIC AES-CCM setups.

2.4 J. Zhou and M. Yung, Eds, "AES against first and second-order differential power
analysis Applied Cryptography and Network Security": vol. 6123, Springer-Verlag, pp.
168–185. Berlin, Germany, Jan, 2010
In this paper, the authors dig into how certain intermediate values from the inner rounds of
AES can be exploited when specific bytes of plaintext or ciphertext are fixed. They lay out
five important principles regarding DPA vulnerability that can snag AES setups if they’re not
guarded properly, and they offer tips for boosting AES implementation security. These tips
emphasize the parts of AES that are most vulnerable to first and second-order DPA attacks.
To drive the point home,they tested two different AES setups with various power analysis
countermeasures and unfortunately found there still some cracks when it comes to DPA.
2.5 D. Gu, J. Li, S. Li, Z. Ma, Z. Guo, and J. Liu,” Differential fault analysis on
lightweight block ciphers with statistical cryptanalysis techniques”, Fault Diagnosis and
Tolerance in Cryptography (FDTC), September 2012
Differential fault analysis is one of the top side channel attack techniques that really threatens
the security of block ciphers. But here’s the catch: it usually needs a faulty encryption from
either the second-to-last or third-to-last round and doesn’t really work for faults happening in
the middle rounds. This paper dives into some cool attacks that blend differential fault
analysis with statistical cryptanalysis methods specifically aimed at lightweight ciphers.
Instead of getting bogged down in theoretical stuff, we use practical statistical cryptanalysis
techniques and exploit some weaknesses in bit-permutation that many lightweight block
ciphers have when they face fault attacks

2.6 Ho Keun Kim1&Myung Hoon Sunwoo,” Low Power AES Using 8-Bit and 32-Bit
Data path Optimization for Small Internet-of-Things (IoT)”, Journal of Signal
Processing Systems,Mar, 2019
This study introduces a low-power AES that’s perfect for small-scale IoT applications.
What’s neat about this AES is that it uses both 8-bit and 32-bit data paths, making sure it
keeps power usage low while being compact. The 32-bit path is used just in the Mix Columns
step, while the 8-bit path handles other parts like Sub Bytes, Byte Permutation, Add Round
Key, and Key Expansion. Plus, we roll out optimized versions of Sub Bytes and Mix Columns
to conserve even more power in a small area. For optimizing Sub Bytes, we optimize the
process block by block to keep the area small. With Mix Columns, we introduce a 32-bit path
that uses the proposed 0 × 02 and 0 × 03 multipliers. The AES design we discuss here is built
in Verilog-HDL and synthesized using the Samsung 65 nm standard cell library. The AES
implementation is equivalent to about 5400 2-input NAND gates and shows a power
consumption of 10.01 μW (@0.9V) at a frequency of 10 MHz.

2.7 A. Shreedhar, K.-S. Chong, N. K. Z. Lwin, N. A. Kyaw, L. Nalangilli, W. Shu, J. S.

Chang, and B.-H. Gwee,” Low Gate-Count Ultra-Small Area Nano Advanced
Encryption Standard (AES) Design”, IEEE International Symposium on Circuits and
Systems (ISCAS), Feb,2019
So, we’ve come up with a cool Nano AES design that’s super compact and uses way fewer
gates. How did we pull this off? First off, we’re all about efficient design, so we reused an 8-
bit Substitute-Box (S-Box) and a 32-bit Mix Column circuit throughout the AES process,
which really saves space. Then, we mixed things up by integrating input flip-flops (FFs)
directly into our data transfer setup, letting the Mix Column circuit outputs go straight to the
initial 32-bit input FFs without extra multiplexers getting in the way. We also made the Shift
Row operation smoother by mapping the data sequence right to the input FFs as we worked
through the S-Box and Mix Column processes. Plus, we added separate XOR gates for the
Add Round and Key Expansion steps. Thanks to these strategies, our design only needs 1457
gates and takes up a tiny 100um×100um area using a 65nm CMOS process. When we stack it
up against previous AES designs at 65nm CMOS, ours has the smallest normalized area and
is actually 10% more compact than the runner-up. We think it’s perfect for ultra-small
applications, especially in the biomedical field.

2.8 Karim Shahbazi, Seok-Bum Ko,” High throughput and area-efficient FPGA
implementation of AES for high-traffic applications”, IET Computers & Digital
Techniques, Aug,2019
We’re excited to share our take on implementing the advanced encryption standard-128
(AES-128) using a high-speed field-programmable gate array (FPGA). AES is a trusted
symmetric key encryption method that packs a punch against a variety of attacks, making it a
great fit for tons of applications. Our main focus here is building a cryptosystem that boosts
both throughput and FPGA efficiency (FPGA-Eff) for high-traffic scenarios. To crank up the
throughput, we used techniques like loop-unrolling and pipelining both inside and outside.
The Sub-Bytes function in AES is notorious for being resource-heavy and slow, so we came
up with a new affine transformation that blends inverse isomorphic with affine transformation
to lighten the load. We even reworked some parts of AES; for instance, we swapped the order
of Shift-Rows and Sub-Bytes in the first nine rounds, combining Shift-Rows with Add-
Round-Key for efficiency. To keep latency consistent, we split the Mix-Columns operation
into two phases. We ran the AES algorithm in counter mode on the Xilinx Virtex-5 platform
using VHDL, and the outcome? A throughput of 79.7 Gbps, an FPGA-Eff of 13.3 Mbps/slice,
and it runs at a frequency of 622.4 MHz. Compared to other designs out there, our
implementation improves data throughput by 8.02% and boosts FPGA-Eff by 22.63%.
2.9 Arash Reyhani-Masoleh, Mostafa Taha and Doaa Ashmawy,” New Area Record for
the AES Combined S-box/Inverse S-box”, Int. J. Internet Technol. Secured Trans., vol.
4, no. 1, pp. 12–25,Dec,2018
So, the AES uses this neat combined S-box/inverse S-box for both encrypting and decrypting
data. As of now, the most efficient version of this design stems from Canright’s work back in
2005. Even though there have been a lot of tweaks and optimizations suggested for the S-box
over the years, the combined S-box/inverse S-box hasn’t really gotten much love. We're
shaking things up a bit by using a new tower field and really fine-tuning every part of this
combined setup for that field. When we looked into complexity and checked out how our
design performed with ASIC implementations in CMOS technologies of 65nm and Nan Gate
15nm, the results showed that we outperformed existing options in both area and speed.

2.10 J. Zhou and M.Yung, Eds,”AES against first and second-order differential power
analysis Applied Cryptography and Network Security”, vol. 6123, Springer-Verlag, pp.
168–185. Berlin, Germany,2010
In this paper, the authors reveal that some values from the inner rounds can be manipulated by
using tactics like fixing certain plaintext or ciphertext bytes. We outline five key insights into
DPA vulnerabilities in unprotected AES setups, and a few general tips on the DPA
vulnerabilities of protected AES implementations. These principles emphasize which parts of
AES are vulnerable to both first and second-order DPA attacks. To put our findings to the
test, we conducted attacks on two AES implementations that had countermeasures intended to
fend off power analysis, and surprisingly, they were still susceptible to DPA.

2.11 D. Gu, J. Li, S. Li, Z. Ma, Z. Guo, and J. Liu,” Differential fault analysis on
lightweight block ciphers with statistical cryptanalysis techniques”, Fault Diagnosis and
Tolerance in Cryptography (FDTC), September 2012
Differential fault analysis is one of the sharpest side-channel attack approaches that can really
jeopardize the security of block ciphers. In this paper, we combine differential fault analysis
with statistical cryptanalysis techniques against lightweight ciphers. Instead of just talking
theory, we actually dive into the practical applications of statistical cryptanalysis methods,
using the weaknesses in the bit-permutation methods that many lightweight block ciphers use
when under fault attacks.
2.12 Ho Keun Kim1&Myung Hoon Sunwoo,”Low Power AES Using 8-Bit and 32-Bit
Data path Optimization for Small Internet-of-Things(IoT)”, Journal of Signal
Processing Systems, 2019
This paper presents a low-power AES that’s personalize-made for smaller applications, like
those tiny IoT devices. The AES we’re proposing takes advantage of both 8-bit and 32-bit
data paths to keep power usage low and fit into small spaces. We use the 32-bit data path for
just the Mix Columns stage, while the 8-bit path handles the other blocks, including Sub
Bytes, Byte Permutation, Add Round Key, and Key Expansion. We’ve optimized Sub Bytes
and Mix Columns to minimize power consumption while keeping a tiny footprint. To simplify
Sub Bytes, we’ve simplified the algorithm step-by-step.
 CHAPTER 3
EXISTING SYSTEM

3.1 ENHANCING AES SECURITY WITH SDRR:

So, we've decided to team up SDRR with good old AES-128 to really beef up our
cryptographic hardware and ward off those sneaky attacks lurking out there. By blending
AES-128 with SDRR, our system can handle random data like a champ throughout the clock
cycle, and honestly, that’s pretty cool. The best part? This combination of random data with
the real stuff seriously boosts our security, making it much trickier for any unauthorized
access to sneak in.
These days, with data breaches and cyber threats popping up everywhere, having solid
security is more critical than ever. That’s why we brought SDRR into the mix. We’re not just
stepping up our system’s performance; we’re also making sure that our hardware is equipped
to tackle those tricky hacking attempts that always seem to be lurking around.
Every choice we make is backed by the latest research in cryptography, showing that we’re
serious about getting it right. This smart mix of random and real data adds an extra layer of
complexity that makes it a lot tougher for shady characters to spot and exploit any weak spots.
Eventually, we want our users to feel completely secure, knowing their info is backed by top-
notch technology and clever engineering. As we keep refining our methods, we’re committed
to pushing the limits of what’s possible in secure data processing. When you check out the
block diagram, it gives a clear view of the AES architecture, making it easier to understand
some of the complexities behind the encryption process.
In an online world filled with potential threats, the Advanced Encryption Standard (AES)
really stands out as a reliable choice. Its strong track record and solid security measures make
it a must-have for any organization that’s serious about protecting their data.
AES plays a key role in today’s cryptography, balancing security, efficiency, and flexibility to
ensure information stays safe across different platforms and services.
3.2 EXISTING BLOCK DIAGRAM:

Fig 3.1: Existing System Block Diagram

AES encryption system works in a neat and tidy way. Right in the middle, you've got
the main module that handles the data encryption, pulling together different tasks like
substitution, permutation, and mixing. Around this core, there are special register banks that
safely store the plaintext inputs, the encryption keys, and any intermediate results, making
sure everything runs smoothly.
You can see the input and output interfaces, which show how the data gets in and out of the
system. They’ve designed it to do things in parallel, which cuts down on any delays and
boosts performance. Plus, there’s some control logic in place to manage how everything flows
during the encryption process. They’ve also built in some safety features to guard against side
channel attacks—it’s super important to keep everything secure.
3.3 EXISTING SYSTEM ALGORITHM FOR SDRR IN AES-128
FRAMEWORK
This algorithm outlines the implementation of Secure Dynamic Random Response
(SDRR) within the AES-128 framework, specifically designed to strengthen cryptographic
hardware against power analysis attacks (PAAs).

1. Initialization
 Define input parameters:
 plaintext: 128-bit data for encryption.
 key: 128-bit encryption key.
 Activate SDRR to generate random values for enhanced security.
2. Key Expansion
 Derive round keys from the original key using the AES key schedule, ensuring
strong encryption for each round.
3. AES Operation
Set the number of rounds `Nr = 10`. For each round from `i = 0` to `Nr - 1`:
 AddRoundKey: XOR the current state with the round key.
 SDRR Integration:
 Generate and mix `random_data` with actual data to boost security.
 Use a combinational path to process both types simultaneously.
 SubBytes: Substitute each byte in the state using the S-box.
 ShiftRows: Shift rows of the state for enhanced diffusion.
 MixColumns (if not the final round): Combine bytes in each column for further
data obfuscation.
 Dynamic Timing Adjustment: Maintain consistent timing to prevent timing
attacks.
4. Final Round (i = Nr)
 AddRoundKey: Combine the state key with the last round key.
 SubBytes: Apply the S-box substitution.
 ShiftRows: Execute the final row shift.
 Output Generation: Produce the encrypted ciphertext.
 5. Post-Processing
 Clear sensitive data from memory to prevent leakage and securely store the
ciphertext.

3.4 EXISTING SYSTEM TECHNIQUE:

So, we’re currently using this pretty awesome technique called Secure Energetic
Random Read (SDRR) in our AES setup. It’s really stepping up how well our cryptographic
hardware can tackle power analysis attacks (PAAs).

Here are some key features:

 Consistent Data Handling: We’ve set it up so that random data gets treated the same way
during every single clock cycle. This helps us cover up any patterns that hackers might try
to take advantage of.
 Mixed Data Strategy: We’re blending random and actual data to enhance both
combinational and sequential logic, keeping any leaks from happening due to shifts in
power usage.
 Strong Security Design: The SDRR method uses advanced algorithms to really strengthen
AES encryption’s defenses against side channel attacks, ensuring things stay secure even
under a lot of scrutiny.
 Real-Time Adaptive Response: This setup adapts to new threats instantly, making our
cryptographic processes even more reliable. Overall, the SDRR method not only boosts
our AES encryption but also raises the bar for data security in today’s environment.
3.5 EXISTING SYSTEM ADVANTAGES
 AES is designed to be secure against various attack vectors, including brute force
attacks, differential cryptanalysis, and linear cryptanalysis.
 Due to its efficient design, AES can achieve high performance on both software and
dedicated hardware implementations.
 Used for encrypting sensitive data in databases, file systems, and cloud storage.
 Enhanced Security: Strengthened against power analysis attacks via SDRR
integration.
 Optimized Resource Usage: Efficient 8-bit architecture tailored for low-power IoT
devices.
 Improve Performance: Pipelining reduces processing delays for faster encryption.

3.6 EXISTING SYSTEM DRABACKS:

 Increased Complexity: SDRR complicates implementation and maintenance,
potentially raising costs.
 Resource Demands: Advanced security may increase resource use, impacting low-
power IoT devices.
 Performance Issues: Enhanced security can introduce latency, slowing down system
performance.
 Debugging Challenges: Mixing random data with plaintext complicates issue
resolution, especially for less experienced users.
 Potential Vulnerabilities: SDRR may expose new threats, requiring ongoing updates.
 Variable Effectiveness: Inconsistent performance across SDRR implementations
complicates standardization.
 User Awareness: Lack of understanding about encryption can create a false sense of
security, highlighting the need for education.
 CHAPTER 4
PROPOSED SYSTEM

4.1 PROPOSED SYSTEM ENCRYPTION DESIGN:

So, here’s the deal with how AES works: it’s all about this masked AES core and
some clever clock gating that helps create those encryption masks. The masked AES core
takes care of the 128-bit encryption, and it does this over 10 cycles – one round per cycle.
Instead of going all out with a totally unrolled setup, we reuse the hardware for each round to
save some space. You can check out how this looks in the figure below. First off, we take the
original data (that’s the plaintext) and put it through a random mask. Then, we send both the
masked plaintext and that mask to the “Nano AES core,” which uses the secret key to encrypt
the masked data. What we get at the end is the masked ciphertext, which then goes into the
module to give us the final ciphertext.
 To keep things simple with the logic, we’ve built the Shift-Rows operation right into
the State-Register.
 We’re also optimizing the Sub-Bytes block by sharing it between the key expansion
phase and the encryption phase, so we don’t waste resources.
 For the Mix-Columns part, we designed an optimized 8-bit block that works with 8-bit
inputs and outputs, sticking to the 8-bit data path structure, which is then handled by
Add-Round-Key. So that's nice; we send the results to Add-Round-Key one byte at a
time.
 Unlike a 32-bit Mix-Columns approach, we don’t need to store results in registers or
upgrade the Key-Register data path to 32 bits.
 To save on power, we incorporated the clock gating technique across different
components, which really helps cut down on power usage.

Throughout the design, we used clock gating to bring down energetic power consumption.
This is applied specifically to the State-Register, the internal registers of Mix-Columns, the
Key-Register, and RCON. For example, there’s a decent power saving during the key
expansion phase since we can turn off the clock for the State-Register and Mix-Columns –
these guys aren’t doing anything during key expansion anyway.
4.2 PROPOSED SYSTEM BLOCK DIAGRAM:
The AES design is pretty cool, especially when you think about all those little gadgets
we lug around every day. At its heart is the masked AES module, which is awesome at
handling 128-bit encryption in just 10 cycles. It’s designed to make the most out of those tight
resources we often see in smaller devices. To keep things organized and save on space, we’ve
cleverly built in key operations like Shift-Rows right into the State-Register. This not only
saves precious room but also keeps everything running smoothly. And the best part? We’ve
shared the Sub-Bytes block between the key expansion and encryption phases, cutting out any
unnecessary overhead that might slow things down during operation.
Now, let’s chat about conserving power. We really believe in using smart strategies, like
clever clock gating techniques that let us switch off any components that aren’t in use. This
method brings some serious energy savings! But it’s not just about being power-efficient; our
design also lays down a solid foundation for secure image encryption and decryption. It’s a
big step forward in protecting our data and really shows how innovation can take our security
to the next level. So, when you’re using your everyday devices, you can feel a bit more at ease
knowing there’s a strong encryption system working its magic behind the scenes to keep your
info safe.

Fig 4.1: Block scheme of the proposed

4.3 PROPOSED APPLICATION BLOCK DIAGRAM:
AES design,It’s all about making encryption super-efficient, especially for those small
devices we use every day. Our main goal is pretty clear: keep power usage low while making
sure everything stays secure. To achieve this, we’ve smartly built in some essential steps like
Shift-Rows right into the State-Register. This saves space and helps things run smoothly,
which is a big plus. And here’s the cool part—we're using smart clock gating techniques to
save energy by turning off parts of the system that aren’t being used while processing. This
approach really helps us make the most of our resources and takes secure image encryption
and decryption to a whole new level.
So, this is a big step forward in building reliable and effective cryptographic systems.
Plus, this design is super user-friendly, which means we can achieve fast processing speeds
when it counts, especially for real-time applications. Power efficiency matters a lot for
devices with limited battery life, like IoT gadgets and smartphones. By fine-tuning the
encryption process, we’re aiming for a smooth user experience without compromising on
security. These updates could open up new opportunities for our technology, from finance to
healthcare and more. As we move forward, finding the right balance between ease of use and
strong security will be essential in our digital world.

Fig 4.2: Block Diagram of the proposed system Application

4.4 PROPOSED SYSTEM TECHNIQUE:
This new system, It brings in a cool low-power design for Advanced Encryption
Standard (AES), and it’s all about making image encryption super-efficient. That’s a big deal
for keeping our data private in today’s digital age.
At the core of it, there’s this nifty AES module that can handle 128-bit encryption in just 10
cycles. That’s a fantastic win for both speed and resource conservation. This really matters for
mobile devices and IoT gadgets, where every little bit of battery life is essential.
By combining high performance with energy efficiency, this AES setup makes secure image
processing a breeze. Users can keep their sensitive visuals safe without compromising the
overall experience. It’s a game-changing approach that tackles today’s security challenges and
paves the way for future innovations in protecting our data.
4.5 PROPOSED ALGORITHM:
The system diagram we're proposing shines a light on a really innovative low-power
AES design that's specifically created for smaller applications, and it puts a strong emphasis
on performing encryption efficiently. At its heart, there's a masked AES module that pulls off
impressive 128-bit encryption in just 10 cycles, which is fantastic because it really optimizes
using resources. One of the key operations you’ll notice, like the Shift-Rows operation, has
been cleverly integrated into the State-Register itself. This thoughtful arrangement maximizes
the space usage, making the whole setup much more compact.
What's more, by employing some advanced clock gating techniques, we're able to save on
energy. This is done by turning off unnecessary components while they're not needed during
processing. This innovative strategy not only enhances security for tasks like image
encryption and decryption but also establishes a new standard for what energy-efficient
cryptographic systems can achieve. It’s pretty exciting to think about how these advancements
can reshape the future of digital security.
 Fig 4.3: Proposed system Algorithm

4.5 PROPOSED SYSTEM ADVANTAGES:

 Design focused on low power consumption
 AES encryption module with low energy usage and high throughput, offering
various security levels
 Strong security featuring an optimal attack prevention strategy
 Protects sensitive information from potential attacks.
 Quickly encrypts data while conserving energy.
 Key operations are integrated to make the design compact, fitting well into small
applications.

CHAPTER 5
 PROJECT DESCRIPTION

5.1 AES AND THE ROLE OF RELIABLE CRYPTOGRAPHY:

Cryptographic systems are super important for keeping sensitive stuff safe in our modern
world. We're talking about secure healthcare networks, smart grids, cool textiles, and home
automation systems. This whole area of cryptography is tied up with cryptology and
cryptanalysis, so it's quite the field.
Now, there are some neat techniques that folks use—like microdots or blending text with
images—to hide data when it's stored or sent around. But nowadays, cryptography is mostly
about turning readable text (that's the plaintext) into a scrambled version (known as
ciphertext), which is what we call encryption. And then there’s decryption, which is just the
process to turn it back to readable text again. The people who work in this field and make all
of this happen are called cryptographers. But remember that just because we have
cryptographic systems doesn’t mean they’re foolproof. Things can still go haywire
sometimes!
Take Very Large-Scale Integration (VLSI) systems—if there’s a defect, it can throw a wrench
in smart applications that rely on these systems. There's a ton of research out there aimed at
figuring out how to catch issues in cryptographic methods like elliptic curve cryptography and
the Advanced Encryption Standard (AES). By focusing on reliability and fault tolerance when
putting these systems together, we can make sure that even if something goes wrong, the key
cryptographic frameworks can keep chugging along smoothly.
Modules:
 Substitution Box (S-Box)
 Multiplier in GF (2^4)
 Shift Rows operation
 Mix Columns operation
 Add Round Key
 Transformation matrix and its inverse
 Key Expansion Module
 AES Encryption and Decryption process (Flow Chart)

5.2 MODULE DESCRIPTION:

5.2.1 GF (2^4) MULTIPLIER
So, here’s the deal with Sub Bytes: it’s a nonlinear transformation that uses 16 S-
Boxes to swap out bytes. This whole process is based on finding the multiplicative inverse in
the Galois field GF(2^4), and then we follow that up with an affine transformation. Now,
while Galois fields of the same size might seem similar, the complexity can really change
depending on how you represent those elements. To make things easier for hardware, we use
composite field arithmetic. When it comes to finding the multiplicative inverse in GF(2^8),
we actually need three GF(2^4) multipliers. These are constructed using three GF(2^2)
multipliers, which involve some 4 XOR gates and a constant multiplier θ. This θ takes two
bits as input and outputs results based on some smart bitwise tricks. If you’re curious about
how to build this circuit.

Fig 5.1: GF (24) Multiplier

5.2.2 ADDROUNDKEY TRANSFORMATION:

 In the AddRoundKey transformation, we tweak the state by applying a round key
through a Bitwise XOR operation. Check out the illustration below that shows how the
AddRoundKey process works. This step stays the same whether we’re encrypting or
decrypting.

Fig 5.2: Addroundkey Transformation

5.2.3 SHIFT ROWS TRANSFORMATION:

The Shift Rows operation is where we cyclically shift the bytes in each row of the
State. The first row doesn't budge, while the second, third, and fourth rows shift one, two, and
three bytes to the left, respectively. You can see the details in the figure. And don’t forget, the
inv Shift Row reverses the process.

Fig 5.3: Shift Rows

5.2.4 MIX COLUMN TRANSFORMATION (INV MIX COLUMN):

 The Mix Column transformation is executed separately for each column of the state.
Each column is viewed as a four-term polynomial over GF (2^8) and is multiplied by
a(x) modulo (x4 + 1) where a(x) = {03}x3 + {01}x2 + {01}x + {02}

This transformation can be expressed in matrix form as

Fig 5.4: Mix Column

5.2.5 TRANSFORMATION MATRIX & INVERSE TRANSFORMATION MATRIX:

So, a transformation matrix (M) is used to switch things up from the binary field to
this composite field called GF((23)3). Then, we do some operations in these composite fields
to get the inverse. Once we have that, we flip it back to the binary field using an inverse
transformation matrix (M-1). In the end, we take out the two most and least important bits to
create that uneven structure we want for the substitution box.
 Fig 5.5: Transformation Matrix & Inverse Transformation Matrix:

5.2.6 SUBSTITUTION BOX (S-Box):

So, during the Sub Bytes operation, there’s this cool nonlinear swap
involving bytes. Each byte in the input state gets switched out for a different
byte according to the substitution box, which we call the S-box.
S BOX Truth Table:

Table 5.1 S-Box

5.2.7 KEY EXPANSION UNIT:

So, here’s the deal: the key expansion works pretty much like the encryption part, but
with some cool upgrades for the S-boxes and how we load info into the key registers
depending on the key size. To keep things efficient and lower power use, we mask the S-box
inputs with constant values when they’re not doing anything. The expanded key is generated
on the fly and goes straight into the key registers to make the most of the space we have. The
key expansion module has two shift registers set up in a 4×4 grid, plus there’s a key
transformation part that holds four S-boxes and does an XOR operation.

Fig 5.6: Key Expansion Unit

5.2.8. AES FLOW CHART:

 Fig 5.7 AES Flow Chart

Overview of AES Algorithm Flow Chart:

1. Start: Initiate the process of encryption or decryption.

2. Input Data & Key: Prepare the data (either plaintext or ciphertext) along with the

secret key.

3. Initial Add Round Key: Combine the data with the key using the XOR operation to

mask it.

4. Main Rounds (10, 12, or 14 rounds depending on the key size):

 Substitute Bytes: Use the S-box to substitute the bytes.

 Shift Rows: Shift the rows within the data matrix.

 Mix Columns: Blend the columns to improve diffusion.

 Add Round Key: Apply XOR between the data and the round key.

5. Final Round: Repeat the first three steps (excluding Mix Columns) to finalize the

encryption.

6. Output Ciphertext: Generate the encrypted data.

 7. Decryption Process: Reverse the procedures to obtain the original plaintext through

inverse operations.

8. End: Complete the process, having protected the data.

This summary effectively captures the key steps of the AES algorithm,

emphasizing its systematic approach to ensuring data security.

CHAPTER 6
 AES ALGORITHM

6.1 THE BASICS OF SECURE ENCRYPTION:

AES, short for Advanced Encryption Standard, is a symmetric block cipher. This
means it uses the same key for both encrypting and decrypting data. It works with a fixed
block size of 128 bits and supports key lengths of 128, 192, or even 256 bits. Unlike its
predecessor, DES (Data Encryption Standard), which sticks to fixed sizes of 64 bits for blocks
and 56 bits for keys, AES is built on the Rijndael algorithm. This gives a lot more room for
flexibility when it comes to key sizes.

AES does its thing by processing data in parallel, using substitutions and permutations. This is
different from the Feistel structure that DES uses. Depending on the key length, AES runs
through a certain number of rounds: 10 for 128-bit keys, 12 for 192-bit keys, and 14 for the
256-bit ones. In each of these rounds, a new round key is taken from the original key.

Pipelined is another symmetric iterated block cipher, matching AES in terms of block and key
length. This one organizes its transformations in a rectangular array. When it comes to
decryption, Pipelined simply reverses the encryption steps by applying inverse
transformations in the opposite order.

Overall, AES is the go-to choice for many because of its strong security and efficiency,
especially when using that common 128-bit key size.

Rijndael was designed with some key features in mind:

• It should resist all known attack methods.
• It's efficient and can work on various platforms with minimal code.
• The design is straightforward.
The process kicks off with an Add round key phase, followed by nine rounds that have four
stages each, then a final round with three stages. This is how both encryption and decryption
work, but during decryption, each stage does the opposite of what it does in encryption.
The four stages are as follows:
1. Substitute bytes
2. Shift rows
3. Mix Columns
4. Add Round Key

In the final round, we skip the Mix Columns step. For the first nine rounds of decryption,
here's what happens:
1. Inverse Shift rows
2. Inverse Substitute bytes
3. Inverse Add Round Key
4. Inverse Mix Columns

Fig 6.1: AES Architecture

Take a look at the diagram below, which breaks down how AES encryption and decryption
work. When it comes to decrypting AES ciphertext, the steps are pretty much the same as
encryption, just flipped around. Each round involves four key steps:
 Add the round key
 Mix up the columns
 Shift the rows
 Substitute bytes

Fig 6.2: AES Encryption and Decryption Process

So, let’s talk about the Advanced Encryption Standard, or AES for short. It’s a really popular
way to keep your data safe by scrambling it up in several steps. First off, we have encryption,
where we take our readable message, known as plaintext, and mix it up with a secret key
using something called XOR (exclusive OR). This first step, called AddRoundKey, basically
locks the message into the key right away. Then, the data goes through a bunch of rounds,
which can be 10, 12, or even 14 rounds depending on how long the key is. Each round has
transformations that mess with the data and spread it out. We’ve got things like SubBytes,
where we swap each byte using a special S-box; ShiftRows, which slides the rows of our data
to the left; and MixColumns, which mixes up the columns with some math magic. After each
round, we add another round key that's derived from our original key. The last round skips the
MixColumns step but still does the SubBytes, ShiftRows, and AddRoundKey business,
leaving us with the final output: the ciphertext, which is just the scrambled data.

Now, when it comes to decryption, it’s like a dance in reverse. We just go back through all
these steps to get back to the original plaintext from the ciphertext. It kicks off with an
AddRoundKey operation using the final round key, and then we do a series of backtrack
moves. First, we have InvShiftRows, which shifts those rows back to their original spots; then
InvSubBytes, which swaps the bytes back; and finally InvMixColumns, which separates the
columns again. Just like in encryption, we apply a round key after each stage. The final
decryption round skips the InvMixColumns step and finishes off with InvSubBytes,
InvShiftRows, and one last AddRoundKey with the original key. This careful reversing means
that only someone with the right key can decode the message, keeping it all private and
secure.

6.2 APPLICATIONS:
 Data goes through encryption and decryption
 Protection system is in place
 Digital data is protected
 Security for computers and networks is set up
 CHAPTER 7
SIMULATION IMPLEMENTATION

7.1 VERILOG HDL IN DIGITAL DESIGN:

Verilog HDL is part of a group known as Hardware Description Languages (HDLs).
These languages are designed to describe digital systems, like computers and their
components. You can represent digital systems at various levels. For example, an HDL can
explain how components like wires, resistors, and transistors are laid out on an Integrated
Circuit (IC) chip—this is what's called the switch level. It can also show the logical gates and
flip-flops that are part of a digital system, which we refer to as the gate level.

VHDL originally came into play for monitoring and logging ASICs in microelectronic
devices. Back in the day, designers who were working with VHDL—when logic simulators
were still being developed—started picking up VHDL to build their own implementations. A
lot of VHDL’s growth was influenced by the Ada programming language, especially
regarding concepts and syntax.

This was pretty handy for avoiding any unnecessary duplicate work while developing VHDL
for military applications, given they needed a good amount of syntax for their Ada-based
projects. The very first version of VHDL was created to align with IEEE standards, which
resulted in the inclusion of various data types like logical, character, time, arrays, strings, and
numeric types.

If we look at it from a broader perspective, there's a higher level of abstraction that focuses on
registers and how information flows between them. That’s called the Register Transfer Level
(RTL), and the neat thing is Verilog can handle all these different levels. But in this
document, we’re zeroing in on the RTL aspects of Verilog.
7.2 VERILOG:
Verilog is kind of the go-to Hardware Description Language (HDL) for anyone
jumping into the awesome world of digital systems design. It’s super flexible and lets you dig
into the details as much as you like, making it a breeze for designers at any skill level to
model. One of the neat features of Verilog is its Register Transfer Level (RTL) capability,
which is a big reason why so many engineers love using it. If you’ve ever coded before, the
syntax will probably feel familiar since it’s a lot like C, which definitely makes the learning
curve a bit easier.

When you get started with Verilog, the process is pretty simple: you write out your design
using code, run some tests to make sure everything's working as it should, and then turn that
code into real hardware for things like Field Programmable Gate Arrays (FPGAs) or
Application-Specific Integrated Circuits (ASICs). A key concept you need to grasp when
using Verilog is modules.

Think of modules as the building blocks of your design; they help keep everything neat and
structured, especially when you’re tackling larger projects. Plus, you can use testbenches to
simulate different inputs and see how the outputs respond. This versatility is what really
makes Verilog shine, whether you're simulating or building hardware.

Since it first came on the scene in the mid-1980s, Verilog has become a staple in both the
industry and educational spaces for digital design. If you talk to engineers about what they
love most about Verilog, you’ll often hear them rave about how much it resembles C. That
familiarity can really help anyone with a programming background jump right in.

So, the typical game plan with Verilog looks like this: you write your code, simulate it to
double-check everything’s working smoothly, synthesize it into hardware, and then
implement it on devices like FPGAs or ASICs.

Thanks to its modular design, keeping your projects organized is super easy. Another big plus
is how straightforward it is to set up testbenches. This feature lets you thoroughly test your
designs by simulating inputs and closely monitoring the outputs.
That kind of flexibility is super critical during the verification phase, making sure
everything’s functioning properly as you synthesize that design into real hardware.
When you compare Verilog with VHDL, it’s pretty cool to see how they really work well
together like a energetic duo in Hardware Description Languages.. Both of these languages
are well-respected by hardware designers across a range of industries and in academic circles.
While there are certainly spirited discussions about which language is the best, many find
Verilog to be more approachable, especially since its syntax feels pretty natural for electrical
and computer engineers who have been exposed to C in their studies. On the flip side, VHDL,
which was officially standardized by the IEEE back in 1987, might not be as familiar to many
engineers, which can create a bit of a obstacle for those trying to pick it up.
7.3 XILINX
Xilinx Tools is an impressive software suite that really enables engineers and
designers to create sophisticated digital circuits using Xilinx’s FPGA and CPLD technologies.
The design process is incredibly simplified, making it simple and engaging to go from a
creative spark to a tangible, finished product that you can actually use.

To kick things off, you jump right into the energetic world of design entry, where you have an
array of options at your fingertips. If you’re someone who enjoys a visual approach, then
schematic entry is a fantastic way to bring your circuits to life by placing and connecting
various components. On the other hand, if coding is more your style, you can dive into
hardware description languages (HDL) like Verilog and VHDL.

Verilog tends to be a favorite among many because its syntax is reminiscent of C, which
makes it a breeze for a lot of engineers. And if you’re tackling a more complex project,
there’s even a hybrid method available that beautifully combines schematics and HDL, giving
you that extra freedom to explore your creative ideas.

So, once you've wrapped up your design and it's looking super sharp, you enter an exciting
new phase known as synthesis. This is where the real magic comes into play! During
synthesis, those high-level descriptions that you've painstakingly crafted get changed into a
netlist. This netlist goes into great detail, outlining all the components involved and showing
precisely how they're interconnected, making everything crystal clear and organized.

Xilinx’s synthesis tools really shine in this stage; they're incredibly smart and work tirelessly
to tweak and optimize your design for essential factors like area, speed, and power efficiency.
Once this synthesis phase wraps up, you’ll shift gears and move into implementation. This is
the moment when your design gets carefully mapped onto an FPGA or CPLD architecture.
Here, it’s all about positioning the components just right and establishing those important
connections to ensure everything operates like a well-oiled machine.

Now, let's dive into functional simulations! You definitely want to run these because they’re
critical for double-checking that everything is functioning as it should. These simulations
provide engineers with an opportunity to observe how the circuit behaves under different
conditions, making sure that it meets all the necessary specifications. And the best part? The
final step involves testing your design on actual hardware. This is the moment when you get
to see if everything works smoothly in real-world scenarios. This thorough and systematic
approach ensures that your design evolves from just a collection of ideas to something that
demonstrates reliability when it really counts.

In a summary, Xilinx Tools offer a strong and energetic platform for digital circuit design,
enabling engineers to translate their imaginative ideas into functional hardware solutions.
With a clear and structured design workflow and a special focus on Verilog HDL, we really
have the opportunity to shine and achieve fantastic results in our digital design projects.
7.4 CODING IMPLEMENTATION:
Main Code:
module
AES_TOP_FINAL(clk, rst, en, kld, key, text_in, enc_data, dec_data,
enc_complete, dec_complete);
input clk;
input rst;
input en;
input kld;
input [127:0] key;
input [127:0] text_in;
output [127:0] enc_data;
output [127:0] dec_data;

output enc_complete;
output dec_complete;

Nano_AES_ENCRYPT MM0
(.Clk(clk), .Rst(rst), .En(en), .ld(kld), .Done(enc_complete), .Key(key), .Text_In
(text_in), .Text_Out(enc_data));

Nano_AES_DECRYPT MM1
(.clk(clk), .rst(rst), .En(en), .kld(kld), .ld(enc_complete), .done(dec_complete), .
key(key), .enc_data(enc_data), .dec_data(dec_data));

Endmodule
 CHAPTER 8
EXPERIMENTAL RESULTS
8.1 SIMULATION RESULTS
ENCRYPTION:

SINGLE ROUND OPERATION:

AES ENCRYPTION:

TEN ROUNDS OF OPERATION:

PROPOSED:
IMAGE DATA:

TEXT DATA:
8.2 SYNTHESIS RESULTS

Table 8.1: Device Utilisation Summary

Fig 8.1: RTL View of MAIN AES Block

Fig 8.2: Inner View of AES MAIN Module
 Fig 8.3: Technological Schematic of AES Module

COMPARISON TABLE:

S. Method Name Area Delay

No
Slice Flip LUT Max Gate Path
Flops Delay Delay Delay
1 Conventional 7734 21207 2120 160.860ns 25.302ns 135.558ns
Design 7
2 Proposed 1670 1066 3900 3.405ns 2.923ns 0.482ns
Pipelined
Design
Table 8.2: Comparison Table:
25000

20000

15000

Conventional Design
Proposed Pipelined Design
10000

5000

0
LUT Slices Gates

Fig 8.4 AREA GRAPH

180

160

140

120

100
Conventional Design
80 Proposed Pipelined Design

60

40

20

0
Overall Delay Gate Delay Path Delay

Fig 8.5: DELAY GRAPH

 CHAPTER 9
CONCLUSION AND FUTURE WORK

9.1 CONCLUSION
Nano AES is a really cool symmetric encryption algorithm that packs a serious punch
when it comes to security. It's widely used in all sorts of applications and networks. Because
it's so powerful yet lightweight, AES is perfect for those little Internet of Things (IoT)
devices, which usually don’t have a lot of resources to spare. In this article, we’re excited to
share our experience developing a lightweight AES architecture that’s customize-made for
these resource-constrained devices. We designed it with an 8-bit data path that’s just right for
these small gadgets and added two specific register banks. These banks play a important role
—they hold the plaintext, the encryption keys, and any intermediate values we work with
during the encryption process. To keep things smooth and efficient, we carried out the Shift-
Rows operation right inside the State-Register. Plus, we crafted an optimized Sub-Bytes
function, which is super important during both the encryption phases and the key expansion.
And to wrap it all up, we put together a Mix-Columns function that takes in and outputs 8-bit
data—perfect for a low-area design. One of our main goals was to cut down on both area and
power consumption, so we implemented clock gating techniques in different parts of the
design. Thanks to all these efforts, we achieved an impressive 30% reduction in area when we
tested it on the Virtex 5 xcVLX330T FF1738 -2 board.
9.2 FUTURE WORK
As we look ahead, we can’t help but feel excited about the plans we have in store to
upgrade our lightweight AES architecture, especially when it comes to those IoT devices that
may not have a lot of resources at their disposal:

1. Boosting Performance: We’re all about finding ways to speed things up and make them
more efficient. With some smart pipelining and innovative optimization techniques, we want
to ensure our setup can keep pace with the fast-moving demands of the latest IoT
technologies.
2. Working with IoT Protocols: By weaving our architecture into the fabric of popular IoT
communication protocols, we plan to subject it to real-world scenarios to ensure it truly meets
the needs of users on the ground.
3. Strengthening Security Features: We’re downright committed to enhancing our AES setup
to help shield against the cybersecurity threats. This means examining advanced protective
measures, such as defenses against side-channel attacks and greatly improving our key
management practices.
4. Exploring Scalability: Our plans also include customizing our design for a wide range of
IoT devices, from the simplest microcontrollers to much more sophisticated systems, so it can
smoothly fit into the entire IoT ecosystem.
5. Benchmarking: We intend to conduct comprehensive comparisons with other lightweight
cryptographic algorithms, displaying what makes our architecture stand out and ensuring it
stays ahead in the game.
6. Real-world Testing: By partnering with industry experts for actual deployments, we’ll gain
invaluable insights that will help us refine our design based on genuine user feedback.

With these strategic moves, we’re genuinely pumped to enhance our lightweight AES
architecture, aiming to make a major impact on both security and performance for IoT devices
in our increasingly connected world.
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 Evaluation Rubrics for Project work:

Rubric (CO) Excellent (Wt = 3) Good (Wt = 2) Fair (Wt = 1)

Select a latest topic through Select a topic through partial Select a topic through improper
Selection of Topic (CO1) complete knowledge of facts and knowledge of facts and knowledge of facts and
concepts. concepts. concepts.

Thorough comprehension Reasonable comprehension Improper comprehension

Analysis and Synthesis (CO2)
through analysis/ synthesis. through analysis/ synthesis. through analysis/ synthesis.

Thorough comprehension about Reasonable comprehension about Improper comprehension

Problem Solving (CO3) what is proposed in the literature what is proposed in the literature about what is proposed in
papers. papers. the literature.

Extensive literature survey with Considerable literature survey Incomplete literature survey
Literature Survey (CO4)
standard references. with standard references. with substandard references.

Clearly identified and has complete Identified and has

Identified and has sufficient
Usage of Techniques & knowledge of techniques & tools inadequate knowledge of
knowledge of techniques & tools
Tools (CO5) used in the project work. techniques & tools used in
used in the project work.
project work.

Project work impact on Society Conclusion of project work has Conclusion of project work has Conclusion of project work has
(CO6) strong impact on society. considerable impact on society. feeble impact on society.

Conclusion of project work has Conclusion of project work

Project work impact on Conclusion of project work has
considerable impact on has feeble impact on
Environment (CO7) strong impact on Environment.
environment. environment.

Clearly understands ethical and Moderate understanding of Insufficient understanding of

Ethical aFtude (CO8)
social practices. ethical and social practices. ethical and social practices.

Did literature survey and selected Did literature survey and

Selected a topic as suggested
Independent Learning (CO9) topic with a little guidance selected topic with
by the supervisor
considerable guidance

Presentation in logical
Presentation with
sequence with key points, clear Presentation with key points,
Oral Presentation (CO10) insufficient key points and
conclusion and excellent language conclusion and good language
improper conclusion

Status report with clear and Status report with logical

Status report not properly
Report Writing (CO10) logical sequence of chapters sequence of chapters using
organized
using excellent language understandable language

Comprehensive time and cost Moderate time and cost Reasonable time and cost
Time and Cost Analysis (CO11)
analysis analysis analysis

Highly enthusiastic towards Interested in continuous Inadequate interest in

Continuous learning (CO12)
continuous learning learning continuous learning
Title of the Project- VLSI DESIGN FOR AES CRYPTOGRAPHY: OPTIMIZING
ENCRYPTION FOR TEXT AND IMAGE DATA WITH PIPELINED ARCHITECTURE
Name of the students:
M. KISHORE KUMAR 21751A0469
P. GOWTHAM KUMAR 21751A0489
P. HEMANTH 21751A0490
P. YOGANTH 21751A0497

Name of the Guide & Designation: Mr. P.C. BHARATH KUMAR, M.E.,
Assistant Professor.

TABLE 1: OUTCOME ATTAINED AND ITS JUSTIFICATION

PO No. Justification

PO1 Applied domain knowledge in cryptography and VLSI design to develop a lightweight AES
architecture suited for IoT devices.

PO2 Analyzed and addressed system inefficiencies such as power consumption, area usage, and
encryption delay through pipelining and logic optimization.
PO3 Designed and implemented a secure AES encryption system that meets real-time constraints and
performance needs of modern embedded and IoT applications.
PO4 Utilized current research and literature surveys to identify gaps in AES implementations and
proposed improved techniques like SDRR and clock gating.
Employed Verilog HDL, Xilinx FPGA tools, and modern simulation environments to realize and
PO5
test the proposed cryptographic design.

The proposed system enhances energy efficiency and processing performance, promoting and
PO6
scalable solutions in embedded systems.
The pipelined, low-power design reduces hardware overhead and resource wastage, supporting
PO7
optimal use of silicon and energy.

PO8 We followed the ethical principles.

PO9 Collaborated effectively as a team to manage design, development, testing, and documentation
responsibilities.
Developed strong technical writing and presentation skills through project reporting, simulation
PO10
documentation, and oral reviews.

Understood and managed trade-offs involving cost, delay, and complexity during system
PO11
optimization phases.

Continuously learned and applied new cryptographic methods and digital design techniques to
PO12
improve system design and future project potential.