Circuit Design for Modern

Applications

This book offers a clear exploration of cutting-edge semiconductor circuit technolo-

gies and their practical applications. It covers topics like advanced transistor design,
low-power consumption techniques, and high-performance circuit design.
Circuit Design for Modern Applications explores the recent innovations in semi-
conductor technology. Bandgap reference circuits, quad model transistors, voltage-
controlled oscillators, LDO regulators, power amplifiers, low noise amplifiers,
operational amplifiers, low-power CNTFET-based quaternary multipliers, and STT
MRAM-based cache memory for multicore systems are discussed. It points out the
difficulties in designing CMOS analog and RF circuits for mmWave applications
and looks into newly developed field-effect transistors for an alternate solution.
Innovative devices such as III-V material-based HEMTs, and junctionless FETs are
discussed. The book also looks at creative ways to improve circuit performance and
energy efficiency, which is a useful resource for academics, researchers, and indus-
try experts working in semiconductors.
This book will help the readers to stay on the cutting edge of contemporary cir-
cuit design technologies, covering various topics from fundamental circuit design to
high-performance circuits.
 Taylor & Francis
(9
a1 Talor & Francis Group
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Circuit Design for Modern
Applications

Edited by
A. Andrew Roobert, M. Venkatesh,
Shiromani Balmukund Rahi, G. Lakshmi Priya
and Samuel Tensingh
Designed cover image: Shutterstock

First edition published 2025

by CRC Press
2385 NW Executive Center Drive, Suite 320, Boca Raton FL 33431

and by CRC Press

4 Park Square, Milton Park, Abingdon, Oxon, OX14 4RN

CRC Press is an imprint of Taylor & Francis Group, LLC

© 2025 A. Andrew Roobert, M. Venkatesh, Shiromani Balmukund Rahi, G. Lakshmi Priya, and Samuel
Tensingh

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Library of Congress Cataloging‑in‑Publication Data

ISBN: 978-1-032-77431-2 (hbk)

ISBN: 978-1-032-77432-9 (pbk)
ISBN: 978-1-003-48305-2 (ebk)

DOI: 10.1201/9781003483052

Typeset in Times
by Deanta Global Publishing Services, Chennai, India
Contents

About the editors..................................................................................................... viii
List of contributors......................................................................................................x
Preface.....................................................................................................................xiv
Acknowledgments....................................................................................................xvi

Chapter 1 Design an Inverter with a Quad-Model Transistor................................ 1

Alok Kumar, Bhavana P. Shrivastava, Tarun Kumar Gupta,
and Vivek Patel

Chapter 2 Exploring the Design and Performance Dynamics of CMOS

Voltage-Controlled Ring Oscillator Stages......................................... 22
M.V. Rajee and C. Mythili

Chapter 3 A 3.1 ppm/ºC Sub-1V Bandgap Reference in 28 nm CMOS

Technology Operating from a 1V Supply Voltage.............................. 37
Rajasekhar Nagulapalli, Khaled Hayatleh, and Nabil Yassine

Chapter 4 Advancements in Contemporary Circuit Design:

Exploring Alternatives to CMOS for Enhanced Performance............ 48
G. Boopathi Raja

Chapter 5 STT-MRAM based Cache Memory Design for Multicore Systems... 74

Yogendra Gupta, Ashish Sharma, Niketa Sharma, Vinay
Kanungo, and Amit Kumar Sharma

Chapter 6 Optimal Approaches for Enhancing Energy Efficiency in Circuits....92

A. Rameshbabu, V.R.S. Mani, V.N. Senthil Kumaran, and
Neethu Anna Sabu

Chapter 7 Design and Analysis of Optimized Area and Energy-Efficient

QCA-based 8 × 8 Butterfly Switching Network............................... 103
Premananda B.S. and Ajith R.

 v
vi Contents

Chapter 8 Advanced Operational Amplifier with Emerging CMOS

Technology........................................................................................ 120
Shiromani Balmukund Rahi, Young Suh Song, and Jyoti Kandpal

Chapter 9 Circuit Design for Accurate Digitized Urine Weight

Measurement..................................................................................... 137
Siva Lakshmi M., E. Andrea Gracelin, G. Gifta, A. Andrew
Roobert, and M. Suresh Chinnathampy

Chapter 10 Low-Power Energy-Efficient CNTFET-Based Quaternary

Multipliers......................................................................................... 150
Sarada Musala, G. V. S. Ajay, and Neelima N.

Chapter 11 Advanced Semiconductor Devices: FET Down-scaling and

Next-Gen Transistors......................................................................... 168
Mohamed Salah Benlatreche, Billel Smaani, Ismahan Mahdi,
Omari Tahar, and Cheriet Mohammed El Amine

Chapter 12 Investigation of the Challenges in Analog/RF Circuit Design for

Millimeter Wave Applications and Possible Solutions..................... 186
P. Sherly Arunodhayamary, G. Rajakumar, M. Venkatesh, and
A. Andrew Roobert

Chapter 13 Performance Analysis of an Inner Gate Vertical TFET................... 201

K. Kalai Selvi, K.S. Dhanalakshmi, Sathashivam G, and K.
Lakshmi Narayanan

Chapter 14 Low-Power CNTFET-Based Single-Ended Write Driver Circuit

for SRAM Design.............................................................................. 215
Aswini Valluri, Posani Vijaya Lakshmi, and Avireni Srinivasulu

Chapter 15 Electron Mobility Models and Subthreshold Swing for Modern

Semiconductors................................................................................. 228
Shiromani Balmukund Rahi and Young Suh Song

Chapter 16 Multiple-Gate MOSFET Model Implemented in Analog

Circuits for Simulations and Co-Design Applications...................... 241
Ismahan Mahdi, Billel Smaani, and Mohamed Salah Benlatreche
Contents vii

Chapter 17 Design of an Impedance Attenuated Control Loop for

Flipped Voltage Follower-Based Output-Capacitor-Less
LDO Regulators................................................................................ 265
Shri Antaryami Panigrahi

Chapter 18 Beyond Silicon: III-V Material-Based Lateral and Vertical

HEMTs for High-Power and High-Speed Switching
Applications....................................................................................... 281
Danielraj A, Saravana Kumar R, Sanjoy Deb, and Balakrishnan R

Chapter 19 Advanced Compound Semiconductor Based Heterostructure

Devices for Next Generation Electronics.......................................... 301
Saravana Kumar R, Leeban Moses M, Lino L, and Papanasam E

Chapter 20 GaN HEMT-Based Power Amplifiers: Advancements and

Applications....................................................................................... 320
T Venish Kumar, R Karthick, C Nandhini, M Annalakshmi, and
R Rajesh Kanna

Chapter 21 New Approaches for Modeling Nanoscale Junctionless FETs:

Device and Circuit-Level Performance Assessment......................... 334
H. Ferhati, T. Berghout, and F. Djeffal

Chapter 22 Survey of Machine Learning-Augmented TCAD Algorithms for

Modeling GaN HEMTs..................................................................... 353
Niketa Sharma, Yogendra Gupta, Vinay Kanungo, Amit Kumar
Sharma, and Ashish Sharma

Chapter 23 Implementation of Modified Dual-Coupled Linear Congruential

Generator with Parallel Prefix Adder................................................ 371
Hima Bindu Katikala and Gajula Ramana Murthy
Index....................................................................................................................... 383
About the editors
A. Andrew Roobert is currently a Postdoctoral Fellow in the Department of
Electronics and Electrical Engineering, Indian Institute of Technology Guwahati,
Assam, India. He has completed his Ph.D. degree in RFIC Design at Thiagarajar
College of Engineering, Madurai, M.E. degree in VLSI Design at Francis Xavier
Engineering College, Tirunelveli, and B.E. degree in Electronics and Communication
Engineering at National Engineering College Kovilpatti. His research interests
include RFIC Design, LNA Design, Circuit optimization, Low-power VLSI Design,
Physical Design, VLSI architecture design, electronic system design and wireless
communication. He is a member of IEEE and other technical societies.

M. Venkatesh is currently an Assistant Professor in the Department of Electronics

and Communication Engineering, CMR Institute of Technology, Bengaluru, India.
He received a B.E. degree in Electronics and Communication Engineering from
SACS MAVMM Engineering College, Madurai (2013) and an M.E. degree in VLSI
Design from P.S.N.A. College of Engineering and Technology, Dindigul (2015). He
completed his Ph.D. at Thiagarajar College of Engineering, Madurai (2020). His
research interests include analytical modeling and simulation of Nanoscale SOI
MOSFETs, Nanowire Transistors, HEMTs, Tunnel FET and Quantum Effects in
Multigate MOSFETs.

Shiromani Balmukund Rahi completed his Ph.D. (2018) from the Indian Institute
of Technology Kanpur (India) and postdoctoral research (2021) with Professor N.
Guenifi (Electronics Department, University Mostefa Benboulaid of Batna, Algeria.
Currently he works at School of Information and Technology (SoICT), Gautam
Buddh University Greater Noida Uttar Pradesh, India and associated with the Indian
Institute of Technology Kanpur (India) for advanced research for ultra-low-power
devices, circuits, and systems. He is actively working for various advanced Field-
Effect devices such as Tunnel FETs, negative FETs, Nanosheet FETs, NC-Tunnel
FETs, NC-FinFETs, and FeFETs. He is a member of IEEE (student member) and
International Association of Engineers (Lifetime).

G. Lakshmi Priya is currently an Assistant Professor Senior Grade II in the School

of Electronics Engineering (SENSE), VIT University, Chennai. She has completed
her Ph.D. in Semiconductor Device Modeling (2020), M.E. in Communication
Systems, and B.E. in Electronics and Communication Engineering from Thiagarajar
College of Engineering, Madurai affiliated with Anna University Chennai. Her
area of research is Semiconductor Devices and Nanoscale Transistors. She is a Life
Member of ISTE and an Associate Member of IEI (AMIE).

viii
About the editors ix

Samuel Tensingh is currently a PhD candidate at the School of Biomedical

Engineering at the University of Sydney, Australia. He earned his Bachelor’s degree
in Electronics and Communication Engineering from Anna University, India,
in 2008, followed by a Master of Business Administration from Anglia Ruskin
University in the United Kingdom in 2012. With 15 years of experience in designing
Digital Integrated Circuits, Samuel has held roles as an Associate Lecturer at the
University of Sydney and as a Senior IC Design Engineer at Avago Technologies,
Broadcom Limited, and STMicroelectronics in Singapore, where he successfully
delivered numerous ASIC designs. He is a Senior Member of IEEE and an active
member of 35 technical societies across the globe.
Contributors
Ajay G. V. S. Avireni Srinivasulu
Vignan’s Foundation for Science, Mohan Babu University
Technology and Research India
Andhra Pradesh, India
Balakrishnan R
Ajith R. Vellore Institute of Technology
RV College of Engineering Chennai, India
Bengaluru, India
Berghout T
Alok Kumar University of Batna 2
MANIT Bhopal, India Algeria
Bhopal, India
Bhavana P. Shrivastava
Amit Kumar Sharma MANIT Bhopal, India
Swami Keshvanand Institute of Bhopal, India
Technology Management &
Gramothan Billel Smaani
Jaipur, India Abdelhafid Boussouf University Centre
of Mila, Algeria, Laboratory of
Andrea Gracelin E. Hyperfrequency and Semiconductors,
Karunya Institute of Technology and University of Constantine
Sciences Algeria
Coimbatore, India
Boopathi Raja G.
Andrew Roobert A. Velalar College of Engineering and
Indian Institute of Technology Technology
Guwahati Erode, India
Guwahati, India
Cheriet Mohammed El Amine
Annalakshmi M Satellite Development Centre Oran
Vellammal College of Engineering Algeria
and Technology Algeria
Madurai, India
Danielraj A
Ashish Sharma Bannari Amman Institute of
Manipal University Technology
Jaipur, India Sathyamangalam, India

Aswini Valluri Dhanalakshmi K S

Vignan’s Foundation for Science Kalasalingam Academy of Research
Technology and Research & Education
India Srivilliputhur, India

x
Contributors xi

Djeffal F Karthick R
University of Batna 2 K.L.N College of Engineering
Algeria India

Ferhati H. Khaled Hayatleh

University of Batna 2, University Oxford Brookes University
of Larbi Ben M’hidi, Oum El Headington, United Kingdom
Bouaghi
Algeria Lakshmi Narayanan K
Francis Xavier Engineering College
Gajula Ramana Murthy Tirunelveli, India
Alliance University
India Leeban Moses. M
Bannari Amman Institute of
Gifta G. Technology
Karunya Institute of Technology and Sathyamangalam, India
Sciences
Coimbatore, India Lino. L
Bannari Amman Institute of
Hima Bindu Katikala Technology
Vignan’s Foundation for Science Sathyamangalam, India
Technology and Research
India Mani V.R.S.
Francis Xavier Engineering College
Ismahan Mahdi Tirunelveli, India
M’hamed Bougara Boumerdes
University Algeria Mohamed Salah Benlatreche
Algeria Abdelhafid Boussouf University
Centre of Mila
Jerart Julus L Algeria
School of Computer Science
Engineering and Information Mythili C.
System, Vellore Institute of University College of Engineering
Technology Nagercoil, India
Vellore
Nabil Yassine
Jyoti Kandpal Oxford Brookes University,
Graphic Era Hill University Headington
Dehradun United Kingdom
Uttarakhand, India
Nandhini C
Kalai Selvi K Nadar Saraswathi College of
Government College of Engineering Engineering and Technology
Tirunelveli, India India
xii Contributors

Neelima N Rajesh Kanna R

Amrita School of Engineering M. Kumarasamy College of
Bengaluru, India Engineering
India
Neethu Anna Sabu
K J Somaiya College of Engineering Rameshbabu A.
Mumbai, India Ramco Institute of Technology
Rajapalayam, India
Niketa Sharma
Swami Keshvanand Institute of Sanjoy Deb
Technology Management & Bannari Amman Institute of
Gramothan Technology
Jaipur, India Sathyamangalam, India

Omari Tahar Sarada Musala

M’hamed Bougara Boumerdes Vignan’s Foundation for Science,
University Algeria Technology and Research
Algeria Andhra Pradesh, India

Papanasam E Saravana Kumar. R

Vellore Institute of Technology Vellore Institute of Technology
Chennai, India Chennai, India

Posani Vijaya Lakshmi Sathashivam G

Vignan’s Foundation for Science Government College of Engineering
Technology and Research Tirunelveli, India
India
Senthil Kumaran V.N.
Premananda B.S. SRM Institute of Science and
RV College of Engineering Technology, Tiruchirappalli
Bengaluru, India Campus
Tiruchirappalli, India
Rajakumar G
Francis Xavier Engineering College Sherly Arunodhayamary P
Tirunelveli, India Francis Xavier Engineering College
Tirunelveli, India
Rajasekhar Nagulapalli
Oxford Brookes University Shiromani Balmukund Rahi
Headington, United Kingdom School of Information and
Technology (SoICT)
Rajee M.V. Gautam Buddha University
Francis Xavier Engineering College Uttar Pradesh, India
Tirunelveli, India
Contributors xiii

Shri Antaryami Panigrahi Venkatesh M

Central Institute of Technology CMR Institute of Technology
Kokrajhar Bengaluru, Karnataka, India
Assam, India
Vinay Kanungo
Siva Lakshmi M Swami Keshvanand Institute of
Karunya Institute of Technology and Technology Management &
Sciences Gramothan
Coimbatore, India Jaipur, India

Suresh Chinnathampy M. Vivek Patel

Vel Tech High Tech Dr. Rangarajan MANIT Bhopal
Dr. Sakunthala Engineering Bhopal, India
College
Chennai, India Yogendra Gupta
Swami Keshvanand Institute of
Tarun Kumar Gupta Technology Management &
University of Allahabad Gramothan
Prayagraj, India Jaipur, India

Venish Kumar T Young Suh Song

Nadar Saraswathi College of Korea Military Academy
Engineering and Technology Seoul, Republic of Korea
India
Preface
Nowadays circuit design is one of the most important fields from consumer elec-
tronics to industrial systems, and from medical devices to quantum computing. The
objective of this book is to give a thorough and deep look at the modern techniques
and methods used in circuit design, with a focus on what they mean in real life and
what they could mean in the future.
The idea for this book came from the realization that modern applications need
new approaches in circuit design and device modeling perspectives. Even though tra-
ditional methods are important, they don’t always meet the complex needs of current
applications. The never-ending quest for smaller size, better speed, lower power use,
and higher reliability calls for new ways of designing things and creative solutions.
This book tries to connect theory and practice by showing the most recent study
results and how they can be used in real-time applications.
Another idea of this book is to look into new materials and device designs that
could change the way circuits are designed. As silicon-based technology gets closer
to its physical limits, there is a lot more interest in finding other materials. This book
talks about the possibilities of compound semiconductors like Gallium Nitride (GaN)
and other III-V materials. These materials have better electrical properties that can
make gadgets work better and use less energy. These materials are not just new ideas
in theory; they can also be used in high-power and high-frequency devices, which
makes them very important to the progress of modern electronics.
The importance of saving energy comes up frequently in this book. As the world
moves toward greener gadgets and sustainable technology becomes more important,
it is more important than ever to make circuits use less power. A number of tac-
tics are talked about, ranging from low-power design methods in CMOS technology
to using new gadgets such as Spin-Transfer Torque Magnetic RAM (STT MRAM)
and Carbon Nanotube Field-Effect Transistors (CNTFETs). Not only are these
approaches given in a theoretical way, but they are also given as design examples.
This book also talks about the special problems and chances that come up when
designing analog and RF circuits, especially for the millimeter-wave (mmWave)
range. Higher frequency operations create some problems for designers, but it also
opens up new ways to improve bandwidth and data rate. This book shows how to
deal with the problems in these circuits.
Moreover, evaluating the performance at both the device and circuit levels is more
important. The relationship between device physics and circuit function gets more
complicated when it comes to nanoscale devices. There are detailed modeling and
simulation methods shown that help show how things that happen at the nanoscale
level affect how a circuit works as a whole. This all-around method makes sure that
readers not only learn how to design circuits, but also how to predict and improve
their performance in a wide range of settings.
One thing that makes this book stand out is that it focuses on real-world, appli-
cation-based design examples. Each chapter is designed to give a mix of theory

xiv
Preface xv

background and practical design information. This way, the material can be used by
both academics and engineers who are currently working.
We are on the verge of a new era in modern electronics, and it’s important that
circuit designers keep coming up with new ideas. We need to be able to push the
limits of what is possible, to see the future of technology. This book encourages such
new ideas to deal with the difficulties of current circuit design.
You’re in Circuit Design for Modern Applications. We want you to learn about the
pioneering ideas and cutting-edge techniques that are changing the future of circuit
design.
 
Acknowledgments
First of all I would like to thank God Almighty for all blessings. I thank the family
members, my parents, wife and daughter for their support and understanding. My
heartfelt thanks to the authors and reviewers, their hard work, insightful research,
and innovative approaches form the backbone of this book, providing invaluable
knowledge to both readers and scholars in the field of circuit design. I especially
thank each editor for their unique contribution to this book in all aspects. Their
motivation, effort, wide range of experience, and spirit of coordination have greatly
influenced this work. A special thanks to my mentor of postdoctoral research and
a constant source of inspiration Professor Gaurav Trivedi for shaping my research.
I dedicate this book to my family members.
Dr. A. Andrew Roobert (Editor)

The book Circuit Design Approach for Modern Applications, is dedicated to the
Almighty, who granted me the strength and health to complete this work. I extend
my heartfelt thanks to my parents, Mr. C. Meenakshi Sundaram and Mrs. M.
Nagalakshmi, for their unwavering support. I am very grateful to Dr. Sanjay Jain,
Principal of CMR Institute of Technology, for his continuous support. My deepest
gratitude goes to Dr. M. Pappa, Professor and Head of the Department of ECE at
CMR Institute of Technology, Bengaluru, for providing me with the necessary time
and resources to undertake this exciting project.
This work is dedicated to my family members.
Dr. Venkatesh M (Editor)

The book Circuit Design Approach for Modern Applications is dedicated to

Almighty God for providing me time and courage to execute this project. After
Almighty God, I am also thankful to my family members for helping me at all
desirable time domains. I am also thankful to my HoD (Dr. Neeta Singh), University
School of Information and Communication Technology Gautam Buddha University
Greater Noida, Uttar Pradesh, India for providing me time for this exciting project.
This work is dedicated to my family members and my daughter Snnavi.
Dr. Shiromani Balmukund Rahi (Editor)

With all my heart, I want to sincerely thank Almighty God for giving me the inspira-
tion and fortitude that I required to finish this endeavor. I am grateful to my family
for their constant support and encouragement during this journey. Special thanks to
my grandfather, the late Dr. N. Balusamy, for instilling in me a love for knowledge.
Your support and affection for me have been priceless. I express my gratitude to
my mentors and teachers for their vital guidance and fundamental insight. Sincere

xvi 
Acknowledgments xvii

thanks to Dr. N. B. Balamurugan (Professor, Department of ECE, Thiagarajar

College of Engineering, Madurai), who has mentored me in academic pursuits and
has always been a source of guidance in my life. Finally, I want to thank the editorial
and publishing teams at CRC Press, particularly Dr. A. Andrew Roobert (Editor),
for their professionalism and constructive criticism, which helped ensure the finest
possible version of this book.
Dr. G. Lakshmi Priya (Editor)

The book Circuit Design Approach for Modern Applications is dedicated to God,
whose steadfast guidance has provided me with the time and courage to undertake
this transformative project. I am profoundly grateful to my parents for their unwav-
ering encouragement and belief in my abilities. I also extend my deepest gratitude
to my supervisor, Dr. Omid Kavehei, Associate Professor and Deputy Head of the
School of Biomedical Engineering at the University of Sydney, Australia, for his
support and inspiration. Additionally, I would like to acknowledge Dr. A. Andrew
Roobert, the editor, for fostering a collaborative environment that was crucial for the
successful completion of this endeavour.
Mr. Samuel Tensingh (Editor)
 Taylor & Francis
(9
a1 Talor & Francis Group
http://taylorandfrancis.com
 1 Design an Inverter with a
Quad-Model Transistor
Alok Kumar, Bhavana P. Shrivastava,
Tarun Kumar Gupta, and Vivek Patel

1.1 INTRODUCTION
This chapter covers the design of an inverter using a quad-model transistor. It entails
the use of an abridged transistor model, which turns several transistors into one com-
parable model. This method keeps key features for fundamental circuit operation
while streamlining the design process. The quad-model transistor approximates the
behavior of a single transistor with improved current-driving capabilities by connect-
ing four identical transistors in parallel. The threshold voltage, transconductance,
and drain–source resistance of separate transistors are combined into a single model
known as the quad-model transistor. For this a quad-model transistor is selected that
will work well under the specified circumstances. It must also be ensured that the
voltage ratings are appropriate for the intended use and that it can handle a sufficient
amount of current. The transistor quad-model is set up in an inverter architecture. A
transistor (or quad-model transistor in this case) linked in series with a load resistor
between the ground and the supply voltage (Vdd) is the standard configuration of an
inverter. Based on the specifications of the quad-model transistor and the intended
logic swing levels, select a suitable supply voltage (Vdd). It is necessary to choose
an appropriate load resistor (R L) to control the inverter’s switching speed and power
usage. The load resistor is typically used to guarantee appropriate voltage swing and
reduce propagation delay. The quad-model transistor must be given the appropri-
ate biasing. This entails making sure the transistor in CMOS inverters functions
in its active zone for the right switching and amplification characteristics. In order
to reduce signal degradation and maximum performance, arrange the circuit tak-
ing into account resistances, parasitic capacitances, and the physical architecture
of the quad-model transistor. Utilize simulation tools such as SPICE to confirm the
inverter’s functionality. To make sure they adhere to design criteria, verify the volt-
age transfer characteristic (VTC), noise margins, propagation latency, and power
usage. It should be ensured that the datasheet for the quad-model transistor contains
enough information about its specifications, including input capacitance, maximum
drain–source voltage (Vds), and maximum drain current (Id). The value of R L is
determined by taking into account the required speed and desirable voltage swing.
While too low a value can result in increased power consumption, too high a value

DOI: 10.1201/9781003483052-1 1
2 Circuit Design for Modern Applications

can cause slow switching speeds. Before putting your design into practice, always
use simulation to make sure it satisfies performance requirements and performs
dependably under anticipated operating conditions.
The concept of digital data manipulation has been greatly impacted by research-
ers and the concept of digital computers has been in the minds of researchers for a
long time. The steady of evolution of computers from mainframes and minicomput-
ers to personal computers and laptops has led to their widespread use in everyday
life. However, the ongoing shift toward digital solutions across the board in elec-
tronics is more noteworthy. When the advantages of digital data manipulation over
analog processing were first revealed, for this instrumentation was among the first
non-competing field to implement it physically; other domains, including control,
subsequently followed. We have only just begun to see the shift toward digital for-
mats in consumer electronics and telecoms. Data sent and processed digitally across
wired and wireless networks is rapidly replacing analog methods in the telephone
industry. Digital video immediately followed in the footsteps of the compact disc,
which utterly transformed the music industry. Research has shown that high-density
circuits are more likely to contain manufacturing flaws and be vulnerable to dynamic
errors when operating, as a result of improvements in the CMOS technologies and
the reduction of feature size in relation to the nanoscale scale [1, 2]. Among the many
drawbacks of nanoscale electronics, the most notable is their greater vulnerability to
soft mistakes and higher failure rates. You can’t run a circuit without addressing both
of these kinds of faults. The capacity of a circuit to continue functioning correctly
in the presence of such mistakes is known as its reliability. The causes of transient
(soft) mistakes are rather varied. Examples of these include coupling, leakage, high-
energy particles, noise from the power source, and fluctuations in the circuit over
time. The transitory error(s) caused by a soft error could persist for the duration of
one or more clock cycles. There is a transient current pulse that happens if a charged
particle contacts the combinational logic, and this is known as a single event tran-
sient (SET). An inaccurate value at the gate output can be the consequence of a suf-
ficiently wide and magnitude transient. The mistaken value is stuck to an element in
memory, turning a SET into a single event upset (SEU). The use of a single SET may
generate several current pulses that are transitory at their output [3]. This happened
as a result of the logic fan-out in the circuit.
When opposed to the situation in which redundancy is supplied at a higher level
of abstraction, the addition of redundancy at the level of the transistors is advanta-
geous because it enables larger fault coverage in addition to offering inherent protec-
tion from errors that are present inside a circuit [4]. Due to the increasing likelihood
of chip failures caused by the high integration ratio of transistors, fault tolerance has
recently taken on more significance. Hardware fault tolerance methods are catego-
rized into two types: static and dynamic. While dynamic reconfiguration methods
[5] are more space and power-efficient than static methods due to the selective activa-
tion of spare modules in response to the detection of defective active modules, static
methods [6, 7] can tolerate any type of defect, whether permanent, intermittent, or
transient, and hence offer more reliable solutions. Sporadic faults have become ubiq-
uitous in modern microcomputer systems [8], whereas single event upsets [9] are
Design an Inverter with a Quad-Model Transistor 3

prevalent in space applications and satellite communications [10]. Those kinds of

errors are too many for the dynamic recovery approach to handle. Furthermore,
dynamic reconfiguration does not apply to real-time fault tolerance for safety-critical
applications due to the additional amount of time necessary for testing and reconfig-
uring. Static approaches are ideal in these situations since they may hide mistakes
right away. However, most static techniques now available have huge area overheads
[11], which limits their usefulness in applications with limited resources [12]. To
minimize space overhead and maximize hardware utilization efficiency, it is often
necessary to initially make just the most crucial parts of a fault-resistant system [13].
Fabrication defects and radiation exposure of integrated circuits lead to their fail-
ure. If circuits are to be used for space applications, they cannot be replaced readily
[14, 15]. So, we need a fault-tolerant design that can withstand some defects and
still work as per our requirements. The idea is to replace every transistor with a
quad transistor so that the failure of any one transistor does not lead to the failure
of a complete circuit [16]. This is mainly providing a fault-tolerant inverter with and
without isolation transistors as many as possible at the physical description level.
Here the main focus is on architecture having to work properly rather than fail-
ing. So, we did not give much preference to power, area, and delay but these can be
reduced, if possible, in all logic gates and circuits. Now, first, we discuss faults.

1.2 FAULT MODEL
Static fault-tolerant solutions can accept any type of fault, regardless of whether it is
permanent or temporary. In the technology we have developed, we have taken into
account both stuck-ON and stuck-OFF transistor faults. The terms “sticky-ON” and
“sticky-OFF” defects in MOSFET refer to the persistent closing (shortening) and the
opening of the pathway at the source and drain of the device, respectively [17]. As
a result, in reality, stuck-OFF faults act appropriately and are represented as stuck-
ON faults, but stuck-open faults are equivalent to transistor stuck-OFF faults and
are therefore modeled as such. If an NMOS transistor has a stuck input AT-1 (SA-1)
fault at its gate terminal, the drain–source connection will be permanently blocked,
which is similar to a stuck fault of the transistor. An input stuck-at-0 (SA-0) fault in
an NMOS transistor causes an opening in the channel between the drain and source,
resulting in a stuck-OFF fault in the transistor. Similar to the previous example, a
PMOS transistor with an SA-1 or SA-0 gate defect may be represented as a transistor
with its ON gate defect, or the other way around.

1.2.1 Fault Types
A fault refers to any deviation or abnormality in the operation, behavior, or perfor-
mance of a system or component from its expected or intended state. Faults can arise
from various sources, including design flaws, manufacturing defects, environmental
factors, wear and tear, and human error. They can manifest as errors, malfunctions,
or failures that adversely affect the functionality, reliability, or safety of a system.
Faults in integrated circuits occur due to many reasons but mainly due to fabrication
4 Circuit Design for Modern Applications

defects and radiations. So, if any transistor fails the circuit output is incorrect. These
fault types are crucial for MOSFET designers, manufacturers, and users to ensure
device reliability and performance in various applications. Additionally, fault analy-
sis techniques such as reliability testing, failure analysis, and modeling help identify
and mitigate these issues during the design and manufacturing stages. Here are some
common fault types across different domains:
The faults are two types:

1. The transistor is always ON, also called a stuck-ON fault.

2. The transistor is always OFF also called a stuck-OFF fault.

These faults occur temporarily and may result from momentary disturbances such
as electrical noise, voltage spikes, or signal interference. Transient faults typically do
not cause permanent damage but can lead to temporary disruptions in system opera-
tion. These faults can occur both in NMOS as well as PMOS. In the PMOS (NMOS)
transistor, a fault occurs if the gate terminal connects to the power supply (ground).
The transistor is always OFF. The other case is; that if the gate terminal of the PMOS
(NMOS) transistor connects to the ground (supply voltage); the transistor is always
ON. This fault is shown in Figures 1.1 and 1.2.

1.2.2 Quad Model
The single transistor is replaced by four transistors in the quad model, which is the
simplest definition of the quad model. The illustration of the quad model concerning
NMOS and PMOS transistors is shown here [18]. However, quad logic (QL) technol-
ogy is superior to Triple Modular Redundancy (TMR) technology reliability-wise
and along the crucial route. However, quad logic technology requires approximately

FIGURE 1.1 Faults in PMOS.

FIGURE 1.2 Faults in NMOS.

Design an Inverter with a Quad-Model Transistor 5

FIGURE 1.3 Fault-tolerant PMOS quad model.

FIGURE 1.4 Fault-tolerant NMOS quad model.

eight times the area of non-redundant technology, and it takes up to the latter two
degrees of error absorption, rendering it wasteful for logic–depth–limited circuits.
It is possible to choose the final output from the quadrangle using majority voters
at the output; however, this method is not without its shortcomings for voters who
are not trustworthy. By the methods described above, the quad transistor (QT) logic
which was developed by El-Maleh et al. [19] contains a solution that is more cost-
effective than QL logic. In this logic, each transistor in the circuit being studied is
quadrated. In the past [4, 20], have investigated further concepts on quadrature com-
ponents to promote circuit reliability. When using QT, the transistors in the circuit
are swapped out for two sets of transistors linked in series or parallel, as seen in
Figures 1.3 and 1.4, respectively. Both these connections are illustrated respectively.
In the context of a single transistor, the value obtained from the quadrant input is the
same as the value obtained from the first input. As can be seen from the structures
shown in Figures 1.3 and 1.4, the circuit continues to function normally if a single
transistor in the fault-tolerant QT fails for which it was initially designed. It is also
possible for systems to be able to tolerate multiple failures affecting a specific group
of transistors.

1.2.3 Quad Model of PMOS and NMOS Transistors

Below is the circuit diagram of the quad PMOS transistor. Here in fault-tolerant
architectures, each conventional PMOS is replaced with four PMOS transistors.
The quad model of PMOS is given by two series and two parallel connections of
6 Circuit Design for Modern Applications

transistors. If any PMOS transistor is faulty, say shorted (ON), then it will not affect
the performance as obtaining a HIGH output is not a problem. But if the PMOS tran-
sistor is permanently open (OFF) then it has some effects on the circuit performance
but we get the desired logic output. If we want the output HIGH, then due to a faulty
transistor that path is completely OFF the circuit model chooses the other path so
there will be a slight increase in the delay.
Below is the circuit diagram of the quad NMOS transistor. Here in fault-tolerant
architectures, each conventional NMOS is replaced with four NMOS transistors.
The connection among four transistor is given by parallel connection of two pairs of
transistors connected in series. If any NMOS transistors among the four are faulty
say permanently shorted (ON), then it will not affect the performance much because
if we want the output to go LOW it is not a problem. But if the NMOS transistor is
permanently open (OFF), then it has some effect on circuit performance, but we get
the exact same output. If we want the output LOW, then due to a faulty transistor that
path is completely OFF and the circuit model chooses the other path, so there will be
a slight increase in delay.

1.2.4 Natation of PMOS and NMOS

The notation of the quad model of the PMOS and NMOS are represented in Figures
1.5 and 1.6. This notation will be used in all the architectures in future work.

FIGURE 1.5 Simple notation of fault-tolerant PMOS quad model.

FIGURE 1.6 Simple notation of fault-tolerant NMOS quad model.

Design an Inverter with a Quad-Model Transistor 7

FIGURE 1.7 Fault-tolerant quad NMOS with isolation transistors.

1.2.5 A Quad Model with Isolation Transistors

Here in this chapter fault-tolerant standard gates and circuits with isolation tran-
sistors are described with their schematic diagram, layout, and the corresponding
simulation. The reason for going with isolation transistors is that there is a chance
of getting a fault for two neighboring transistors that share a common source/drain
[21]. Due to having a common source/drain if one transistor is faulted, its effect will
automatically be there on another transistor. The other reason for putting isolation
transistors is that the complexity of the circuit will become huge as the area of the
circuit becomes large so if we can put an isolation transistor between them saying
that if we follow a semi-custom design style, it can reduce the complexity. Figure 1.7
shows how a fault-tolerant NMOS transistor is represented with an isolation transis-
tor, where the red line indicates the isolation transistor.

CONVENTIONAL CMOS INVERTERS

Below is the schematic for a static CMOS inverter. An enhancement-type PMOS
load transistor and an enhancement-type NMOS driver transistor make up the cir-
cuit. With the help of the MOS transistor’s basic switch concept, its functioning may
be easily understood. The transistor is a switch that has an infinite OFF-resistance
when the voltage drop across its gate (VGS ) is less than the value of the V T, and a finite
on-resistance when the voltage across its gate (VGS ) is more than the value of V T [22].
There is a connection made between the gate terminals of NMOS as well as
PMOS transistors and the input voltage. The GND is connected to the substrate of
the NMOS transistor, whereas the VDD is connected to the substrate of the PMOS
transistor. The symbol and truth table are presented in Figure 1.8.

1.3.1 Circuit Operation
In Figure 1.9, both the NMOS and PMOS transistors’ gate terminals have connec-
tions to the voltage at the input [23]. When VIN is elevated and matches VDD, then
the NMOS transistor is turned ON and the PMOS transistor is turned OFF. A value
of 0 V in steady state is produced because VOUT has a direct route to the ground
node. For input voltages of 0 V (LOW), PMOS transistors are turned ON and NMOS
8 Circuit Design for Modern Applications

FIGURE 1.8 Conventional CMOS inverter and truth table.

FIGURE 1.9 Switch models of a conventional CMOS inverter.

transistors are turned OFF, respectively [24]. Furthermore, a high output voltage
may be achieved since a route does exist between VDD and VOUT (Figure 1.9).

1.3.2 Internal Capacitance
To understand the parasitic capacitances that are connected with each MOSFET,
take into consideration the cascade connection of two CMOS inverter circuits, which
is shown in Figure 1.10. Gate overlap with diffusion is the primary cause of the

FIGURE 1.10 Internal parasitic capacitance in a CMOS inverter

Design an Inverter with a Quad-Model Transistor 9

capacitance Cgs and Cgd to be present. Voltage-dependent junction capacitances are

denoted by the symbols Cdb and Csb . Across the gate region, the thin oxide capaci-
tance is the component of capacitance denoted by Cg . Also, we take into account the
lumped interconnect capacitance, denoted by the symbol Cint , which is the parasitic
capacitance involvement of the linking among the two inverters, whether it be made
of metal or polysilicon [24, 25]. The term “load capacitance” will be used to refer to
the total capacitance at the output node, Cload .

Cload  Cgd , n  C gd , p  Cdb, n  Cdb, p  Cint  Cg (1.1)

Quadrupling the gate capacitances of the QT logic as a result of every transistor

being changed out for a quad structure. As a result, the system becomes rather slug-
gish and consumes a lot of power, which is why the approach is not suitable for real
designs. In order to boost the speed of the system, it is possible to increase the size of
the transistors; however, this would result in an increase in the area overhead present
in the overall design. When each of the quadrupled inputs of a single transistor is fed
independently from a single output of the level below it, the interconnections become
rather complicated. It is possible to lessen the difficulty by quadrupling the quadded
gates at each level. This will allow for the generation of four distinct outputs, which
can then be fed into the QT [26] gate at the following level. On the other hand, such
a design necessitates an impractical amount of hardware overhead, which has been
resolved through the implementation of a gate-specific QT (QT8) constructed with
SEU mitigation method. This technique involves making a link to the particular
inputs for a quadratic gate by utilizing two replicas of the quad gates from the level
below it. This reduction in the total number of transistors is approximately 50%.
In contrast to the design that does not use redundancy, this one nevertheless needs
around eight times the amount of space. For the TMR–QT approach [27], QT is used
in the design of the electorates in TMR, which results in an exceptionally high level
of circuit dependability. However, due to the fact that the majority voter is a quadded
structure, this technique requires a huge space in addition to delay overheads.

1.3.3 Calculation of Delay Time

The calculation of the delay time depends on several factors such as the sizes of the
transistors, the load capacitance, and the properties of the technology (like process
and temperature) [28]. Here, I will provide an overview of the calculation without
specific numerical values. It is evident from Figure 1.11 that the propagation delay
periods t PHL and t PLH are responsible for determining the signal delay from input to
output that occurs during the change from high to low of the output and switching
from low to high in the output, respectively. The amount of time that passes between
the V 50% transition of the rising input voltage and the V 50% transition of the drop-
ping output voltage is shown by the variable t PHL [29, 30]. A similar definition can
be found for tPLH, which is the amount of time that elapses between the V 50% transi-
tion of the falling input voltage and the V 50% transition of the rising input voltage.
10 Circuit Design for Modern Applications

FIGURE 1.11 Input and output waveforms of the inverter and the propagation delay.

In most cases, it is assumed that the waveform of the input voltage is an ideal step
pulse with no rise and fall time [31]. Under this assumption, the time necessary for
the output voltage to decrease from VOH to the V 50% level is denoted by t PHL , while
the time required for the output voltage to increase from VOL to the V50% level is
denoted by t PLH . The voltage point V50% is defined as follows:

1 1
V50%  VOL  VOH  VOL   VOH  VOL  (1.2)
2 2
Thus, the propagation delay time t PHL and t PLH are found:

t PHL  t1  t0 (1.3)

t PLH  t3  t2 (1.4)

A characteristic of the inverter is the average propagation delay, denoted by the sym-
bol t P . This delay represents the average amount of time that is necessary for the
input signal to go through the inverter.

t PHL  t PLH
tp  (1.4)
2

1.3.4 Results and Discussion

Here we discussed the schematic and layout of the conventional CMOS inverter and
fault-tolerant quad inverter. We found the faults in the conventional inverter, and
identified the changes in output due to the fault. We also discussed how to resolve the
fault and found the desired output using a quad-model inverter.
Design an Inverter with a Quad-Model Transistor 11

FIGURE 1.12 Schematic circuit of the CMOS inverter.

1.4.1 Layout Design of CMOS Inverters

Building a physical representation of the inverter circuit on a semiconductor sub-
strate, which is commonly silicon, is an essential part of the layout design procedure
for a CMOS inverter.

1.4.1.1 Schematic Circuit of the CMOS Inverter

Figure 1.12 displays the schematic circuit of the CMOS inverter. The width of PMOS
is three times greater than the NMOS.
The source and substrate terminals of NMOS are connected to the ground termi-
nal and the source and substrate terminals of PMOS are connected to VDD termi-
nals. The drain terminals of both PMOS and NMOS are common and connected to
the output terminal. The gate terminal of both MOSFETs is common and connected
with the input terminal [32].

1.4.1.2 Layout of the CMOS Inverter

Figure 1.13 shows the layout of the CMOS inverter. The width of the PMOS transis-
tor is three times that of the NMOS transistor to maintain equal rise and fall time as
the mobility of the hole is 1/3 of that of electron mobility.

FIGURE 1.13 Layout circuit of the CMOS inverter.

12 Circuit Design for Modern Applications

FIGURE 1.14 Output waveforms of the CMOS inverter.

1.4.1.3 Output Waveform of the CMOS Inverter

Figure 1.14 shows the output waveform of the CMOS inverter for both schematic and
layout circuits, and Table 1.1 shows the propagation delay of both circuits with and
without parasitic capacitance.
Table 1.1 shows the propagation delay of the conventional CMOS inverter for
different dimensions. Here the propagation delay is found with parasitic capacitance
and without parasitic capacitance. It was observed that the propagation delay is mini-
mal when parasitic capacitance is not included in Table 1.1.

1.4.2 Fault-Tolerant Inverter
As mentioned above, the propagation delay was calculated for different dimensions
of the CMOS inverter. Now if any type of fault is found in a single transistor, the
desired output will not be found. Table 1.2 shows the truth table of the inverter if any

TABLE 1.1
Propagation Delays for a CMOS Inverter
Propagation Without With
Size of Transistor Delay Parasitic (in ps) Parasitic (in ps)
Width of PMOS (720nm) and t PHL 8.9650 11.1477
Width of NMOS (240nm)
t PLH 8.4752 11.6754

tP 8.7608 11.4115
Width of PMOS (1440nm) and t PHL 15.3653 18.3895
Width of NMOS (480nm)
t PLH 12.0104 15.0159

tP 13.6878 16.7027

Width of PMOS (720nm) and t PHL 9.0208 12.7851

Width of NMOS (480nm) 15.0602 21.8844
t PLH

tP 12.0442 17.3347
Design an Inverter with a Quad-Model Transistor 13

TABLE 1.2
Truth Table of a Normal CMOS Inverter if a Transistor is Faulty
A Y M1 M2
ON OFF ON OFF
0 1 1 Z VDD 1
2
1 0 VDD 0 0 Z
2

of the transistors has a fault. Here the PMOS is represented as M1, NMOS as M2, A
as input, and Y as an output. The fault type has already been discussed above.
It is seen in Table 1.2 that if any of transistor produces any type of fault the
inverter will not give the desired output. Therefore, quad-model transistors are used
to tackle this issue and also getting the desired output.
The design style of the fault-tolerant inverter is the same as the CMOS inverter.
As we said above each transistor is replaced with four transistors [4], so the total
number of transistors here in the fault-tolerant inverter is now eight, which means
the area is increased four times. A schematic diagram of the fault-tolerant inverter is
shown in Figure 1.15. The width of the PMOS transistor is increased three times of
the NMOS transistor to maintain equal charging and discharging currents.
In a fault-tolerant inverter if any one transistor is faulty there is no effect on the
output of the inverter. Here, Table 1.3 shows the truth table of a fault-tolerant inverter.

1.4.2.1 Schematic Circuit of CMOS Inverter Using a Quad Transistor

Figure 1.16 displays the schematic circuit of the fault-tolerant inverter where the size
of PMOS and NMOS are 720nm/180nm and 240nm/180nm, respectively. Here, it is
seen that a single transistor was replaced with four transistors.

FIGURE 1.15 Fault-tolerant inverter.

 14

TABLE 1.3
Truth Table of a Fault-Tolerant Inverter
A Y M1 M2 M3 M4 M5 M6 M7 M8
ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Circuit Design for Modern Applications
Design an Inverter with a Quad-Model Transistor 15

FIGURE 1.16 Schematic circuit fault-tolerant inverter.

FIGURE 1.17 Layout circuit of fault-tolerant inverter.

1.4.2.2 Layout of CMOS Inverter Using a Quad Transistor

Figure 1.17 depicts the layout of a fault-tolerant inverter using a quad model and
drawn according to the schematic circuit. This layout of a CMOS inverter using quad
transistors provides an inverting logic operation where the output is a complement
of the input.

1.4.2.3 Output Waveforms of CMOS Inverter Using a Quad Transistor

The output waveform of a CMOS inverter using quad transistors exhibits the typical
behavior of an inverter. The output waveform of an is seen in Figure 1.18 of fault-
tolerant inverter for both schematic and layout circuits. In Figure 1.18 the red line
illustrates the input and the green and pink lines demonstrate the outputs. Where the
green line shows the output without parasitic capacitance and the pink line shows the
output with parasitic capacitance.
Table 1.4 shows the propagation delay of the fault-tolerant inverter. It was observed
that the propagation delay is minimal when no parasitic capacitor is considered but
when the parasitic capacitor is included the propagation delay increases.
16 Circuit Design for Modern Applications

FIGURE 1.18 Output waveform of fault-tolerant inverter.

TABLE 1.4
Propagation Delay of a Fault-Tolerant Inverter
Propagation Without With Parasitic
Size of Transistor Delay Parasitic (in ps) (in ps)
The size of PMOS and NMOS are t PHL 25.0498 35.3916
(720nm/180nm) and (240nm/180nm)
t PLH 33.5569 47.1899

tP 29.3033 40.7907

1.4.3 Fault-Tolerant Inverter with Isolation Transistors

The design style of a fault-tolerant inverter with isolation transistors is the same as
that of a fault-tolerant inverter without isolation transistors, except here an isolation
transistor is placed between two neighboring transistors that share a common source/
drain. So, the area required for a fault-tolerant inverter with isolation is six times
more. The schematic diagram of the fault-tolerant inverter with isolation transistors
is given in Figure 1.19.

FIGURE 1.19 Fault-tolerant inverter with isolation transistors.

Design an Inverter with a Quad-Model Transistor 17

FIGURE 1.20 Schematic circuit fault-tolerant inverter with isolation transistors.

1.4.3.1 Schematic Circuit of a Fault-Tolerant Inverter with Isolation

Figure 1.20 shows the schematic circuit of a fault-tolerant inverter with isola-
tion where the size of PMOS and NMOS are 720nm/180nm and 240nm/180nm,
respectively.

1.4.3.2 Layout of a Fault-Tolerant Inverter with Isolation

Figure 1.21 shows the layout of the fault-tolerant inverter with isolation drawn as per
the schematic circuit of the fault-tolerant inverter with isolation.

1.4.3.3 Output Waveform of a Fault-tolerant Inverter with Isolation

Figure 1.22 shows the output waveform of a fault-tolerant inverter with isolation for
both schematic and layout circuits. In Figure 1.22 the red line demonstrates the input
and the green and pink lines illustrate the outputs. Where the green line shows the
output for those without parasitic capacitance and the pink line shows the output for
those with parasitic capacitance.
Table 1.5 shows the propagation delay of both the circuits with and without para-
sitic capacitance. It was observed that the propagation delay was minimal without
parasitic capacitance.

FIGURE 1.21 Layout of a fault-tolerant inverter with isolation transistors.

18 Circuit Design for Modern Applications

FIGURE 1.22 Output waveform of a fault-tolerant invertor with isolation.

TABLE 1.5
Propagation Delay of a Fault-Tolerant Inverter with Isolation
Propagation Without With Parasitic
Size of Transistor Delay Parasitic (in ps) (in ps)
The size of PMOS and NMOS are t PHL 25.0498 35.3916
(720nm/180nm) and (240nm/180nm)
t PLH 33.5569 47.1899

tP 29.3033 40.7907

1.5 AREA AND DELAY

In order to get a comparison of area and delay, all of the circuits were simulated in
Cadence by making use of the UMC 180 nm standard cell library. The results of our
simulations for area and delay below are shown in Table 1.6, which demonstrates that
QT needs a greater area overhead than other approaches; however, this also includes
the QGT method that was recently introduced for the purpose of creating QT. This
is suitable for the applications with restricted resources. Although QT necessitates
a much longer critical path than other approaches, it still necessitates a significantly
longer latency than other methods that are being considered, including QT8, which is
a modified version of QT. It is possible that the QT approach that has been provided

TABLE 1.6
Comparative Analysis of QT and the Existing
Architecture of Inverters
Inverter Area Average propagation delay
(NOT gate) (in µm2 ) (in ps)
Non-redundant 6.25 18.27
TT 18.49 29.74
QT 24.27 43.27
Design an Inverter with a Quad-Model Transistor 19

does not seem to be the most effective solution for fault-tolerant circuit design; none-
theless, it does give much fewer fabrication flaws and radiation hardening concerns
that have been resolved. The provision of fault-tolerant solutions for applications that
demand larger space is thus a beneficial use of this. Here increase in area is a signifi-
cant problem, but in other hand it can tolerate a little delay in the processing time.
The complexity of chip design may grow if one transistor is replaced with four
transistors by the same amount. Because of this modification, the circuitry will
most likely need to be redesigned to fit the extra transistors. This may need more
complex layout planning, routing, and testing procedures. In addition, the presence
of a greater number of transistors results in increased power consumption and an
increased number of possible failure spots, which further complicates the design
process. Nevertheless, such alterations may also give advantages such as better per-
formance, functionality, or dependability, which would make the complexity ben-
eficial in some circumstances. Overall, it’s a trade-off between complexity and the
desired outcomes of the chip design.

1.6 CONCLUSION
Fault-tolerant design is essential for space applications because once the chip is
placed in a satellite and sent to space if it fails then it leads to the failure of the
vehicle, and the mission. So, chip failure in space is a major problem. So, we need
to provide a chip architecture that works even if some of the transistors fail, so that
it merely increases delay rather than failing completely. By considering these issues
a fault-tolerant standard cell library was designed. As expected, when we adopted a
fault-tolerant architecture with the QT the area increased by four times for transis-
tors without isolation and increased up to five times for with transistors with isolation
when compared to the CMOS technology. Delay is expected to increase more when
the transistor fails, but it is decreased in some architectures when it is compared with
no-fault condition delays. As the chip area grows, power consumption increases, but
it does not consider because we are more concerned with functionality than power.

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 2 Exploring the Design
and Performance
Dynamics of CMOS
Voltage-Controlled
Ring Oscillator Stages
M.V. Rajee and C. Mythili

2.1 INTRODUCTION
Voltage-controlled oscillators (VCOs) play a pivotal role in various applications
and industries, contributing to the advancement of modern electronics in specific
domains. In telecommunications and wireless communication systems, VCOs are
essential components in frequency synthesizers used for signal modulation and
demodulation, frequency conversion, and channel tuning in devices such as mobile
phones, Wi-Fi routers, and satellite communication systems. In radar and navigation
systems, VCOs are crucial for generating microwave signals used in radar trans-
mitters, altimeters, and navigational aids, enabling precise distance measurement,
target detection, and location tracking. Moreover, in medical imaging and diagnos-
tic equipment, VCOs are employed in magnetic resonance imaging (MRI) systems,
ultrasound scanners, and spectroscopy devices to generate radio-frequency signals
for tissue excitation and signal acquisition, facilitating non-invasive imaging and
diagnosis of various medical conditions. Additionally, in aerospace and defense
applications, VCOs are utilized in radar systems, electronic warfare systems, and
missile guidance systems for target detection, jamming, and precision guidance,
enhancing national security and military capabilities.
A VCO is a crucial electronic circuit employed in various applications, especially
in the field of analog and radio-frequency integrated circuits. The primary function
of a VCO is to generate an oscillating signal whose frequency can be modulated
by an external voltage, making it a versatile component in communication systems
and frequency synthesizers. The VCO operates on the principle of utilizing a ring
of interconnected inverters or delay elements to produce a continuous oscillating
waveform. By adjusting the input voltage, the oscillation frequency can be precisely
controlled, providing a means to achieve frequency modulation or demodulation.

22 DOI: 10.1201/9781003483052-2
Exploring the Design and Performance 23

The design and optimization of voltage-controlled ring oscillators are critical tasks,
involving considerations such as tuning range, phase noise, and power consumption.
These characteristics make VCOs indispensable in modern electronics, contributing
to the efficient generation of clock signals and meeting the dynamic requirements of
contemporary communication devices.
One key feature is their unparalleled frequency tunability, allowing precise
adjustment of the output frequency by varying the control voltage. This attribute
is particularly vital in applications like frequency synthesis and modulation, where
the ability to fine-tune frequencies is critical. VCOs also boast a wide operating
frequency range, accommodating diverse communication standards and system
requirements. Renowned for low phase noise, they ensure stable and high-quality
signal output, crucial in communication systems where signal fidelity is paramount.
Many VCOs are designed with low power consumption, making them suitable for
energy-efficient devices and battery-powered applications. Their compact design
facilitates integration into integrated circuits, often providing versatile outputs such
as sine, square, or triangle waves. Whether applied in wireless communication, radar
systems, or frequency synthesis, the versatility, precision, and adaptability of VCOs
underscore their significance in modern electronic systems.
VCOs exhibit several key advantages that contribute to their widespread use in
electronic circuits. One primary advantage lies in their inherent frequency tunabil-
ity, allowing precise control of the oscillation frequency by adjusting the input volt-
age. This feature is particularly valuable in applications such as frequency synthesis
and modulation, where flexibility in signal generation is paramount. Additionally,
VCOs offer a compact design, making them well-suited for integration into inte-
grated circuits. Their low power consumption enhances energy efficiency, a critical
consideration in battery-powered devices and energy-conscious systems. The sim-
plicity of the ring oscillator structure, typically comprising a loop of interconnected
inverters, not only aids in ease of design but also contributes to cost-effectiveness.
Versatility in applications, ease of integration with digital technologies, and the abil-
ity to operate across a wide temperature range further underscore the advantages of
voltage-controlled ring oscillators in meeting the dynamic requirements of modern
electronic systems.
In recent years, significant advancements and emerging trends have been observed
in CMOS VCO design and optimization, reflecting the ongoing pursuit of higher
performance, lower power consumption, and enhanced integration capabilities. One
notable trend is the increasing utilization of advanced semiconductor technologies,
such as FinFET and FD-SOI, to achieve superior performance and efficiency. These
technologies offer improved transistor characteristics, reduced leakage currents, and
enhanced scalability, enabling the development of highly integrated and energy-effi-
cient VCOs for a wide range of applications.
Moreover, there has been a growing emphasis on the development of novel VCO
architectures and topologies to address specific challenges and requirements in
emerging applications. For instance, fractional-N synthesizers and digitally con-
trolled oscillators (DCOs) have gained prominence in wireless communication
systems, offering enhanced frequency resolution, agility, and spectral purity while
24 Circuit Design for Modern Applications

minimizing phase noise and spurious emissions. Additionally, ring oscillator-based

VCOs with digitally assisted tuning techniques have emerged as viable solutions for
frequency-agile and multi-band communication systems, providing flexibility and
adaptability to dynamic operating conditions. Furthermore, advancements in cir-
cuit design techniques, such as noise-aware optimization, layout-aware synthesis,
and adaptive biasing, have played a crucial role in improving the performance and
robustness of CMOS VCOs. These techniques aim to mitigate the impact of process
variations, device mismatch, and environmental noise on VCO performance, thereby
enhancing yield, reliability, and manufacturability. Another notable trend is the inte-
gration of advanced digital signal processing (DSP) algorithms and techniques into
VCO designs to enable adaptive calibration, self-correction, and dynamic reconfigu-
ration in response to changing operating conditions and requirements. This integra-
tion facilitates the implementation of intelligent, self-optimizing VCOs capable of
continuously monitoring and adjusting their performance parameters to maximize
efficiency and reliability.
Overall, recent advancements in CMOS VCO design and optimization have led
to the development of highly integrated, energy-efficient, and adaptive VCOs tai-
lored to meet the demanding requirements of modern communication, sensing, and
computing systems. These advancements not only enhance the performance and
functionality of VCOs but also pave the way for the realization of next-generation
wireless networks, IoT devices, and smart sensor systems.
This chapter delves into the exploration of various types of CMOS VCOs and pro-
vides a comprehensive comparison of their diverse performance metrics. The focus
lies on understanding and evaluating the unique characteristics of different CMOS
VCO architectures, each designed to meet specific performance requirements. The
comparison encompasses crucial performance metrics such as operating frequency
range, power consumption, and phase noise. By thoroughly examining these met-
rics, the chapter aims to shed light on the strengths and weaknesses of each CMOS
VCO type, providing valuable insights into their suitability for different applications.
The goal is to offer readers a nuanced understanding of the trade-offs involved in
choosing a particular CMOS VCO design, aiding researchers and practitioners in
making informed decisions based on the specific performance criteria relevant to
their applications.

2.2 LITERATURE SURVEY
Here is an overview of the different single-ended CMOS voltage-controlled ring
oscillators that have been published in the literature.
Hajimiri et al. [1] proposed a time-variant model for the investigation of phase
noise in differential and single-ended ring oscillators. A formula for the impulse
sensitivity function (ISF) root mean square value is obtained. A phase noise lower
bound for ring oscillators is presented along with a closed-form equation for ring
oscillators’ phase noise. Measurements of phase noise in oscillators operating at up
to 5.5 GHz show good agreement with the theory. Rezayee et al. [2] describe a two-
stage CMOS VCO functioning at 900 MHz that has good phase-noise performance.
Exploring the Design and Performance 25

The VCO is implemented in a 0.5-/spl mu/m CMOS technology and functions at a

2.5-V supply voltage, has a peak VCO gain (K/sub VCO/) of –630 MHz/V and an
extensive operating frequency range of 661.5 MHz to 1.27 GHz. The VCO has low
power consumption of 15.4 mW and phase noise of –105.5 dBc/Hz at 600 kHz fre-
quency offset at 900 MHz. There is an image rejection of better than 31 dB because
the phase and gain mismatches are less than 0.5/spl deg/ and less than 0.25 dB,
respectively. Merely 125/spl times/102 /spl mu/m/sup 2/ makes up the chip area.
Do et al. [3] describe a wideband VCO that operates in the 830 MHz to 2.4 GHz
frequency range. The VCO features two quadrature outputs in addition to two con-
trol inputs—one for band switching and the other for continuous output frequency
control. This VCO is simulated at a supply voltage of 2 V, using a 0.25 μm CMOS
technology. Two distinct bands yield a broad tuning range of 98%. Throughout the
whole frequency range, the harmonic distortions are sufficiently reduced. For the
oscillation frequency of 830 MHz, the phase noise is –105 dBc/Hz at 400 kHz off-
set, and for the oscillation frequency of 2.42 GHz, it is –89 dBc/Hz at 400 kHz
offset. The VCO’s first band gain is 745.6 MHz/V, while its second band gain is
1.22 GHz/V. Since accurate quadrature outputs are required in all contemporary
transceiver topologies, they are maintained over the whole frequency range. At 2.42
GHz, a compensation circuit reduces its second harmonic to less than –33 dB in the
worst scenario.
Eken et al. [4] presented oscillation frequencies up to 5.9 GHz are presented
for three- and nine-stage voltage-controlled ring oscillators that were produced in
TSMC 0.18-/spl mu/m CMOS technology. The circuits employ cross-coupled FETs
in delay stages and a multiple-pass loop architecture to enhance the noise charac-
teristics and speed up switching. The oscillators have linear frequency-voltage char-
acteristics over a broad tuning range, as demonstrated by the measurements. The
frequency ranges of 5.16–5.93 GHz and 1.1–1.86 GHz, respectively, are achieved by
the three- and nine-stage rings. While the three-stage ring oscillator was simulated
to have phase noise of –99.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center fre-
quency, the nine-stage ring oscillator’s measured phase noise was –105.5 dBc/Hz at
a 1-MHz offset from a 5.79-GHz center frequency.
Wei et al. [5] proposed an ultra-wideband CMOS VCO with a tuning range of
3–5 GHz. The circuit was created using the 0.18-/spl mu/m TSMC CMOS process.
The passive spiral inductor is being replaced by an adjustable active inductor in the
proposed VCO. Through the use of a feedback adjustable resistor, the active inductor
may adjust the inductance between 1.5/spl sim/7 nH with a quality factor of > 30.
This design delivers higher performance with a very wide tuning range and compact
chip size, according to comparisons with traditional VCOs. About 3 to 5 GHz is the
tuning range for ultra-wideband system applications.
A CMOS differential delay cell for tuning range in low voltage operation was
described by Yu-Sheng Tiao et al. [6]. A 0.18 μm CMOS process is utilized to cre-
ate a three-stage ring oscillator by means of a delay cell. The high-speed and tuning
range are attained by using the multiple-pass loop approach. VCO operates with a
control voltage fluctuation of 0 V to 1.8 V, covering a frequency range of 1.29 GHz
to 8.36 GHz. The phase noise of the VCO circuit is –100.22 dBc/Hz at 1 MHz offset
26 Circuit Design for Modern Applications

from the oscillation frequency of 8.35 GHz. For the VCO, the figure of merit (FoM)
is –159.95 dBc/Hz. A CMOS differential delay cell for tuning range in low voltage
operation was described by Yu-Sheng Tiao et al. [7]. A 0.18 μm CMOS process is
utilized to create a three-stage ring oscillator by means of a delay cell. The high
speed and tuning range are attained by using the multiple-pass loop approach. VCO
operates with a control voltage fluctuation of 0 V to 1.8 V, covering a frequency
range of 1.29 GHz to 8.36 GHz. The phase noise of the VCO circuit at 1 MHz offset
from the oscillation frequency of 8.35 GHz is –100.22 dBc/Hz. The VCO has a FoM
of –159.95 dBc/Hz.
In order to modify the current of the output node in a 180 nm CMOS process, L.
Xuemei et al. [8] proposed a three-stage ring voltage-controlled oscillator based on
a distinct cascade voltage logic delay cell with current source load. The VCO design
has a frequency range of 0.770 GHz to 3.286 GHz, with a power consumption of
15.1 mW and phase noise of –97.93 dBc/Hz at a 1 MHz offset from the 5.2684 GHz
carrier frequency. C. Zhang et al. [9] describe a four-stage differential ring voltage-
regulated oscillator in 0.18 μm CMOS technology. To produce a frequency range, the
inductive shunt peaking approach is applied using an active inductor. The VCO cir-
cuit exhibits phase noise of –86.7 dBc/Hz at 1 MHz offset, a figure of merit of –149.7
dBc/Hz, and oscillations within the tuning range of 4.9 GHz to 5.9 GHz. Moreover,
VCO uses 8.1 mW of power.
Ebrahim Abiri et al. [10] proposed a low-power frequency synthesizer for WLAN
applications. The goal of the NMOS transistor-feedback VCO is to reduce phase
noise. The purpose of the TSPC frequency splitter is to increase frequency range
while consuming less power. In addition to having a low blind and dead zone and
neutralizing charge pump (CP) output currents, the phase frequency detector (PFD)
with XOR delay cell is designed to include miller capacitors and a high-gain opera-
tional amplifier in the circuit. Operating at 1.8 V supply voltage, the frequency syn-
thesizer is simulated on 0.18 µm CMOS technology. The phase noise of the VCO at
1 MHz offset is –136 dBc/Hz. The tuning range is 10.2%. The output frequency of
the VCO can be divided into a maximum ratio of 18 thanks to the presence of a fre-
quency divider in the frequency synthesizer loop. It is estimated that the frequency
synthesizer has a chip area of 10,400 µm2 and a power consumption of 4 mW.
J. Jin et al. [11] proposed a novel gain linearized varactor bank for wideband
VCOs. Low tuning gain is achieved in the varactor bank by using linearized VCO
tuning gain techniques including gain variation compensation and linear tuning
range extension. The 0.18 μm CMOS technology is utilized to create the VCO cir-
cuit. The VCO circuit has a 4.2 GHz to 5.0 GHz operational range and a 7.2 mW
power consumption. Zina Saheb et al. [12] created a CMOS-based VCO in TSMC
65 nm technology for wireless sensor applications. The first design uses the IMOS
varactor approach to generate a tuning range of 166 MHz to 600 MHz, whereas the
second design uses the same range but with a power consumption of 146.19 μW.
Suraj Kumar et al. [13] report on a VCO based on a common source (CS) ampli-
fier in a 90 nm CMOS technology. The propagation delay of each delay stage is
controlled, allowing the frequency to be adjusted, by varying the active load of
the CS amplifier. The VCO circuit has a phase noise of –137.9 dBc/Hz with power
Exploring the Design and Performance 27

consumption and frequency of 2.092 mW and 9.21 GHz, respectively. Sharma et

al. [14] have documented the use of a delay cell in the design of a three- and four-
stage differential ring oscillator to obtain a tuning range. A single control voltage is
used in the four-stage DRO to acquire a tuning range from 574 MHz to 20.49 GHz,
whereas dual control voltages are used in the three-stage DRO to obtain a frequency
range from 351 MHz to 30.33 GHz. The power consumption of the three-stage and
four-stage DRO circuits is 866 μW and 783 μW, respectively. Phase noise measured
by the oscillator circuits at an offset of 10 MHz from the oscillation frequency is
–96.7 dBc/Hz and –99.54 dBc/Hz.
Ellaithy et al. [15] address the critical need for energy-efficient integrated circuit
designs in medical implants and portable wireless sensors, where battery life is a pri-
mary concern. It focuses on power consumption and heat dissipation, crucial factors
affecting battery longevity. The paper introduces a power-efficient analog-to-digital
converter (ADC) based on a VCO for converting analog vital signs into digital data.
Employing a current-starved scheme with a five-stage VCO yields significant power
and area savings. A D-flip flop (D-FF) scheme simplifies the hardware architecture
of the reset counter. Implemented in 130 nm CMOS technology, the architecture
achieves analog-to-digital conversion using a straightforward hardware structure.
The proposed VCO-based ADC demonstrates enhanced energy efficiency, with
simulation results showing a power dissipation of 0.257 mW, an active area of 0.007
mm2, and an impressive Walden figure of merit (FOMW) of 125 dB. Moreover, the
methodology enables the implementation of ADCs with varying bit resolutions by
selecting an appropriate voltage-controlled oscillator and reset counter configuration.
Kumar et al. [16] present a novel three-stage ring VCO employing MOS varac-
tors and active inductor tuning. Utilizing a CMOS three-transistor “NOR” gate as
the inverting delay stage, the VCO achieves frequency variation from 1.490 to 3.734
GHz with MOS varactor voltage alterations from 0.7 to 1.8 V, exhibiting power dis-
sipation ranging from 4.314 to 6.820 mW. Varied results are obtained with varactor
widths of 5, 10, and 15 µm. Frequency tuning across a range of 0.624 to 4.496 GHz is
demonstrated by varying the power supply from 1 to 2.4 V, with power consumption
ranging from 3.174 to 6.114 mW. Furthermore, the inductive tuning mode, employ-
ing bias voltage variation from 0.4 to 1.4 V, achieves frequency tuning from 1.856
to 4.095 GHz. The proposed VCO exhibits phase noise of −83.864, −101.419, and
−105.350 dBc/Hz at 1 MHz offset with varactor tuning, power supply variation, and
inductor bias voltage tuning, respectively.
Panagiotis Bertsias et al. [17] present a novel VCO topology tailored for
Serializer–Deserializer (SerDes) applications such as SATA, PCI Express, and USB
3 protocols is introduced. This VCO utilizes two-ring oscillator cores and operates
across multiple frequency bands mandated by respective protocol specifications. It
maintains a constant VCO gain and offers enhanced linear control over frequency
tuning. Moreover, it incorporates automatic digital compensation to address pro-
cess variations. Designed in a CMOS 22 nm technology node with a 0.8 V sup-
ply voltage, it achieves superior performance across various speeds of SATA and
PCI Express protocols. At 3 GHz frequency, it boasts phase noise better than −90
dBc/Hz at 1 MHz offset and consumes an average power of 3.84 mW. Extensive
28 Circuit Design for Modern Applications

post-layout simulations validate its exceptional performance, with extended digital

control enabling optimized configurations for phase noise, current consumption, and
VCO gain against process variations.
Hyeon Jin Son et al. [18] proposed a CMOS VCO utilizing half-oscillation fre-
quency signals for switched biasing is proposed, enhancing phase noise and DC-to-RF
conversion efficiency. Flicker noise, a primary factor in phase noise, is mitigated by
modulating with half-frequency signals. Improved efficiency is achieved through
second harmonics leakage modulation. Differential half-frequency signals, gener-
ated within a frequency divider employing current-mode logic, minimize parasitic
effects. Fabricated in a 65-nm CMOS process, the VCO exhibits an 11.2% tuning
range in the K-band, with –109.86 dBc/Hz phase noise at a 1-MHz offset. Peak out-
put power reaches 0.95 dBm with a 16.64% DC-to-RF efficiency at 1.2 V supply
voltage. The figure of merit stands at –188.03 dBc/Hz.

2.2.1 Comparative Analysis of Various Performance Specifications

of Voltage-Controlled Ring Oscillators

Table 2.1 compares the various performance metrics across the listed VCOs, and
certain trends emerge regarding their technological parameters, power consumption,
and phase noise characteristics. Notably, the technology node varies from 0.18 μm
to 0.9 μm, with smaller nodes generally associated with lower power consumption
and better performance. For instance, VCOs implemented in 0.18 μm technology

TABLE 2.1
Comparative Analysis of Various Performance Specifications of Voltage-
Controlled Ring Oscillators
Frequency Power Phase noise FoM
Ref Tech (μm) Vdd N (GHz) (mW) (dBc/Hz) (dBc/Hz)
[1] 0.25 2 — 0.285-1.270 10 –104.4@1MHz 156.4
[2] 0.5 2.5 2 0.66-1.27 15.5 –106@600 KHz —
[3] 0.25 2 2 0.8-2.4 59 –98.5@400KHz 152.83
[4] 0.18 1.8 3 5.16-5.93 80 –99.5@1MHz 155.72
[5] 0.18 1.5 — 2.7-5.4 18.4 –90@1MHz 149.5
[6] 0.18 1.8 4 1.77-1.92 13 –102@1MHz 156.3
[7] 0.18 1.8 3 8.36-1.29 74.25 –100.22@1MHz 159.95
[8] 0.18 1.8 — 03-5.0 4 –136@1MHz —
[9] 0.18 1.8 3 0.770-5.287 15.1 –97.93@1MHz 160.6
[10] 0.18 1.8 4 4.9-5.9 8.1 –86.7@1MHz 149.7
[11] 0.18 2 — 4.1-5 7.2 –90.2 @1MHz 155.1
[12] 0.65 0.6 3 0.166-0.6 0.151 –78@1MHz 141.77
[13] 0.9 1.2 5 4.22-6.22 2.092 –137.9@1MHZ —
[14] 0.45 1.1 3 0.361-30.33 0.886 96.7@10MHz 146.16
Exploring the Design and Performance 29

exhibit both low power consumption and competitive phase noise levels, exemplified
by Design [5] with a power consumption of 18.4 mW and phase noise of –90 dBc/
Hz at 1 MHz offset. In contrast, Design [13] utilizing a larger 0.9 μm technology
node shows significantly higher power consumption at 2.092 mW and poorer phase
noise performance at –137.9 dBc/Hz. Additionally, variations in supply voltage
(Vdd) influence power consumption levels, where lower voltages like 0.6 V in Design
[12] contribute to ultra-low power consumption of 0.151 mW. Moreover, frequency
range and number of stages (N) impact the performance envelope, with wider fre-
quency ranges typically associated with higher power consumption, exemplified by
Design [14] with a frequency range of 0.361–30.33 GHz and a power consumption of
0.886 mW. Conversely, Designs [3] and [9] demonstrate how increasing the number
of stages can accommodate broader frequency ranges while maintaining relatively
low power consumption. Overall, these comparisons underline the intricate trade-
offs involved in VCO design, where technology selection, supply voltage, frequency
range, and number of stages collectively influence power consumption and phase
noise performance.
Oscillators with lower phase noise values are desirable for applications requiring
precise timing and low jitter. The figure of merit provides a holistic measure of oscil-
lator performance, considering factors such as frequency, power consumption, and
phase noise. Oscillators with higher FoM values are considered more efficient and
suitable for a wide range of applications. Based on the provided data, the oscillators
offer a good balance of operating frequency, power consumption, and phase noise,
making them suitable for various applications requiring stable clock signals or tim-
ing references. Additionally, the choice of oscillator depends on specific application
requirements, such as power constraints, operating frequency range, and phase noise
tolerance.

2.3 RING OSCILLATOR
Ring Oscillators are electronic circuits that consist of an odd number of inverters
connected in a ring configuration, where the output of the last inverter is fed back
to the input of the first inverter. They are used to generate a continuous oscillating
signal, whose frequency is influenced by environmental conditions such as tempera-
ture and voltage. Additionally, ring oscillators have been explored for their potential
applications in Physical Unclonable Functions which can generate unique identifiers
based on the characteristics of the oscillators.

2.3.1 Three-Stage Single-Ended Ring Oscillator

The single-ended three-stage ring oscillator operates as a vital component in inte-
grated circuits for clock signal generation, with its intricate working mechanism
rooted in the principles of positive feedback and CMOS inverter dynamics. Figure 2.1
shows the block diagram of a three-stage single-ended voltage-controlled ring oscil-
lator. Figure 2.2 shows the circuit diagram of a three-stage single-ended voltage-con-
trolled ring oscillator. Comprising three stages of CMOS inverters interconnected in
30 Circuit Design for Modern Applications

FIGURE 2.1 Block diagram of a three-stage single-ended voltage-controlled ring oscillator.

FIGURE 2.2 Circuit of a three-stage single-ended voltage-controlled ring oscillator.

a closed loop, the oscillator exploits the inherent delay in each stage to sustain oscil-
lations. The positive feedback loop ensures that the output of the last inverter is fed
back to the first, creating a regenerative process. The oscillation frequency is directly
tied to the cumulative propagation delays of the individual inverter stages, offer-
ing a straightforward frequency control mechanism. Voltage control, facilitated by a
varactor or similar elements, enables precise adjustment of the oscillation frequency.
Furthermore, resistive and capacitive tuning methods provide additional means for
frequency modulation. This oscillator’s ability to balance simplicity with versatility,
making it adaptable to high-speed digital and mixed-signal circuitry, underscores its
significance in contemporary integrated circuit designs. Understanding the detailed
workings of this oscillator is pivotal for engineers aiming to optimize its perfor-
mance for specific applications.

2.3.2 Five-Stage Single-Ended Ring Oscillator

The single-ended five-stage ring oscillator stands as a critical component in inte-
grated circuits for clock signal generation, leveraging its intricate working principles.
Figure 2.3 shows the Block Diagram of a five-stage single-ended voltage-controlled
ring oscillator. Figure 2.4 shows a five-stage single-ended voltage-controlled ring
oscillator. Comprising five CMOS inverters arranged in a closed loop, it capitalizes

FIGURE 2.3 Block diagram of a five-stage single-ended voltage-controlled ring oscillator.

Exploring the Design and Performance 31

FIGURE 2.4 Circuit of a five-stage single-ended voltage-controlled ring oscillator.

on positive feedback and the inherent delay in each inverter stage to sustain oscil-
lations [19]. The positive feedback loop ensures that the output of the fifth inverter
is fed back to the input of the first, establishing a regenerative process. The cumu-
lative propagation delays of the individual inverter stages collectively dictate the
oscillation frequency, offering a direct means of frequency control. Voltage control,
typically facilitated by a varactor or similar elements, allows precise adjustment of
the oscillation frequency [20]. Additionally, resistive and capacitive tuning meth-
ods enable further modulation of the frequency range. This oscillator’s complex yet
versatile design renders it suitable for applications in high-speed digital and mixed-
signal circuitry, providing a balance between intricacy and precision. A comprehen-
sive understanding of its detailed workings is imperative for engineers aiming to
optimize its performance for specific integrated circuit designs.

2.3.3 Seven-Stage Single-Ended Ring Oscillator

A seven-stage single-ended CMOS ring oscillator operates by utilizing the inherent
delay in each stage of CMOS inverters to create a closed-loop feedback system. Each
stage of the oscillator consists of a CMOS inverter, which comprises a PMOS tran-
sistor connected in series with an NMOS transistor, forming a complementary pair.
Figure 2.5 shows the block diagram of a seven-stage single-ended voltage-controlled
ring oscillator. Figure 2.6 shows the circuit diagram of a seven-stage single-ended
voltage-controlled ring oscillator. Initially an input signal is applied to the first stage

FIGURE 2.5 Block diagram of a seven-stage single-ended voltage-controlled ring oscillator.

FIGURE 2.6 A seven-stage single-ended voltage-controlled ring oscillator.

32 Circuit Design for Modern Applications

of the oscillator. The input signal is then inverted by the first CMOS inverter stage,
resulting in a delayed output. This delayed output is then fed into the next stage of
the oscillator. At each subsequent stage, the signal is inverted again, further delay-
ing the signal and completing the feedback loop. As the signal propagates through
the seven stages of CMOS inverters, it undergoes multiple inversions, resulting in a
phase shift with each stage. Due to the delay introduced by the transistors in each
stage, the signal eventually reaches the input of the first stage again, completing one
full cycle of oscillation. As the signal propagates through the seven stages of CMOS
inverters, it undergoes multiple inversions, resulting in a phase shift with each stage.
Due to the delay introduced by the transistors in each stage, the signal eventually
reaches the input of the first stage again, completing one full cycle of oscillation.
The oscillation frequency of the CMOS ring oscillator is primarily determined by
the delay introduced by each CMOS inverter stage and the total number of stages
in the loop. Typically, shorter delays in the CMOS inverters result in higher oscilla-
tion frequencies. However, the actual frequency is also influenced by factors such as
transistor sizing, load capacitance, and power supply voltage. By carefully designing
the CMOS inverters and optimizing the layout and sizing of the transistors engineers
can adjust the oscillation frequency of the ring oscillator to meet the specific require-
ments of their application. CMOS ring oscillators are commonly used in integrated
circuits for generating clock signals, timing references, and other periodic wave-
forms due to their simplicity, low power consumption and ease of integration.

2.4 PERFORMANCE ANALYSIS
To analyze the performance of the three-, five-, and seven-stage single-ended volt-
age-controlled ring oscillators the following performance metrics were used number
of stages, technology node, supply voltage, frequency range, phase noise, power con-
sumption, and figure of merit [21].

Number of Stages: The number of stages in the ring oscillator determines

its frequency of operation and stability. Generally, more stages result in
higher oscillation frequencies but may also increase power consumption
and complexity.
Technology Node: The technology node indicates the feature size of the
CMOS process used to fabricate the ring oscillator. Smaller technology
nodes typically offer advantages such as higher speed and lower power
consumption.
Supply Voltage: The supply voltage determines the operating voltage of the
ring oscillator circuit. Lower supply voltages are desirable for reducing
power consumption and heat dissipation.
Frequency Range: The frequency range over which the oscillator operates
is crucial for determining its suitability for specific applications. A wider
frequency range provides more flexibility for various applications.
Phase Noise @ 1MHz: Phase noise measures the stability and purity of the
output waveform. Lower phase noise values indicate better signal quality,
which is essential for applications sensitive to timing jitter and noise.
Exploring the Design and Performance 33

TABLE 2.2
Comparison of the Various Performance Specifications of Different Stages of
Ring VCOs
Performance
Specification Performance Values
No of stages Three Five Seven
Technology 180nm 180nm 180nm
Supply of voltage 1.8V 1.8V 1.8V
Frequency range 0.556–2.584 GHz 1.153–5.130 GHz 0.874–3.678 GHz
Phase noise @ 1Mhz –89.77 dBc/Hz –90.6 dBc/Hz –90.8 dBc/Hz
Power consumption 1.26 mW 1.124 mW 1.632 mW
Figure of merit (FoM) 154.51 dBc/Hz 160.8 dBc/Hz 156.5 dBc/Hz

Power Consumption: Power consumption is a critical metric, particularly for

battery-powered or low-power applications. Lower power consumption is
generally preferred to prolong battery life and reduce heat dissipation.
Figure of Merit (FoM): The figure of merit provides a comprehensive metric
for evaluating the overall performance of the oscillator, considering factors
such as frequency, power consumption, and phase noise. Higher FoM val-
ues indicate superior performance.

Table 2.2 compares the various performance specifications of different stages of

ring VCOs found in the literature based on factors such as technology employed,
supply voltage (Vdd), number of delay stages (N), frequency range, power dissipa-
tion, phase noise, and figure of merit (FoM). The five-stage ring oscillator offers the
highest oscillation frequency range and FoM, making it suitable for applications
requiring high-speed operation and low phase noise. The three-stage ring oscilla-
tor has the lowest power consumption but a narrower frequency range compared to
the five-stage and seven-stage oscillators. The seven-stage ring oscillator provides a
wider frequency range than the three-stage oscillator but has slightly higher power
consumption. The choice of the oscillator depends on specific application require-
ments, such as operating frequency range, power consumption constraints, and phase
noise tolerance. Advanced transistors can be used to improve the performance of the
ring VCO [22–26].

CONCLUSION
This chapter offers insight into a fundamental building block of frequency synthesis
and timing generation circuits by examining the design and performance dynamics
of CMOS voltage-controlled ring oscillator (VCRO) stages. Applications needing
accurate and consistent clock signals, like data converters, communication systems,
and microprocessors, depend on VCRO stages.
34 Circuit Design for Modern Applications

The purpose of VCRO stages is to produce stable oscillation frequencies in the

presence of process, temperature, and supply voltage (Vdd) changes. The implemen-
tation of temperature-compensated designs, feedback control methods, and meticu-
lous component value selection all contribute to this stability.
The oscillation signal’s spectral purity is characterized by phase noise. Phase
noise in VCRO stages is affected by transistor flicker noise, power supply noise, and
thermal noise, among other things. For applications that need precise clock signals,
such as radar systems and high-speed data transmission, minimizing phase noise is
essential.
Because CMOS technology inherently has low power consumption, CMOS
VCRO stages usually have minimal power consumption. Transistor sizing, supply
voltage selection, and circuit design strategies that reduce needless switching and
leakage currents can all be used to further maximize power efficiency.
The range of Vctrl and the inverters’ design specifications determine the fre-
quency tuning range of a VCRO stage. For applications that need frequency agility,
like frequency synthesizers in wireless communication systems, wide tuning ranges
are preferred.

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 3 A 3.1 ppm/ºC Sub-1V
Bandgap Reference
in 28 nm CMOS
Technology Operating
from a 1V Supply Voltage
Rajasekhar Nagulapalli, Khaled Hayatleh,
and Nabil Yassine

3.1 NATURE OF THE WORK

Every analog/electronic system requires a constant reference voltage/bias for a sta-
ble operating point of the transistors (could be MOSFET or BJT devices) (Chen et
al. 2023). In the past, zener diode-based references were very popular as they pro-
vided stable voltage without requiring any additional circuit design techniques; how-
ever, building a zener in a CMOS process is very difficult and expensive due to the
requirement of many process stages. In modern CMOS technologies, this is almost
impossible. Since 350nm CMOS technology was introduced, circuits like regula-
tors have replaced the zener diode. However, the temperature drift is unactable for
several applications (Chen et al. 2023). Bandgap reference (BGR) circuits are critical
analogue blocks for many electronic systems. A BGR circuit produces a reference
current to bias core analogue blocks, such as operational amplifiers (op-amps). It
also provides a stable reference voltage for low dropout regulators (LDO), wireless
transceivers, and analogue to digital data converters. BGR output stability can be
attributed to the process and temperature stability of BJT parameters (Awny et al.
2016; Chen et al. 2023). The temperature stability of the reference voltage to the core
analogue block significantly affects the system specification and performance. For
example, a 10-bit analogue digital converter (ADC) built-in 1-V supply would require
the least significant bit (LSB) of less than 1mV. Hence, the BGR temperature drift
should be much less than 0.5 mV; this mandates around 9 ppm/0C over the industrial
temp range (Awny et al. 2016). Any additional drift beyond this would create the
Signal to Noise ratio (SNR) degradation and distortion impairments. Typically, 12
ppm/OC is targeted for temperature sensor applications to meet specific temperature

DOI: 10.1201/9781003483052-3 37
38 Circuit Design for Modern Applications

accuracy. Often, this process variation can be minimised by one-point trimming.

Although it is time-consuming, it has been proven to be an efficient technique in
terms of performance. However, due to the temperature, the output voltage drift can-
not be solved by any known methods (Brokaw 1974).

3.2 REVIEW OF EXISTING BGR ARCHITECTURES

In 1974, Brokaw proposed a BGR circuit, integrating proportional to absolute tem-
perature (PTAT) into his design. The circuit also integrated complementary to abso-
lute temperature (CTAT) components in a proportional manner (Awny et al. 2017;
Brokaw 1974; Chen et al. 2023). Equation 3.1 expresses the negative temperature
coefficient (TC) of the base-emitter voltage (VBE) in a Bipolar Junction Transistor
(BJT). In Equation 3.1, Eg is the silicon bandgap, while V T is the thermal voltage, and
q is the electron charge. In a typical corner, this coefficient is –1.8 mV/K, serving as
a CTAT voltage (Nagulapalli et al. 2020).

Eg
VBE   4  m VT 
dVBE q
 (3.1)
dT T
Equation 3.2 expresses the PTAT voltage. This voltage is generated by the differ-
ence in VBE values between two BJTs with distinct current densities. In Equation
3.2, the parameter n represents the two BJTs ratio of current density. Brokaw’s pro-
posed design and methodology provided a foundation for designing BGR circuits
and achieving a reliable and scalable reference voltage by utilising the temperature-
dependent characteristics of the VBE in BJTs (Brokaw 1974; Nagulapalli et al. 2024).

VBE  VT ln ln n (3.2)

Equation 3.2 shows that the TC of the PTAT voltage will be approximately 0.087
mV/K, which depends on BJT devices’ current density and emitter ratio. To achieve
0 V for the BGR TC, the scaled summation of PTAT and CTAT is necessary. It is
increasingly necessary for modern CMOS technologies to operate with high electric
fields in small geometries and decrease VDD at the same time, specifically under
a 1V supply. Brokaw’s proposed design required a supply voltage larger than 2V
(VDD) and produced an output voltage of 1.23 V (Brokaw 1974). Due to these limi-
tations, when compared to current requirements, an active research community is
looking at developing more efficient BGR circuit designs that operate under 1 V
(Nagulapalli et al. 2024).
The small PTAT voltage is created from the bandgap core, with the difference
in the emitter-base voltages (Nagulapalli and Palani 2023). This must be ampli-
fied before addition with the diode voltage to create a stable voltage, as shown in
Figure 3.1(a). The first implementation by Brokaw used pure BJT technology, which
produced an output voltage of 1.23 V (Brokaw 1974). Unfortunately, this requires a
supply voltage over 1.8 V, which may not be possible in modern CMOS technologies.
28 nm CMOS Technology 39

FIGURE 3.1 (a) Conventional BGR architecture. (b) The BGR circuit was proposed by
Banba (Banba et al. 1999).

In Figure 3.1(a), node x and y potentials are the same due to the negative feed-
back of the op-amp. Equation 3.3 shows how the current through resistor 1 can be
expressed. However, the base current neglects one major approximation in Equation
3.3 (Nagulapalli et al. 2024).

VT ln n
I R1 = (3.3)
R1
Typically, the CMOS process has vertical BJT devices formed in the N-well (form-
ing the base). The p-substrate establishes the collector while the p+ diffusion estab-
lishes the emitter. Since the base is very wide here, it will create so much carrier
recombination and decrease the BJT’s beta as fewer carriers enter the collector
(Palani et al. 2023). Such a low beta introduces the CTAT error term in the PTAT
current; hence, accuracy will be compromised. Several expensive CMOS processes
have been tailored to form the best BJT, like SOI technology, but this increases the
die size and cost; hence, this may not be a generic process option. Also, lateral BJT
in the CMOS can be exploited for better current gain. However, this structure’s small
signal parameters are very sensitive to the package stress and temperature gradient,
which requires post-packaging on-chip trimming (digital). This current has a PTAT
nature, and this will be used to mirror into the output stage to create a scaled PTAT
voltage rather than current. The constant BGR voltage will be added to the CTAT
voltage, and the final output voltage can be expressed as shown in Equation 3.4
(Nagulapalli and Palani 2023; Nagulapalli et al. 2024).

R 
VBG   2 VT ln n  VBE1  (3.4)
 R1 
Banba (Banba et al. 1999) proposed a current mode BGR, shown in Figure 3.1(b),
that operates at a supply voltage under 1 V. In Figure 3.1(b), Q1, R1, and Q2 form
the PTAT loop, and R1 and N decide the PTAT current. Resistance R2 is connected
across the VBE of the BJT; hence, it will produce the CTAT current. The sum of the
PTAT and CTAT current will be flowing through PMOS current sources (M1, M2).
By adjusting the ratio of R1 and R2 currents, one could cancel the TC of the current
40 Circuit Design for Modern Applications

and achieve zero TC. This current will be converted as voltage through external
resistance R L. From (3.7), it is clear that it will always be more than 1.2 V, which may
not be compatible with the present FinFET technologies. Recently, FinFET technol-
ogy has become very popular compared to CMOS technology due to excellent leak-
age performance, high analogue gain, low thermal noise, and high signal bandwidth.
Figure 3.1(a) shows a conventional BGR circuit, where its biggest disadvantage is a
high output voltage. However, this architecture produces high linear PTAT voltage,
which can be used to compensate for the temperature sensitivity of the differential
pair. Also, voltage control oscillator (VCO) circuits require PTAT voltage to improve
the start-up margin, where this circuit can be primarily used. Also, this BGR circuit
has only two operating points, where one is zero current, and the other one is the
desired bias current. A start-up would be required to push the circuit out of the zero
current state; hence, the circuit can be moved into the actual current and used to bias
the rest of the op-amps. A typical start circuit consists of a current comparator that
compares the fixed current and BGR current; based on this comparator output, the
BGR output will be pulled up or down to move it in the desired direction (Palani et
al. 2023).
Figure 3.1(b) shows the curvature compensated Banba to improve TC, program-
mable output voltage and accuracy (Banba et al. 1999). Current summation has been
proposed rather than voltage summation to get the programmable and lower voltage.
Two large resistors (R2) have been added across the base-emitter junction of the
BJTs, which will produce the CTAT current as the VBE has a CTAT nature and R2
has a very low-temperature coefficient. The CTAT current can be expressed as (3.5).
The PTAT current from R1 and CTAT current of R2 will be added, and the resultant
current will flow through M1 or M0, which will have zero temperature coefficient
(ZTAT), and this can be pumped into the load resistance R3 and generate the BGR
voltage. Equation 3.6 shows the output of the current mode BGR, which shows that
the achievable output voltage is lower than 1 V. Hence, this has also been named
sub-1 V BGR (Banba et al. 1999; Nagulapalli and Palani 2023; Nagulapalli et al.
2024).

VBE1
I R2 = (3.5)
R2

RL  R2 
VBG   R VT ln n  VBE1  (3.6)
R2  1 
Though this works very well and is compatible with advanced CMOS technologies,
unfortunately, this has several downsides. First, the CTAT resistance R2 should be
sized to balance PTAT current gain with CTAT one. Generally, the CTAT slope is
–2 mV and the PTAT slope is 100 uV, so R2 should be 25 times higher than R1. The
R1 value decided by the bias current would typically be targeted as 10 uA, which
means R1 is 25 kΩ and R2 will be 225 KΩ. Typical CMOS process resistance sheet
resistance will be 800 ohms per square, so to emulate 225 k, one would require
28 nm CMOS Technology 41

275 um2 silicon area, which is as big as an audio ADC (Varun et al. 2021). Due to
the current summation at node z, only ZTAT nature current is available (constant
with respect to the temp). PTAT is not available; this is relatively disadvantageous
compared to the current mode BGR. Any VCO or temperature sensor in the same
chip would need another explicit PTAT generator apart from the BGR, which costs
power and valuable silicon area. In voltage mode BGR, there are only two operating
points; this is because the op-amp input terminals experience different small signal
impedances at every current value (node y experiences 1/gm and node z experi-
ences R1+1/gm), so the op-amp differential input voltage will be zero only at the two
points. One point would be zero current, and another would be at the current given
by Equation 3.3. The op-amp will move towards the desired operating point thanks
to the start-up circuit. Unfortunately, this is not the case with the current mode BGR
because the op-amp is loaded by CTAT resistors (R2). Suppose the current of the
BGR is low enough that the BJT devices Q1 and Q2 are off, so the input impedance
is mostly dominated by R2. So, the input impedance is the same at low current, and
op-amp inputs experience zero differential voltage until the current increases so that
both BJTs can be turned on. Indeed, this situation creates multiple operating points.
Designing a start-up circuit would be very challenging as it has to distinguish several
points and place the op-amp at the voltage corresponding to the appropriate current.
This is often referred to as the biggest disadvantage of the Banba BGR, and several
scenarios of large SOC or analogue systems fail in the real-time field. The solution
to this problem is to keep a digital wake circuit, which will ensure BGR is always
on (power-hungry solution) or create some mismatch between both R2 values, which
introduces a mismatch in the BGR output voltage (Desai et al. 2010).
Nagulapalli proposed a mixed-mode circuit to fix some of these problems
(Nagulapalli et al. 2020); however, it has TC problems compared to Banba. Because
it uses additional op-amp compared to the Banba structure (Banba et al. 1999);
hence there is more mismatch-induced error and TC. The proposals from Brokaw
and Banba used imbalance in the PTAT and CTA currents to improve the TC but at
the cost of stability (Banba et al. 1999; Brokaw 1974). Palani et al. introduced a cur-
vature-compensated BGR to improve the accuracy; this has added much complexity
to the circuit and is prone to PVR corner variation, which often mandates two-point
trimming (Palani et al. 2023). Varun et al. introduce a gate resistance in series with
the base of the BJT to compensate for the inaccuracy due to the limited current gain
of the BJT (β) at the cost of additional bias current (Varun et al. 2021).

3.3 PROPOSED ARCHITECTURE
In this chapter, we have proposed and implemented a curvature compensation, sub-1
V, architecture, injecting a nonlinear current into the BJT emitter to linearise this
curvature. The main issue with the Banba (Banba et al. 1999) architecture is the
CTAT resistors connected at nodes x and y (Figure 3.1), which will occupy an unac-
ceptable area and amplify the op-amp offset. Figure 3.2(a) shows the proposed cir-
cuit, where the CTAT resistors at nodes x and y have been removed, and a CTAT
current has been created using a single resistor, R2. The node-CTAT voltage has
42 Circuit Design for Modern Applications

FIGURE 3.2 (a) Proposed curvature compensated BGR. (b) Self-bias Low voltage op-amp.

CTAT characteristics, and the voltage across R1 will have PTAT characteristics. The
sum of the PTAT and CTAT currents will flow into the output resistor. The output
R R 
voltage expression, Equation 3.1, includes the PTAT voltage gain term  1  2 2  .
R
 p R p 

By adjusting this voltage gain, the TC of PTAT, CTAT can be cancelled, and eventu-
ally minimise TC.

RL   R1 R 
VBGR  VBE  VT ln ln n  2 2  (3.7)
R2   Rp Rp  
The above Equation 3.7 shows a very similar kind of output voltage expression to
Banba architecture in Equation 3.6, without having the issues listed. The op-amp
(A1) offset will affect the accuracy of the output voltage as its bias current is different
from the BJT core current. This will introduce the op-amp’s systematic offset and an
error term in the BGR output voltage. A self-bias op-amp has been the popular choice
for BGR applications as it senses the BGR core bias current (PTAT) and reuses it to
bias the op-amp; hence, the systematic offset will be nullified. In 2016, Awny et al.
proposed an increased loop gain self-bias path to decrease the offset even more, but
this requires a complex op-amp in the feedback, which is also prone to oscillations.
Also, increasing the bias circuitry’s loop gain in this architecture will decrease the
main op-amp and BGR bandwidth (Awny et al. 2016). Awny et al. proposed, in 2017,
a simple self-bias circuit, which improved the systematic offset by three times (Awny
et al. 2017). Figure 3.2(b) proposes a high gain self-bias op-amp architecture without
any oscillations problem, and its gain is decoupled from the BGR bandwidth. This
will increase the bias loop gain by at least five times and have excellent system-
atic offset performance. The first stage of the conventional single-stage op-amp is
formed by the transistors M0, M1, M9, M10, and M7; typically, the output of this op-
amp (node y) will drive the BGR current sources to minimise the systematic offset.
The transistors M2 and M3, which form a gain stage trans conductance, produce a
high voltage gain due to the negative resistance created by the cross-coupled pair M4
and M5. Due to the negative resistance developed at node y, the resultant small signal
impedance will increase, and the same amount will enhance gain. To decouple the
self-bias gain and BGR bandwidth, the self-bias op-amp (Figure 3.2b) loop has to
28 nm CMOS Technology 43

be much slower than the actual BGR loop. To achieve this, a low pass filter formed
by the RF, CF, with an extremely low cut-off frequency, is used at the output of the
self-bias loop and tail current source (M7) gate terminal. Typically, low filter resis-
tance is formed by poly resistance and capacitance, formed by the combination of
metal-oxide-semiconductor (MOS) and metal-to-metal capacitance, and the cut-off
frequency is approximately 500 KHz. The overall self-bias has improved the loop
gain of the BGR by 25 dB (Nagulapalli et al. 2021).

3.4 SIMULATION RESULTS AND DISCUSSION

WITH THE STATE-OF-THE-ART
The proposed BGR circuit has been designed using 1 poly 10 metal 28 nm TSMC
CMOS high performance (HP) technology. The mean output voltage of the BGR
is 400 mV with a target temperature drift of 4 ppm/0C. This circuit operates from
a 1 V supply (worst) with a supply variation of +/– 50 mV. The circuit draws 25 μA
from the 1 V supply in the FF-1250C process corner. A conventional current mode
(Banba) circuit was also designed to compare the results. Figure 3.3 shows the post-
layout simulation results of output voltage across the temperature range for different
process corners (TT, FF, SS, SF, FS). It shows 400 mV mean voltage with 0.85 mV
peak-to-peak voltage variation, corresponding to a TC of 3.1 ppm/oC. The offset of
the op-amp and mismatch of the current mirrors contribute most of the temperature
coefficient. Typical op-amp offset dominates the threshold voltage temp coefficient,
and its slope is very complicated and uncertain, which will significantly contribute
to the BGR TC. Out of all process corners, the NMOS fast and PMOS fast corners
are the worst because, in this corner, the current mirror’s transconductance (gm)
is too high, adding a significant current mismatch. Any current mismatch between
both BJTs would significantly contribute to the temperature inaccuracy of the BGR.
In the present CMOS process, the resistor variation is much lower (less than 1%);
hence, resistor corners were not included, and only process corners were included.
The stability of the BGR is one of the critical parameters, as any frequency insta-
bility will be introduced, and it can compromise the accuracy of the output voltage
(Desai et al. 2010). The loop gain of the op-amp has been simulated with the STB
probe in cadence and the frequency response of magnitude and phase, as depicted

FIGURE 3.3 Post-layout simulation results of the proposed circuit.

44 Circuit Design for Modern Applications

FIGURE 3.4 Frequency response for finding the phase margin and gain margin.

in Figure 3.4. It shows the loop gain of 56 dB (op-amp contribution – 42 dB and

PMOS current sources gain – 14 dB) in the worst corner of SS, cold temperature and
low voltage. Typically, slow corners will have a very high gain due to the mobility
degradation of the transistor and velocity saturation introduced by the high-energy
electrons. Also, cold temperature corners will have very high output impedance (also
known as gds), producing very high voltage gain, so usually the worst case for stabil-
ity. Also, phase margin (PM) and gain margin (GM) are the metrics used to quantify
the strength of any feedback (Nagulapalli et al. 2021). High PM and GM are desir-
able for having a good step response and less ringing. Usually, 600 of phase margin
and 12dB of GM will result in an over-damped feedback system. This plot shows
the phase margin of 68 deg and 13.8 dB gain margin. Several compensation tech-
niques are similar to Miller, Ahuja, and Dominate pole techniques. However, several
trade-offs exist, such as compensation capacitor area and power supply rejection
ratio (PSRR). Of all trade-offs, the Miller is best as it works on capacitor multipli-
cation by the gain of the op-amp, so it is a very small capacitor occupying a very
small silicon area. Hence, the proposed BGR has been compensated with a Miller
capacitor to push the dominant pole towards low frequency and the second dominant
pole to high frequency so that the phase margin will be very high. The Unity gain
bandwidth (UGB) of the BGR is 100 MHz. The step response due to the supply at
the output has a very smooth small signal settling with a time constant of 10 ns and
a total of 10–90% settling time of 65 ns (Nagulapalli and Palani 2023).
Due to the digital switching of the logic gates, there will be a significant amount
of power supply noise in modern analogue systems. This noise will be coupled to
the analogue systems through the low-resistance substrate and power supply imped-
ance. Sometimes, the high resistive substrate will be used to improve the coupling
performance, but at the cost of latch-up danger (which could damage the chip).
Usually, RF chips will use this kind of substrate (Hayatleh et al. 2019). In this work,
a low-resistive substrate has been used. Hence, there will be a power supply on the
BGR supply. This power supply noise introduces the error in the output of the BGR
through modulating the op-amp small signal parameters and BJT VBE. The impact
of the power supply noise on the BGR output will be quantified by the PSRR, the
output voltage ratio due to the power supply and power supply noise. Very low PSRR
is desired across the frequency band of interest. PSRR of the BGR or any feedback
system is inversely proportional to the loop gain. Hence, high loop gain would result
28 nm CMOS Technology 45

FIGURE 3.5 Frequency response of the PSRR across different PVT corners.

in a better PSRR. Figure 3.5 shows the simulated PSRR frequency response across
PVT corners (Zourob et al. 2018). At very low frequencies, the feedback loop gain
is so high that the output voltage will be independent of the power supply voltage;
hence, it will be very low (desired). As the frequency increases, the loop gain will be
degraded due to the junction and parasitic capacitance so that output voltage will be
degraded and dominated by the power supply, so degraded PSRR (around 10 MHz
frequency). As the frequency reaches a very high level, the output capacitance will
filter the power noise, and PSRR will be improved. Generally, the PSRR of the BGR
will be quantified by the mid-frequency range as it will be worse there. Across PVT
corners, it will be worse in the fast NMOS and fast PMOS corners as it will have very
low poor loop gain and high parasitic capacitance. Temperature and supply voltage
will have less impact on the PSRR because temperature increases the looping but
weakens the gain from the power supply so that the first order will be independent.
Typical BGR applications target –10 dB, worst case PSRR; in the proposed case, it
will be around –15 dB, meaning only 20% of the high-frequency power supply noise
will appear at the output.
Noise performance will also be the critical parameter impacting the BGR output
accuracy. Figure 3.6 shows the noise power spectral density (PSD) of the proposed
(blue trace) and conventional technique (red trace). Most of the noise is dominated
by the op-amp input-referred noise, also present in the proposed technique due to the
current injection into the VBE.

3.5 GENERAL SUMMARY
In 28nm CMOS technology, a 3.1 ppm/°C sub-1-V bandgap reference that operates
on a 1-V supply voltage is designed to be stable and to have a low-temperature coeffi-
cient and a high supply rejection ratio (PSRR). Make use of a core bandgap reference
architecture that can withstand temperature fluctuations and process variations. To
achieve low TC, common strategies involve combining complementary-to-absolute-
temperature circuits with proportional-to-absolute-temperature circuits. Use meth-
ods to fine-tune temperature compensation components, such as resistor trimming
or current mirror matching, to make sure the appropriate TC is maintained in a
range of environmental circumstances. Provide a high PSRR bandgap reference in
46 Circuit Design for Modern Applications

FIGURE 3.6 Noise power spectral density (PSD) of the Banba and proposed technique.

order to reduce the impact of power supply fluctuations on the output voltage. In the
design, techniques could include capacitance multipliers, active control, or filtering.
Optimising the layout is essential to reduce resistances and parasitic capacitances
that can impair performance, particularly at higher frequencies or when there are
noise sources present. Use strong design strategies and perhaps calibration systems
to address the inherent variability in threshold voltages and transistor characteristics
in CMOS technology. Make that all circuit components, taking into account thresh-
old voltages and headroom requirements, function within acceptable bounds at 1-V
supply voltage. Check the bandgap reference’s stability with respect to temperature
and load to make sure it stays linear and accurate throughout its working range. Give
digital-to-analog and analog-to-digital converters steady reference voltages. Assure
precise and stable reference voltages for sensor signal conditioning circuits; act as
a stable reference voltage for low-dropout (LDO) regulators in low-power applica-
tions. To summarise, careful consideration of TC, PSRR, and operational voltage
limitations is necessary while constructing a 3.1 ppm/°C sub-1V bandgap reference
in 28nm CMOS technology. Through the application of sophisticated design meth-
odologies and layout optimisation, engineers can attain a resilient voltage reference
that is appropriate for high-precision uses in low-power electronics.

3.6 CONCLUSIONS
A detailed explanation of bandgap reference functionality has been described. The
main problems in the Banba/current mode BGR were explained, mainly multiple
unstable operating points and unacceptable silicon occupied by the resistors. A sim-
ple modification was proposed to improve the accuracy of the BGR by introducing
the nonlinear current injection into the CTAT voltage. It improved the area efficiency
by moving the CTAT resistor taping point from the op-amp input to the output.
Also, the proposed technique preserves the PTAT current nature of the bias current
to bias the VCO or temperature sensors without requiring external PTAT current
generators. A prototype has been built, and post-layout simulations were performed
to prove the curvature-compensated nature.
28 nm CMOS Technology 47

REFERENCES
Awny, A., R. Nagulapalli, M. Kroh, J. Hoffmann, P. Runge, D. Micusik, G. Fischer, A. C.
Ulusoy, M. Ko, and D. Kissinger. 2017. “A linear differential transimpedance ampli-
fier for 100-Gb/s integrated coherent optical fiber receivers.” IEEE Transactions on
Microwave Theory and Techniques 66 (2):973–986.
Awny, A., R. Nagulapalli, D. Micusik, J. Hoffmann, G. Fischer, D. Kissinger, and A. C.
Ulusoy. 2016. “23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimped-
ance amplifier with automatic gain control in 0.13 µm BiCMOS technology for opti-
cal fiber coherent receivers.” 2016 IEEE International Solid-State Circuits Conference
(ISSCC). pp. 406–407.
Banba, H., H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui. 1999. “A
CMOS bandgap reference circuit with sub-1-V operation.” IEEE Journal of Solid-State
Circuits 34 (5):670–674.
Brokaw, A. P. 1974. “A simple three-terminal IC bandgap reference.” IEEE Journal of Solid-
State Circuits 9 (6):388–393.
Chen, Z., Q. Wang, X. Li, S. Song, H. Chen, and Z. Song. 2023. “A high-precision current-
mode bandgap reference with nonlinear temperature compensation.” Micromachines
14 (7):1420.
Desai, K., R. Nagulapalli, V. Krishna, R. Palwai, P. K. Venkatesan, and V. Khawshe. 2010.
“High speed clock and data recovery circuit with novel jitter reduction technique.” 2010
23rd International Conference on VLSI Design.
Hayatleh, K., S. Zourob, R. Nagulapalli, S. Barker, N. Yassine, P. Georgiou, and F. J. Lidgey.
2019. “A high-performance skin impedance measurement circuit for biomedical appli-
cations.” Journal of Circuits, Systems and Computers 28 (07):1950110.
Nagulapalli, R. and R. K. Palani. 2023. “A 4.5 X noise improved split-resistance current mode
bandgap with 18.4 ppm/° C in 28nm CMOS.” 2023 34th Irish Signals and Systems
Conference (ISSC).
Nagulapalli, R., R. K. Palani, and S. Bhagavatula. 2020. “A 24.4 ppm/° C voltage mode
bandgap reference with a 1.05 V supply.” IEEE Transactions on Circuits and Systems
II: Express Briefs 68 (4):1088–1092.
Nagulapalli, R., R. K. Palani, K. Hayatleh, N. Yassine, and S. Barker. 2021. “A 0.82 V supply
and 23.4 ppm/° C current mirror assisted bandgap reference.” 2021 32nd Irish Signals
and Systems Conference (ISSC).
Nagulapalli, R., N. Yassine, A. A. Tammam, S. Barker, and K. Hayatleh. 2024. “A 10.5 ppm/°
C modified sub-1 V bandgap in 28 nm CMOS technology with only two operating
points.” Electronics 13 (6):1011.
Palani, R. K., R. Nagulapalli, and S. Bhagavatula. 2023. “Dynamic averager based sub-1V
bandgap voltage reference.” 2023 IEEE 66th International Midwest Symposium on
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Varun, T. R., R. Nagulapalli, and I. Raja. 2021. “A 82μW mixed-mode sub-1V bandgap refer-
ence with 25 ppm/° C temperature Co-efficient with simultaneous PTAT generation.”
2021 25th International Symposium on VLSI Design and Test (VDAT).
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mentation systems.” Analog Integrated Circuits and Signal Processing 95:403–408.
 4 Advancements
in Contemporary
Circuit Design
Exploring Alternatives
to CMOS for Enhanced
Performance
G. Boopathi Raja

4.1 INTRODUCTION TO CONTEMPORARY
CIRCUIT DESIGN CHALLENGES
In the realm of modern PCB manufacturing and design, engineers face multifac-
eted challenges demanding a delicate equilibrium between functionality, power
efficiency, and form factor optimization. Maximizing signal integrity, thermal man-
agement, and adaptability to component shortages further complicates the landscape
[1, 2]. Concurrently, the evolution of IoT devices causes meticulous attention to net-
work protocols and communication channels, all while striving for compactness,
lightness, and speed [3]. To meet these demands, there is a pressing need to har-
ness existing design technologies while simultaneously pioneering new ones. PCB
designers are tasked with navigating a complex web of conflicting requirements to
realize their design goals [4, 5].
Contemporary circuit design encounters a plethora of obstacles spanning various
technologies, notably including FinFET-, CNTFET-, and GNRFET-based circuits
[6–8]. The following are the key challenges encompassed by contemporary circuit
design:

Process Variability: The continuous reduction in the size of semiconduc-

tor technology increases concerns regarding process unpredictability.
Variations in device characteristics, such as threshold voltage and oxide
thickness, may cause differences in performance and reduce overall yield.
Power Consumption: The demand for integration and portability highlights
the need to reduce power consumption while maintaining performance,
especially in areas such as IoT and mobile electronics [9, 10].

48 DOI: 10.1201/9781003483052-4
Advancements in Contemporary Circuit Design 49

Signal Integrity and Noise: The reduction in feature sizes increases the
susceptibility to noise, crosstalk, and other forms of interference, hence
emphasizing the need for methods including shielding and noise isolation
to ensure dependable operation [11].
High-Frequency Operation: In order to meet the growing demand for
processing data at high speeds, it is necessary to create circuits that can
function at higher frequencies. However, intrinsic parasitic effects pose sig-
nificant obstacles.
Reliability and Aging: The reduction in device size and operating voltages
increases concerns about reliability and aging effects. This requires the
implementation of techniques to mitigate phenomena such as bias tempera-
ture instability and electro-migration.
Design for Manufacturability (DFM): The progression of semiconductor
technology results in a simultaneous increase in the complexity of manu-
facturing procedures. Designers must effectively manage restrictions, such
as limits in lithography and variances in the production process, to enable
cost-effective manufacturing.
Thermal Management: With the rapid increase in transistor and power den-
sities, it has become crucial to prioritize excellent thermal management in
order to prevent performance decline and maintain device reliability.
Design Automation and Tools: The increasing complexity of contemporary
circuits emphasizes the need for effective design automation tools and
approaches to simplify the design process and enhance performance.

Therefore, it is essential for device engineers, circuit designers, and manufacturing

experts to work together in order to develop creative solutions and design approaches
for developing technologies such as FinFETs, CNTFETs, and GNR-FETs [12, 13]
(Table 4.1).

4.2 BICMOS TECHNOLOGY
A complex semiconductor device manufacturing process produces integrated cir-
cuits and essential electronics components. Today’s electrical circuits are made on
silicon and other semiconductor wafers [14]. This manufacturing technique includes
photolithography, chemical procedures, and sophisticated electronic circuit build-
ing. Semiconductor manufacturing expanded internationally from Texas in the early
1960s, underlying current technology.
BiCMOS, a significant development in semiconductor technology, emerged dur-
ing the 1990s and facilitated surface-mount integration (SEMI). BiCMOS pioneered
the combination of bipolar junction transistors with CMOS transistors [15].

4.2.1 BiCMOS Logic
This technique combines the low power consumption of bipolar technology with the
fast operating speed of CMOS technology, resulting in the integration of NMOS and
50 Circuit Design for Modern Applications

TABLE 4.1
Various Designs and Competing Factors of Circuit Design
Design Factor Motivation Competing Factors
Size A compact size is preferred, since there Characteristics, effectiveness, overall
is a prevalent trend toward portable execution, thermal management.
consumer-grade gadgets.
Power The power of a device may be defined Thermal characteristics, dimensions,
as either the cumulative power output and mass.
of the device between charges, which
is relevant for portable devices, or the
highest power output it can achieve.
Functionality In order to increase their marketability Factors to consider for highly high-end
and appeal, devices often use a Swiss gadgets include size, weight,
army knife strategy of adding features cost-effectiveness, design intricacy,
or overlapping existing ones. and probable long-term durability.
Thermal Devices designed for prolonged use or Size, power.
Performance direct touch with people must not
generate excessive heat, since this
might hinder performance and user
comfort.
Communication There is an increasing industry emphasis Key considerations include security,
on enhancing communication efforts the availability of the network,
with the advancing IoT market to battery life for autonomous
optimize performance and enhance deployment, and extra
user happiness. electromagnetic interference (EMI)
problems.
Security Besides the promotion of IoT, customers Characteristics, effectiveness.
are seeking enhanced safeguards for
their identifying information.

PMOS. Within this paradigm, MOSFETs provide logic gates with high input imped-
ance, whereas bipolar transistors are used to amplify current greatly [16]. BiCMOS
production entails the smooth incorporation of NMOS, PMOS, and BJT technolo-
gies, using various layers throughout the manufacturing process, such as channel
stop implantation, thick layer oxidation, and protective rings. Figure 4.1 provides
a visual representation of a standard BiCMOS inverter circuit, which includes four
MOSFETs and two BJTs.
Incorporating traditional CMOS and bipolar technology into the production pro-
cess will provide significant theoretical challenges. Manufacturing problems arise
when parasitical bipolar transistors are accidentally produced during the p-well and
n-well CMOS processing phases. The BiCMOS manufacturing method involves
many additional operations that optimize the performance of the bipolar and CMOS
components. Consequently, the overall manufacturing costs increase.
Advancements in Contemporary Circuit Design 51

FIGURE 4.1 The typical BiCMOS inverter circuit comprises four MOSFETs and two BJTs.

The figure shown above shows the integration of a channel barrier into semi-
conductor devices using implantation, diffusion, or other techniques. By employing
this approach, the expansion of the channel area is restricted and the generation of
unwanted parasitic channels is prevented. Guard rings are used in areas where cur-
rent flow is limited, often because of high-impedance nodes that cause surface leak-
age currents, in order to prevent the flow of current.

4.2.2 Advantages of BiCMOS Technology

• Using bipolar transistors for other components, together with the use of a
high-impedance CMOS circuit as the input, improves the design of analog
amplifiers [17].
• BiCMOS has exceptional robustness against temperature and process vari-
ations, leading to economic benefits by achieving a high output of high-
quality units and minimum variability in electrical properties.
• BiCMOS devices can provide high-load current sinking and sourcing as
needed.
• When evaluating a combination of bipolar and CMOS technologies, the use
of BJTs offers benefits in terms of speed, whilst MOS is more desirable for
applications that need low power consumption. In addition, MOS technol-
ogy is very effective at driving loads with substantial capacitance while
minimizing cycle time.
• BiCMOS technology has lower power dissipation compared to the sole use
of bipolar technology.
• BiCMOS technology is often used in various power management and
amplifier circuits, including BiCMOS amplifiers.
• It is ideal for applications that need a lot of input/output processes, provid-
ing flexible I/O choices, including TTL, CMOS, and ECL.
• Integrating CMOS technology with other technologies improves the speed
performance.
• BiCMOS systems have improved resistance to latch-up.
• The bidirectional capability of the device enables the interchangeability of
the source and drain as required.
52 Circuit Design for Modern Applications

4.2.3 Drawbacks of BiCMOS Technology

• The combination of CMOS and bipolar technology requires an increasingly
complex manufacturing process.
• As manufacturing processes get more complex, the prices of fabrication
also increase.
• The increase in the number of devices is followed by a decrease in lithog-
raphy capabilities.

4.2.4 BiCMOS Technology and Applications

This analysis arises from the combination of velocity and elevated concentration
that comes with this technology. BiCMOS provides a faster speed performance com-
pared to bipolar technology in specific situations, especially when power resources
are limited. It serves as an alternative to previous technologies, including bipolar,
ECL, and CMOS. BiCMOS technology gained significance in RISC microproces-
sors because of its suitability for applications with complicated input and output
processes, as opposed to typical CISC microprocessors. It performs exceptionally
well in a variety of applications, most notably memory and input/output in micro-
processors. BiCMOS technology enables the integration of analog and digital sys-
tems by bridging the gap between circuit boundaries and operational channels. The
supply of inputs with high impedance facilitates its utilization in the sample and
holds applications. This adaptable feature is used in several fields, including adders,
mixers, ADCs, and DACs. BiCMOS techniques are utilized in the design of opera-
tional amplifiers to overcome the constraints of both bipolar and CMOS equivalents,
with the goal of achieving both high gain and high-frequency characteristics concur-
rently. By utilizing these BiCMOS amplifiers, it becomes possible to achieve all the
characteristics in the construction of operational amplifiers.

CHALLENGES OF CONTEMPORARY CIRCUIT DESIGN

With the continuous progress of semiconductor technology, it becomes more and
more crucial to guarantee the dependability of integrated circuits. Phenomena such
as negative bias temperature instability (NBTI) and hot carrier injection (HCI) cause
gradual changes in device parameters over time, which result in parameter drift dur-
ing operation. It is crucial to consider and tackle these degradation processes in the
design phase in order to create reliable and competitive goods.
The diminishing gap between the actual lifespan of MOSFETs and the longev-
ity demands of items incorporating advanced technologies underscores the impor-
tance of a change in responsibilities. Technological advancement alone is no longer
enough; it is important to have coordinated initiatives that involve engineers, reli-
ability specialists, and circuit designers [18].

1. Form Factor vs. Functionality:

The problem of balancing the utility and form factor when design-
ing circuit boards is always present. Designers must carefully organize
Advancements in Contemporary Circuit Design 53

components to guarantee optimal signal integrity and thermal efficiency

while also accommodating essential functions.
2. Power Efficiency:
Given the increasing need for portable devices, ensuring power effi-
ciency is of utmost importance. Designers face the challenge of reducing
power usage while preserving performance. Dynamic voltage scaling,
Power gating, and clock gating techniques are used to attain this intricate
equilibrium [19].
3. High-Speed Design:
As the pace at which data is sent increases, ensuring the integrity of
high-speed signals becomes essential. Challenges include the management
of electromagnetic reflections, crosstalk, and timing closure. Non-reliable
high-speed designs need proper routing, impedance management, and
termination.
4. Component Shortages and Supply Chain Disruptions:
The global supply chain encounters interruptions caused by geopoliti-
cal conflicts, natural catastrophes, and pandemics. Circuit designers must
adjust to shortages of components and identify alternate remedies.
5. Mixed-Signal Integration:
Integrating analog and digital components on a single chip presents dif-
ficulties with noise, interference, and compatibility. It ensures a smooth
connection between analog and digital realms and requires meticulous
design methodologies [20].
6. Security and Trust:
Protecting circuits against unauthorized access, alteration, and counter-
feiting is crucial. The designers must include resilient security measures.
Techniques including safeguarding hardware modules, secure boot, and
encryption are crucial.
7. Design for Manufacturability:
It ensures manufacturability entails considering variables such as yield
and process variances, including design rule checks throughout the design
stage. It operates together with manufacturing teams to facilitate a more
streamlined production process.

4.4 SILICON-ON-INSULATOR AS A PROMISING ALTERNATIVE

Silicon-on-insulator (SOI) is a semiconductor fabrication technique used to enhance
the performance of integrated circuits (ICs) by reducing parasitic capacitance and
improving the speed and efficiency of electronic devices. In SOI technology, a thin
layer of silicon (usually a few hundred nanometers thick) is placed on top of an insu-
lating substrate, such as silicon dioxide (SiO2) or sapphire. This creates a sandwich
structure, where the active silicon layer is isolated from the substrate by the insulator.
The electrical issues with junction area, isolation, leakage current, and parasitic
capacitance in conventional bulk silicon devices have been addressed by SOI archi-
tectures, which have garnered considerable interest. Using meticulous engineering,
54 Circuit Design for Modern Applications

FIGURE 4.2 Cross-sectional view of a bulk CMOS and SOI CMOS structure.

SOI wafers are composed of multilayer semiconductors and dielectrics, which pro-
vide sophisticated Si devices with novel functionalities [21]. By employing SOI
wafers, monolithic semiconductor circuits are assembled with dielectric isolation
in place of junctions. Figure 4.2 shows the cross-sectional view of Bulk CMOS and
SOI CMOS structure.
In other words, SOI is a semiconductor technique that involves the transfer of a
thin layer of crystalline silicon over an oxidized silicon handle substrate. SOI wafers,
in contrast to conventional bulk silicon wafers, do not depend on a continuous bulk
silicon structure. Conversely, they are comprised of a thin silicon layer over an insu-
lating layer. The interoperability between SOI and CMOS infrastructure has facili-
tated the development of commercially accessible photonic integrated circuits (PICs)
on SOI wafers [22].

4.4.1 Characteristics of Silicon-on-Insulator Wafers

SOI structures comprise a single-crystalline Si film that is separated by a SiO2 layer
from the bulk substrate. SOI structures depend highly on the submerged oxide (BOX)
layer, also known as the SiO2 layer. SOI wafers provide dielectric isolation, low volt-
age operation, short-channel effects, vertical junctions, flexibility in circuit design
and processing, and reliability over bulk silicon. Vertical isolation reduces leakage
currents, radiation-induced photocurrents, and latch-up effects on the thin active sili-
con layer caused by the voluminous substrate. Implementing lateral isolation in SOI
obviates the necessity for complex schemes to achieve separation between devices.
The junction surface area, leakage current, and capacitance are all diminished by
the concealed oxide layer. Because of these conditions, power consumption is dimin-
ished, velocity is increased, and the temperature spectrum is broadened. Scalability
is crucial for SOI wafers. Unlike bulk Si, SOI wafer sheet thickness is adjustable. SOI
devices are more resistant to short-channel effects (SCE) because the tiny junction
area limits drain and source region expansion and provides dual-gate control over
body potential. Charge sharing between gate and junction regions causes SCE [23].
However, SOI wafer implementation faces several obstacles. Transistor effects
such as self-heating, floating body, interface coupling, and dynamic transients, as
well as integrated circuit development and SOI technology customization, are the
main challenges.
Advancements in Contemporary Circuit Design 55

4.4.2 Methods of Fabricating SOI Wafers

Several methodologies have been devised to manufacture SOI wafers, resulting in
the creation of different SOI configurations throughout time. Some methods used in
this context include separation by implanted oxygen (SIMOX), zone melting recrys-
tallization (ZMR), epitaxial lateral growth (ELO), silicon-on-sapphire (SOS), full
isolation by oxidized porous silicon (FIPOS), and wafer bonding.
The SOS technique involves the growth of a silicon layer on top of an aluminum
oxide substrate by epitaxy. The downsides of SOS film include the impact of lateral
stress, non-homogeneous regions inside the film, and the existence of flaws at the
interface. However, these obstacles may be overcome by the use of solid-phase epi-
taxial regrowth and re-epitaxy. Using this technique, commercially workable SOS
wafers of 6 inches in diameter and covered with coatings that are 100 nanometers
thick may be produced.
The ELO technique uses the formation of a single crystal film from a Si substrate
to the oxide layer. To use this technology, it is necessary to further decrease the
thickness of the Si layer. This is usually done after the epitaxial growth by applying
a patterned oxide. In the ZMR process, an energy source such as lasers, strip heaters,
e-beams, or lamps is used to apply a polysilicon layer on the BOX and recrystal-
lize it. In the FIPOS technique, a certain part of the silicon layer is converted into
the submerged oxide layer by the process of anodic polymerization and oxidation
processes.
SIMOX is a widely used method for manufacturing SOI wafers. Interior oxidation
of an oxygen wafer occurs because of the deep oxygen ion implantation procedure.
The annealing process uses temperatures up to 1320°C to reinstate the crystalline
nature of the film. The SIMOX wafer is characterized by its high carrier mobility,
strong BOX, consistent thickness, low defect density, and accurate Si–SiO2 inter-
face. SIMOX offers several configurations including low-dose SIMOX with a BOX
thickness of 100 nm or less, standard SIMOX with a 0.2 μm thick Si film and a 0.4
μm thick BOX, double SIMOX with a sandwiched Si layer surrounded by two buried
oxide interconnects, and interrupted oxides.
The wafer bonding method is also essential for the manufacturing of SOIs. Wafer
bonding is the fusion of an oxidized silicon wafer with another silicon wafer. The
Si layer is progressively reducing in thickness to the intended magnitude. Etch-stop
layers are essential for this operation and are often produced by methods like doping,
epitaxy, or porous silicon. UNIBOND is a customized iteration of the semiconductor
bonding process. Unlike traditional wafer bonding, the etch-back operation is not
included. Hydrogen micro-cavities occurring naturally are used to separate the semi-
conductors after the bonding and annealing procedures. The Smart Cut method, also
referred to as this technique, offers several advantages. These include eliminating
the need for the etch-back phase, producing wafers of excellent quality, using stan-
dard equipment, achieving cost-effective wafer manufacturing, and providing a wide
range of options for BOX and thin-film combinations. The resulting wafers have a
superior BOX layer, little defect density, and favorable electrical characteristics.
56 Circuit Design for Modern Applications

4.4.3 Applications of SOI Wafers

SOI technology has found widespread use in various applications, including micro-
processors, RF (radio frequency) circuits, power management ICs, and high-speed
communication devices. It continues to be an area of active research and development
in the semiconductor industry. Some applications of SOI technology are discussed:

4.4.3.1 CMOS Circuits
Complementary metal-oxide-semiconductor (CMOS) technology has proven to be a
crucial instrument in meeting the demands of continuously advancing technology.
The semiconductor industry currently regards Si-based CMOS as the benchmark
technology for RF devices. Fully depleted CMOS/SOI circuits, which operate at
temperatures above 300°C, are used in a vast array of processes. These circuits are
extremely appealing to the automotive, aviation, and petrochemical industries. Fully
depleted CMOS has a significantly lower leakage current and a threshold voltage that
is less temperature-sensitive (> 0.5 mV/°C) than bulk Si. At a 25 nanometer scale,
partially depleted CMOS is also extensively used in the digital industry as a low-
power, high-performance alternative to bulk silicon. Utilization of SOI MOSFET
(metal-oxide-semiconductor field-effect transistor) technology has been facilitated
by the continued demand for CMOS circuits to incorporate a more compact device,
faster operation, and more affordable components. MOSFET technology for SOI has
proven to be effective in industrial settings characterized by extreme temperatures
and radiation, as well as high frequencies. To further improve the performance of
CMOS circuits, various SOI MOSFET configurations have been created, including
ultra-thin body (UTB), strained, Schottky barrier, and multi-gate MOSFETs.
Because of their resistance to short-channel effects, UTB and ultra-thin BOX
(UTBB, UTBOX, or UTB2) SOI MOSFETs are widely regarded as some of the
most potential candidates for the ultimate device scalability. In addition, UTB SOI
MOSFETs offer back-gate control schemes and help reduce the self-heating effect.
Strained MOSFETs increase the mobility of carriers by employing strained SOI
wafers. Low Schottky barrier contacts are considered a highly promising alternative
for reducing the resistance to source/drain (S/D) contacts, establishing abrupt junc-
tions (without capacitance overlap), and significantly decreasing the thermal budget
of the CMOS process. To reduce the SCE in nanometer-scale MOSFETs, multiple-
gate architectures have emerged as one of the most promising novel device structures
because of the simultaneous control of the channel by more than one gate. A wide
variety of multi-gate MOSFETs are commercially available, such as omega-gate (γ-
G), triple-gate (TG), pi-gate (PG), and quadruple-gate (QG). Each of these structures
is constructed using a unique arrangement of SOI wafers.
In addition, SOI substrates are used to integrate CMOS electronics with MEMS
devices to produce more precise MEMS applications. The utilization of SOI sub-
strates facilitates the combination of microelectronics and MEMS devices and sim-
plifies the manufacturing processes of MEMS. The conventional microelectronics
device industry can benefit from the concealed oxide layer in SOI wafers in several
Advancements in Contemporary Circuit Design 57

ways, including increased transistor switching speed at the expense of decreased

power consumption and decreased latch-up. By utilizing MEMS devices with SOI
substrates, accelerometers, and gyroscopes are being manufactured.

4.4.3.2 Bipolar and High-Voltage SOI Devices

BiCMOS circuits and thin-film bipolar transistors featuring lateral configurations
have a high cutoff frequency, whereas hybrid MOS-bipolar transistors exhibit
enhanced current drive and transconductance. LDMOSFETs, or lateral double-dif-
fused MOS transistors, are an additional configuration that possesses an extended
drift region. LDMOSFETs can withstand voltages of 90 V to 1.3 A. Thick-film SOI
can accommodate vertical DMOS. Vertical power devices (LDMOS, IGBT, UMOS)
that use local buried oxide are in the non-SOI region of the wafer. Intelligence for
the entire circuit is supplied by a nearby low-power CMOS/SOI circuit. Intelligent
power devices with 600-V/25-A capabilities that use these bulk Si/SOI structures are
accessible for high-voltage applications.
Besides optical switches, waveguides, and modulators, the extensive selection of
SOI devices encompasses microwave transistors integrated into high-resistivity SOI
substrates and a variety of 3D circuits, including inverters featuring superimposed
n- and p-channel transistors.

4.4.4 Advantages of SOI
• High-Quality Crystalline Films: SOI overcomes limitations imposed by
crystal development by integrating high-quality crystalline films on differ-
ent base materials.
• CMOS Compatibility: CMOS methods may be used with SOI wafers,
allowing for efficient large-scale manufacturing.
• Reduced Parasitic Capacitance: Because the active silicon layer is elec-
trically isolated from the substrate, parasitic capacitance is significantly
reduced. This results in faster switching speeds and lower power con-
sumption, making SOI particularly suitable for high-speed and low-power
applications.
• Elimination of Latch-Up: SOI technology effectively mitigates the occur-
rence of latch-up, a prevalent problem seen in bulk silicon technology.
• Resistance to Radiation: SOI is the preferred choice for microelectronic
devices that need to withstand high temperatures and resist radiation. It
offers inherent radiation hardness, making it suitable for applications in
harsh environments such as aerospace and defense.
• Improved Device Performance: SOI technology helps to minimize the
effects of electrical noise and interference, leading to improved signal
integrity and device performance.
• Better Integration: SOI technology allows for tighter integration of
devices and circuits on a single chip, enabling higher levels of functionality
in a smaller footprint.
58 Circuit Design for Modern Applications

4.4.5 Beyond SOI: Compound Semiconductor on Insulator (CSOI)

CSOI integrates non-silicon crystalline materials with insulators to provide a foun-
dation for innovative technologies. These devices include:

• Surface-Normal Optical Interference Structures: used in precise mea-

surement and calibration.
• High-Performance Transceivers: Relevant to applications involving the
transmission of data.
• Nonclassical Light Sources: Enabling the development of integrated quan-
tum photonic technology for the future.

4.4.5.1 Materials in CSOI
• CSOI encompasses compound semiconductors, which are created by com-
bining elements from Group III and Group V on the periodic table.
• Integrating these innovative combinations onto low-index base materials
shows potential for improving device performance.

SOI and CSOI provide promising opportunities for the advancement of photonics
and integrated circuits. They serve as a connection between conventional microelec-
tronics and state-of-the-art optical technologies.

4.5 MEMRISTOR-BASED CIRCUIT ARCHITECTURES

An increasing number of high-resolution mixed-signal applications currently call for
the integration of analog and digital features. The aim is to attain system dependabil-
ity, decrease expenses, and enhance compactness. Nonetheless, creating integrated
circuits that include both analog and digital subsystems poses significant difficulties.
Analog subsystems may have limitations in their operation because of switching
noise produced by the digital subsystems, which are often designed using comple-
mentary MOS (CMOS) logic [24].
The progression of computer capabilities over the past five decades has been
intricately linked to the miniaturization of CMOS technology. In contrast, digital
computing systems have been built upon von Neumann architecture, which estab-
lishes a logical and physical separation between the memory and execution units
and facilitates communication between them via a variety of interconnect types. In
recent times, there has been a deceleration in the rate of device scaling, accompa-
nied by electrical interconnect turning into a significant source of power dissipation
and a performance impediment. This is the most critical constraint on technology
development at present. Traditional memory technologies, such as Flash, DRAM,
and SRAM, are struggling to meet the demands of the market in terms of power
efficiency and density. Physically, Flash memory has been depleted and cannot be
expanded further; this is primarily because of its short lifespan [25].
Advancements in Contemporary Circuit Design 59

Emerging semiconductor devices, such as memristors, which serve as memory

cells and innovative switching circuits that can be utilized to augment conventional
CMOS gates, can mitigate these issues.
A memristor, short for “memory resistor,” is a two-terminal electronic compo-
nent that behaves as a resistor with memory. Unlike traditional resistors, which obey
Ohm’s law and have a linear relationship between voltage and current, memristors
exhibit a non-linear relationship between the electric charge and the magnetic flux
linkage, which means their resistance can change over time based on the voltage or
current applied to them.
One of the most remarkable properties of memristors is their ability to “remem-
ber” the amount of charge that has previously flowed through them and to keep that
resistance state even after the power is turned off. This behavior enables them to
function as non-volatile memory elements, capable of storing information with no
continuous power.
Additionally, memristors may be linked in order to execute Boolean operations.
Because high-density memristors can be manufactured at the point where metal
lines of nanoscale width intersect, which is a characteristic shared by all silicon
circuits and above the silicon layer, these novel devices exhibit potential for further
functional density expansion [26–29]. The primary focus of this thesis is to integrate
memory with computational capabilities architecturally using these new devices.
Beyond Moore scaling, these structures composed of memristors will significantly
increase the speed and power of digital computation without compromising com-
patibility with conventional CMOS technology. Architecturally, memristor-based
circuits will cause novel systems and structures for memory-intensive computation.

4.5.1 Applications of Memristors
• Non-Volatile Memory: Memristors can create next-generation non-volatile
memory devices that offer higher density, faster access times, and lower
power consumption compared to traditional Flash memory.
• Neuromorphic Computing: Memristors have shown promise in neuro-
morphic computing, which aims to mimic the structure and function of the
human brain’s neural networks. Their ability to store and process informa-
tion in a single device makes them well-suited for applications such as pat-
tern recognition and machine learning.
• Reconfigurable Logic: Memristors can implement reconfigurable logic
circuits that can adapt their functionality on-the-fly based on changing
requirements, offering flexibility and efficiency in digital circuit design.
• Analog Signal Processing: Memristors can be used in analog signal-
processing applications such as filters, oscillators, and neural network cir-
cuits because of their non-linear behavior and ability to store analog state
information.

At the architecture and circuit levels, the development of memristor-based applica-

tions is the primary aim of this study. From the perspective of a computer architect
60 Circuit Design for Modern Applications

FIGURE 4.3 Memristor-based Wien-bridge oscillator.

and circuit designer, memristors are examined, including the description of the
intended device for various applications and the modeling of a general memristor
model – TEAM – to accommodate various memristive technologies. The accuracy
of the TEAM model is adequate despite its simplicity (i.e., low computational effort
requirement of 2). VerilogA is utilized to implement the TEAM model for SPICE
simulations.
A multitude of logic circuits incorporating memristors have been suggested,
accompanied by the development of design methodologies. The logic families
IMPLY (material implication), MAGIC (memristor ratioed logic), and Akers logic
arrays enable in-memory computing by being executed within memristive memo-
ries. MRL (memristor ratioed logic) is an alternative logic family that is imple-
mented in hybrid CMOS memristor logic gates in order to extend Moore’s law and
increase logic density. Figure 4.3 shows the circuit diagram of the memristor-based
Wien-bridge oscillator.
A novel memory structure called the multistate register is introduced, which has
the capability of storing multiple values within a single register. The construction
of a multistate register involves the placement of an RRAM crosspoint array atop a
relatively small-area CMOS register. A single state in a 64-state RRAM multistate
register occupies a mere 1.3% of the area of a state stored in a CMOS register. In
order to facilitate the implementation of memory-intensive architectures, including
Continuous Flow Multithreading (CFMT), the multistate register is integrated into
CPU pipelines. CFMT is a low-energy, high-performance multithreaded processor
that can be configured as straightforward as Switch on Event Multithreading (SoE
MT). Compared to SoE MT, CFMT is designed and implemented using an FPGA,
resulting in an average performance enhancement of 32% and an energy conserva-
tion of 8.5%.

4.5.2 Positive Feedback Source-Coupled Logic (PFSCL)

PFSCL is a logic family that functions by using current steering principles. The aim
is to tackle concerns pertaining to power consumption, system dependability, and
noise in mixed-signal systems. Existing PFSCL designs have constraints, particu-
larly for performing logical operations in NOR/OR form or sum of two minterms.
Advancements in Contemporary Circuit Design 61

4.5.3 Memristor Integration
Integrating memristors represents a recent technological advancement in nanoelec-
tronics, into PFSCL-style circuits. Two novel PFSCL designs based on memristors
are suggested:

• Mem-PA1: By integrating memristors into a PFSCL inverter.

• Mem-PA2: With the aid of memristors and a PFSCL NOR/OR gate.

By overcoming the limitations of existing designs, these architectures provide ben-

efits in terms of propagation latency, power consumption, and gate count. The utili-
zation of simulations incorporating CMOS PTM 180 nm technology parameters and
a TiO3 memristor reveals substantial enhancements in both power and delay metrics.

4.5.4 Memristor-Based Logic Circuits

Logic circuits based on memristors can be classified into two general categories:

• State-based logic circuits: The output has been kept as a resistance state.
• Voltage-based logic circuits: Scouting logic, material implication logic
(IMPLY), and memristor-assisted logic (MAGIC) should be implemented.

Memristors present promising prospects for augmenting circuit design by facilitat-

ing the transition from analog to digital domains.

4.6 QUANTUM-DOT CELLULAR AUTOMATA

Proposed enhancements on conventional computer design (CMOS), quantum-dot
cellular automata (QDCA), are also known as quantum cellular automata (QCA)
[30]. This has been designed in a manner similar to the conventional models of cel-
lular automata that John von Neumann initially introduced.
QCA is a promising nanotechnology-based computing paradigm that uses the
quantum properties of electron charges confined in quantum dots to perform digi-
tal computation. QCA offers potential advantages over conventional CMOS-based
technologies, such as lower power consumption, higher device density, and faster
operation.
A discrete dynamical system composed of an even (finite or infinite) grid of cells
is referred to as a cellular automaton (CA). A discrete time can only be spent among
a finite number of states per cell. The state of every cell in the grid is determined as
time progresses by a transformation formula that considers both its prior state and
the states of the cells immediately next to it (referred to as the cell’s “neighborhood”).
“Game of Life” by John Horton Conway, which he described in 1970, is the most
widely recognized case of a cellular automaton.
62 Circuit Design for Modern Applications

QCA operates based on the Coulombic repulsion and attraction between elec-
trons confined in quantum dots. Quantum dots are nanoscale semiconductor struc-
tures that confine electrons in three dimensions, creating discrete energy levels. By
arranging quantum dots in a regular grid pattern, it’s possible to encode binary infor-
mation using the spatial arrangement of electrons.
QCA is a suggested enhancement to traditional computer design (CMOS) that is
based on the ideas of cellular automata. Cellular automata are discrete dynamical
systems composed of a grid of cells, where each cell may exist in one of several
states. QCA uses quantum dots, which are nanoscale devices, to perform computa-
tions with quick switching rates and little power usage [31–33].
QCA is modeled as a cellular automaton, where cells represent individual quan-
tum dots, and the state of each cell (presence or absence of an electron) determines
the computation. Information is propagated through the QCA array by local interac-
tions between neighboring cells, similar to the rules governing cellular automata.
Logic gates and complex circuits can be constructed by arranging and configuring
the QCA cells appropriately. The essential characteristics of QCA comprise the abil-
ity to differentiate and the capacity for conditional alteration of the state.
QCA logic gates are constructed using the Coulombic interactions between
electrons in neighboring quantum dots. The basic QCA logic gates include major-
ity gates, inverter gates, and wires, which can be combined to implement complex
Boolean functions. QCA gates operate based on the polarization of charge within
the quantum dots, where the alignment of electron spins determines the logic state.

4.6.1 Quantum-Dot Cells
It is typical for cellular automata to be executed as software applications. Conversely,
a physical implementation of an automaton using quantum-dot cells was postulated
by Lent et al. in 1993. Instantaneously gaining in popularity, the automaton was
initially constructed in 1997. By integrating the discrete characteristics of cellular
automata and quantum mechanics, Lent could fabricate nanoscale devices that could
execute computations at switching velocities on the order of Terahertz while con-
suming negligible quantities of electrical power.
QCA cells are fabricated by arranging four quantum dots in a square configura-
tion. Quantum dots enable electrons to occupy precise locations via the phenomenon
of tunneling, [30]. Figure 4.4 depicts a simplified representation of a four-dot QCA
cell and Figure 4.5 illustrates the two potential states of a four-dot QCA cell.

FIGURE 4.4 Basic four-dot QCA cell.

Advancements in Contemporary Circuit Design 63

FIGURE 4.5 Two potential states of a four-dot QCA cell.

4.6.2 Modern QCA Design

At present, the distance between quantum dots in standard solid-state QCA cells is
estimated to be 20 nm, while the distance between cells is estimated to be 60 nm.
Quantum (-dot) cellular automata, similar to other CAs, operate based on straight-
forward interaction principles among cells arranged in a grid. The building blocks
of a QCA cell comprise four quantum dots that are squarely arranged. These quan-
tum dots are locations that electrons can tunnel to inhabit. It provides benefits in
terms of gate count, speed, and energy usage as compared to conventional CMOS
architectures.

4.6.3 Advantages
• QCA offers potential advantages over conventional CMOS technology,
including extremely low power consumption because of the absence of
static power dissipation and ultra-small device size.
• QCA devices can operate at room temperature and are highly resilient to
electromagnetic interference, making them suitable for harsh environments.
• The intrinsic quantum nature of QCA enables inherently secure computa-
tion, as quantum properties such as superposition and entanglement can be
exploited for cryptographic applications.

4.6.4 Challenges
• Despite its potential advantages, QCA faces several challenges, including
fabrication complexity, clocking and synchronization issues, and intercon-
nect challenges.
• Fabricating QCA devices with precise positioning of quantum dots and
controlling their interactions at the nanoscale is technically demanding.
• Clocking and synchronization mechanisms are essential for ensuring the
reliable operation of QCA circuits, especially as device densities increase.
• Interconnects between QCA cells must be carefully designed to minimize
signal degradation and delay, particularly in large-scale circuits.

4.6.5 Applications
• Quantum circuitry analysis (QCA) has versatile applications in logic cir-
cuits, memory systems, and many computing tasks.
64 Circuit Design for Modern Applications

• Quantum cellular automata (QCA) is an innovative field in nanoscale com-

puting that connects the realms of classical and quantum physics. The
distinctive characteristics of this hold potential for future progress in infor-
mation processing.

4.7 NEUROMORPHIC COMPUTING APPROACHES

Neuromorphic computing is a fascinating discipline that seeks to replicate the archi-
tecture and functioning of the human brain via the use of artificial neurons and syn-
apses. Neuromorphic computing is creating computers that replicate the structure
and functionality of the brain [34]. Neuromorphic computers may enhance problem-
solving, pattern recognition, and decision-making capabilities compared to conven-
tional computers by mimicking the information-processing mechanisms of human
brains.
Neuromorphic computing is a branch of computing that draws inspiration from
the structure and function of the human brain to develop more efficient and intel-
ligent computing systems. Unlike traditional von Neumann architecture, which
separates processing and memory, neuromorphic computing aims to integrate these
functions, mimicking the parallelism, plasticity, and energy efficiency of the brain.
There are several approaches to neuromorphic computing, each with its own prin-
ciples, advantages, and challenges. Some of them are listed:

Spiking Neural Networks (SNNs): SNNs are inspired by the way neurons
communicate in the brain through spikes or action potentials. They operate
in an event-driven manner, where neurons generate spikes in response to
input stimuli. SNNs are highly efficient in terms of energy consumption and
can handle asynchronous data processing. Implementations include hard-
ware-based approaches using neuromorphic chips like IBM’s TrueNorth,
Intel’s Loihi, and SpiNNaker.
Memristive Neuromorphic Systems: Memristors are resistive devices that
change their resistance based on the history of applied voltage/current.
Memristive neuromorphic systems use memristors as synapses to mimic
synaptic plasticity, enabling learning and memory functionalities. These
systems might achieve high-density integration and low-power operation.
Research focuses on developing memristive devices with desirable charac-
teristics for neuromorphic applications.
Optoelectronic Neuromorphic Computing: This approach leverages the
speed and energy efficiency of light-based communication in combination
with electronic neurons and synapses. Photonic devices such as lasers, mod-
ulators, and photodetectors are integrated with electronic circuits to imple-
ment neuromorphic functionalities. Optoelectronic neuromorphic systems
offer potential advantages in terms of speed, bandwidth, and scalability.
Bio-Inspired Neuromorphic Computing: This approach aims to mimic not
only the structure and function of biological neurons but also the principles
of neural development and organization. It involves exploring concepts such
Advancements in Contemporary Circuit Design 65

as neural plasticity, self-organization, and hierarchical processing. Bio-

inspired neuromorphic systems often employ complex, hierarchical archi-
tectures and learning algorithms inspired by biological neural networks.
Analog Neuromorphic Computing: Analog neuromorphic computing relies
on analog circuits to emulate the behavior of neurons and synapses. Analog
circuits can efficiently model neural dynamics and synaptic weights, poten-
tially offering high computational efficiency. Challenges include device
mismatch, noise, and nonlinearity, which affect the accuracy and stability
of analog neuromorphic systems.
Quantum Neuromorphic Computing: Quantum neuromorphic computing
combines principles from quantum computing and neuromorphic comput-
ing to develop systems capable of processing information using quantum-
mechanical phenomena. Quantum neural networks and quantum-inspired
algorithms are explored for solving optimization, pattern recognition, and
other tasks. Challenges include Qubit coherence times, error rates, and scal-
ability of quantum hardware.

Each approach to neuromorphic computing has its own set of advantages and chal-
lenges, and ongoing research aims to address these challenges and unlock the full
potential of brain-inspired computing systems for various applications, including
artificial intelligence, robotics, sensor networks, and more. The technique involves
the integration of biological and technological elements, including brain-inspired
hardware and algorithms [32]. Neuromorphic computing has the potential in several
domains:

• Edge Computing: Processing at the network’s periphery, where speed is

critical, with maximum efficiency.
• Autonomous Vehicles: Self-driving vehicles decide instantly.
• Cognitive Computing: Improvement of Artificial Intelligence (AI)
capabilities.

In contrast to the doubling of computational capacity every two years, as pre-

dicted by Moore’s law, neuromorphic computing presents an improved alternative.
Neuromorphic designs simulate the neocortex, which is the outer layer of the brain
that handles advanced cognitive tasks. The neocortex has a layered structure and
complex connections that facilitate the fast processing of information. Spiking neu-
ral networks are used by neuromorphic computers to achieve this efficiency. These
networks comprise synthetic synapses and neurons that can connect almost instantly.

4.7.1 Applications
Neuromorphic computing holds promise for a wide range of applications across vari-
ous domains because of its ability to mimic the parallelism, plasticity, and energy
efficiency of the human brain. Some of the application areas of neuromorphic com-
puting include:
66 Circuit Design for Modern Applications

AI and Machine Learning: Neuromorphic computing can speed up AI and

machine learning tasks by providing highly efficient hardware for train-
ing and inference. It enables the implementation of SNNs, which are well-
suited for event-driven processing and can efficiently handle tasks such as
pattern recognition, classification, and anomaly detection. Neuromorphic
hardware offers advantages in terms of low power consumption, real-time
processing, and scalability, making it suitable for edge and embedded AI
applications.
Robotics and Autonomous Systems: Neuromorphic computing can enhance
the intelligence and autonomy of robotic systems by enabling real-time
perception, decision-making, and control. Spiking neural networks can be
used for sensor fusion, motor control, navigation, and adaptive behavior
in robots and autonomous vehicles. Neuromorphic hardware offers low-
latency processing, robustness to noise, and energy efficiency, which are
critical for real-time and energy-constrained robotic applications.
Neuromorphic Sensing and Signal Processing: Neuromorphic computing
can improve the efficiency and performance of sensing and signal-pro-
cessing systems by mimicking biological sensory systems. It enables the
development of event-based sensors and signal-processing algorithms that
respond dynamically to changes in the environment. Neuromorphic hard-
ware can be used for tasks such as audio and image processing, environ-
mental monitoring, and biomedical sensing, with advantages in terms of
low power consumption and adaptability.
Brain-Computer Interfaces (BCIs): Neuromorphic computing can facilitate
the development of advanced BCIs for communication, control, and reha-
bilitation applications. It enables the real-time decoding of neural signals
and the generation of feedback signals to interact with external devices.
Neuromorphic BCIs offer advantages in terms of low-latency interaction,
adaptability to user preferences, and the potential for closed-loop control in
prosthetics and assistive technologies.
Cognitive Computing and Brain-Inspired Systems: Neuromorphic comput-
ing can advance the field of cognitive computing by providing hardware
platforms for simulating brain-inspired algorithms and architectures. It
enables research into cognitive functions such as learning, memory, atten-
tion, and decision-making, leading to the development of more human-like
intelligent systems. Neuromorphic hardware offers advantages in terms
of scalability, fault tolerance, and energy efficiency, making it suitable for
large-scale brain-inspired computing systems.
Neuromorphic Hardware Acceleration: Neuromorphic computing can
speed up a wide range of computational tasks, including simulation, optimi-
zation, and data analysis, by leveraging specialized hardware architectures.
It enables the development of energy-efficient accelerators for specific neu-
romorphic algorithms and applications, such as neuromorphic vision chips,
spiking neural network accelerators, and neuromorphic inference engines.
Advancements in Contemporary Circuit Design 67

Hence, neuromorphic computing has the potential to revolutionize various fields

by providing efficient and brain-inspired solutions to complex computational prob-
lems, leading to advancements in AI, robotics, sensing, and cognitive computing.
Neuromorphic computing promises more rapid and efficient computation by bridg-
ing the divide between biology and technology.

4.8 PHOTONICS IN CIRCUIT DESIGN

Photonics in circuit design refers to integrating photonic components and tech-
nologies within traditional electronic circuits. Photonics deals with the generation,
transmission, modulation, and detection of light, and it offers several advantages
over electronics, such as higher bandwidth, lower latency, and reduced power con-
sumption. In circuit design, photonics can be used in various applications, including
telecommunications, data communication, sensing, and computing. Photonics are
integrated into circuit design based on the following ways:

Optical Interconnects: Instead of traditional copper wires, optical intercon-

nects use light to transmit data between components on a chip or between
chips. This can significantly increase data transfer rates and reduce power
consumption, especially in high-performance computing and data centers.
Optical Sensors: Photonics-based sensors can be integrated into circuits for
various applications, such as environmental monitoring, biomedical sens-
ing, and industrial automation. These sensors offer high sensitivity, fast
response times, and immunity to electromagnetic interference.
Photonic Integrated Circuits: PICs are like electronic integrated circuits but
use optical components such as lasers, modulators, detectors, and wave-
guides to process and manipulate light signals. PICs can perform functions
such as routing, switching, and signal processing, and they are essential for
building complex optical communication systems.
Optoelectronic Devices: These devices combine electronic and optical func-
tionalities, such as light-emitting diodes (LEDs), photodiodes, and laser
diodes. Optoelectronic devices are used in various circuit applications,
including displays, optical communication systems, and sensing.
Fiber-Optic Communication: Fiber-optic communication systems transmit
data over long distances using optical fibers. In circuit design, fiber-optic
transceivers and interfaces are used to connect electronic circuits to fiber-
optic networks, enabling high-speed and long-distance data transmission.
Photonic Crystals: Photonic crystals are periodic nanostructured materials
that manipulate the flow of light. They can be integrated into circuits to
control and manipulate light at the nanoscale, enabling the development of
compact and efficient photonic devices.

Integrating photonics into circuit design requires expertise in photonics and elec-
tronics, as well as specialized design tools and fabrication techniques. However,
the benefits of photonics, such as higher bandwidth, lower power consumption, and
68 Circuit Design for Modern Applications

faster data transmission, make it an attractive option for various applications in mod-
ern circuit design.

4.8.1 Photonic Integrated Circuits

Photonics is a captivating discipline that encompasses the identification, creation,
and control of photons, known as light particles. PICs are essential in circuit design
[35].
PICs are integrated circuits that use optical components and technologies to pro-
cess and manipulate light signals. Similar to electronic ICs, PICs contain multiple
optical elements, such as lasers, modulators, detectors, waveguides, and couplers,
on a single chip. These components are interconnected using optical waveguides,
allowing for complex optical functionalities in a compact and integrated form. It
is a compact electronic device that incorporates many photonic components, hence
creating a fully operational circuit. PICs, in contrast to conventional electrical inte-
grated circuits that rely on electrons, use photons for information processing. These
circuits function within the range of wavelengths that are visible to the human eye or
in the near-infrared spectrum, often between 850 and 1650 nm. Indium phosphide
(InP) is the predominant material platform for PICs, enabling the combination of
several optically active and passive functionalities on a single chip [36–39]. Some
examples of PICs comprise tunable lasers, integrated receivers, and broadly tunable
lasers. The essential components of photonic integrated circuits are listed:

Waveguides: Waveguides are structures that guide and confine light within
the chip. They can be made from materials such as silicon, silicon nitride,
or polymers and are used to route light between different components of
the PIC.
Lasers: Laser sources are crucial components of PICs for generating coherent
light signals. Different lasers, such as semiconductor lasers or distributed
feedback lasers, can be integrated into the chip to provide the required opti-
cal sources.
Modulators: Optical modulators are used to encode information into the opti-
cal signals by modulating their intensity, phase, or polarization. Various
types of modulators, including electro-optic modulators, Mach–Zehnder
interferometers, and ring resonators, can be integrated into PICs for signal
modulation.
Detectors: Photodetectors are used to convert optical signals back into elec-
trical signals. Integrated detectors, such as PIN photodiodes or avalanche
photodiodes, enable the detection of optical signals within the PIC.
Couplers and Splitters: Optical couplers and splitters are used to divide,
combine, or distribute optical signals within the chip. Directional couplers,
multi-mode interference couplers, and Y-junction splitters are commonly
used components in PICs for signal routing and distribution.
Filters and Gratings: Optical filters and gratings are used to manipulate the
spectral characteristics of light signals. They can be integrated into PICs
Advancements in Contemporary Circuit Design 69

to select specific wavelengths, filter out unwanted wavelengths, or per-

form wavelength division multiplexing (WDM) for optical communication
applications.
Phase Shifters: Phase shifters are used to control the phase of light signals in
PICs. They are essential for implementing phase modulation, phase tuning,
and phase-sensitive signal-processing functionalities.

4.8.2 Advantages of PICs
• Speed: Because optical signals propagate at the speed of light, PICs are
more rapid compared to their electronic counterparts.
• Compactness: It is possible to incorporate many functions into a single
microprocessor.

PICs offer several advantages over discrete optical components, including compact-
ness, low power consumption, high integration density, and potential for large-scale
integration. They are used in various applications, including optical communica-
tion networks, optical interconnects for data centers, sensing systems, biomedical
devices, and quantum photonics. Edge computing, fiber-optic communication, and
autonomous vehicles are all areas in which PICs are used. PICs are fabricated using
advanced semiconductor fabrication techniques, such as CMOS processes, silicon
photonics, or III-V compound semiconductor technologies, depending on the spe-
cific requirements of the application.

4.9 FUTURE PERSPECTIVES AND CHALLENGES

Several perspectives and challenges emerge that will shape the trajectory of the field:

Scaling and Integration: One of the enduring challenges is scaling down

electronic components to smaller sizes while maintaining performance and
energy efficiency. As transistor sizes approach physical limits, innovative
techniques such as 3D integration and novel materials will be crucial for
continuing the trend of increasing integration density.
Power Efficiency: With the proliferation of portable and IoT devices, power
efficiency remains a paramount concern. Future circuit designs must priori-
tize low-power operation without sacrificing performance, enabling longer
battery life and reducing environmental impact.
Security and Privacy: As computing systems become more interconnected,
the need for robust security and privacy measures becomes increasingly
critical. Future circuit designs must integrate hardware-level security fea-
tures to protect against emerging threats such as side-channel attacks and
hardware Trojans.
Heterogeneous Integration: Future systems will probably incorporate a
diverse mix of computing elements, including traditional CPUs, special-
ized accelerators, and domain-specific processors. Designing efficient
70 Circuit Design for Modern Applications

heterogeneous systems that seamlessly integrate different components and

maximize overall performance remains a significant challenge.
Emerging Technologies: The rapid pace of technological innovation intro-
duces both opportunities and challenges. Emerging technologies such as
quantum computing, neuromorphic computing, and photonic computing
hold the potential to revolutionize computing paradigms but require signifi-
cant research and development to realize their full potential.
Manufacturability and Reliability: As circuit designs become increasingly
complex, ensuring manufacturability and reliability becomes more chal-
lenging. Future designs must account for variability in manufacturing
processes and incorporate fault-tolerant techniques to maintain system
integrity.
Environmental Sustainability: The electronics industry has a significant
environmental footprint, from resource extraction to end-of-life disposal.
Future circuit designs must prioritize sustainability by minimizing energy
consumption, reducing electronic waste, and exploring eco-friendly materi-
als and manufacturing processes.
Interdisciplinary Collaboration: To address these upcoming issues, it is
essential to collaborate across several fields, including electrical engineer-
ing, materials science, computer science, and physics. By collaborating
across disciplines, researchers may use knowledge from other fields to
develop innovative answers to complex issues.

The path of circuit design has great potential to advance technology and address
social problems. By embracing innovation, cooperation, and a commitment to
sustainability, researchers and engineers may pave the way for a future in which
electronic systems are not only more powerful and efficient but also secure and eco-
logically sustainable.

4.10 CONCLUSION
This chapter focuses on advanced circuit design, moving away from typical CMOS
approaches to investigate possibly better options that provide improved perfor-
mance. Despite a technological environment that is fast-changing and requires more
speed, efficiency, and flexibility, researchers and engineers are driven to investigate
novel methods to address these requirements efficiently. The chapter offers a thor-
ough examination of innovative technologies, including BiCMOS, GaAs, and SOI,
emphasizing their unique features and benefits compared to traditional CMOS sys-
tems. The chapter emphasizes the importance of adopting new approaches through
an examination of the limits of CMOS technology and an evaluation of the charac-
teristics and uses of other circuit design paradigms. Each technique is assessed for
its appropriateness in different applications, ranging from using bipolar transistors in
BiCMOS to improve performance to using the high-frequency capabilities of GaAs.
The conversation emphasizes the increasing need for sophisticated methods such as
SOI in tackling the inherent difficulties of conventional designs. This chapter seeks
Advancements in Contemporary Circuit Design 71

to enhance the discussion on the future of circuit design by surveying non-CMOS

options. It strives to provide engineers, researchers, and enthusiasts with useful
insights and techniques to fully exploit the capabilities of current technology.

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 5 STT-MRAM based
Cache Memory Design
for Multicore Systems
Yogendra Gupta, Ashish Sharma, Niketa Sharma,
Vinay Kanungo, and Amit Kumar Sharma

5.1 INTRODUCTION
The rapid advancement of microprocessor design has been significantly influenced
by the rapid evolution of computational technologies, particularly with the emer-
gence of multicore systems. The demand for high-capacity and efficient cache mem-
ory is on the rise as the number of cores in these systems continues to increase.
This demand has stimulated the investigation of emergent memory technologies that
can circumvent the constraints of conventional cache memories. Spin-transfer torque
magnetic random-access memory (STT-MRAM) has emerged as a promising candi-
date among these, providing high density, rapid access times, and negligible leakage
power.
The memory/bandwidth wall continues to be a significant obstacle in the field
of computer architecture. STT-MRAM’s distinctive characteristics offer a potential
solution to this problem. Nevertheless, the integration of STT-MRAM into contem-
porary multicore systems is not without its challenges. The objective of this book
chapter is to confront these obstacles by offering a comprehensive overview of STT-
MRAM-based cache design techniques, as seen from both the circuit and system
perspectives.
Our discussion will commence with an examination of the fundamental prin-
ciples of STT-MRAM and its advantages over traditional memory technologies. We
then explore a variety of design methodologies that have been suggested as a means
of effectively integrating STT-MRAM into multicore architectures. In this chapter,
we emphasize the advantages and potential disadvantages of these methodologies,
providing recommendations for optimizing their performance and efficiency.
Researchers, engineers, and students who are engaged in the design and devel-
opment of high-performance computing systems are the intended audience for this
chapter. We aspire to create a valuable resource that will motivate additional innova-
tion and research in this critical field by compiling and analyzing the most recent
developments in STT-MRAM-based cache memory design.

74 DOI: 10.1201/9781003483052-5
STT-MRAM based Cache Memory Design for Multicore Systems 75

We are grateful to the numerous researchers and practitioners whose work has
enhanced our understanding and knowledge of STT-MRAM technology. Their
endeavors have opened up new avenues for cache memory design, thereby expand-
ing the limits of what is feasible in contemporary computing systems.
The performance of the entire system has been largely influenced by the mem-
ory hierarchy for many years. Traditional CMOS devices get smaller and denser
with each new technology generation and as a result leakage current increases. The
sub-threshold leakage current increases exponentially as the transistor is scaled
down. The on-chip memories have a power consumption that is about 80%, which
is leakage-related [1]. The constant scaling of process technology to meet power,
bandwidth, and memory wall restrictions causes major modifications to a modern
processor’s architecture. Large capacity caches are required for current data-inten-
sive applications. The current SRAM architecture for cache memory has significant
drawbacks. Because of its low density and high leakage power, SRAM is impracti-
cal for current processors to use in lower technology nodes. Large cache memory is
necessary to lower bandwidth, and in future process technology generations, if it is
constructed using SRAM, it will consume 90% of the on-chip’s region [2].
According to Moore’s law [5], a CPU or integrated circuit transistor count doubles
every 18 months. A processor chip’s transistor count increases due to the decreas-
ing size of transistors with each technology generation. Small transistors made it
possible to drive circuits at high clock rates, which increased processing speed. We
are aware that multicore architectures have revolutionized contemporary computer
architecture. The first commercially available multicore processor was the IBM
Power 4 developed by IBM [6], and since then every desktop and laptop has a mul-
ticore processor inside it. This trend is evident in the potential for the number of
microprocessors on a single chip to double every few years. These multiprocessor
processors will be used extensively in high-end servers, embedded systems, super-
computers, and high-performance computing.
The number of processor cores that a chip contains may eventually be limited
as a result, restricting multicore scaling [3]. Large SRAM caches may also require
pricey cooling methods, which drives up the chip’s cost and complexity. Thermal
problems are also brought on by SRAM’s high leakage power. These challenges
have prompted researchers to look at cache memory construction methods other than
SRAM.
To overcome some of the difficulties related to the advancing of CMOS tech-
nology, notably in cache memory, spin-transfer-torque magneto-resistive random-
access memory (STT-MRAM) is seen as a viable substitute. The integration density
of STT-MRAM is similar to that of dynamic RAM (DRAM). Furthermore, because
of its inherent qualities—such as “non-volatility”, “high endurance” (> 1015 cycles),
radiation hardening (important in space and military applications), fast speed (~ 10
ns), scalability, and high retention time (~ 10 years) [4]. STT-MRAM has been con-
sidered a potential solution for overcoming scaling issues associated with traditional
memory technologies such as “static random-access memory (SRAM), Dynamic
Random-Access Memory (DRAM), and flash memory”.
76 Circuit Design for Modern Applications

5.2 BACKGROUND
In this section, we describe the complete memory hierarchy of a multicore system.
Then, we give an illustration of integrating cache memory using STT-MRAM. STT-
MRAM cell characteristics and integration possibilities are introduced as we wrap
up this section.

5.2.1 Multicore Computer Architecture

A collection of connected individual processors combined into a single chip is
referred to as a multicore processor, as shown in Figure 5.1. In a multicore processor,
each processing core operates independently and collaborates with other cores to
speed up processing [7]. Each processing core has its own private cache, and these
cores communicate with one another via an interconnection network.

5.2.2 Why Multicore?
According to Moore’s law “the number of transistors on a single chip doubles every
18 months”, as we discovered in the previous section, designers have been able to
put 1 billion transistors onto the microprocessors that are currently in use. Here, the
challenge of how to use all these transistors in the microprocessor design arises. We
are aware that all significant computer programs are sequential in design and written
in C or C++. These programs were converted by the compiler into a set of paralleliz-
able instructions. For example, in the instruction:

x   a  b   (c x   a  b    c  d    d / f  (5.1)

We could operate in parallel on addition, multiplication, and division. “Instruction

Level Parallelism” is the name of this system. However, we wouldn’t be able to
perform this concurrent operation until the CPU had three arithmetic units. This

FIGURE 5.1 Structure of multicore processor.

STT-MRAM based Cache Memory Design for Multicore Systems 77

motivates processor designers to add more arithmetic units. However, this straight-
forward sort of parallelism is uncommon, and processor designers typically only
include up to four arithmetic cores [7]. “thread-level parallelism” is another paral-
lelism that led to the development of multicore. For instance, a “for” loop has a set
of sequential instructions that are termed a thread. A thread is the smallest group
of sequential instructions that may be managed separately by a scheduler. These
threads are independent in many programs and can be executed concurrently by the
processing units. However, because of the limitations of this thread-level parallel-
ism, it is neither advantageous nor cost-effective to expand the number of arithmetic
units in a processor beyond 3 or 4. Using transistors to build and create on-chip
memory is another way to boost the performance of the processor. We are aware
that the speed gap between the CPU and memory has widened considerably with the
development of computer systems. Computer architects refer to this problem as the
“memory wall” because memory speed has always lagged behind processor speed
[8]. Furthermore, the data bus took a while to send data from the off-chip main mem-
ory to the processor because the main memory is off-chip. CPU was always forced
to wait for data and instructions to come in. The development of on-chip memory or
cache memory solved this issue. A small, extremely quick memory called a cache is
built into the processor’s chip. There is a size restriction for cache memory that can-
not be exceeded. Computer designers are searching for fresh and workable solutions
to utilize the available transistor. This inspires the notion of duplicating the proces-
sor (cores), placing them on a single chip, and connecting them so they can cooperate
to run programs. Because a simple processing core is repeated, developing a multi-
core processor is less expensive than designing a complicated single-core processor.

5.3 CHALLENGES IN MULTICORE COMPUTER ARCHITECTURE

5.3.1 Power Wall and the Rise of Dark Silicon
Roughly three decades ago, Moore’s law and Dennard’s scaling helped devices, cir-
cuits, and systems expand significantly, leading to steadily increasing performance.
However, the semiconductor industry struck with a “power wall” a few years ago.
The reason for this power wall is that although the number of transistors on a chip
is growing exponentially, the voltage needed to power them does not drop suffi-
ciently. According to statistics, a ten-time rise in transistor counts over the previous
decade was accompanied by just a 30% decrease in operational supply voltage [9].
According to Dennard’s scaling, reducing the transistor size enables operation at
lower voltages and powers while maintaining a consistent power density. Dennard’s
scaling was unsuccessful because voltage could not be reduced by as much as tran-
sistor length. This caused the power density to grow, which in turn led to hotspots,
and reliability and thermal concerns. A specific area of the chip is left inactive or idle
to prevent excessive power dissipation; this area is known as “dark silicon” [10]. The
chief contributors of dark silicon is shown in Figure 5.2. The research community
has been attempting to solve this problem for multicore systems with architectural
and circuit-level solutions over the last few years [11–13]. Dynamic power dissipation
78 Circuit Design for Modern Applications

FIGURE 5.2 Dark silicon chief contributors.

in digital circuits is influenced by supply voltage, load capacitance, and clock rate.
More cooling is needed as the clock frequency rises due to the increased power dis-
sipation. Voltage reduction reduces dynamic power usage but increases transistor
leakage power. The feasible power limit for cooling common microprocessors has
been achieved. Without an expensive cooling process, the clock frequency cannot
be increased

5.3.2 Memory Wall
The performance difference between the processor clock speed and the off-chip
memory speed, which leaves the processors starving for data, has been referred to
as a “memory wall” since the late 1980s. As seen in Figure 5.3, there has been a sig-
nificant performance difference between the CPU and memory over time. Although
we are aware that CPU speeds nearly double every 18 months, memory latency does
not decrease at the same rate, which causes memory wall issues. The memory wall
was meant to come falling thanks to on-chip cache memory, which is 10 to 100 times
quicker than off-chip DRAM. Cache memories, however, come with their own set
of issues. More than half of the silicon area of processors is taken up by the L1 and
L2 caches. As a result, cache memory uses a large portion of processing resources
rather than computations.

5.4 MEMORY HIERARCHY OVERVIEW

The importance of memories in computer systems has increased over time, as has
the degree to which they have been incorporated into them. As a result, the research
community has created a broad range of developing products and technologies.
The initial split in the memory hierarchy of modern computers is between the
primary or main memory, which supports quick data movement and is essential for

FIGURE 5.3 Performance gap between processor and memory [18].

STT-MRAM based Cache Memory Design for Multicore Systems 79

FIGURE 5.4 The memory hierarchy pyramid.

running applications, and the mass storage memory, which is slower than primary
memory.
The memory hierarchy in contemporary computer systems is depicted in
Figure 5.4. The closer it is to the central processing unit, the better it performs in
terms of bandwidth, latency, and endurance. The CPU registers are faster and located
closer to the CPU, as illustrated in the figure. Cache memory is located next to the
CPU, after registers.

5.4.1 Magnetic Memory
Electronics often use the electric charge of an electron, which is an electron’s fun-
damental feature, to process and store information. Spintronics was created when
researchers in the 1980s discovered a further dimension of electrons: spin-dependent
electron transport [14]. A brand-new approach to information processing and storage
called spintronics takes advantage of the electron’s spin, which is an essential char-
acteristic. In spintronic devices, the information is carried by the electron spin rather
than the electrical charge. Spintronic devices are quicker, more energy-efficient, and
non-volatile than semiconductor ones.
The phenomenon known as “magnetoresistance” [15] describes how some mate-
rials, ideally ferromagnetic materials, have a propensity to modify the value of their
electrical resistance when a magnetic field is applied externally. We are aware that
the velocity of an electron in conductive materials is inversely proportional to the
applied electric field. This could be expressed as

v  E (5.2)

Where E is the applied electric field, v is the electron’s velocity, and µ is the electron’s
mobility. Additionally, the Lorentz force has an impact on electron transport when a
magnetic field is present. This effect is defined as

F = evB (5.3)
80 Circuit Design for Modern Applications

Where B is the magnetic field density and e is the charge on an electron. This results
in the magneto-resistive (MR) effect, whereby the resistance of the material changes
in the presence of a magnetic field. William Thomson made the initial discovery of
this phenomenon, which is also known as anisotropic magnetoresistance, in 1856.
A few years later, scientists would identify gigantic magnetoresistance and tunnel
magnetoresistance, two more strong MR phenomena.

5.4.2 STT-MRAM Overview
STT-MRAM relies on the manipulation of electron spin to store and read data. Spin
is an intrinsic property of electrons and is used to represent the binary states (0 or 1)
in STT-MRAM cells. The basic operation involves passing a spin-polarized current
through a Magnetic Tunnel Junction (MTJ), which consists of two ferromagnetic lay-
ers separated by a thin insulating layer. The relative orientation of the magnetization
in the two ferromagnetic layers determines the resistance of the MTJ, representing
the stored data [16].
An access transistor and MTJ make up the STT-MRAM cell, as depicted in
Figure 5.5 [17]. The STT-MRAM cell’s magnetic tunnel junction is where the data
is stored. STT-MRAM cells with an MTJ (1T1J) structure and one access transistor
are the most common form. The MTJ structure is shown in Figure 5.6. An external
magnetic field can independently alter the direction of the magnetizations in either
of the two ferromagnetic films in STT-MRAM. An electrical signal is defined by the
magnetic direction of the two FM layers, which can be either parallel (low-resistance
state) or anti-parallel (high-resistance state). Turning on the Word Line allows access
to the gate terminal of the NMOS transistor. In the circuit, MTJ is referred to as a
current-dependent resistor.
Reducing the write energy of the MTJ is the main problem at the device level
[33]. STT-MRAM has a higher write energy than SRAM which will be utilized as
an on-chip cache. The critical switching current (IC) of an MTJ can be made to be
smaller than 25 nm to lower write energy and make it comparable to the write cur-
rent of SRAM.

FIGURE 5.5 Magnetic tunnel junction.

STT-MRAM based Cache Memory Design for Multicore Systems 81

FIGURE 5.6 STT-MRAM 1T-1MTJ cell.

Another major challenge is improving read yield, which can be accomplished by

designing an MTJ device with a higher tunnel magnetoresistance (TMR) ratio and a
narrower resistance distribution. The definition and expression of the TMR ratio is:

TMR   RH  RL  / RL * 100% (5.4)

R L and R H are also expressed as RP and R AP, respectively. RP represents resistance

when the magnetization direction of the free layer and pinned layer is parallel and
R AP for anti-parallel magnetization directions.
A narrow resistance distribution in MTJs is beneficial for several reasons:

1. Read and Write Stability: In MRAM, data is stored as a high or low-

resistance state of the MTJ. A narrow resistance distribution ensures that
the resistance states are well-defined and distinct, improving the reliability
of both reading and writing operations.
2. Data Retention: A narrow distribution contributes to the long-term stabil-
ity of the stored data. If the resistance values of MTJs were widely distrib-
uted, it could lead to errors in reading and potential data loss over time.
3. Device Uniformity: A narrow resistance distribution indicates uniformity
among MTJs in a device or a batch. This uniformity is essential for manu-
facturing consistent and reliable MRAM devices.
4. Reduced Write Error Rates: During the writing process, where the mag-
netic orientation is manipulated to change the resistance state, a narrow dis-
tribution minimizes the likelihood of errors by ensuring that the intended
resistance change is achieved reliably.

To achieve a narrow resistance distribution in MTJs, manufacturing processes

must be carefully controlled. This involves precise deposition of materials, control
over layer thickness, and optimization of fabrication techniques. Quality control
82 Circuit Design for Modern Applications

measures are also implemented to screen out MTJs that fall outside specified resis-
tance tolerances.
To write the number “1” in, a positive voltage is placed between the Source Line
and Bit Line which represents the high-resistance anti-parallel state. The low-resis-
tance parallel state, represented by the number “0”, on the other hand, requires the
application of a negative voltage between the Source Line and Bit Line. A sensing
current is injected to create bit line voltage during a read operation. It is possible to
determine the resistance state of a Magnetic Tunnel Junction by comparing VBL to
a reference voltage.

5.4.3 STT-MRAM Array Architecture

Figure 5.7 illustrates a prevalent architecture of an STT-MRAM-based memory
array, comprising three primary components: “sense amplifiers (SAs), sensing cir-
cuits (SCs), data arrays, and a reference array”. In this configuration, the magneti-
zation direction of the “pinned layer” remains constant, while the magnetization
direction of the “free layer” is modified by applying a write current (Iwrite) through
the MTJ. As depicted in the figure, writing the low-resistance state (RL) involves
directing Iwrite (> IC) from the bit line (BL) to the source line (SL), whereas writ-
ing the high-resistance state (RH) involves channeling Iwrite (> IC) from the SL to
the BL. Notably, for state 0 (RL, parallel) and during the read operation where Iread
flows from BL to SL, the direction of Iwrite is the same. This alignment raises the
risk of an unintended state 0 write (read disturbance) during the read operation if the
selected MTJ is in state 1 (RH, anti-parallel). Consequently, as the critical switch-
ing current (IC) diminishes, it is imperative for Iread to decrease correspondingly to
maintain optimal read yield. The relationship between IC and Iread is evident in the
figure, indicating that these parameters scale with MTJ size.

5.5 COMPARISON OF SRAM AND STT-

MRAM-BASED CACHE MEMORY
Utilizing the CACTI [34] and NVsim [35] frameworks, we examined area, delay,
leakage, and dynamic power across variations in cache size, the number of banks,
block size, and associativity. We have compared SRAM and STT-MRAM caches

FIGURE 5.7 STT-MRAM array architecture.

STT-MRAM based Cache Memory Design for Multicore Systems 83

TABLE 5.1
Comparison of 32 nm, 8MB Cache Built with
SRAM and STT-MRAM
Parameter SRAM STT-MRAM
Read latency 1:777 ns 1:916 ns
Write latency 1:777 ns 4:506 ns
Retention time – 10 years
Read energy (per access nJ) 0:475 nJ 1:364 nJ
Write energy (per access nJ) 0:485 nJ 2:787 nJ
Leakage power (mW) 385:70 133:39
Area 7:451 mm2 2:666 mm2
Memory cell Factor (F2) 50–120 16–40

with these modeling frameworks, as shown in Table 5.1. We also investigate cache
design with technology scaling. We utilize the following cache characteristics as the
primary comparison metrics: “read latency (ns), write latency (ns), read energy (nJ),
write energy (nJ), leakage power (mW ), refresh power (mW ), and area (mm2)”.

5.5.1 Memory Technology Comparison

• Read Energy and Read Latency: Our experiments indicate that the read
latency of SRAM and STT-MRAM is nearly identical. In high-capacity
cache memory, interconnections significantly influence access time and
access energy. Therefore, owing to the smaller cell size and shorter wires,
the read latency and read energy of STT-MRAM are almost equivalent to
SRAM.
• Write Energy and Write Latency: The STT-MRAM cell requires a longer
write time and a larger write current. Consequently, the STT-MRAM cache
exhibits increased write latency and greater write energy consumption. Our
findings indicate that the STT-MRAM cache has approximately 2.5 times
longer write latency and six times higher write energy per access compared
to the SRAM cache.
• Leakage Power: The leakage power in SRAM cache memory is gener-
ated by both the SRAM cell and the peripheral circuitry. In contrast, in
STT-MRAM, the leakage power is primarily attributed to the peripheral
circuitry, while the leakage power of the STT-MRAM cell itself is close
to zero. Consequently, the SRAM cache memory consumes more leakage
power compared to the STT-MRAM in these two memory designs.
• Area: The size of the memory cell plays a crucial role in determining the
cache area. Our findings reveal that the SRAM cache is approximately
three times larger than the STT-RAM caches.
84 Circuit Design for Modern Applications

5.6 SPINTRONIC CACHE ARCHITECTURE

We provide an overview of methods for designing STT-MRAM-based caches in this
section.

5.6.1 Write Energy Minimization Techniques

Early write termination (EWT) is a strategy that Ping Zhou et al. [18] developed
for reducing write energy. This technique can drastically lower the write energy
of a STT-MRAM. EWT is based on the observation that there is a strong likeli-
hood that many locations will remain unchanged after a write operation into a cache
memory. This finding has been applied to the L1 cache’s word-level granularity [26].
Therefore, we have the chance to delete many bits that were written with values iden-
tical to those already present in the cache. We can cut the write energy and eliminate
the unneeded writes. They presented a straightforward EWT circuit to halt superflu-
ous bit writes at their earliest stages using the EWT technique, which is proposed
at the bit level of granularity. There is no access latency overhead introduced by it.
For last-level cache memory, Masayuki Sato et al. [19] suggested the Adjacent
Line-Merging Writeback Scheme. Cache lines, which are fixed-size blocks that are
used to transfer data between memory and cache, are used. To the STT-MRAM
LLC, this approach applies a huge cache line size. The upper-level cache (L1 and
L2) combines two neighboring short lines into one long line and writes the combined
line back to the STT-RAM LLC. With this method, the write energy to the STT-
MRAM LLC is reduced. Junwhan Ahn et al. [20] introduced a unique technique
called “Dead Write Prediction Assisted STT-RAM Cache Architecture (DASCA)”.
The important finding in the last-level cache is that a sizable portion of data written
is not really referenced again throughout the existence of the relevant cache blocks.
Write operations, which we refer to as dead writes, can avoid the cache without
resulting in additional misses. To reduce write energy, this method anticipates dead
writes and avoids them.
Park et al. [21] proposed a technique called on a last-level STT-RAM cache using
a cache line update technique as shown in Figure 5.8. The cache line is conceptu-
ally segmented into multiple partial lines; for example, a 64B cache line is divided
into four partial lines. Each partial line contains a history bit stored in the L1 cache
to monitor which partial lines have been modified. With this information, only the
altered partial lines are written when a dirty L1 block is transferred to the last-level
cache. Moreover, this approach facilitates sequential tag-data access to an STT-
RAM cache, reducing the read energy.
To minimize the dynamic energy during a cache read access, initially only the tag
values are read. If a hit occurs, only the designated cache line is accessed. According
to the assumption that L1 caches are based on static random-access memory and
L2 caches are based on STT-RAM, Kim et al. [22] assessed several cache memory
hierarchy management policies. For the first time, they assessed inclusion-related
policies (inclusive, non-inclusive, exclusive, non-exclusive), and they discovered that
the non-exclusive policy is the most energy-efficient option for L2 cache writes. Data
STT-MRAM based Cache Memory Design for Multicore Systems 85

FIGURE 5.8 Partial cache line update scheme [6].

migration for subblock-sized data is made possible via Discard Unused. Our Discard
Unused approach assumes that unused subblocks won’t be used later and that the
spatial locality will be disclosed during the residency in the L1 data cache. By add-
ing an extra status bit when a cache block is in the L1 data cache, the Discard Unused
technique keeps track of used subblocks.

5.6.2 Hybrid Cache Memory

The authors [23–25] introduced a hybrid cache memory that integrates a large, albeit
slow, MRAM-based memory with a smaller, faster SRAM-based memory. Other
researchers have also investigated a hybrid cache memory design that incorporates
both SRAM and MRAM within a single cache level. Data migration strategies are
employed to primarily write to the SRAM region, which is faster, and read data from
the MRAM portion. This approach mitigates the performance degradation caused by
the high write latency of MRAM. Additionally, the cache capacity can be enhanced
due to the higher density of MRAM. Wu et al. [26] devised a hybrid cache design that
leverages the optimal characteristics of both SRAM and STT-MRAM technologies.
The hybrid cache architecture comes in two variations, both of which we examine
and assess: the inter-cache level hybrid cache architecture (LHCA), where different
memory technologies can compose levels in a cache hierarchy, and the intra-cache
level or cache region-based hybrid cache architecture (RHCA), allowing a single
cache level to be partitioned into multiple regions, each employing a distinct memory
technology. The researchers examined potential hardware support for intra-cache
data mobility and power consumption management within HCA caches, exploring
different HCA topologies. A write merging method was put forth by Jadidi et al.
[27] for the run-time STT-MRAM-based last-level cache in chip microprocessors.
Every cache set is typically divided into a small number of SRAM lines and many
STT-RAM lines. Data that is frequently written is directed to SRAM-based cache
lines, whereas data that is rarely written or is read-only directed to STT-RAM. They
suggested a hardware method with little overhead to identify the write-intensive data
86 Circuit Design for Modern Applications

blocks. In a novel contribution, the working set’s write-intensive data blocks are
detected and placed into SRAM lines using a low overhead, fully hardware tech-
nique, while the working set’s non-write-intensive data blocks are candidates to be
remapped into STT-RAM blocks during system operation. Consequently, the STT-
RAM array ensures dynamic write energy, tolerable write latency, and a long life-
time, while the SRAM array ensures large capacity and nearly no leakage energy.

5.6.3 Write Energy-Aware Replacement Algorithms

A write energy-aware cache replacement technique was put out by Liu et al. [28].
They used MinHash to find similarities in the cache line. The cache line with the
highest resemblance is selected as the victim and replacement candidate. To decrease
the write energy and write error rate in STT-MRAM-based L2 cache, Monazzah et
al. [29] devised a cache replacement mechanism known as least error rate (LER).
Their algorithm positions the incoming block in the line that results in the fewest
write errors. By comparing the contents of the arriving block with the cache line,
this is accomplished.

5.6.4 3D Stacking STT-MRAM

Some writers assess the benefits of adding an L2 cache based on STT-MRAM on top
of a 2D CPU architecture [30]. Before comparing it to its SRAM counterpart with the
same area in terms of energy and performance, they first built a die-stacking cache
model. They go on to explain that the MRAM-based cache results in performance
and power degradations for applications that frequently write data to L2 caches
because of the lengthy latency and high energy of STT-MRAM write operations.

5.6.5 Reliability Aware STT-MRAM Cache

STT-MRAM memories exhibit high density and minimal leakage power, yet they
grapple with reliability challenges such as read disturbance, write failure, and reten-
tion failure. Among these, write failure, occurring when an incorrect value is written
to an STT-MRAM cell during a write operation, stands out as a critical reliability
issue. In the present study, the authors [31] introduce ROCKY, a strong architecture
with effective replacement methods for the cache memory hierarchy based on STT-
MRAM. Improving STT-MRAM’s resistance to write failures is the goal. By reduc-
ing vulnerable transitions in STT-MRAM cache memories, this method promotes
more reliable write operations. Rahbari et al. [32] also address the write failure prob-
lem in STT-MRAM. By reducing the frequency of both read disturbance and write
failure, they presented a conditional replacement policy (CRP), an error-aware cache
replacement method, to raise the dependability of STT-MRAM caches. By select-
ing an appropriate data block from the cache for replacement with an incoming data
block while minimizing the error rate, this is established. The efficiency and latency
of write and read operations are also considered. Simulation results indicate that,
compared to the latest replacement policy, CRP reduces the overall error rate in STT-
MRAM caches by 68%.
STT-MRAM based Cache Memory Design for Multicore Systems 87

5.7 FUTURE PERSPECTIVE AND RESEARCH DIRECTION

This chapter displayed some advantages of utilizing STT-MRAM in the cache
memory hierarchy and on-chip network. Even though STT-MRAM is a rising NVM
technology, it needs more improvement, and study is essential to investigate how
new characteristics and future development could help to mitigate recent issues of
multicore computer architecture. In this chapter, a discussion of STT-MRAM was
limited to its performance and energy perspective. Further, parameters need to be
investigated for the utilization of STT-MRAM in multicore memory, such as endur-
ance, reliability, and security. From a security perspective, any possible attack based
on data obtained from the physical implementation of a computer system or crypto-
graphic algorithm is termed a “side channel attack”. The frequent information used
for SCAs is EM (electromagnetic) emission, timing, and power consumption. In
SCAs, the attacker analyzes the relation between the leaked data and the processed
information. SCAs have been discussed by the researchers for CMOS-based systems
utilizing SRAM and flash memories [36–39]. As STT-MRAM has the potential to
be included in upcoming memory devices, probable future research is to investigate
the use of STT-MRAM against SCAs. Also, a random number generator is certainly
advantageous for cryptography because “random cryptographic keys” would be gen-
erated to securely transmit the information. There are two types of “random number
generators” that exist: PRNG (“Pseudo RNG”) and TRNG (“True RNG”). PRNGs
are software-based random number generators and use deterministic methods to
generate random numbers. Contrarily, TRNGs are hardware-based and use a non-
deterministic physical process to generate random numbers. Eventually, TRNGs
are more useful for encryption and data security. The researchers [33] have shown
through experiments that STT-MRAM could be used as a true RNG. The stochastic
characteristics of STT-MRAM switching [34] have been utilized to generate a series
of random numbers. Thus, it motivates us to put more effort into the progress of STT-
MRAM-based TRNGs. The reliability of STT-MRAM technology is a crucial issue
that limits its monetary deployment. The limited endurance of STT-MRAM caused
hard errors; in the future, these errors can be lowered to a certain extent that can
work for most applications. Soft errors are also a principal source of errors, which
is due to process and thermal variations. The errors in memory can be categorized
as read failure, write failure and retention failure. In the future, we can explore error
correction codes for STT-MRAM-based cache memories.
Research in spin-transfer-torque magneto-resistive random-access memory (STT-
MRAM) cache design is an evolving field, and several directions are being explored
to address challenges and enhance the performance of STT-MRAM caches. Here are
some key research directions in STT-MRAM cache design:

• Write Circuit Optimization: Developing efficient write circuits to mini-

mize energy consumption and reduce write latency in STT-MRAM is a
critical research area. Researchers are exploring novel write-assist tech-
niques, voltage control schemes, and circuit architectures to optimize the
write process.
88 Circuit Design for Modern Applications

• Read Circuit Design: Improving the read circuitry to enhance the sensing
accuracy and speed during read operations is an ongoing research direction.
Techniques such as reference voltage optimization, sense amplifier design,
and adaptive read circuits are explored to mitigate read disturbances.
• Reliability Improvement: Addressing reliability issues such as write fail-
ures, read disturbances, and retention failures remains a crucial focus.
Researchers are exploring architectural and circuit-level techniques to
enhance the robustness of STT-MRAM caches.
• Write Endurance Enhancement: Improving the endurance of STT-
MRAM, which refers to the ability to withstand many write-erase cycles, is
an ongoing area of research. Strategies involve exploring materials, designs,
and algorithms to mitigate the impact of repeated write operations.
• Write Energy Reduction: Reducing the write energy consumption in
STT-MRAM caches is essential for improving overall energy efficiency.
Researchers are investigating novel write-assist techniques, voltage control,
and other design optimizations to minimize the energy required for write
operations.
• Performance Optimization: Enhancing the overall performance of STT-
MRAM caches is a critical research direction. This includes exploring
novel cache architectures, access schemes, and algorithms to maximize the
benefits of STT-MRAM in terms of speed and efficiency.
• Hybrid Memory Architectures: Integrating STT-MRAM with other
memory technologies, such as SRAM or non-volatile memories, in hybrid
memory architectures is being explored. This approach aims to combine
the strengths of different memory types to achieve better overall system
performance and energy efficiency.
• Data Management and Migration: Investigating efficient data manage-
ment and migration strategies within STT-MRAM caches is crucial for
optimizing performance. Researchers are exploring ways to minimize
data movement and maximize the utilization of STT-MRAM in cache
hierarchies.
• Error Correction Techniques: Developing effective error correction tech-
niques tailored for STT-MRAM is a key area of research. This involves
designing algorithms and error correction codes to address potential errors
and improve the reliability of stored data.

5.8 CONCLUSION
Emerging memory technologies including eDRAM, STT-RAM, RRAM, PCM, and
DWM offer new design opportunities because they have various desirable qualities
like low leakage power and high density. However, they also have several draw-
backs that must be fixed, including low write endurance, excessive write latency, etc.
We provided a summary of architectural approaches in this study for dealing with
problems in caches created with cutting-edge memory technology. Additionally, we
STT-MRAM based Cache Memory Design for Multicore Systems 89

provided a classification of the techniques based on crucial factors. According to our

predictions, these cutting-edge methods and technology will improve steadily and be
included in conventional processors.

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Singapore, 2020), pp. 335–349.
 6 Optimal Approaches
for Enhancing Energy
Efficiency in Circuits
A. Rameshbabu, V.R.S. Mani,
V.N. Senthil Kumaran, and Neethu Anna Sabu

6.1 INTRODUCTION
The evolution of digital circuits has been consistently driven by the relentless
progression of technology, which has pushed the boundaries of performance,
efficiency, and miniaturization [1]. In recent decades, the necessity to decrease
energy consumption and noise in very large scale integration (VLSI) circuits has
prompted a greater emphasis on low-power design solutions [2]. This emphasis has
resulted in the development of innovative methodologies that have fundamentally
altered the digital circuit design landscape, with a particular emphasis on optimiz-
ing the efficacy of functional units, including adders, multipliers, and arithmetic
logic units (ALUs).
Moore’s law, which anticipates a doubling of integrated circuit efficiency and
component density every two years, continues to influence the design and optimiza-
tion of VLSI circuits [3]. The delicate balancing act of managing energy consump-
tion and performance is a significant challenge for designers as transistors become
more numerous and compact [4]. The performance of the ALU, a critical component
capable of executing both arithmetic and logic operations, is intrinsically linked to
the efficacy of the latest processors, which is pivotal to modern computing.
The adder is a fundamental component of an ALU, unique among the numerous
components. This investigation examines the efficacy of Parallel Prefix Adders, with
a particular emphasis on those that employ pass transistor logic (PTL). Insights into
the efficiency and potential for development of these adders are obtained by com-
paring them to key performance metrics, including power consumption, delay, and
area [5].
This chapter introduces a modified Parallel Prefix Adder architecture that tran-
scends conventional designs in order to achieve optimal performance [6]. This
improved architecture not only satisfies rigorous performance standards but also
provides substantial benefits for industrial applications. Our objective is to advance
the field of low-power VLSI design by investigating these innovative approaches,

92 DOI: 10.1201/9781003483052-6
Optimal Approaches for Enhancing Energy Efficiency In Circuits 93

which will contribute to the ongoing pursuit of high-performance, efficient digital

circuits [7].
It is our aspiration that this investigation will offer practical solutions and valu-
able insights to industry professionals, engineers, and researchers who are commit-
ted to the ongoing development of digital circuit technology.
In general, any digital-based processor or control system is capable of performing
fundamental operations like addition, subtraction, and division by utilizing many
different types of binary adders [8]. The device’s adder performance is evaluated
only by a processor or system’s accuracy and quickness. 32-bit carry adders like
the Carry Look Ahead Adder (CLA), Carry Propagate Adder (CPA), and Ripple
Carry Adder (RCA) that have various addition durations (delays), areas, and power
consumptions are utilized by the processors. The speed at which the carry reaches
each and every bit position is the foundation for calculating any binary adder’s delay
[9–11]. Therefore, the main difficulty in designing the carry chain, that creates the
carry bit, operates as a binary adder.
In the last decade, various adder architectures have been investigated in an effort
to further improve performance. Adders such as the Ripple Carry and Carry Look
Ahead Adder are adequate for smaller bit counts. Parallel Prefix Adders are recom-
mended for higher bit counts because longer carry chains result in increased delay
[12–15]. Due to their low latency and excellent area efficiency, Parallel Prefix Adders
are high-speed adders. Because every adder level must wait for the preceded carry
result. In higher-order bits, the basic carry adders have considerable delay values.
In VLSI technology, Parallel Prefix Adders are a well-suited adder for fast addition
operations with very little delay [16]. One of the most frequently employed designs
that offers good area, speed, and power optimization is the Parallel Prefix Adders.
This chapter investigates the simulation results, including the waveform and reports,
of the Parallel Prefix Adder we have created, taking into performance considerations
like power, area, and latency as well.

6.2 PARALLEL PREFIX ADDERS

The Prefix Adders are constructed in a variety of ways depending on the various
demands and carry production. Recently, the addition function in all types of CPUs
has been enhanced through the implementation of adders with a tree structure.
Parallel Prefix Adders are the fastest adders constructed using a tree structure, and
are commonly used in DSP labs and subsequent corporations for outstanding perfor-
mance arithmetic operations. Another name for the Parallel Prefix Adders is loga-
rithmic delay adders because to determine the delay value, logarithmic functions
are utilized [17]. Three primary actions can be utilized for carrying out addition in
Parallel Prefix Adders: Pre-computation (creation of P and G signals), prefix-com-
putation (production of carry signals groups), and Post-computation (generation of
sum signals). Another trend in VLSI design is the shorter duration to market and the
rising importance of automated design. Prefix adders additionally fulfil this need
because of their consistency, which makes it simple to incorporate them into com-
puter-aided design (CAD) systems.
94 Circuit Design for Modern Applications

6.2.1 Pre-Computation
In the pre-processing stage, the computation of propagate and generate functions is
dependent on the input signals provided. The equation accomplishes the propagate
functions.

Pi  Ai  Bi (6.1)

Equation 6.1 demonstrates how an XOR logic gate processes the input signals A and
B. The above equation accomplishes the propagate functions.

Gi  Ai  Bi (6.2)

According to Equation 6.2, the input signals that make up the AND logic gate are A
and B. Although the previously mentioned equations are executed in parallel, there is
no noticeable rise in the computation of area consumption, and the delay is entirely
dependent on a specified bit size at the input.

6.2.2 Prefix-Computation
This prefix-computation stage, instantly computes the carry signal groups using the
input and values that are calculated during the first pre-computation step [18]. When
creating carry signals, the delay increases by default because more than two inputs
are utilized. Equations 6.3 and 6.4 describe the carry-propagation and carry-gener-
ation functions.

Pi: j  Pi:k  Pk 1: (6.3)

Gi: j  Gi:k  Pi:k  Gk 1: j (6.4)

6.2.3 Post-Computation
In this stage, the sum result is generated by an Ex–OR process that incorporates
the carry-generating stage values (In prefix-computation). The final sum output is
calculated by Equation 6.5.

Si:k  Pi  Ci 1 (6.5)

where P is the propagate function and C is the final carry signal.

Optimal Approaches for Enhancing Energy Efficiency In Circuits 95

6.3 LADNER-FISCHER ADDER
In this chapter, first, the traditional Ladner-Fischer Adder prefix circuit is analyzed.
Based on the simulated results observation, a new proposed efficient adder is intro-
duced. The Ladner-Fischer Adder has a tree-like structure that provides excellent
arithmetic operation performance and is adaptable for accelerating binary addition
[19]. Device development is made easier by research on binary operation charac-
teristics. As a result, their increased speed of microprocessor-based applications
such as DSP, telephone service, and mobile devices field programmable gate arrays
[FPGA’s] have become growing in popularity. The Ladner-Fischer Adder’s structure
consists of the following important three stages called the pre-processing stage, the
carry-generation stage and the post-processing stage.
Gray and black cells make up the Ladner-Fischer Adder. Two AND gates and one
OR gate contribute to each black cell. There are several inputs and one output in this
combinational circuit. There is only a single AND gate in every gray cell. P stands
for propagate, whereas there is only one AND gate in it. G stands for generate, and it
has one AND gate and one OR gate. The structure of Ladner-Fischer Adder is shown
in Figure 6.1.

FIGURE 6.1 Ladner-Fischer Adder structure.

FIGURE 6.2 RTL schematic view of 8bit Ladner-Fischer Adder.

96 Circuit Design for Modern Applications

FIGURE 6.3 Simulated result of 8-bit Ladner-Fischer Adder.

FIGURE 6.4 Technology schematic view of 8-bit Ladner-Fischer Adder.

A conventional 8-bit Ladner-Fischer Adder is designed using the Xilinx 14.7 ISE
design tool. The RTL schematic view of a conventional 8-bit Ladner-Fischer Adder
is shown in Figure 6.2 and the simulated output results are displayed in Figure 6.3.
In Figure 6.4, a technology schematic view of the 8-bit Ladner-Fischer Adder
is displayed. From the figure we can easily identify how many internal blocks are

FIGURE 6.5 8-bit Ladner-Fischer Adder power, delay, and area summary report.
Optimal Approaches for Enhancing Energy Efficiency In Circuits 97

FIGURE 6.6 Pass transistor logic – AND gate.

available in this traditional 8-bit Ladner-Fischer Adder design. These blocks con-
sume more area as well as more power. The overall design summary report is shown
in Figure 6.5.
The conventional Ladner-Fischer Adder has 18 LUTs in Spartan 3E FPGA imple-
mentation. So it has a maximum combinational path delay of 9.973 ns. Similarly it
consumes 53.11 mW power from its power source. It consumes 52.28 mW power as a
Static power and 0.83 mW power as a Dynamic power. Based on observations above
the efficient Ladner-Fischer Adder is designed using pass transistor logic.

6.4 PASS TRANSISTOR LOGIC

An alternative to complementary CMOS that is widely used is pass transistor logic,
which tries to reduce the total amount of transistors needed for constructing logic
by allowing the main inputs to drive gate terminals in addition to source/drain ter-
minals [20, 21].
Figure 6.6 shows the AND function’s implementation employing only NMOS
pass transistors. This gate replicates the input A to the output F and turns on the left
NMOS if the B input is high. The right NMOS pass transistor turns on and sends
a ‘0’ to the output F when B is low. This fulfils the AND gate truth table, which is
replicated in Figure 6.6 below for verification.

6.5 PROPOSED PTL-BASED LADNER-FISCHER ADDER

The suggested Ladner-Fischer Adder is adjustable for speeding up binary addition,
and its configuration resembles a tree for optimal arithmetic operation performance.
The main reason field programmable gate arrays, or FPGAs, have been so popu-
lar recently is that they have increased the speed of microprocessor-based appli-
cations, such as DSP, telecommunication, and mobile data communication. Device
development results from research on inspiration and the basic principles of binary
operations.
98 Circuit Design for Modern Applications

The transformation of a prefix circuit-level design into a gate-level implementa-

tion of the circuit is the next problem in the current dissertation. To compare the per-
formances of several mapped gate-level implementations, a computer-aided mapping
procedure is required because the number of possible prefix circuits grows exponen-
tially with the number of inputs. Gate sizing has a significant impact on the over-
all efficiency of the gate-level implementation, so the automated translation process
should be able to do it. Analyses of transistor area and delay should also be feasible
in the procedure to generate the best possible gate-level implementation design.
The highly efficient Ladner-Fischer Adder, which focuses on gate-level logic,
is an effective adder for high-performance arithmetic operations. Each gate in the
architecture contains a lower number of transistors than before. Therefore, it reduces
the delay, power and chip area used in this architecture. Conventionally, the Ladner-
Fischer Adder is created by employing CMOS transistor-based logic gates. In con-
trast, the proposed efficient Ladner-Fischer Adder is designed using a pass transistor
logic.
The efficient Ladner-Fischer Adder is designed based on the pass transistor logic.
PTL-based AND gates, OR gates, and Ex–OR gates are used in the architecture
shown in Figure 6.7. The VHDL code for the proposed PTL-based Ladner-Fischer
Adder is executed in Xilinx ISE 14.7 tool for the Spartan 3E FPGA implementations.

6.6 SIMULATION METHODOLOGY
In this chapter, Spartan 3E FPGA implementations are used to analyze the Ladner-
Fischer Prefix Adder in parallel with respect to specific performance metrics (Area,
Power, and Delay). Xilinx ISE 14.7 tool has been used to implement pass transis-
tor logic-based Ladner-Fischer Parallel Prefix Adder. Initially, the adder is designed
using Hardware Description Language based on its hierarchical structure. The
behavioral simulation is done using the Xilinx ISE 14.7 tool to verify its simulated
functional specifications. The design moves on to the next stage if the requirements
are satisfied; if not, behavioral modeling is repeated. The design constraints (output

FIGURE 6.7 8-bit Ladner-Fischer Adder logic diagram.

Optimal Approaches for Enhancing Energy Efficiency In Circuits 99

FIGURE 6.8 RTL schematic view of 8-bit PTL Ladner-Fischer Adder.

and input delay, clock period, etc.) for synthesis are then provided. Next, the post-
synthesis simulation is evaluated for functioning. If it succeeds in the test, then the
design moves on to the next phase, but if not, its behavioral modeling is examined
again for modification. The implementation stage comes next; at this phase, the tool
handles the placement, routing, and functional correctness checks. At last, we have
STA (Static Timing Analysis), Power, and Area from the implementation overview.

FIGURE 6.9 Simulated result of 8-bit PTL Ladner-Fischer Adder.

FIGURE 6.10 Technology schematic view of 8-bit PTL Ladner-Fischer Adder.

100 Circuit Design for Modern Applications

FIGURE 6.11 8-bit PTL Ladner-Fischer Adder power, delay, and area summary report.

FIGURE 6.12 Comparative analysis chart.

A proposed energy-efficient 8-bit PTL Ladner-Fischer Adder is designed using

the Xilinx 14.7 ISE design tool. The RTL schematic view of the 8-bit PTL Ladner-
Fischer Adder is shown in Figure 6.8 and the simulated output results are displayed
in Figure 6.9.
In Figure 6.10, the technology schematic view of 8-bit PTL Ladner-Fischer Adder
is displayed. Compared to conventional adders this proposed energy-efficient 8-bit
PTL Ladner-Fischer Adder has less number of internal blocks available in this
design. These blocks consume less area as well as less power. The overall design
summary report of the proposed adder is shown in Figure 6.11.
The proposed energy-efficient PTL-based 8-bit Ladner-Fischer Adder has 14
LUTs in Spartan 3E FPGA implementation. Therefore, it has a minimum combi-
national path delay of 7.930 ns. Similarly, it consumes 52.32 mW of power from its
power source. It consumes 52.27 mW power as a Static power and 0.05 mW power
as a Dynamic power.

6.7 COMPARATIVE ANALYSIS
The power, area & delay comparative analysis chart of conventional and proposed
Ladner-Fischer Adder is shown in Figure 6.12.
Optimal Approaches for Enhancing Energy Efficiency In Circuits 101

The above comparative analysis chart clearly shows proposed efficient pass tran-
sistor logic-based Ladner-Fischer Adder has better performance in terms of area,
delay and power consumption than the traditional Ladner-Fischer Adder.

6.8 CONCLUSION
The latest technique for creating an effective Ladner-Fischer Adder focuses on gate
levels in order to increase speed and reduce power usage. The fabrication of inte-
grated circuits has consistently demanded the best performance in terms of speed,
consumption of power, and area usage in every IC. This analysis chapter found that
the implementation of the pass transistor logic would decrease the propagation delay,
power consumption and the layout design area. Furthermore, when compared to a
basic logic gate schematic, the pass transistor logic design is able to reduce the com-
plexity of the circuit while using fewer transistors overall. Meanwhile, less time on
the propagation delay and reduce the adder’s power consumption.

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 7 Design and Analysis of
Optimized Area and
Energy-Efficient QCA-
based 8 × 8 Butterfly
Switching Network
Premananda B.S. and Ajith R.

INTRODUCTION
The demand for efficient and high-performance interconnected networks has been
substantially elevated as a result of the accelerated evolution of parallel computing.
Multi-stage interconnect networks (MINs) are essential for the optimal distribution
of data across computing nodes, thereby ensuring minimal latency and maximum
bandwidth. The demand for architectures that are more compact, energy-efficient,
and high-performance is increasing in tandem with the growth of computational
demands. Quantum-dot cellular automata (QCA) is a prospective technology that
aims to address these requirements by providing improved performance and reduced
energy dissipation through its distinctive computational paradigm.
This chapter, “Design and Analysis of Optimized Area and Energy-Efficient
QCA-based 8 × 8 Butterfly Switching Network”, explores the innovative design of a
QCA-based 8 × 8 butterfly switching network (BSN), a critical variant of MINs in
parallel computing systems. The 8 × 8 BSN is essential for the efficient implementa-
tion of internal bus architectures and the dynamic distribution of data, as it facilitates
the organization of system components into stages.
Our investigation commences with the fundamental 2 × 2 switching element (SE)
that is constructed using a five-input majority gate and configured with fixed logic
inputs. This SE is the fundamental component for the development of higher-order
switching networks, which are necessary for the realization of 4 × 4 and 8 × 8 BSNs.
Two distinct design approaches are the primary focus: the proposed-1 design, which
is an optimized version of the traditional BSN, and the proposed-2 design, which
utilizes gate polarization and a specific arrangement sequence of majority gates to
accomplish significant improvements.

DOI: 10.1201/9781003483052-7 103

104 Circuit Design for Modern Applications

The proposed-2 design is distinguished by a 26.2% reduction in cell count and

a 39.4% reduction in total energy dissipation, despite a minor increase in area
usage from 27.5 to 36.5%. The potential of QCA technology to revolutionize inter-
connect networks was demonstrated through the meticulous modeling of these
designs in QCADesigner and the comprehensive analysis of their performances in
QCADesigner-E.
This chapter serves as a testament to the rigorous research and collaborative
endeavors that are designed to expand the limits of parallel computation. We trust
that this work will offer valuable insights and motivation for future developments
in the field of QCA-based multi-stage interconnect networks. We are grateful to all
those who have supported and contributed to this research, and we eagerly anticipate
the ongoing exploration and development of this thrilling field.
To achieve feature size and enhanced processing power, the use of CMOS logic
has been employed. The current implementation addresses challenges related to
physical scaling, leakage current, and slower operation speeds [1]. Quantum-dot cel-
lular automata, is used to address these drawbacks. QCA promises an increased
speed of operation with minimum power dissipation in addition to enabling the
realization of systems at the nano-scale [2]. QCA provides a unique paradigm for
information transfer and computing. It has been demonstrated that a multiproces-
sor’s performance is influenced by the bus architecture as well as the CPU’s speed.
For connecting microprocessors and other resources, including memory, the major-
ity of contemporary systems adopted multi-stage interconnection networks [3]. The
building blocks of computer systems are communication-capable processor units
that enable multiprocessing. Effective and efficient communication between high-
capacity processors is essential in multiprocessor systems [4]. To achieve this, it is
crucial to design efficient MINs.
The development of MINs involves the use of switching elements, which are
linked in stages between the input and output stations [4, 5] based on specific topolo-
gies. In terms of point size, the fabrication of a nano-scale QCA cell can be achieved
through molecular fabrication using tone assembly techniques. The physical layout
and configuration of QCA cells present unique challenges. Although the ability to
cross QCA wires on a thin fabric chip offers an advantage over conventional CMOS
technology [6], it’s important to note that long lines of QCA may introduce delays
in signal movement and switching, potentially reducing the operational speed of cir-
cuits made with this technology [7]. Notably, research has demonstrated that rotated
cells do not interfere with normal cells. This lack of effect is because signals in the
QCA propagate through the Coulombic interaction of electrons rather than current
and voltage [8].
The work proposes an energy and area-effective single-layer 8 × 8 butterfly
switching network through the utilization of a modified majority voter (MMV) gate.
The 8 × 8 BSN was developed by utilizing the area-effective 2 × 2 switching ele-
ment and a 4 × 4 BSN. The proposed BSNs were implemented using the CAD tool
QCADesigner 2.0.3, while QCADesigner-E was used to calculate the energy dis-
sipation. Additionally, the BSN can be expanded to accommodate an N × N BSN.
Design and Analysis of Optimized Area and Energy-Efficient 105

Literature Review
Interconnection networks are an appealing and cost-effective way to make things in
a computer system communicate with each other. Due to advancements in similar
computing, these networks have become a useful choice for handling the increasing
demands of powerful computers [1]. MINs are used to connect different parts of a
computer with multiple processors or network switches [4, 5]. The MINs offer the
highest data transfer capacity to the components while ensuring minimal interrup-
tion to access memory modules. These networks are seen as a knowledgeable solu-
tion because they can be customized to let data move between different parts of the
computer in a flexible way [3].
Modern infrastructures widely embrace MINs to connect microprocessors and
other resources, such as memory. MINs find usage in networks on chips to connect
processors and memory for multiprocessor systems [4, 9]. MIN uses simple switches
with two input and two output parts that can be used to create multiple pathways.
These networks can have many paths in their design, or extra paths can be created
by altering the network’s configuration [5]. The switching complexity of a MIN can
be determined by considering several switching stages, the number of switches per
stage, and the size of the individual switching elements [7, 10]. Another aspect to
evaluate the cost of a MIN network is its link complexity, which depends on the
presence of intrastate links and the number of stages. Link complexity is significant
because it impacts the network’s ability to handle input and output, which can be a
limiting factor at each integration stage [4, 11].
QCA relies on encoding digital information based on the configuration of charges
within the cells. Processing capabilities are derived from the Coulombic interaction
among QCA cells [12]. QCA-based MINs for parallel computing are discussed in
[4–6]. QCA is one of the replacing technologies for CMOS, it uses less energy and
works faster, especially when building tiny circuits [13, 14]. This makes QCA tech-
nology very promising for the future. In the context of designing an 8 × 8 switching
network, a modified majority gate called M(x, y) is employed. This gate stands out
because it consists of two hard-coded cells placed along the select line to choose one
input at a time. It operates based on the configured cells [x, y] to switch the inputs at
the output, which makes it adaptable to various scenarios. This adaptability proves
crucial in complex switching networks where signal routing patterns can vary sig-
nificantly [15, 16].
The M(x, y) gate makes decisions based on majority input values and enhances net-
work efficiency by facilitating load balancing and optimizing signal paths. Butterfly
networks are normally used as interconnection networks in high-performance com-
puting structures and resemblant processing infrastructures. Butterfly networks may
be hired in packet switching structures, which assist with the inside powerful switch
of information packets among one-of-a-kind community nodes. BSNs may be hired
in large-scale information facilities to produce scalable and powerful communica-
tion infrastructures [10, 17]. QCA stands out as a highly promising and extensively
studied nanotechnology with the potential to advance the development of compact
digital circuits.
106 Circuit Design for Modern Applications

Tougaw et al. introduced the processing of digital data in QCA computing. Several
nanoscale QCA cells and a semiconductor QCA have been fabricated successfully.
They are capable of functioning at a temperature of 293K [12]. Researchers were
motivated by these findings to develop more complex architectures for the next gen-
eration, such as adders, multipliers, computation sense units, periodic-resemblance
recollections, microprocessors, and nanoscale networks [18]. Various studies con-
cluded that the efficiency of a multiprocessor relies not just on the CPU’s speed but
also on the configuration of the machine architecture [19–23].
The rest of the chapter is organized as follows: The basics of QCA and switching
networks are discussed in Section 7.3. Implementation of the proposed-1 and pro-
posed-2 SE and BSNs are discussed in Section 7.4. The obtained results are analyzed
in Section 7.5 along with conclusions derived in Section 7.6.

METHODOLOGY
QCA has emerged as a swiftly advancing nanotechnology, offering a well-suited
platform for designing high-performance, compact, and low-energy digital circuits.
The basic building block of QCA technology is the QCA cell, composed of four small
quantum dots arranged in a square lattice. Each cell has two independent electrons,
usually positioned diagonally due to Coulomb repulsion [1]. The cell polarizations
are P = –1 and P = +1, depending on the position of the electrons used to represent the
binary values “1” and “0”. Figures 7.1(a) and (b) represent two distinct polarized cell
types. Coplanar crossovers generally use 45° rotated cells. QCA cells can function as
wires, inverters, and logical devices like majority gates, AND, and OR [4]. In a series
arrangement of QCA cells, the polarization of the series is influenced by the input
[5]. This configuration represents a binary wire in QCA. Only five QCA units are
needed to complete the logic functions of our overall setup, as shown in Figure 7.2.
The crossovers in QCA can be either coplanar or multi-layer. A coplanar crossing
can be formed using either normal cells or rotated cells, referred to as a single-layer
crossing. In contrast, a multi-layer crossing involves a minimum of three layers [24].

FIGURE 7.1 (a) Distinct polarized QCA cell, (b) 45° rotated cells.
Design and Analysis of Optimized Area and Energy-Efficient 107

FIGURE 7.2 QCA-based three-input majority gate.

Although designing a multi-layer crossing requires less device area, executing it is

more challenging. Thus, a single-layer crossover appears to be more feasible in prac-
tical implementation [25].

QCA Clocking: In QCA, a four-phase clocking method is employed to prop-

agate the signal. This method comprises switch, hold, release, and relax
phases, each having a 90° phase difference from the others [26]. Cell polar-
ization occurs exclusively during the switching phase. In the hold phase, the
cell retains its polarity, while during the release phase, it loses polarization,
and in the relax phase, the cell remains unpolarized, as shown in Figure 7.3.
Modified Majority Gate: The existing majority voter gate can be used for
basic logical operations like AND, OR, and NOT, but it is not suitable for
switching operations [3]. To overcome this limitation, the concept of a modi-
fied majority voter gate was introduced [16]. This adapted gate incorporates
two extra cells configured as (x, y), each cell polarized as [1, –1], and a clock
“S” has been introduced within the device cell, as shown in Figure 7.4.

FIGURE 7.3 Four-phase clocking scheme.

108 Circuit Design for Modern Applications

FIGURE 7.4 QCA representation of MMV.

Switching Networks
2 × 2 Switching Element: The 2 × 2 switching element presented in [19], has
been designed using six majority gates, the design utilizes the basic logical
operations to switch the inputs at the output. To overcome multiple uses of
majority gates an SE presented in [1], introduced a concept of MMV, where
the design uses only two majority gates with configured cells (x, y) polar-
ized as [1, –1] as shown in Figure 7.4.
The 2 × 2 SE consists of three inputs S, X1, and X2, and the outputs Y1
and Y2, the system-level representation of 2 × 2 SE is shown in Figure 7.5.
Input is selected by controlling two fixed hardcode cells (x, y) and selec-
tion bit “S”. When S = 0, X1 will appear at Y1, and X2 will appear at Y2.
Similarly, when S = 1, X1 will appear at Y2, and X2 will appear at Y1.
4 × 4 Butterfly Switching Network: The 4 × 4 BSN consists of two stages
and four switches each stage consists of two switches. The high-level dia-
gram of 4 × 4 BSN is shown in Figure 7.6. Here the four inputs and four

FIGURE 7.5 System-level representation of 2 × 2 switching element.

Design and Analysis of Optimized Area and Energy-Efficient 109

FIGURE 7.6 High-level diagram of 4 × 4 butterfly switching network.

outputs are controlled by four select lines S11, S12, S21, and S22. If the select
lines S11 and S22 are hard-coded as 1, then input X1 will appear at output Y4.
Similarly, when S12 and S21 are hard-coded as 0, then input X3 will appear at
output Y2. Based on the required switching, the select bits are hard-coded
so that the input bits can be directed to any of the output pins.
8 × 8 Butterfly Switching Network: The 8 × 8 BSN was designed by extend-
ing the 4 × 4 BSN. The design consists of three stages and 12 switches,
each stage consists of four switches. A high-level representation of 8 × 8
BSN is shown in Figure 7.7. The output of 8 × 8 BSN was controlled by 12
select lines S11 to S43, by hard coding the required select bits the input bits
are switched to output pins.

IMPLEMENTATION OF BUTTERFLY SWITCHING NETWORKS

The implementation details of the proposed QCA-based designs (switching elements
and butterfly switching elements) are discussed in this section. The circuits are real-
ized in QCADesigner2.0.3 and QCADesigner-E used for energy analysis.

FIGURE 7.7 High-level diagram of 8 × 8 butterfly switching network.

110 Circuit Design for Modern Applications

FIGURE 7.8 QCA schematic of 2 × 2 switching element.

Proposed-1 Butterfly Switching Networks

Proposed-1 2 × 2 Switching Element: In proposed-1, the 2 × 2 SE was
designed to reduce cell count by 3, achieved by strategically placing the
select bit “S” inside the input signal X1, the design strategically prevents
the crossover between two signals to avoid cell-to-cell interaction, ensuring
a smooth passage of two signals. QCA representation of proposed-1 2 × 2
SE is shown in Figure 7.8.
Proposed-1 2 × 2 SE consists of 69 QCA cells employed, the key fea-
ture lies in the strategic incorporation of the “S” selection line within the
circuit configuration. This strategic placement optimizes the circuit’s per-
formance, enhancing its efficiency and functionality while simplifying its
physical layout. The proposed-1 reduces cell count and a crossover.
Proposed-1 4 × 4 Butterfly Switching Networks: The Proposed-1, 4 × 4
BSN uses four proposed-1 2 × 2 SE. The design was hard-coded with a
selection of bits S11 and S22 as “1”, and similarly S12 and S21 as “0” as shown
in Figure 7.9. Based on the required hard code in select bits the input will

FIGURE 7.9 QCA schematic of proposed-1 4 × 4 BSN.

Design and Analysis of Optimized Area and Energy-Efficient 111

FIGURE 7.10 QCA schematic of proposed-1 8 × 8 BSN.

be switched at the output, the 4 × 4 BSN introduces a new design structure

where all the select bits are placed inside the circuit configuration, which
results in simplifying the crossovers and overall device area. Although
the design only reduces the total cells by 11%, it will be more effective in
higher-order networks.
Proposed-1 8 × 8 Butterfly Switching Networks: The proposed-1 8 × 8 BSN
is achieved by extending the proposed 4 × 4 BSN as shown in Figure 7.10.
To understand the operation of 8 × 8 BSN a vector table was created to
analyze the switching between input and output. The vector table is used
to represent input signals (i.e., X1 to X8). In the proposed-1 8 × 8 BSN, the
cells and crossovers have been reduced by 77 and 14 respectively. Reducing
the cell count by 3 in a 2 × 2 SE has a noteworthy effect on an 8 × 8 BSN.
Hence the total area usage will be increased and cell area will be reduced
compared to reference 8 × 8 BSN. The detailed parameters of the QCA
schematics, including cell count, area usage, energy dissipation, and other
parameters will be discussed in Section 1.4.

Proposed-2 Butterfly Switching Networks

Proposed-2 2 × 2 Switching Element: The proposed-2 SE utilizes two MMV
gates arranged sequentially to minimize crossovers and enhance the uti-
lization of area. The reconfigured cells (x, y) in the first MMV have been
hard-coded as [–1, 1], whereas the second MMV reconfigured cells are
hard-coded as [1, –1] as shown in Figure 7.11. The two MMVs are arranged
one after the other with an alternating hard coding of reconfigured cells.
The polarization of the first and second MMV should be different to achieve
switching between input and output. By hard coding the polarization of
reconfigured cells (x, y), the switching operation can be accomplished.
The 2 × 2 SE output Y1 is obtained by adding an extra cell to achieve iso-
lation and to avoid signal transition between input X1 and output Y1, where
112 Circuit Design for Modern Applications

FIGURE 7.11 QCA schematic of proposed-2 2 × 2 SE.

this cell can be removed in a multi-stage switching network by proper use

of clocking and without any added delay.
Proposed-2 4 × 4 Butterfly Switching Network: The 4 × 4 BSN is made
up of two stages, each containing two switches. In total, there are four
switches. Figure 7.12 shows the QCA schematic of the proposed-2 4 × 4
BSN. By modifying the select control bits, it is possible to transmit any of
the input bits through a specific output pin. As discussed in the previous
section the 2 × 2 SE implies two possible switching operations (i.e., S = “0”
and “1”) out of which by selecting one switching operation at a time the 4
× 4 was proposed. However, the proposed 2 × 2 extends the proposed 4 × 4
BSN, with the first stage switches outputs being crossed over directly with-
out the need for an additional cell, and the outputs Y1 and Y3 being added
with an additional cell in the second stage to make a crossover to reduce the
cell-to-cell interaction.

FIGURE 7.12 QCA schematic of proposed-2 4 × 4 BSN.

Design and Analysis of Optimized Area and Energy-Efficient 113

FIGURE 7.13 QCA schematic of proposed-2 8 × 8 BSN.

Proposed-2 8 × 8 Butterfly Switching Network: The proposed-2 8 × 8 BSN

was designed by extending the proposed-2 4 × 4 BSN, which consists of
three stages and 12 switches, each stage consisting of four switches (S11 –
S43). Figure 7.13 shows the QCA schematic of the proposed-2 8 × 8 BSN.
The proposed-2 8 × 8 BSN switches are hard-coded based on the required
switching between input and output. However, the proposed-2 4 × 4 extends
the proposed-2 8 × 8 BSN, the first and second stage switches output being
crossed over directly without an additional cell to avoid signal transition,
this can be achieved by logical clocking. The QCA parameters, such as
cell area, area usage, cost function analysis, and energy dissipation, will be
discussed in Section 7.5.

RESULTS AND DISCUSSION

The simulation and performance analysis were carried out using CAD tools
QCADesigner2.0.3 and QCADesigner-E. In QCADesigner two simulation engine
options are provided namely Coherence Vector and Bistable Approximation. The
Bistable Approximation offers flexibility in input provision. The default simula-
tion engine is a Bistable Approximation [27]. In the vector table simulation mode,
users can define their input vectors. With the exhaustive simulation mode, the circuit
undergoes simulation with every conceivable combination of input vectors. However,
in the proposed 8 × 8 BSNs vector table simulation is used to analyze the output.
Figure 7.14 illustrates the simulation results of the 2 × 2 switching element,
wherein the first valid output will appear after an initial delay of 1.25 clock cycles
(CC). The delay is determined based on the clock zones used. Each complete clock
zone corresponds to a delay of one CC.
Cost becomes a key factor in assessing the design merit of semiconductor QCA.
This evaluation takes into account three aspects: latency (T), number of crossovers
(C), and number of majority gates (M), all included in the cost function [1].
114 Circuit Design for Modern Applications

FIGURE 7.14 Simulation result of proposed 2 × 2 SE.

QCA  cost    M ²  C²   T ² (7.1)

For instance, in a 2 × 2 SE, with two majority gates, two crossovers, and a latency
of 1.25 CC, the QCA cost is calculated as 12.5. The cost function is analyzed by the
equation presented in [1]. Taking into account the complexity of physical implemen-
tation, the expense associated with multi-layer crossing is three times greater than
that of coplanar crossing. Table 7.1 compares QCA parameters, such as cell count,
cell area, total area, latency, area usage, and cost analysis, with the switching ele-
ment presented in [1].
From Table 7.1, it can be analyzed that the proposed-1 2 × 2 SE requires a total of
69 cells and has a device area of 0.06 μm². Compared to SE presented in [1], the total
number of crossovers is reduced to 2, and area usage increases to 34% from 28.75%.
Area usage refers to the efficiency with which cells are organized in the device layout
(higher the usage is better).
Proposed-2 2 × 2 SE signifies a notable improvement over proposed-1, present-
ing a novel architecture that reduces the cell count by 21%. The design introduces a

TABLE 7.1
QCA Parameter Analysis of Various Switching Elements
2 × 2 Switching Elements
QCA
Parameters [1] Proposed-1 Proposed-2
Cell count 72 69 55
Total area (μm²) 0.08 0.06 0.04
Cell area (μm²) 0.023 0.022 0.017
Latency (CC) 1.25 1.25 1.25
Area usage (%) 28.75 34 42.5
QCA cost 20.31 12.5 12.5
Design and Analysis of Optimized Area and Energy-Efficient 115

unique structure, reducing the device area by 50%, and increasing area usage to 43%.
The proposed-2 design uses 55 QCA cells, with a sequential arrangement of MMVs
and no crossover between inputs. Additionally, a separation of two cells between
connecting wires is implemented to avoid cell-to-cell interaction.
The sequential arrangement in proposed-2 leads to a change in the hard code of
the reconfigured cells in MMV. If the polarization of reconfigured cells in MMV
didn’t change, having the same polarization in the reconfigured cells of MMV would
block the switching process at the outputs. To match the delay in both outputs, an
extra cell is added at the first output (Y1). Logical clocking maintains consistent
circuit delay, with Y1 appearing first. Table 7.1 provides a thorough analysis of the
cost functions, offering a comparative study between the proposed SE and reference
designs. In contrast to the configuration outlined in [1], the proposed SE showcases a
notable 39% decrease in QCA cost. Additionally, when compared with the most opti-
mal current SE design, the proposed SE displays significant enhancements, achiev-
ing a 43% reduction in area usage.
Table 7.2 presents a summary of the data that highlights the significant enhance-
ment of the proposed-1 4 × 4 BSN. Compared to reference [1], it has 310 cells with
a total size of 0.3 μm², there are nine fewer crossovers, and the area utilization has
increased by 33.3%. The proposed-2 4 × 4 BSN is an improved version of BSN
presented in [1] as well as proposed-1, the cell count is reduced by 20% over 48%
total device area has been reduced, and 42% of the device area has been utilized. No
additional cells are added to achieve isolation at the first stage outputs, this can be
achieved by clocking between two wire crossings. The first valid output will appear
after a delay of 3.25 CC. Table 7.2 also provides a notable improvement of 8 × 8 BSN
over the reference [1] and proposed-1. The simulation results of the 8 × 8 BSN are
presented in Figure 7.15.
Inputs for simulating the 8 × 8 BSN circuit were applied by creating the vector
table. A vector can be created by the add option presented in the simulation type
setup [27]. The design requires 860 cells and a device area of 0.76 μm². Since the
design is a single-layer and clock-based coplanar crossing, it produces a delay of 5.25
CC to generate the first valid output.

TABLE 7.2
QCA Parameter Analysis of Various Butterfly Switching Networks
4 × 4 BSN 8 × 8 BSN
QCA
Parameters [1] Proposed-1 Proposed-2 [1] Proposed-1 Proposed-2
Cell count 349 310 245 1164 1086 860
Total area (μm²) 0.36 0.30 0.19 1.37 1.17 0.76
Cell area (μm²) 0.11 0.10 0.079 0.377 0.351 0.278
Latency (CC) 3.25 3.25 3.25 5.25 5.25 5.25
Area usage (%) 30.5 33.3 41.5 27.51 30 36.65
QCA cost 2462 1532 1532 79,380 51,597 47,738
116 Circuit Design for Modern Applications

FIGURE 7.15 Simulation result of proposed 8 × 8 BSN.

The 2 × 2 SE serves as a basic building block for the 8 × 8 BSN, and the design
framework of the 4 × 4 BSN is employed in the construction of the 8 × 8 BSN. The
design utilizes area efficiently by 36.6% and over 30% of crossovers are reduced.
The overall cell area required for the proposed design is 0.27 μm², whereas the BSN
in [1] and proposed-1 uses 0.37, and 0.35 μm² respectively.
Energy dissipation is a loss of electrical energy as it flows through the various
components of the circuit, this energy is lost in the form of heat. Optimizing the
design can help reduce energy dissipation. Table 7.3 presents the total and aver-
age energy dissipation for the proposed BSNs. The proposed architecture is recon-
structed in the CAD tool QCADesigner-E to analyze energy dissipation, considering
the loss of energy through its conversion into heat. The proposed designs provide
more than 40% lower generation of total and average energy dissipation.
Total energy dissipation represents the overall energy loss converted to heat
within the circuit, while average energy loss per unit indicates the mean energy dis-
sipation. These metrics are crucial in evaluating the performance of the designs. The
proposed-1 and proposed-2 8 x 8 BSNs generate lower energy dissipation of 11%,
and 40% compared to BSN presented in [1].

CONCLUSION AND FUTURE SCOPE

The chapter presents the implementation of a single-layer 2 × 2 switching element and
8 × 8 butterfly switching network for parallel computing. This network helps orga-
nize system components into different stages. The realization and simulation results
of this proposed work are obtained using QCADesigner2.0.3. The design parameters
are verified using QCADesigner-E. The proposed-1 design is an optimized version
of the reference 8 × 8 BSN architecture. The proposed-1 design reduced the cell
count by 78 cells and achieved a 6.9% decrease in the cell area, a 10.6% reduction
in average energy dissipation, and a 35% reduction in QCA cost compared to the
reference architecture. Whereas the proposed-2 design introduces new architectural
novelty which results in a reduction of cell count by 304, a 26.3% reduction in the
TABLE 7.3
Energy Analysis of 2 × 2 SE, 4 × 4, and 8 × 8 Butterfly Switching Networks
2 × 2 SE 4 × 4 BSN 8 × 8 BSN
QCA
Parameters [1] Proposed-1 Proposed-2 [1] Proposed-1 Proposed-2 [1] Proposed-1 Proposed-2
Total energy dissipated (meV) 25.1 18.8 14.9 97.6 75.1 48.3 259 232 157
Average energy dissipated (meV) 2.28 1.71 1.36 8.87 6.83 4.39 23.6 21.1 14.3
Design and Analysis of Optimized Area and Energy-Efficient
117
118 Circuit Design for Modern Applications

cell area, and over 39.5% reduction in both QCA cost and average energy dissipation
compared to the reference BSN. The proposed 4 × 4 BSN can be used as a building
block for higher-order BSNs, and the cost function holds well for N × N BSN. These
proposed designs highlight significant improvements in area usage, cell count, and
device area while reducing energy dissipation compared to previous designs. The
design can be expanded to higher-order N × N BSN configurations and holds the
potential to restructure switching networks by offering ultra-secure communication.

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 8 Advanced Operational
Amplifier with Emerging
CMOS Technology
Shiromani Balmukund Rahi,
Young Suh Song, and Jyoti Kandpal

8.1 INTRODUCTION TO OPERATIONAL AMPLIFIERS:

DEFINITION AND APPLICATIONS
Operational amplifiers (often abbreviated as op-amp or OPAMP) have been a major
component in designing many electronic circuits. This is because op-amp has very
crucial amplifying characteristics, and therefore it could be widely utilized for signal
processing and various applications [1–3]. Op-amps are highly versatile electronic
devices that serve as essential and critical components, especially in the design of
analog and mixed-signal circuits [4]. At their essence, op-amps function as voltage
(V) amplifiers, possessing high gain (Av) and the ability to handle differential inputs.
Typically, considering the advancement in the packaging and semiconductor pro-
cess, they are integrated into circuits as compact integrated circuits (ICs), featuring
various terminals such as inverting and non-inverting inputs, an output, and connec-
tions for power supply.
The primary purpose of an operational amplifier is to magnify the voltage dis-
parity between its two input terminals, referred to as the differential voltage. This
amplified voltage is subsequently emitted through the amplifier’s output terminal.
Op-amps are distinguished by their high input impedance, low output impedance,
and broad bandwidth, rendering them suitable for an extensive array of applications.
Operational amplifiers hold pivotal roles within electronic circuits owing to their
adaptability and extensive applicability. They serve as foundational elements for
various analog signal-processing tasks, encompassing amplification, filtering, and
signal conditioning, as well as mathematical operations like addition, subtraction,
integration, and differentiation [5].
In numerous electronic systems, op-amps facilitate the interface between analog
and digital realms by converting signals between different forms [6]. They are integral
constituents in a diverse array of applications including audio amplifiers, instrumen-
tation amplifiers, active filters, voltage regulators, oscillators, and control systems.
Furthermore, op-amps find widespread usage in sensor interfaces, data acquisition
systems, medical devices, communication systems, and power electronics.

120 DOI: 10.1201/9781003483052-8

Advanced Operational Amplifier with Emerging CMOS Technology 121

The significance of operational amplifiers in electronic circuits lies in their capa-

bility to deliver high-gain, high-precision signal-processing functionalities within
a compact and cost-effective framework [7, 8]. Their versatility, dependability, and
ease of incorporation establish them as indispensable tools for engineers and design-
ers across various domains spanning from consumer electronics to aerospace and
defense industries.

8.2 HISTORICAL EVOLUTION OF OPERATIONAL AMPLIFIERS

8.2.1 Early Developments and Analog Computing
The op-amp has about 100 years of history, and it has undergone various techno-
logical developments and advancements. The history of operational amplifiers traces
back to the early 20th century, with notable developments in the field of analog
computing. In the 1930s and 1940s, pioneering work by engineers such as Karl D.
Swartzel Jr., George A. Philbrick, and Otto H. Schmitt laid the groundwork for the
concept of operational amplifiers [9–13]. These early amplifiers were primarily used
in analog computers, which were prevalent before the advent of digital computers.
Analog computers relied on continuous physical quantities, such as voltage
and current, to perform mathematical calculations and solve complex problems.
Operational amplifiers played a crucial role in analog computing systems, serving
as building blocks for mathematical operations and signal-processing tasks. They
were employed in various applications, including differential analyzers, electronic
integrators, and differential amplifiers, to simulate real-world phenomena and solve
differential equations.
During World War II, operational amplifiers found extensive use in military
applications, such as fire control systems, radar systems, and electronic warfare
equipment. Their ability to accurately process analog signals made them indispens-
able for tasks such as signal conditioning, filtering, and amplification in these critical
defense applications.
The early developments in operational amplifiers and their integration into analog
computing systems paved the way for further advancements in electronic engineer-
ing and paved the way for the widespread adoption of operational amplifiers in a
myriad of applications beyond analog computing.

8.2.2 Integrated Circuit Era and Mass Production

In addition, as time passed, the advancement of operational amplifiers finally reached
a pivotal juncture with the emergence of the IC era. During the late 1960s and early
1970s, progress in semiconductor technology paved the way for the creation of oper-
ational amplifier ICs, fundamentally transforming the electronics landscape [9–13].
Integrated circuit technology facilitated the consolidation of various electronic
components, encompassing transistors, resistors, and capacitors, onto a singular
semiconductor substrate. This amalgamation and downsizing of components facili-
tated the development of exceedingly compact and cost-effective operational ampli-
fier chips.
122 Circuit Design for Modern Applications

The mass production of operational amplifier ICs democratized access to these

devices, rendering them readily available and economically viable for engineers and
designers. With standardized IC packages and pinouts, circuit design and implemen-
tation became more streamlined, catalyzing the widespread adoption of operational
amplifiers across diverse applications.
The accessibility of operational amplifier ICs sparked innovation across multiple
domains, including audio amplification, instrumentation, control systems, and tele-
communications. These versatile devices emerged as indispensable components in
electronic circuits, offering superior performance, reliability, and user-friendliness.
Furthermore, the integration of operational amplifiers into ICs facilitated the devel-
opment of specialized variants tailored to specific applications, such as low-noise
amplifiers, high-speed amplifiers, and precision amplifiers. This diversification
broadened the scope of applications for operational amplifiers and contributed to
their ubiquitous utilization across industries.
In essence, the integrated circuit era and the mass production of operational ampli-
fier ICs represented a monumental milestone in the annals of electronic engineering.
This epoch democratized access to advanced analog signal-processing capabilities,
fostering innovation in a myriad of electronic devices and systems.

8.3 FUNDAMENTALS OF CMOS TECHNOLOGY

8.3.1 Introduction to CMOS
Not only in the semiconductor industry but also in several Internet of Things indus-
tries, CMOS (complementary metal-oxide-semiconductor) technology is a key tech-
nique used in the manufacturing of electronic devices [14]. It involves the utilization
of pairs of transistors known as MOSFETs (metal-oxide-semiconductor field-effect
transistors), with one transistor being of the p-type and the other of the n-type.
These complementary pairs work together to perform various digital operations
efficiently [14].
The CMOS technology’s unique feature lies in its ability to minimize power
consumption, making it highly suitable for a wide range of applications [15]. This
technology is extensively employed in digital integrated circuits, microprocessors,
memory chips, and sensor devices, owing to its efficiency and reliability. CMOS
technology has become indispensable in modern electronics, driving advancements
in various fields and enabling the development of innovative electronic devices and
systems.
Nowadays, CMOS technology is going to move from a Fin Field-Effect Transistor
(FinFET) to Gate-All-Around (GAA) MOSFET and Nanosheet (NS) FET, consid-
ering the fact that the improved electrical characteristics could be achieved by the
channel surrounding structure [16–18]. Even though there have been a couple of
fabrication challenges for fabricating GAA MOSFET and NSFET (especially for
“yield rate” and “reliability”), the advancement of EUV lithography and deposition
techniques made it possible to intelligently fabricate GAA MOSFET and NSFET
[19–23].
Advanced Operational Amplifier with Emerging CMOS Technology 123

8.3.2 Fabrication Process and Device Structure

The development of CMOS technology has been achieved by the continuous
advancement of fabrication equipment. The manufacturing process of CMOS tech-
nology comprises numerous intricate stages aimed at constructing the structure of
electronic devices. Initially, it commences with the preparation of a silicon substrate,
serving as the base for assembling the components of the CMOS device.
Following the preparation of the silicon substrate, multiple layers of materials
are applied to it utilizing methods like chemical vapor deposition (CVD) or physical
vapor deposition (PVD). These layers encompass various elements such as the gate
oxide layer, gate polysilicon layer, and metal interconnect layers, among others [24].
The device structure of a CMOS transistor consists of several key components.
These include the source and drain regions, which are formed by selectively doping
the silicon substrate with specific impurities. The gate of the transistor is separated
from the silicon substrate by a thin layer of insulating material, typically silicon
dioxide (SiO2), which serves as the gate oxide [14, 15, 17, 18, 20]. The gate electrode,
made of polysilicon, is used to control the flow of current between the source and
drain regions by applying a voltage.
In a complementary pair of CMOS transistors, one transistor is of the p-type
(PMOS) and the other is of the n-type (NMOS). When a voltage is applied to the gate
of the PMOS transistor, it turns off, while the NMOS transistor turns on, and vice
versa. This complementary behavior allows for efficient switching between logic
states (0 and 1) and enables the implementation of complex digital circuits with mini-
mal power consumption.
Overall, the fabrication process and device structure of CMOS technology are
crucial aspects of semiconductor manufacturing, enabling the creation of high-per-
formance electronic devices used in various applications across industries.

8.4 ADVANCED FEATURES AND CHARACTERISTICS

OF OPERATIONAL AMPLIFIERS
The simplified figure and detailed figure of operational amplifiers are shown in
Figure 8.1. Op-amps play a vital role in electronic circuits due to their adaptability
and broad range of uses. Besides their fundamental functions, contemporary op-
amps boast advanced attributes that enhance their effectiveness and versatility in
diverse electronic systems.
An outstanding advanced capability of operational amplifiers is their high-speed
performance. Advanced op-amp models operate efficiently at high frequencies,
enabling swift and accurate signal processing. This attribute proves particularly
advantageous in applications necessitating rapid signal handling, such as communi-
cation systems, data acquisition, and high-speed instrumentation.
Another crucial trait of modern operational amplifiers is their ability to mini-
mize noise. Op-amps with low-noise characteristics can amplify minute signals with
minimal additional noise, making them suitable for delicate applications like audio
amplification, medical instrumentation, and sensor signal conditioning. Sophisticated
124 Circuit Design for Modern Applications

FIGURE 8.1 The structure and operation principle of op-amp. VCC and VDD mean power
supply (usually, positive voltage). On the other hand, VEE and VSS mean additional power sup-
ply (usually, negative voltage).

noise reduction methods and top-tier manufacturing processes contribute to achiev-

ing low noise levels in these op-amps.
The important traits for designing op-amp are summarized in Table 8.1.
Moreover, many contemporary operational amplifiers boast rail-to-rail input and
output capabilities. This functionality allows the op-amp to accept input signals that
extend to the power supply rails, and the output signal can approach the supply volt-
ages closely. Rail-to-rail operation maximizes the utilization of the available volt-
age range, rendering these op-amps suitable for applications where input and output
signals reach the power supply limits.
Furthermore, advanced operational amplifiers often incorporate precision spec-
ifications such as high-gain accuracy, low offset voltage, and minimal drift over
temperature variations. These specifications ensure that the op-amp maintains accu-
rate and stable performance across a wide range of operating conditions, making
them ideal for precision instrumentation, sensor interfaces, and control systems.
Additionally, contemporary operational amplifiers may include built-in protection
circuitry, programmable gain settings, and advanced packaging options to cater to
diverse application requirements and simplify circuit design.

8.5 INTEGRATION OF EMERGING CMOS

TECHNOLOGY IN OPERATIONAL AMPLIFIERS
8.5.1 Benefits and Advantages of CMOS Integration
The integration of emerging CMOS technology in operational amplifiers (op-amps)
offers numerous benefits and advantages. One significant advantage is the scalability
and miniaturization afforded by CMOS technology. By leveraging CMOS fabrica-
tion processes, op-amp designers can create smaller, more compact devices with
increased functionality and performance. This miniaturization enables the integra-
tion of multiple op-amps on a single chip, reducing overall system footprint and cost.
Additionally, CMOS integration provides enhanced flexibility and versatility in
op-amp design. CMOS technology allows for the integration of various passive and
Advanced Operational Amplifier with Emerging CMOS Technology 125

TABLE 8.1
Important Characteristics for Designing OP-AMP
Type of Description
characteristic
Gain (AV) Gain explains how much an op-amp amplifies the output signal compared to the
input signal. Op-amps are engineered to provide high gain, ensuring that even
small input signals are amplified to the desired levels. Typically specified in
decibels (dB) or as a ratio, gain is pivotal in determining an op-amp’s overall
signal amplification capability.
Bandwidth (BW) Bandwidth denotes the frequency range over which an op-amp can accurately
amplify signals without distortion. It is crucial for applications requiring precise
signal processing across various frequencies. Op-amps with wider bandwidths
can handle higher frequency signals, making them suitable for tasks like audio
amplification, data transmission, and high-speed signal processing.
Linearity Linearity reflects an op-amp’s capacity to produce an output signal directly
proportional to the input signal. A linear response ensures accurate signal
amplification and faithful reproduction of the input signal waveform. Op-amps
with superior linearity characteristics minimize distortion, providing precise
signal amplification ideal for applications like audio equipment, instrumentation,
and communication systems.
Input and output Input and output impedance are essential parameters that dictate an op-amp’s
impedance interaction with external components and circuits. Input impedance refers to the
resistance presented by an op-amp’s input terminals to the incoming signal. High
input impedance minimizes the loading of the input signal source, preserving
signal integrity. Output impedance, on the other hand, pertains to the resistance
observed by an op-amp’s output terminals. Low output impedance facilitates
efficient driving of external loads, minimizing signal loss or distortion. Proper
management of input and output impedance is crucial for designing op-amp
circuits that perform optimally across various applications.
Noise Noise performance and power consumption are key considerations in op-amp
performance design and selection. Noise refers to unwanted electrical signals that can degrade
and power output signal quality. Op-amps with low noise performance mitigate the impact of
consumption noise, ensuring clean and accurate signal amplification. Power consumption,
especially in battery-powered or low-power applications, is another critical factor.
Op-amps with low power consumption help conserve energy and extend the
battery life of electronic devices. Achieving a balance between noise performance
and power consumption is vital for optimal op-amp circuit performance.

active components on the same chip, enabling the implementation of complex signal-
processing functions within the op-amp itself. This integration of passive compo-
nents such as resistors and capacitors, along with active components like transistors,
enables the realization of highly integrated op-amp solutions with improved perfor-
mance and reduced external component count.
126 Circuit Design for Modern Applications

Moreover, CMOS integration offers improved power efficiency and lower power
consumption compared to traditional op-amp technologies. CMOS transistors have
inherently low power consumption characteristics, making them well-suited for
battery-powered and low power applications. By leveraging CMOS technology,
designers can develop energy-efficient op-amp solutions that prolong battery life and
reduce overall system power consumption.
Furthermore, CMOS integration enables the implementation of advanced features
and functionalities in op-amps. With the ability to integrate digital control circuitry
alongside analog signal-processing functions, CMOS op-amps can offer features such
as programmability, adaptive biasing, and built-in self-calibration. These advanced
features enhance the flexibility and performance of op-amp circuits, allowing for
more sophisticated signal-processing tasks and adaptive system behavior.
Overall, the integration of emerging CMOS technology in operational amplifiers
provides numerous benefits, including scalability, flexibility, power efficiency, and
advanced functionality. These advantages make CMOS-integrated op-amps well-
suited for a wide range of applications in fields such as consumer electronics, tele-
communications, medical devices, and industrial automation.
Recently, various topologies for op-amps have been developed. Each has its own
advantages and disadvantages [25–27]. The detailed explanation can be found in
Table 8.2. In addition, various parameters utilized for recent op-amp design have
been explained in Table 8.3 and Table 8.4 [28, 29].

8.5.2 Challenges and Limitations

While CMOS integration in operational amplifiers brings numerous advantages,
there are also several hurdles and constraints that need to be addressed. One such
challenge is striking the right balance between performance and integration density.
With increased integration, there may be compromises in key performance metrics
like gain, bandwidth, and linearity. Designers must carefully manage this trade-off
to ensure that integrated op-amps meet specific performance requirements.
Furthermore, integrating passive components such as resistors and capacitors
alongside active components presents compatibility and performance challenges [30,
31]. These passive components may exhibit performance variations due to process
discrepancies, temperature changes, and aging effects. To counter these variations
and ensure consistent performance, designers need to implement compensation tech-
niques and calibration procedures.
Additionally, CMOS integration introduces issues related to signal integrity,
noise, and interference. The proximity of active and passive components on the same
chip can lead to crosstalk, parasitic capacitance, and electromagnetic interference,
which can degrade overall performance. Designers must employ various strategies
like layout optimization, shielding, and noise filtering to mitigate these effects and
uphold signal integrity in integrated op-amp designs.
Moreover, the adoption of emerging CMOS technologies like FinFET and GAA
MOSFET poses additional challenges in terms of complexity, cost, and readiness.
While these advanced technologies offer potential performance enhancements,
Advanced Operational Amplifier with Emerging CMOS Technology 127

TABLE 8.2
Different Op-Amps with Different Current Mirrors [25–27]

Name of the Circuit Configuration

Design Advantages Disadvantages (circuit topologies)
Cascode High input resistance. High input and
Current output voltage
Mirror [25]

Wilson Significant increases in Higher input and

Current output resistance output voltage
Mirror [25] which is attained by
adding only one MOS
transistor to simple
current mirror.

Modified Symmetrical structure Higher input and

Wilson leading to high output voltages
Current dynamic range and less high input
Mirror [25] current transfer error. resistance

Flipped Input-output voltages Poor dynamic

voltage are low, with low input range and poor
follower- impedance and output current transfer
based current impedance high. error
mirror [26]

Self-cascode Low input and output Low dynamic

current voltage, high range
mirror for bandwidth.
low voltage
application
[27]

Floating gate Low input, and output Poor dynamic

MOS-based voltage, low power range
Current consumption.
Mirror
[27]
128 Circuit Design for Modern Applications

TABLE 8.3
Parameters for Different Op-Amplifier Topologies [28, 29]
Parameters Inverter-Based Bulk Driven
Pro Ultra-Low VDD Compatibility Low VDD compatibility Wide CM
Good GBW Low Complexity
Contra Narrow CM range Low GBW
Dependence on VDD of AC characteristic
FOM 1.6 1.03
Applications Wireless application and Biomedical Application and
Energy harvesting Energy Harvesting
Architecture
(Circuit
Topologies)

Future Direction The technology scaling favors digital The bulk-driven amplifier is
for Working circuits, by improving speed and well-suited for low voltage and low
reducing dynamic power dissipation. power, too, although they require a
Moreover, the voltage supply is voltage supply larger than the
constantly reduced, making the analog inverter-based topology.
design challenging.

they require significant investments in research, development, and manufacturing

infrastructure [14, 15, 19, 20]. Designers must carefully weigh the benefits against
the costs to determine the viability of integrating emerging CMOS technologies in
operational amplifiers.

8.6 RECENT APPLICATIONS AND IMPACT ACROSS INDUSTRIES

8.6.1 Audio Amplification and Signal Processing
Operational amplifiers (op-amps) serve as essential components within a myriad of
signal-processing circuits utilized in audio equipment, encompassing functionalities
like equalization, filtering, and tone control. These circuits leverage op-amps to
execute tasks such as adjusting frequency responses, blending signals, and manag-
ing dynamic ranges, thereby affording users the ability to customize audio outputs
TABLE 8.4
Another Parameters for Different Op-Amplifier Topologies [28, 29]
Hybrid Mode
Parameters Rail to Rail (Mixed mode) NMOS only
Pro (advantage) Low VDD compatibility Wide CM and Good Driving Capability Ultra-Low VDD Compatibility
High Gain Good PM
Contra Higher Complexity Gain of this design is lower than prior arts Poor AC characteristic, Complexity
(disadvantage)
FOM 1.34 1.2 0.2
Applications Energy harvesting, Voltage Regulator, Flexible Organic Tech
Internet-of-Things (IoT) Sensor Active Filter
Architecture
(Circuit
topologies)

Future direction The rail-to-rail topologies can reach a Voltage regulator is another fundamental The NMOS only amplifier is attractive because in
for Working high voltage gain and present a very analog building block, based on an error recent technologies NMOS native transistors (i.e.,
wide common mode input range, too. amplifier and a power transistor which with extremely low threshold voltage) are available
Advanced Operational Amplifier with Emerging CMOS Technology

Moreover, they can reach a trade-off drives the loads. In low voltage and and therefore an architecture based only on NMOS
between bandwidth and power low-power applications, it presents the transistors allows for a very low voltage supply.
consumption, depending on the major challenge of achieving a good
application. dynamic response with a low quiescent
current.
129
130 Circuit Design for Modern Applications

according to their preferences. Op-amps featuring expansive bandwidth and mini-

mal noise characteristics guarantee precise signal processing, minimizing distor-
tions and unwanted noise artifacts, thus upholding audio fidelity.
The influence of op-amps in audio applications resonates throughout various sec-
tors, spanning consumer electronics, professional audio, automotive audio systems,
and telecommunications. Within consumer electronics, op-amps find their place in
audio amplifiers, headphones, smartphones, and home theater systems, enriching
user experiences with immersive soundscapes. In professional audio settings, op-
amps are indispensable in recording studios, concert halls, and broadcasting facili-
ties, facilitating the production and reproduction of high-fidelity audio. Automotive
audio systems leverage op-amps to deliver superior sound quality within vehicles,
elevating the auditory experience for passengers. Furthermore, op-amps play a piv-
otal role in telecommunications equipment like telephones, intercoms, and audio-
conferencing devices, ensuring crystal-clear and dependable voice communications.

8.6.2 Sensor Interfaces and Measurement Circuits

Operational amplifiers stand as vital elements within sensor interfaces and measure-
ment circuits, playing a crucial role in the precise and dependable acquisition of data
from sensors across a diverse array of applications. Within sensor interfaces, op-
amps are tasked with conditioning and amplifying faint electrical signals produced
by sensors in response to physical or environmental stimuli. Through the provision
of high-gain and low-noise amplification, op-amps ensure the faithful capture and
processing of sensor signals, thereby enabling meticulous measurement and analysis.
Furthermore, op-amps find utility in an assortment of measurement circuits
encompassing voltage and current measurement, temperature sensing, pressure sens-
ing, and strain gauges. These circuits harness op-amps to transform sensor signals
into quantifiable electrical magnitudes that can be scrutinized and deciphered by
electronic instrumentation. Op-amps boasting high input impedance and low off-
set voltage guarantee minimal signal distortion and precise measurement outcomes,
even within demanding measurement contexts.
The influence of op-amps within sensor interfaces and measurement circuits
reverberates across a spectrum of industries, spanning industrial automation,
environmental monitoring, biomedical instrumentation, and scientific inquiry. In
industrial automation, op-amps feature prominently within sensors and transduc-
ers, overseeing parameters like temperature, pressure, flow rate, and level within
manufacturing processes to ensure optimal performance and product quality. In
environmental monitoring, op-amps facilitate the measurement of variables such as
humidity, air quality, and pollution levels, contributing to environmental steward-
ship and oversight. Within biomedical instrumentation, op-amps are indispensable
in medical devices like patient monitors, electrocardiographs, and blood pressure
monitors, facilitating precise measurement of physiological indicators for diagnos-
tic and therapeutic purposes. Additionally, op-amps find application in scientific
research contexts such as laboratory instruments, data acquisition systems, and
Advanced Operational Amplifier with Emerging CMOS Technology 131

testing apparatuses, enabling meticulous measurement and analysis across diverse

realms of inquiry.

8.6.3 Communication Systems and Data Acquisition

Operational amplifiers assume a pivotal role in communication systems and data
acquisition endeavors, fostering the conveyance, reception, and manipulation of elec-
trical signals with utmost fidelity and dependability. Within communication systems,
op-amps feature across diverse signal-processing stages encompassing amplifica-
tion, filtration, modulation, demodulation, and equalization. Op-amps distinguished
by high-gain, expansive bandwidth, and minimal distortion characteristics ensure
precise signal amplification and manipulation, thereby facilitating lucid and stead-
fast communication traversing varied channels and mediums.
Furthermore, op-amps stand as indispensable constituents within data acquisi-
tion systems, tasked with the aggregation, conditioning, and amplification of feeble
electrical signals originating from sensors, instruments, and akin sources. Within
the realm of data acquisition, op-amps serve to refine and amplify sensor signals for
their digitization and processing via analog-to-digital converters (ADCs). Op-amps
endowed with low-noise attributes and elevated input impedance guarantee the
faithful capture and conversion of sensor signals into digital form, thereby fostering
meticulous measurement and scrutiny. The ramifications of op-amps within commu-
nication systems and data acquisition reverberate throughout an array of industries,
spanning telecommunications, networking, test and measurement, and scientific
exploration. Within telecommunications and networking domains, op-amps find
employment within devices like modems, routers, amplifiers, and transceivers, cata-
lyzing voice, data, and video communication across wired and wireless networks.
In the realm of test and measurement, op-amps play a pivotal role within instru-
ments such as oscilloscopes, spectrum analyzers, and signal generators, facilitating
precise measurement and analysis of electrical signals across diverse applications.
In the sphere of scientific inquiry, op-amps are integral to laboratory instruments,
data acquisition systems, and experimental configurations, facilitating the capture,
processing, and analysis of data from sensors and instruments, thereby underpin-
ning advancements across domains encompassing physics, chemistry, biology, and
engineering.

8.7 CHALLENGES AND OPPORTUNITIES IN THE DEVELOPMENT

OF ADVANCED OPERATIONAL AMPLIFIERS
8.7.1 Recent Design Challenges and Trade-Offs
The progression of operational amplifiers (op-amps) toward more sophisticated
functionalities has introduced a plethora of design obstacles and compromises. A
significant challenge revolves around striking a delicate balance between improv-
ing performance and maximizing integration density. With increasing demands for
superior performance, designers are tasked with integrating more functions into
132 Circuit Design for Modern Applications

smaller chip footprints while ensuring optimal performance across key parameters
like gain, bandwidth, and linearity. However, heightened integration often neces-
sitates trade-offs in performance, prompting designers to carefully navigate these
compromises to effectively meet design requirements.
Additionally, incorporating passive components within op-amp designs poses
supplementary challenges. Passive components such as resistors and capacitors play
pivotal roles in shaping op-amp circuit performance. However, integrating these
components alongside active components on the same chip presents compatibility
and performance hurdles. Designers must contend with issues like process varia-
tions, temperature effects, and aging phenomena that can impact the performance
and reliability of integrated passive components. This underscores the need for inno-
vative design solutions and meticulous calibration techniques.

8.7.2 Semiconductor Technology Scaling and Performance Enhancement

Advancements in semiconductor technology scaling continue to propel improve-
ments in op-amp performance, offering opportunities for enhanced functionality
and miniaturization. As semiconductor manufacturing processes scale down to
smaller feature sizes, op-amps reap benefits from enhanced transistor performance,
reduced power consumption, and increased integration density. Emerging technolo-
gies like FinFET and Gate-All-Around (GAA) MOSFET hold the promise of further
enhancing op-amp performance, enabling op-amps with higher speeds, lower noise,
and improved linearity [32–35].
Furthermore, advancements in semiconductor process technologies facilitate the
integration of advanced features such as low-power operation, enhanced reliabil-
ity, and improved temperature stability. These developments unlock new avenues
and applications for op-amps in sectors like wearable electronics, Internet of Things
(IoT) devices, and biomedical implants. Nonetheless, challenges related to process
complexity, cost, and technology maturity must be tackled to fully realize the poten-
tial of advanced semiconductor technologies in op-amp design.

8.7.3 Market Trends and Competitive Landscape

In the dynamic realm of op-amp development, market trends and competitive
dynamics shape the course of innovation and technological progress. Market
demands for superior performance, lower power consumption, and expanded func-
tionality compel manufacturers to continually push the boundaries of op-amp design.
Additionally, emerging application areas such as autonomous vehicles, 5G commu-
nication, and artificial intelligence offer fresh opportunities for op-amp integration
and customization.
Moreover, the competitive landscape of the op-amp market is characterized by
intense rivalry among semiconductor manufacturers, each striving for market domi-
nance through innovation, differentiation, and cost competitiveness. As demand for
op-amps continues to surge across diverse industries, manufacturers must remain
attuned to market trends, customer needs, and technological advancements to sustain
their competitive advantage. Collaboration and partnerships between semiconductor
Advanced Operational Amplifier with Emerging CMOS Technology 133

companies, research institutions, and end-users play a pivotal role in propelling inno-
vation and addressing the evolving demands of the market.

8.8 CONCLUSION
In essence, op-amps stand as indispensable elements within electronic circuits,
offering a blend of versatility, top-notch performance, and broad applicability across
diverse industries. From enhancing audio signals and processing data to interfac-
ing with sensors, powering communication systems, and aiding in data acquisition,
op-amps serve as vital enablers for accurate signal amplification, conditioning, and
processing.
Over time, op-amps have undergone substantial evolution, marked by notable
enhancements in performance, integration, and semiconductor technology. Present-
day op-amps tout impressive features, like high-gain, expansive bandwidth, mini-
mal noise, and full rail-to-rail operation, rendering them ideal for demanding tasks
requiring precision signal processing and faithful replication of input signals.
Nevertheless, the integration of sophisticated functionalities and semiconductor
technologies into op-amp design poses its own array of hurdles and compromises.
Design engineers must navigate through challenges related to optimizing perfor-
mance, balancing integration density, managing passive component integration,
and scaling semiconductor technology to deliver op-amps that meet exacting per-
formance criteria while addressing market demands for smaller footprints, reduced
power consumption, and enhanced capabilities.
Despite these challenges, the future prospects for operational amplifiers appear
promising, buoyed by ongoing advancements in semiconductor technology, inno-
vative design approaches, and evolving market dynamics. Collaboration among
semiconductor manufacturers, research entities, and end-users is poised to play a
pivotal role in steering the course of op-amp development, ensuring these crucial
components continue to evolve in sync with the ever-changing demands of modern
electronic systems.

Acknowledgment
In this chapter, the knowledge and information shown in various previous research
have been widely and broadly utilized, and the source of information is listed as ref-
erence format (e.g., [1], [2], …). The author would like to sincerely thank the authors
who have put their sincere effort into publishing many articles and research related
to this chapter. This chapter has been written by utilizing various information, and
the sources of information can be found in references.

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 9 Circuit Design for
Accurate Digitized Urine
Weight Measurement
Siva Lakshmi M., E. Andrea Gracelin, G. Gifta,
A. Andrew Roobert, and M. Suresh Chinnathampy

9.1 INTRODUCTION
Innovative solutions are constantly being developed to improve patient care and
diagnostic accuracy, as the rapid evolution of technology has had a significant impact
on a variety of sectors, including healthcare. In the field of urology, the accurate
measurement of urine flow is crucial for the diagnosis and treatment of a variety of
urinary disorders. Traditional methods, on the other hand, frequently fail to meet
expectations due to their patient discomfort and burdensome nature, resulting in
reduced compliance and inaccuracies.
The current chapter, “Circuit Design for Accurate Digitized Urine Weight
Measurement”, is the first stage in the development of a comprehensive system-on-
chip (SoC) solution that is designed to address these challenges. This work establishes
the groundwork for a connected, accurate, and non-intrusive urine flow measure-
ment system by capitalizing on the symbiosis between a load cell, the HX711 preci-
sion analog-to-digital converter, and the ESP8266 microcontroller.
The load cell functions as a transducer, converting mechanical force into electri-
cal signals that are subsequently amplified and digitized by the HX711 with high
precision and low noise. The ESP8266 microcontroller is renowned for its cost-effec-
tiveness and versatility, as it manages data acquisition, processing, and communi-
cation. This ensures reliable data transmission over Wi-Fi networks and seamless
integration. This design prioritizes patient comfort and simplicity of use in addition
to enhancing the accuracy and reliability of urine weight measurements.
Our objective is to create a system that is user-friendly, scalable, and robust, and
that can be seamlessly implemented into a variety of medical applications. This
system will facilitate real-time monitoring and remote access to critical data. This
preface emphasizes the significance of precise urine flow measurement in urology
and the potential impact of advanced technological solutions on the enhancement of
patient care, as well as the motivation and voyage that led to the research.
We aspire for this work to serve as a catalyst for additional advancements and
innovations in healthcare technology, thereby facilitating the development of more

DOI: 10.1201/9781003483052-9 137

138 Circuit Design for Modern Applications

sophisticated and integrated solutions that improve both patient experiences and
diagnostic capabilities.
Healthcare is constantly evolving, driven by technological advancements that
strive to enhance diagnostics, monitoring, and patient care. In the realm of urology,
the precise measurement of urine flow plays a pivotal role in understanding and
diagnosing various urinary disorders [1]. Traditional methods of urine flow measure-
ment often involve cumbersome and intrusive devices, leading to discomfort and
potential inaccuracies. In this context, the integration of a load cell weight sensor
[2], specifically the HX711 ADC, with the Node MCU ESP8266 microcontroller
emerges as a groundbreaking solution, promising non-intrusive, accurate, and con-
nected urine flow measurements [3]. Monitoring urine flow is a crucial aspect of
urological assessments and is employed in diagnosing conditions such as urinary
obstruction, prostate disorders, and overactive bladder.
To develop an IoT [4] enabled system that continuously monitors the urine volume
collected via the urine collection system and an IoT [5] urine scale to measure fluid
volume collection over a wide-ranging frequency of time, from seconds to hours
depending on the user’s preference, and transmits the data directly to the physi-
cian or other healthcare provider [6]. This comprehensive circuit design for accurate
digitized urine weight measurement aims to detect the continuous urine output mea-
surement using an IoT [7] based system for hospitalized patients who are bedridden,
patients undergone spinal cord surgery, old people and in Intensive Care Units (ICU)
which can be used for detection and prevention of urine related disease.
Urine output and the characteristics of urine can provide valuable information
for diagnosing and monitoring various medical conditions [8]. It can be a significant
component of a broader diagnostic process. Healthcare professionals use urine anal-
ysis as one of the tools to aid in diagnosing and monitoring these and other medical
conditions [9]. Accurate measurements aid healthcare professionals in understanding
the dynamics of the urinary system, allowing for timely interventions and personal-
ized treatment plans. The conventional methods of urine flow measurement [10],
often involving uroflowmetry devices with mechanical components, present limita-
tions in terms of accuracy, patient comfort, and data accessibility [11].
The intersection of IoT technology with healthcare [12] has opened up avenues
for innovative solutions that prioritize patient comfort, real-time data access, and
remote monitoring. In the context of urine flow measurement, the integration of a
load cell weight sensor [13] with a microcontroller becomes a promising approach
to address the shortcomings of traditional methods. By leveraging the power of the
HX711 ADC [14], weight sensor and the NodeMCU ESP8266 [15], healthcare pro-
fessionals can obtain accurate and real-time urine flow data, enabling more informed
decision-making.
The effectiveness and compactness of the disclosed Internet of Things-enabled
urine flow monitoring system would be greatly improved by turning it into a system-
on-chip. A single chip that combines the functions of the load-cell weight sensor,
HX711 ADC, and NodeMCU ESP8266 microcontroller would simplify the physical
footprint of the system and improve its dependability while consuming less power.
By streamlining the manufacturing process, improving data processing rates, and
Circuit Design for Accurate Digitized Urine Weight Measurement 139

facilitating a smooth integration into a variety of medical devices, this SoC solu-
tion would provide patients with more comfort and convenience when it comes to
real-time, precise urine flow measurements. These developments have the potential
to transform continuous patient monitoring and urological diagnostics, providing
healthcare professionals with a scalable and affordable option.

9.2 PROBLEM FORMULATION
Urine output refers to the volume of urine that an individual’s body produces and
excretes from the bladder within a specific period, usually measured in milliliters
(ml) or liters (L) per unit of time (e.g., milliliters per hour or liters per day). It is a
critical measure of kidney function and overall health [16]. Urine output is an essen-
tial parameter in medical and clinical settings, and it is used to assess various aspects
of a person’s health, including hydration status, kidney function, and the effects of
medical treatments [17].
Normal urine output can vary depending on factors such as age, sex, body size,
and individual health, but in adults, a typical range is about 800 to 2000 millili-
ters (mL) of urine produced per day [18]. This output may be distributed through-
out the day and night, with more urine produced during the day and less at night.
Measuring urine output is vital in various clinical situations [19]. In healthcare set-
tings, monitoring urine output is essential for maintaining a patient’s fluid balance.
In the postoperative period, monitoring urine output is important to detect early
signs of complications, such as inadequate organ perfusion or bleeding [20]. In ICUs,
continuous urine measurement is vital for assessing a patient’s overall health and
ensuring that they are receiving appropriate fluid and medication management [21].
The measurement of urine output provides valuable information that helps health-
care professionals make informed decisions regarding patient care and treatment.
In critical care and intensive care settings, continuous urine output monitoring is
vital for assessing AKI (acute kidney injury) and managing patients with severe ill-
nesses, trauma, or surgeries [22]. It helps ensure that patients receive the appropriate
fluid and medication management. Certain medications and treatments can affect
urine output and composition [23]. Monitoring urine output helps assess the effects
and potential side effects of postoperative treatments. For postoperative patients,
monitoring urine output is essential to detect early signs of complications such as
inadequate organ perfusion, bleeding, AKI, or sepsis [24]. Accurate urine output
measurement is essential in clinical research and clinical trials, where precise data
collection is necessary to study the effects of new medications or interventions on
renal function and urinary biomarkers [25].
Continuous urine measurement can provide individualized data that allows
healthcare professionals to tailor treatment plans and interventions based on the
patient’s specific needs and responses. Overall, measuring urine output is a fun-
damental and routine part of patient care in healthcare settings [26]. In order to
estimate the volume of urine collected, nurses typically measure the pee by hand
by looking at the gradation lines on the urine collecting bag. Urine is collected in a
bag using the Foley catheter, which is placed into the patient’s bladder through the
140 Circuit Design for Modern Applications

urethra. The urine output is measured visually and computed as milliliters per hour
(mL/h). This is labor-intensive, and it creates the need for developing urine output
measurements [27].

9.3 DESIGN AND METHODOLOGY

To design a urine output measurement system in real time, we have to integrate a
wooden stand with HX711 ADC, load cell (5 kg) and Node MCU ESP8266 into the
urinary bag. The urinary bag is hung on the wooden apparatus, where the ADC cir-
cuit is mounted. Node MCU ESP8266 acts as the heart of the system. The load cell
is calibrated and connected to the HX711 ADC. Table 9.1 below gives the specifica-
tions of components used in designing.
The collected urine output is in analog value, converting the analog value into a
digital value with HX711 ADC. The converted digital value is given to the micro-
controller (NodeMCU ESP8266). The calibration and urine analysis were done in
the Arduino Integrated Development Environment. Further, the processed output
from the NodeMCU ESP8266 is displayed in the Blynk IoT Application. The real-
time output can be seen in graph form and gauge via mobile. The output can be con-
nected to the healthcare provider for convenient analysis and treatment procedures.
Figure 9.1 shows the block diagram.
(The above-shown image is a pictorial block diagram of the proposed urine output
system, it consists of a power supply from the power bank, a B-type power adapter
to transmit power from the power bank to NodeMCU ESP8266, then the HX711 is
connected via wire with NodeMCU ESP8266, then the 5 kg load cell is connected

TABLE 9.1
Specification Table
S.NO. COMPONENTS POWER SUPPLY QUANTITY
1. LOAD CELL (5KG) 5V 1
2. HX711 ADC 5V 1
3. NODE MCU ESP8266 3.3–5 V 1
4. PCB 5V 1

FIGURE 9.1 Block diagram.

Circuit Design for Accurate Digitized Urine Weight Measurement 141

to HX711 and finally the output was viewed in Blynk IoT connected with NodeMCU
ESP8266 via Wi-Fi to show the real-time urine output.)

9.3.1 Load Cell
A metal bar with strain gauges connected is what makes up strain gauge load cells
(see the strain gauges behind the white glue in the top picture). An electrical sensor
known as a strain gauge converts an applied force or load into an electrical signal by
measuring the strain or force on an item. Load cells are known for their exceptional
accuracy and precision. High-sensitivity load cells can measure forces that are both
extremely small and huge. When an external force is applied to an object, the object’s
(in this case, the metal bar) shape deforms, causing variations in the strain gauges’
resistance. Because the resistance changes in direct proportion to the applied stress,
we can determine an object’s weight. Table 9.2 shows the load cell’s four colors of
wires and their indications are given.

9.3.2 HX711 ADC
The HX711 is a precise 24-bit analog-to-digital converter (ADC) designed for direct
interaction with bridge sensors in industrial control applications and weighing
scales. It features a low noise programmable gain amplifier (PGA) that receives a
differential input from the input multiplexer, allowing selection between Channel
A or B. When a 5-V supply is connected to the AVDD analog power supply pin,
Channel A can be configured with gains of 128 or 64, corresponding to full-scale
differential input voltages of ± 20 mV or ± 40 mV, respectively. Channel B has a
fixed gain of 32. In the absence of an external supply regulator, the HX711 can be
powered through the on-chip power supply regulator, simplifying the setup. Clock
input options include the on-chip oscillator, an external clock source, or a crystal.
Digital interface initialization is streamlined thanks to on-chip power-on-reset cir-
cuitry, eliminating the need for manual programming of internal registers.
Each HX711 control is facilitated through dedicated pins. Notable features of the
ADC include an on-chip active low-noise PGA with configurable gains (32, 64, and
128), two selectable differential input channels, an on-chip power supply regulator

TABLE 9.2
Load Cell Wire and Their Indication
Load Cell connection
indicating with wire color Indication
Red VCC (E+)
Black GND (E–)
White OUTPUT– (A–)
Green OUTPUT+ (A+)
142 Circuit Design for Modern Applications

FIGURE 9.2 Application block diagram for a standard weighing scale.

for both the load cell and ADC’s analog power supply, and an on-chip oscillator with
optional external crystal. The digital control and serial interface are pin-driven, and
users can choose between output data rates of 80 or 10 bps. The ADC also provides
simultaneous 50 and 60 Hz supply rejection. The HX711 boasts low current con-
sumption during regular operation (< 1.5 mA) and power-down mode (< 1uA). The
operating supply voltage ranges from 2.6 V to 5.5 V, and the operational temperature
spans from –40°C to +85°C. Encased in a 16-pin SOP-16 package, the HX711 finds
widespread application in industrial process control and weighing scales. Figure 9.2
will show the illustration of a standard weighing scale’s application block diagram.

Analog Inputs Channel: A differential input’s purpose is to directly communicate

with the differential output of a bridge sensor. It can have a gain of 128 or 64 when
programmed. In order to accommodate the little output signal from the sensor, sub-
stantial gains are required. When a 5V supply is used at the AVDD pin, these gains
correspond to a full-scale differential input voltage of ± 20 mV or ± 40 mV, respec-
tively. The fixed gain of the differential input on Channel B is 32. ± 80 mV is the
full-scale input voltage range when the AVDD pin is powered by a 5-V source.
Figure 9.2 illustrates the block diagram for a standard weighing scale connected to a
load cell which gets its urine output weight as input from a 5 kg load cell that is given
to the multiplexer in HX711, then to the Programmable Gate Array, then to the 24-bit
ADC and finally the output will be converted to digital form via ADC, i.e., ready to
give as input to the NodeMCU ESP8266.

Options for Power Supplies: The MCU power supply and the digital power supply
(DVDD) ought to be the same. The external transistor that is employed determines
the regulator’s dropout voltage when employing an internal analog supply regulator.
The formula for the output voltage is VAVDD = VBG*(R1+R2)/ R1. A minimum of
100 mV below the VSUP value should be included in the design of this voltage. The
Circuit Design for Accurate Digitized Urine Weight Measurement 143

VSUP pin should be connected to either AVDD or DVDD, depending on whether the
voltage is higher, if the on-chip analog supply regulator is not being used. Pin BASE
turns NC and Pin VFB should be linked to Ground.

Clock Source Options: The on-chip oscillator can be turned on by connecting pin
XI to the Ground. When utilizing the internal oscillator, the nominal output data rate
is either 10 (RATE = 0) or 80 SPS (RATE = 1). The use of a crystal or external refer-
ence clock is an option if a precise output data rate is required. The XI and XO pins
can be directly linked to a crystal. Through the use of a 20 pF AC coupled capacitor,
the XI pin can be connected to an external clock. It’s not necessary for this external
clock to be a square wave. It can have an amplitude as low as 150 mV and originate
straight from the MCU chip’s crystal output pin. Upon utilizing an external clock or
a crystal, the internal oscillator shuts down automatically.

Output Data Rate and Format: The output data rate with the on-chip oscillator
is usually 10 (RATE = 0) or 80 SPS (RATE = 1). The output data rate is exactly
proportional to the clock or crystal frequency when an external clock or crystal is
used. The output data rate is precisely 10 (RATE = 0) or 80 SPS (RATE = 1) when
using an 11.0592 MHz clock or crystal. 24 bits of data are output in the format of 2’s
complement. The output data will become saturated at 800,000h (MIN) or 7FFFFFh
(MAX) if the input differential signal leaves the 24-bit range and stays there until it
returns to the input range.

Serial Interface: Power-down controls, input selection, gain selection, and data
retrieval are all done via pins PD_SCK and DOUT. Digital output pin DOUT is
high when the output data is not yet ready to be retrieved. PD_SCK, the serial clock
input, ought to be low. Data is ready for retrieval when DOUT drops to zero. Data is
shifted out of the DOUT output pin by supplying 25–27 positive clock pulses at the
PD_SCK pin. Up until all 24 bits are shifted out, each PD_SCK pulse moves one bit
out, beginning with the MSB bit. The DOUT pin will return to high upon the 25th
pulse at the PD_SCK input. The number of PD_SCK pulses in the input determines
the input and gain selection. To prevent producing a serial communication fault, the
number of PD_SCK clock pulses in a conversion period should not be fewer than 25
or greater than 27.

Reset and Power-Down: Upon activation, the chip will be reset by the on-chip
power-on reset circuitry. The input value is low. HX711 goes into power-down mode
when the PD_SCK pin goes from low to high and remains there for more than 55 µs.
Figure 9.3 shows the Power-down control. Both the HX711 and the external trans-
ducer will shut off when the internal regulator is utilized for both. The chip will reset
and go into a regular operating state when PD_SCK goes back to low. The input
option defaults to Channel A with a gain of 128 following a reset or power-down
event.
It is used to interface with load cells to measure urine output weight and convert
the analog signal into a digital format that can be read by a microcontroller unit. The
144 Circuit Design for Modern Applications

FIGURE 9.3 Power-down control.

HX711 used is a small dual in-line package (DIP) or surface mount device (SMD)
package. HX711’s “HX” stands for “Half of X”, indicating that it offers half of the
24-bit resolution—still a very high resolution for a urine output measurement. The
standard pinouts in the HX711 used for urine output measurement are: A– (negative
differential input): Connects A– pin of HX711 to the white wire (output–) of the load
cell. A+ (positive differential input): Connects the A+ pin of HX711 to the green wire
(output+) of the load cell. E+ (excitation positive): Connects the positive excitation
voltage of HX711 to the red wire (VCC) of the load cells. E– (excitation negative):
Connects the negative excitation voltage of HX711 to the black wire (GND) of the
load cells. VCC (power supply): VCC of HX711 is connected to the positive supply
voltage (3.3 V) of NODE MCU ESP8266. It powers the HX711 chip. GND (ground):
GND of HX711 is connected to the ground of ESP NODE MCU8266. DT (DATA):
The serial data output. DT of HX711 is connected to a digital input (GPIO11) on the
NODE MCU ESP8266 to transmit the converted digital data. SCK (serial clock):
The serial clock input. SCK of HX711 is connected to a digital input (GPIO12) on
the ESP NODE MCU8266 to receive clock pulses from the NodeMCU ESP8266 to
synchronize data transmission.
Figure 9.3 illustrates the power-down control of HX711, when the input value is
low HX711 goes into power-down mode. When the PD_SCK pin goes from low to
high and remains there for more than 55 µs. The chip will reset and go into a regular
operating state when PD_SCK goes back to low.

9.3.4 Node MCU
The GPIO12, GPIO13, GND, and VCC (power supply) pins on the Node MCU
development board are commonly used for interfacing with external devices and
components. The features of GPIO12 (general purpose input/output 12) and GPIO13
(general purpose input/output 13) are it is a digital output pin, supports digital sig-
nals (HIGH/LOW), it is used for interfacing with digital devices (HX711 and mobile
phone). The GND (ground) pin is for reference or 0 V. Serves as the common ground
for the entire circuit. All components in the circuit are in a common ground to ensure
proper reference levels and stable operation. VCC (Voltage Supply) is the power sup-
ply pin. Provides power to the whole circuit. It also ensures that the voltage supplied
is within the specified operating range to prevent damage to the board.
Circuit Design for Accurate Digitized Urine Weight Measurement 145

TABLE 9.3
Connections with the Terminals of All the Three Components
LOAD CELL WIRE COLOR HX711 (indicates) HX711 (refers to) ESP2866
RED (E+) E+ GND GND
BLACK (E–) E– DT D6
WHITE (A–) A– SCK D7
GREEN (A+) A+ VCC 5V

9.4.5 Methodology
Prepare the wooden stand which will hold the load cell in place. As the urine bag is
to be hung the length of the stand must be respective to the urine bag length. Solder
the connections between the load cell and HX711 (as given in the design). After this
step connect the HX711 with the NODE MCU ESP8266 (as given in the design). In
Table 9.3 below connections with the terminals of all three components are given.
After the connection and the soldering are done, in ARDUINO IDE the calibra-
tion will be done with a known weight value. Then the load cell has to be calibrated
with a calibration factor formula, calibration factor = (reading)/(known weight) then
the code has to be dumped into the NODE MCU ESP8266. After calibration, the
NODE MCU ESP8266 has to be connected with Blynk via Wi-Fi, and then the real-
time urine output measurement can be displayed on the connected device.

9.6 RESULT AND DISCUSSION

Urine output measurement can be displayed in a gauge form with a range of 0 ml to
1000 ml and in graph form in Blynk for every 10 seconds or every minute or hourly
manner according to the user’s preferences. Figure 9.4 will show that it represents the
acquired Blynk urine output measurement.

FIGURE 9.4 Blynk output.

146 Circuit Design for Modern Applications

TABLE 9.4
Existing Device for Urine Output Measurement
Sensica Urine Accuryn
EXISTING Renal Sense Clarity Output Monitoring
DEVICE RMS Sensor Kit [28] System [29] System [30]
RESULT Provides accurate real-time urine Provide urine Provide urine
output measurement and temperature output data and output and
measurement. alerts when intra-abdominal
AKI is detected pressure.
DISCUSSION Uses a patented sensor that costs 5000 Recalled due to Was approved and
USD, and 85 USD for each inaccuracies being used only in
single-use specialized temperature- Israel, not in the
sensing urine collection bag. Thermal United States.
transfer is the foundation of the
technology. Most hospitals cannot
afford this equipment, thus only a
small number of hospitals use it.

Figure 9.4 illustrates the real-time output obtained from the designed urine out-
put measurement system using HX711 ADC using a 5 kg load cell and NodeMCU
ESP8266.
Table 9.4 provides an explanation of existing devices for urine output measure-
ment. The history of urine output measurement reflects the ongoing development of
medical knowledge and technology. This makes a need to develop a real-time, reli-
able, accurate, and cost-effective urine output system.
Errors in measurement can occur in load cells. The essentially mathematical dif-
ference between the value represented by the sensor output and the actual value of
the measured variable, or known reference loads, is what constitutes these structural
uncertainties. Numerous things can lead to measurement inaccuracies, including:

• Zero offset, also known as load cell zero balance

• Linearity (or absence of it)
• Hysteresis
• Repeatability (or lack thereof)
• Zero and temperature shift span

The load cell has a “calibration curve” or “characteristic curve” that describes how
the sensor reacts to an input. Figure 9.5 shows the calibration curve is non-linear.
By comparing the sensor output under reference weights and modifying the sensor
response to an ideal linear output, we may verify the sensor’s zero offset and linear-
ity via a routine calibration utilizing the load cell calibration equipment. In addition,
the load cell calibration apparatus verifies temperature shift, repeatability, and hys-
teresis upon client request for certain vital force measuring uses.
Circuit Design for Accurate Digitized Urine Weight Measurement 147

FIGURE 9.5 Load cell calibration curve.

A yearly recalibration is needed for strain gauge load cells due to their exposure
to continuous usage, aging, output drift, overload, and incorrect handling. Regular
recalibration aids in determining whether the sensor has retained its accuracy over
time. However, load cells may need even more frequent calibrations when the sensor
is utilized in severe environments and important applications.
In HX711 ADC the E+ and E– pins are used to provide a stable excitation volt-
age to the load cells, and the A– and A+ pins are used to connect the load cells in a
differential configuration. The DT and SCK pins handle the digital communication
between the HX711 and the microcontroller. Proper wiring and configuration are
essential for accurate weight measurements.
The HX711 offers high resolution, allowing for precise urine output measure-
ments. It incorporates a low-noise PGA to amplify weak input signals from load
cells without introducing significant noise. The HX711 two differential inputs A–
and A+, help cancel out common-mode noise from the external environment. The
device includes an on-chip oscillator and digital filter to improve the stability and
accuracy of the ADC readings. HX711 communicates with NODE MCU ESP8266
using a two-wire serial interface (clock and data lines). The communication protocol
is simple and well-documented.

9.7 CONCLUSION
Measuring urine output using a load cell, HX711 ADC, and Node MCU offers a
promising method for accurate and continuous monitoring in medical and research
settings. The load cell, typically used for weight measurement, can be adapted to
measure the changing weight of a urine collection container. By integrating the load
cell with the HX711 ADC, the analog weight data is converted to a digital signal
suitable for processing by the Node MCU, a microcontroller capable of interfacing
with various sensors and transmitting data wirelessly. This setup allows real-time
monitoring of urine output, which is crucial in critical care environments for assess-
ing kidney function, fluid balance, and overall health status. The Node MCU can be
programmed to send data to a centralized monitoring system or display it locally,
enabling healthcare professionals to make timely interventions based on accurate
urine output measurements. This approach is more convenient and potentially more
accurate than traditional methods relying on manual measurements or visual estima-
tion. In summary, leveraging load cell technology with IoT capabilities through the
HX711 ADC and Node MCU holds significant promise for advancing urine output
148 Circuit Design for Modern Applications

measurement and enhancing patient care in healthcare settings. When this system is
converted into an SoC, it will be comfortable and convenient for the patients.

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 10 Low-Power Energy-
Efficient CNTFET-Based
Quaternary Multipliers
Sarada Musala, G. V. S. Ajay, and Neelima N.

10.1 INTRODUCTION
Binary logic systems, which operate with only two discrete values, 0 and 1, have
historically dominated the landscape of digital electronics and circuit design.
Nevertheless, the constraints of binary logic become increasingly apparent as
technology continues to develop and the demand for more intricate, efficient, and
compact electronic systems increases. Multiple-valued logic (MVL) is a promising
alternative that addresses critical issues such as chip area reduction and connectiv-
ity concerns by providing more than two discrete states. The utilization of Carbon
Nanotube Field-Effect Transistors (CNTFETs) in this context is a revolutionary
approach that capitalizes on their distinctive properties to improve the performance
and efficiency of MVL circuits.
This research explores the creation of an energy-efficient, low-power quaternary
multiplier that employs CNTFET technology. The transistor count is minimized by
designing the quaternary multiplier, a fundamental component in the construction
of quaternary arithmetic and logic circuits, using multiple quaternary multiplexers.
The circuit’s performance metrics, such as power dissipation, propagation delay, and
power-delay product (PDP), are optimized by this innovative approach, which also
reduces its complexity.
The importance of this research is its potential to revolutionize the design and
implementation of digital circuits, particularly in applications where power effi-
ciency and speed are critical. The proposed designs provide a viable solution to the
challenges encountered by traditional binary systems by utilizing CNTFETs and
quaternary logic.
The proposed quaternary multipliers and the 2 × 4 multiplier exhibit superior per-
formance in simulations conducted using Cadence Spectre with a 32-nm CNTFET
technology. The design’s efficacy is confirmed by the substantial improvements in
power consumption, latency, and PDP across various supply voltages.
This previous section establishes the groundwork for a thorough examination
of the empirical validations, design methodologies, and theoretical foundations of

150 DOI: 10.1201/9781003483052-10

Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 151

quaternary multipliers that are based on CNTFETs. It emphasizes the innovative

strategies implemented, the motivation for the research, and the substantial contribu-
tions to the field of advanced semiconductor technologies and multiple-valued logic.

10.1.1 Need for MVL

MVL stands for multi-valued logic. It consists of four logic levels, whereas on the
other hand binary logic consists of two states namely true or false. When we view
the various properties of multiple-valued logic, we see phenomena we would never
experience in binary logic, where there are only two values, null and unit, of Boolean
algebra. These phenomena help us gain a deeper understanding of the MVL when
viewed from the perspective of a two-valued scale [1]. Multiple-valued logic helps
us to better understand binary problems, which are classified into two groups. In the
first group, binary problems are better solved using multiple-valued logic domains.
One well-known way of representing a multiple-output Boolean function is by
decomposing its output into single, multiple-valued variables. In the second group,
designers are concerned with the development of circuits employing more than two
discrete levels of signals, such as memories containing multiple values, equations,
and Field Programmable Gate Arrays.

10.1.2 Advantages of MVL
The use of multi-valued logic provides us with many opportunities to improve the
design of present-day circuits. When signals in the circuit may assume more than
two states instead of only two, there could be a substantial reduction in difficult
situations of a limited number of connections between an integrated circuit and the
external world and in a limited number of connections within the circuit encoun-
tered in some VLSI circuit synthesis. In addition, using multiple-valued numbers as
a representation for many applications has a clear mathematical appeal. In normal
binary addition and subtraction, ripple-through carriers are involved. Using residue
and redundant number systems, it is possible to reduce or eliminate these carries,
thus resulting in high-speed computations.

10.1.3 Types of MVL
There are three groups in multi-valued logic: ternary, quaternary, and pentanary,
each with three, four, and five states [2]; “0”, “1”, and “2” are the three states in
ternary logic. Quaternary logic consists of “0”, “1”, “2”, and “3” states, whereas the
pentanary logic consists of the following states “0”, “1”, “2”, “3”, and “4”. The major-
ity of this study is conducted in the ternary field,. When designing microprocessors,
the quaternary logic between the highest and lowest levels in the MVL circuits can
be thought of as a good choice. Ternary, quaternary, and pentanary circuits make use
of ternary, quaternary, and pentanary logics, respectively.
152 Circuit Design for Modern Applications

10.1.4 Difference Between MVL and Binary Logic

Binary logic consists of two states namely true (1) or false (0), whereas the multi-
valued logic consists of states greater than two [3]. The use of multi-valued logic
reduces the number of connections, thereby reducing circuit complexity and the chip
area. MVL fastens the operation of the circuit when compared with the binary circuit
and decreases the power consumption. It also performs a higher number of rational
and mathematical computations.

10.1.5 Quaternary Logic
As was previously mentioned, four values – 0, 1/3 VDD, 2/3 VDD, and VDD volt-
age levels – are represented by the digits “0”, “1”, “2”, and “3” in quaternary logic
functions [8, 10, 11]. The work utilized three quaternary inverters: the intermediate
quaternary inverter (IQI), the negative quaternary inverter (NQI), and the positive
quaternary inverter (PQI) [1, 3]. Table 10.1 shows the truth table for these inverters.
The circuit diagrams [8] of NQI, IQI, and PQI inverters are shown in Figures 10.1,
10.2, and 10.3.

TABLE 10.1
Truth Table of Quaternary Inverters (Rahmati et al., 2021)
Input NQI out IQI out PQI Out
0 3 3 3
1 0 3 3
2 0 0 3
3 0 0 0

FIGURE 10.1 Schematic of NQI.

Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 153

FIGURE 10.2 Schematic of IQI.

FIGURE 10.3 Schematic of PQI.

10.1.6 CNTFET
A pipe composed of one-atom-thick graphene tubes is called a carbon nanotube
(CNT). Based on their rotating axis, the nanotube plates can be classified as semi-
conductive or conducting. The chiral vector is defined by C = ma1 + na2 where m and
n are integers and a1 and a2 are the unit vectors of the hexagonal lattice [4–6]. The
pair of integers (m, n) determines the structure and electrical properties of a CNT
which can be termed as chirality of the tube. If both m and n are equal or the product
of m, n is a multiple of 3 then it shows metal conductivity. In every other scenario,
it will display a semi-conductive characteristic. The biggest benefit of CNTFETs is
that the threshold voltage changes as the carbon tube diameter changes.

Ebg 3aV  0.436

Vth    (10.1)
2e 3eDCNT DCNT  nm 
154 Circuit Design for Modern Applications

FIGURE 10.4 CNTFET structure (Zahoor F. et al., 2021).

where “a” is the distance (a = 2.49 Å) between two carbon atoms, “e” is the unit
electron charge, and “Vπ” = 3.033 eV is the carbon π–π bond energy between two
carbon atoms [10, 13] (Figure 10.4).

10.1.7 Difference Between CNTFET and MOS Transistors

As with silicon MOSFETs, the CNTFET structure is almost identical to that of a
transistor, but the CNT acts as the channel. CNTFETs operate in the same way
as MOSFETs, which involve electrons traveling from a source terminal to a drain
terminal. CNTFET provides the designer with a unique opportunity to control the
threshold voltage by varying the chirality of the CNT [7]. The drawback of CMOS
is when the channel length is varied it encounters leakage currents, short-channel
effects, and higher power consumption. CNTFETs have lower latency, higher carrier
mobility, and lower power consumption.

10.1.8 Multiplier
One of the most significant and often used arithmetic circuits in the arithmetic logic
unit is the multiplier operator [8–10]. It takes two or more numbers as inputs to give
the product and carry. An array of half adders and full adders [11] is used in an
array multiplier, a type of digital combinational circuit, to multiply two numbers.
The many product keywords involved are added almost simultaneously using this
array. To generate the various product terms, an array of AND gates is used before
the adder array. One by one bit by bit checking of the multiplier and generation of
partial products is a sequential process requiring a sequence of add and shift micro-
operations. By using a combinational circuit that generates the product bits simulta-
neously, two binary values can be multiplied in a single micro-operation. Because
all that is required is for the signals to propagate through the gates that make up the
multiplication array, this is a quick method of multiplying two values. On the other
hand, until integrated circuits were developed, an array multiplier was not economi-
cally viable due to the large number of gates that are required.
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 155

TABLE 10.2
Quaternary Multiplier’s Values for Product and Carry
In Product Out In Carry out
A/B 0 1 2 3 A/B 0 1 2 3
0 0 0 0 0 0 0 0 0 0
1 0 1 2 2 1 0 0 0 0
2 0 2 0 2 2 0 0 1 1
3 0 3 2 1 3 0 0 1 2

10.1.9 Quaternary Multipliers
This multiplier [12] takes inputs as quaternary numbers and gives product and carry
as outputs [13–25]. The truth table of the quaternary multiplier of two inputs is
shown in Table 10.2.

10.1.10 Comparison Between Pass Transistor Logic

and Transmission Gate Logic (TGL)

In CMOS circuit design, switches such as transmission gate logic and pass transistor
logic (PTL) are employed. While TGL employs an NMOS and a PMOS device in
tandem, PTL implements logic functions using a single NMOS or PMOS transistor.
Signals can either be blocked or allowed to pass through the transmission gate or
pass the transistor, depending on the control signal applied to it. Comparing PTL
with TGL, the former requires half as many transistors. PTL experiences voltage
deterioration, which is resolved in TGL.

10.1.11 Organization of the Chapter

The chapter is structured as follows: the second section discusses existing 1-bit qua-
ternary multipliers, followed by the third section, which presents the proposed 1-bit
quaternary multiplier circuits. The fourth section addresses the 2 × 4 multipliers,
while the subsequent section covers simulation results and comparisons. Finally, the
last section offers the conclusion.

10.2 QUATERNARY MULTIPLIERS
10.2.1 Existing Quaternary Multiplier-3
The circuit for the quaternary multiplier the author proposes in this study [10]
employing a 4:1 multiplexer is displayed in Figure 10.5(C). There are 24 transistors
in it. Table 10.2 displays the product and carry values of the multipliers.
156 Circuit Design for Modern Applications

FIGURE 10.5 Existing quaternary multiplier-3, (A) block diagram of product multiplier,
(B) carry multiplier, (C) 4:1 multiplexer, (D) unary operator A3 , (E) unary operator AR.

The truth table demonstrates that, regardless of A, both outputs will be 0 when
B = 0. When A = 0/1/2/3 and B = 1, carry = 0 and product = 1. When A = 0/1/2/3,
Product = 0/2/0/2 and carry = 0/0/1/1 for B = 2 and A = 0/1/2/3. And product =
0/3/2/1 and carry = 0/0/1/2 for B = 3 and A = 0/1/2/3.
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 157

Signal A’s NQI, IQI, and PQI functions are denoted by the symbols AN, AI, and
AP. The signal to be transferred to the output is determined by the selection signal.
D1/D2/D3/D4 data signals will be transmitted for B = 0/1/2/3.
To construct the multiplier, 53 transistors in total are needed. Fewer transistors
are used in the implementation of the carry block. There is an issue with the sug-
gested carry circuit diagram in Figure 10.5(B) [10]. The carry output for A = 3 and
B = 2 should be logic “1”, but since every PCNFET in the circuit is switched, logic
“2” is produced instead.

10.2.2 Existing Quaternary Multiplier-2

In this chapter [11], the gate-level method can be used for designing the multiplier.
Using this method to create quaternary arithmetic circuits results in a tremendous
number of transistors and logic gates, so it is not at all advantageous. The study sug-
gested a novel quaternary literal selector (quaternary decoder) and a CNFET-based
transmission gate (TG) network to create an effective quaternary four-to-one multi-
plexer. Figure 10.6 displays the circuit schematics for the transmission gate network
and quaternary decoder. A transmission gate network consists of both p-type and
n-type transistors. First, the selection signal is decoded into quaternary logic and
this decoded signal is used to switch on the transistors present in the TG network.
The decoded selection signal and its inverter are applied to the transistors present in
the TG network.

10.2.3 Existing Quaternary Multiplier-1

This chapter uses quaternary logic gates to implement the 1-bit multiplier [12]. The
circuit diagrams of the quaternary logic gates are shown in Figure 10.7. Binary and
quaternary logic are represented with the symbols “B” and “Q”, respectively.

10.3 PROPOSED CIRCUITS
This section discusses the various proposed circuits.

10.3.1 Proposed Carry Circuit

By adding a second PCNFET and applying BP as a signal to its gate, the issue with
the original carry circuit has been fixed. Below Figure 10.8 is the modified carry
schematic diagram. With this modified carry, the combination A = 3 and B = 2 yields
a logic “1” result.

10.3.2 Proposed Quaternary Multiplier-1

A multiplier is proposed by making use of a 4:1 MUX. The multiplexer has been
developed using pass transistor logic which resulted in a reduction in the number
of transistors of the multiplexer when compared to the existing multiplexer. Six
158 Circuit Design for Modern Applications

FIGURE 10.6 Existing quaternary multiplier-2, (A) block diagram of quaternary decoder,
(B) block diagram of product, (C) block diagram of carry.

transistors are used to realize the multiplexer [13]. The schematic diagram of the
proposed 4:1 multiplexer is shown in Figure 10.9(A). The MUX uses multi-voltage
levels. All other blocks which are shown in Figure 10.5 are used to implement the
quaternary multiplier except Figure 10.5(D), instead another block is used shown in
Figure 10.9(D). A modified carry block is used instead of the existing carry block. A
total of 46 transistors are used to realize it. The block diagrams of product and carry
blocks are shown in Figure 10.9.
Z0 is switched to output when the MUX operates with select = “0”, which turns
transistors L0, L1, L3, L4, and L5 ON and transistors L2, L4, L5, and L6 OFF.
Transistors L1, L2, and L3 are ON when select = “1”, while transistors L0, L4, and
L5 are OFF. Z1 is to be shifted to output based on the previous operation. Selecting
option “2” activates transistors L2, L3, and L4, and disables transistors L0, L1, and
L5. The Z2 signal is consequently sent to the output. Z3 is copied to the output as
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 159

FIGURE 10.7 Existing quaternary multiplier-1, (A) block diagram of Product, (B) block
diagram of carry.

FIGURE 10.8 Circuit diagram of proposed carry circuit.

soon as select = “3” is chosen since transistors L2, L4, and L5 are ON and transistors
L0, L1, and L3 are OFF.

10.3.3 Proposed Quaternary Multiplier-2

This section deals with the 2:1 multiplexer, which is used as the main block to design
and implement the multiplier. The multiplexer makes use of transmission gate logic.
160 Circuit Design for Modern Applications

FIGURE 10.9 Proposed quaternary multiplier-1, (A) circuit diagram of 4:1 quaternary mul-
tiplexer, (B) block diagram of 4:1 multiplexer, (C) block diagram of product multiplier, (D)
circuit diagram of unary operator AJ, (E) circuit diagram carry multiplier.
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 161

FIGURE 10.10 Proposed quaternary multiplier-2, (A) block diagram of 2:1 multiplexer,
(B) circuit diagram of 2:1 quaternary multiplexer, (C) proposed block diagram of product
multiplier.

TGL comprises p-type and n-type CNTFETs. The symbol for the multiplexer and its
circuit diagram is shown in Figure 10.10 [14]. Figure 10(C) shows the block diagram
of the product block, whereas the carry block diagram is shown in Figure 10.9(E).
The 2:1 multiplexer operates as follows: the output will be I0 in all other situa-
tions, and select = 0 will result in an output of I1. The output of NQI will be three
if select = 0. T0, T1, and T2 transistors are turned on and T2 and T3 transistors are
turned off when the number “0” is selected. Hence, contingent upon the threshold
voltage, the input of I0 is transferred to the output. When select = 1, NQI will pro-
duce a value of 0. Transistors T3, T2, T1, and T0 are therefore activated, and the
input of I1 is routed to the output. There are six transistors in use, and 46 transistors
are used in the multiplier.

10.3.4 Proposed Quaternary Multiplier-3

The above circuit dealt with the 2:1 multiplexer with transmission gate logic. In
this section, a new 2:1 multiplexer is proposed which makes use of pass transistor
logic [15–22]. Pass transistor logic uses either a p-type or n-type transistor. It uses
two transistors. The circuit diagram of the proposed design is shown in the below
Figure 10.11(A).
162 Circuit Design for Modern Applications

FIGURE 10.11 Proposed quaternary multiplier-3, (A) Circuit diagram of 2:1 quaternary
multiplexer, (B) Block diagram of product multiplier.

The operation of the 2:1 MUX is as follows, if select = 0, then on applying to the
NQI, its output will be which switches on the transistor T0 and its data signal I0 will
be sent to the output. The output of the NQI will be 0 which activates T1 and its cor-
responding data signal I1 will appear at the output for select = 1. 40 transistors are
used to implement the multiplier using this approach.

10.3.5 2 × 4 multiplier
A 2 × 4 multiplier is implemented whose structure is shown in below Figure 10.12.
This structure has a multiplier in the M block, a half adder, a sum unit, and a multi-
plier in the MA1 block. A multiplier, a complete adder, and a sum unit are all found
in an MA2 block. The sum unit is in [10]. The multiplier used in this structure is
a proposed multiplier. The block diagrams of MA1 and MA2 are shown in Figure
10.12, and the circuit diagrams of the full adder and half adder are in [10].

10.4 SIMULATION RESULTS
Figure 10.13(A) displays the transient results of each proposed 1-bit multiplier at an
operating voltage of 0.9 V. The 32-nm technology Cadence Spectre software is used
to perform the simulation.
The transient response of a 2 × 4 multiplier using all the proposed multipliers is
shown in Figure 10.13(B) at 0.9 V supply voltage. The inputs applied to the 2 × 4
multiplier are 11 × 0110 and 10 × 1010 and the corresponding outputs are 001110 and
010000 respectively.

10.5 Performance Comparison
All three of the proposed circuits’ performances are compared to the existing circuit
[10] in this section. Table 10.3 illustrates how the power, delay, and power-delay
product are compared when the voltages are changed from 0.7 V to 1.2 V. From
Table 10.3, it can be observed that all proposed quaternary multipliers have better
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 163

FIGURE 10.12 (A) Structure of 2 × 4 multiplier, (B) block diagram of MA2, (C) block
diagram of MA1.

FIGURE 10.13 (A) Transient response of quaternary multiplier, (B) transient response of 2
× 4 multiplier.
164 Circuit Design for Modern Applications

TABLE 10.3
Performance Comparison of Proposed Circuits with Existing Circuits (Circuit
from Rahmati et al., 2021)
Power Dissipation Propagation
1-bit Quaternary Multiplier VDD(V) (UW) Delay (ns) PDP(fJ)
Existing circuit (10) 0.7 2.363 2.044 4.829
Proposed quaternary multiplier-1 2.329 2.038 4.746
Proposed quaternary multiplier-2 2.328 2.060 4.795
Proposed quaternary multiplier-3 2.327 2.039 4.744
Existing circuit (10) 0.8 4.001 2.019 8.078
Proposed quaternary multiplier-1 3.910 2.019 7.894
Proposed quaternary multiplier-2 3.910 2.025 7.917
Proposed quaternary multiplier-3 3.907 2.019 7.888
Existing circuit (10) 0.9 6.178 2.015 12.44
Proposed quaternary multiplier-1 6.015 2.014 12.11
Proposed quaternary multiplier-2 6.004 2.018 12.11
Proposed quaternary multiplier-3 4.415 2.015 8.89
Existing circuit (10) 1.0 9.255 2.012 18.62
Proposed quaternary multiplier-1 9.011 2.012 18.13
Proposed quaternary multiplier-2 8.895 2.015 17.92
Proposed quaternary multiplier-3 8.880 2.014 17.88
Existing circuit (10) 1.1 13.48 2.021 27.24
Proposed quaternary multiplier-1 13.15 2.010 26.43
Proposed quaternary multiplier-2 12.81 2.013 25.78
Proposed quaternary multiplier-3 12.76 2.012 25.63
Existing circuit (10) 1.2 18.83 2.010 37.84
Proposed quaternary multiplier-1 18.38 2.010 36.94
Proposed quaternary multiplier-2 17.69 2.010 35.55
Proposed quaternary multiplier-3 17.57 2.011 35.33

performance than circuit [10], and moreover proposed quaternary multiplier-3 has
least power and energy.
Table 10.4 shows that, in comparison to the existing circuit, the proposed circuits
consume less power. In contrast to the [10] circuit, the proposed circuits share the
same latency. All the circuits that are being proposed have low power-delay prod-
ucts. Here, the power, delay, and PDP performances of a 2 × 4 multiplier utilizing
every proposed multiplier are examined. Table 10.4 displays the results of the 2 × 4
multiplier with the proposed quaternary multiplier-3 with better energy efficiency.
Different types of devices can be used to improve the efficiency in future works
[26–32].
Low-Power Energy-Efficient CNTFET-Based Quaternary Multipliers 165

TABLE 10.4
Power, Delay and PDP of Proposed 2 × 4 Multiplier with Existing 2 × 4
Multiplier (Circuit from Rahmati et al., 2021)
2 × 4 Multiplier Power (uW) Delay (us) PDP (nJ)
2 × 4 multiplier with existing multiplier (10) 72.93 2.00487 0.146
2 × 4 multiplier with proposed quaternary multiplier-1 73.66 2.00486 0.146
2 × 4 multiplier with proposed quaternary multiplier-2 81.87 2.00472 0.164
2 × 4 multiplier with proposed quaternary multiplier-3 72.91 2.00245 0.145

10.6 CONCLUSION
Because of its tremendous capabilities, nanotechnology has been used by many
researchers to construct MVL circuits in the past ten years. By utilizing MVL
logic on the carbon nanotube FET, computational circuits speed up and chip size is
reduced. This study introduced a novel carry block. Several MUXs are used in the
design of the quaternary multiplier. Furthermore, a 2 × 4 multiplier block was imple-
mented. According to the simulation results, under various operating settings, the
suggested 2 × 4 and quaternary multipliers have reduced power, latency, and PDP.
Furthermore, the proposed quaternary multiplier’s transistor counts were far lower
than those of the existing quaternary multipliers.

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 11 Advanced
Semiconductor Devices
FET Down-scaling and
Next-Gen Transistors
Mohamed Salah Benlatreche, Billel Smaani,
Ismahan Mahdi, Omari Tahar, and
Cheriet Mohammed El Amine

11.1 INTRODUCTION
The evolution of semiconductor technology has been marked by continuous advance-
ments aimed at improving performance, reducing power consumption, and enhanc-
ing integration densities. As traditional complementary metal-oxide-semiconductor
(CMOS) technology approaches physical limits, the emergence of two-dimensional
(2D) and three-dimensional (3D) field-effect transistors (FETs) represents a pivotal
shift toward achieving these goals and unlocking new possibilities in electronics.
This chapter, “Advanced Semiconductor Devices: FET Down-scaling and Next-Gen
Transistors”, explores the forefront of semiconductor innovation by examining the
latest developments, design strategies, and potential applications of these revolution-
ary transistor architectures. This introduction presents the motivations, scope, and
objectives that underpin the exploration of these transformative semiconductor tech-
nologies. Traditional CMOS technology, while highly successful, faces challenges
in scaling down to nanometer dimensions due to issues such as leakage currents
and power dissipation. The advent of 2D materials such as graphene and transition
metal dichalcogenides (TMDs), along with 3D transistor structures like FinFETs and
Nanowire FETs, offers new avenues for overcoming these limitations. These tech-
nologies promise significant improvements in speed, efficiency, and scalability, posi-
tioning them at the forefront of next-generation semiconductor devices. This chapter
aims to comprehensively explore the fundamentals of 2D and 3D transistors, design
methodologies, applications across industries, integration challenges and solutions
and comparative analysis with conventional CMOS technologies to assess the advan-
tages and limitations of emerging 2D and 3D FETs, offering insights into their feasi-
bility and scalability in practical applications. “Advancing Semiconductor Devices:
FET Down-scaling and Next-Gen Transistors” represents a critical exploration into

168 DOI: 10.1201/9781003483052-11

Advanced Semiconductor Devices 169

the frontier of semiconductor technology. Through this comprehensive examination,

we endeavor to empower readers with knowledge and insights that can drive inno-
vation and shape the future of electronics. Welcome to the exploration of emerging
2D and 3D FETs and their transformative impact on semiconductor technology and
beyond.
The down-scaling of traditional FET technology is a critical part of semicon-
ductor device development. It entails aggressively reducing device settings while
retaining or boosting performance. This overview will provide an overview of the
down-scaling process, highlighting the approaches employed as well as the obstacles
encountered [1–5].
Two methods exist for scaling FETs: constant voltage scaling and constant field
scaling. In constant voltage scaling, all device dimensions are reduced by a fac-
tor while maintaining a constant power supply and terminal voltage. However, this
approach may result in reliability issues such as oxide breakage and electrical over-
stress. In contrast, constant field scaling involves reducing size and voltage by a fac-
tor while increasing charge densities and doping concentration by the same factor.
This method ensures that the electric field in the transistor remains constant. This
results in an increase in both circuit speed and density [1–16].
FET gate length is an important characteristic in the advancement of FET tech-
nology. It is a critical parameter in the evolution of CMOS circuits. The switching
energy of MOSFETs, which defines their performance, is related to the gate capaci-
tance and the square of the gate-bias. Circuit performance can be increased by short-
ening the gate length [7, 9].
According to data from the International Technology Roadmap for Semiconductors
(ITRS), gate length has decreased rapidly over the years, from 22 nm to less than 10
nm. However, down-scaling is limited by thermal fluctuations when the switching
energy becomes less significant in comparison to thermal energy [10–16].
Down-scaling CMOS circuits has resulted in a rapid decrease in technology
nodes, from 180 nm to 32 nm, 22 nm, and beyond. The 32 nm, 22 nm, and 14 nm
technology nodes are routinely used in volume manufacturing, with 7 nm and 5 nm
nodes still being developed and investigated. Each technology node seeks to maxi-
mize power performance while decreasing transistor density [1–12].
However, shrinking transistors to the nanoscale and beyond involves major
problems. At the device level, issues like quantum tunneling, short-channel effects,
threshold voltage effects, and gate-oxide thickness arise. These difficulties can have
an effect on transistor performance, reliability, and power consumption [5, 7].
Advanced subthreshold-swing devices such as FinFET and Tunnel FET have
been developed to overcome these difficulties. FinFETs are three-dimensional tran-
sistors with increased scalability and resistance to short-channel effects. Major semi-
conductor companies have expressed interest in using them to fabricate nanoscale
CMOS circuits. Tunnel FETs, on the other hand, excel at lowering leakage-current
while having a lower ON-current than conventional MOSFETs [13–15].
The latest review paper presents simulation results for the latest generation of tran-
sistors, such as Tunnel FET, Nanosheet, and FinFET. The purpose of this research
is to evaluate and analyze the efficiency of changes in parameters and dimensions
170 Circuit Design for Modern Applications

suspected of improving the performance of an adequate threshold voltage, allowing

the CPU to run quicker while using less energy [16].

11.2 DOWN-SCALING OF CLASSICAL FET

The down-scaling of FET technology can be defined as the ability to continue for
the next 15 years in parallel with the aggressive reduction of the device parameters
[1]. According to numerous studies and observations, two basic methodologies are
used for scaling FETs. The first is “constant voltage scaling”, which tries to reduce
all device dimensions by a reference factor “α” with the exception of the power sup-
ply and terminal voltage. Various reliability issues, such as oxide breakdown and
electrical overstress, have been discovered in this situation. The second is “constant
field scaling”, in which both the sizes and voltages are downscaled by the factor “α”,
while the charge densities and doping concentration are always increased by the
factor “α”, while the electric field in the transistor stays unaffected. As a result, the
circuit speed is increased with the factor “α”, while the circuit density increases with
the factor of “α2” [2].
Moreover, the progression of FET technology is generally related to the gate length
parameter of the FET, which represents a key parameter for the evolution of CMOS
circuits. In addition, the device switching energy is an important parameter for the
study and the evaluation of CMOS circuit performance. In this context, it should be
noted that the switching energy for the MOSFETs can be equal to Cg × (Vg)2, with
Cg and Vg are the gate capacitance and the gate-bias, respectively. Therefore, the
gate length parameter L combined with the device switching energy gives excellent
characteristics for the down-scaling of FETs. In recent years, targeting better perfor-
mance has been based on ITRS data reports [3]. The gate length of FETs has been
rapidly reduced from 22 nm to below 10 nm. As we can see on Table 11.1 presents
the evolution of the gate length and the switching energy, as described in reference
[3]; by the year 2030, the down-scaling will reach a real limit because of the thermal
fluctuations effect created when the switching energy becomes less important com-
pared with 100 kb < wT, with kb and T are the Boltzmann constant and the tempera-
ture, respectively [16, 17].
Besides, the technology nodes have seen an aggressive reduction from 180 nm to
32 nm, 22 nm and beyond 14 nm [4, 5]. It should be noted that the 32 nm, 22 nm, and

TABLE 11.1
Evolution of the Gate Length and the Switching Energy [3]
Year 2012 2014 2016 2018 2020 2022 2024 2026 2028 2030
Gate length 22 18 15 13 11 9 7 6 5 4
(nm)
Switching 41 21 15 10 7.5 6 4 2 1.5 1
energy
Advanced Semiconductor Devices 171

FIGURE 11.1 Evolution of main technology nodes.

14 nm technology nodes are the most commonly employed in volume manufactur-

ing. Figure 11.1 will illustrate the progression of the main technological nodes over
the period up to 2026. The 7 nm technological node is being developed, and the 5 nm
is being investigated. The goal for each new technological node is to get the optimum
power performance while continuously improving transistor density [1, 18].
In addition, reducing the size of the transistor to the nanometer scale and beyond
creates a number of major issues at the device level: quantum tunneling limit, short-
channel effects (SCE), threshold voltage effect, and gate-oxide thickness. In Table
11.2, we introduce the main issues that appear at the device level [19, 20].
Such advanced technology nodes face serious device and interconnect challenges.
At the device level, there is the problem of the “front end of the line” arising from
short-channel effects [6, 14]. In this scenario, the short-channel devices allow the
transistors to be completely turned off. Another major worry in wiring levels is the
connection delay caused by RC coupling, also known as the “back end of the line”
[7, 15]. In addition, the steadily increasing lithographic patterning barriers represent
a serious challenge related to the growing gap between required and available opti-
cal resolution. For further alternatives, FinFET and gate-all-around transistors are
excellent solutions for future technology nodes.
There are three main options in the logic technologies: low operating power, low
standby power, and higher performance [8, 9, 16]. For the low operating power, the
aim is to increase the circuit performance by minimizing the electrical consumption
parallel to the on-state of the circuit. In the case of higher performance, we need
more complex integrated circuits based on higher clock frequencies. Hence, the tar-
get is to increase the clock frequency from one technology node to the next, which
can be converted at the transistor level by an enhancement of the intrinsic switching
time (switching energy divided by the on-state current multiplied by the gate-bias) of
the transistor by 17% per year. For low standby power, the static power consumption
is governed by the device’s leakage-current. This type of option requires extremely
low transistor off-state currents and low parasitic currents [17].
To achieve these different types of performances, two alternatives are addressed.
The first one is the electrostatic control device, which should be enhanced by moving
from the conventional MOSFETs to advanced FETs such as thin film MuGFETs and
172 Circuit Design for Modern Applications

TABLE 11.2
Main Issues Appear at the Device Level [6–13]
Issue Description
quantum The problem of quantum tunnelling is mainly related to the transistor oxide thickness.
tunnelling Moreover, following ITRS, the reduction in oxide thickness affects the flow of current
limit by the gate. As a result, the oxide thickness is exponentially associated with the gate
current where carrier tunneling via the insulator potential barrier causes a current. In
addition, the barrier distance reduces, and the tunnelling effect increases more quickly
(exponentially) [6, 7].
Short- This issue has been identified as a serious problem limiting transistor down-scaling.
channel When the device channel length is reducing to smaller or equal to 50 nm, various
effects undesirable short-channel effects are observed: drain-induced barrier lowering,
mobility degradation, velocity saturation, and threshold voltage roll-off [8, 9].
Threshold We have to know that the transistor threshold voltage does not decrease compared to
voltage the down-scaling of the transistor. Hence, when the device channel length is strongly
effect reduced to below 50 nm, the threshold voltage current does not become zero instantly,
but it is reduced exponentially, and this decrease is inversely proportional to thermal
energy. Therefore, a higher leakage-current is observed due to the higher threshold
voltage [10, 11].
Gate-oxide There are two principal limitations related to the gate-oxide thickness. The first one is
thickness the thin oxide layer, which increases the leakage-current. This effect is linked to the
tunneling effect that appears when the thickness of oxide is aggressively decreased.
Furthermore, the tunnelling current of the large oxide layer is insignificant compared
to the chip current in the “on state”. Second, since the thickness of the oxide layer is
such that the inversion charge waste and transconductance loss resulting from the
depletion effect of the poly-silicon gate and the quantization effect of the inversion
layer are present [12, 13].

tunnel FETs. The second is higher permittivity gate dielectrics, which are neces-
sary to reduce the gate leakage-current effect and to keep on increasing the gate-to-
channel capacitive coupling. These two topics will be detailed in the next sections
[18–24].
On the other hand, the scaling-down of CMOS circuits is also related to the tech-
nology nodes that are evaluated generally in two-year cadence.

11.3 SUBTHRESHOLD-SWING
Circuit speed improves with increasing ION; therefore, it is probably best to use
a small Vt. Only one cannot arbitrarily decrease the value of Vt. At Vgs < Vt, an
N-channel MOSFET is inside the off-state. However, leakage is a current which can
flow between the drain and the source. The MOSFET modern discovered at Vgs < Vt
is referred to as the subthreshold current or the subthreshold drain-current; it is the
current that flows between the source and drain. It is the principal contributor to the
OFF-state current of the MOSFET, IOFF [18].
Advanced Semiconductor Devices 173

IOFF is the ID measured at Vgs = 0 and Vds = Vdd. This energy intake in CMOS
circuits in large part results from the charging and the discharging of the inner node
capacitances and may be reduced quadratically with the aid of decreasing delivery
voltage Vdd [19–27].

11.4 INTEREST IN SUBTHRESHOLD-SWING
The subthreshold conduction of transistors has previously been smaller, but as tran-
sistors have been scaled down, leakage has become more prevalent. Across a thresh-
old voltage of 0.2 V, leakage can account for 50% of total power consumption [16]. It
is essential to maintain IOFF smaller in an effort to decrease the static energy that a
circuit attracts while in sleep mode. For example, if IOFF is a modest 100 nA in keep-
ing with the transistor, a cell phone chip containing a 100 million transistors could
draw 10 A even on standby. The battery might drain in a couple of minutes without
receiving or transmitting calls. A desktop PC processor could expend more energy
as it includes extra transistors and faces costly chip and device cooling issues. It is
widely recognized that CMOS circuits function at lower voltages and stay practical
even if Vdd drops under the threshold voltage Vth. Recently, there was interest in the
subthreshold operation, to begin with, for analog circuits [24, 25] and more recently
for digital processors, demonstrating operation at Vdd beneath 200 mV [22–29].
Perfecting the slope below the sill:
Recall that the slope below the threshold is defined by :

 nkT 
SS    lnln 10  (11.1)
 e 
 C 
Where   1  dep  is the substrate factor.
 Cox 
Where:

 CSi CSi 

 C   Cox CBox 
  1  si   (11.2)
 COx   CSi 
1 
 C 
 Box 

CSi denotes the capacitance of the completely depleted silicon film.

COX the oxide capacitances.
CBOX, the silicon film capacitances.
Usually, for thin films, CBOX << COX and COX << CSi; therefore, we obtain a value
of n close to the unity and the slope under the optimal threshold.
The slope below the threshold at room temperature is practically a maximum of
60 mV/dec for n = 1.
174 Circuit Design for Modern Applications

FIGURE 11.2 3D structure of a FinFET transistor; horizontal and vertical sections of the
FinFET [25].

11.5 ADVANCED SUBTHRESHOLD-SWING DEVICES

This section examines different types of subthreshold-swing transistors that are can-
didates for rapid development in order to improve the performance of electronic
systems.

11.5.1 FinFET
The FinFET is a 3D device whose structure consists of a vertical silicon film (very
thin). Grid surrounds both sides of “End”, allowing channels to be created on either
side; Figure 11.2 illustrates the three-dimensional structure of a FinFET transistor,
as well as the horizontal and vertical sections of the FinFET [25, 30].
The transistor horizontal portion is comparable to that of a DG-MOSFET, but the
height of the transistor end corresponds to the width of a DG-MOSFET channel. The
production of the FinFET is more compatible with that of the bulk MOSFET than
that with the DG-MOSFET.
In the last 20 years, the FinFET technology has been known as a solid consid-
eration by a variety of companies’ production, such as Intel, TSMC and Samsung,
which are targeting the higher performance of microprocessors below 14 nm [31].
The reason is that FinFET devices are very attractive for the fabrication of nanoscale
CMOS circuits. This kind of transistor provides a better scalability characteristic
due to its exceptional immunity to SCEs. Also, the FinFET device offers better elec-
trical potential control over the channel, which improves the device’s performance
[32–35]. Figure 11.3 a provides an overview of the general cross-sectional structure
of the SOI FinFET.
The subthreshold-swing (SS) defines the transistor transition from the OFF to ON
state and the ratio between the ON- and the OFF-current:

K T
SS  Log 10   (11.3)
q
Advanced Semiconductor Devices 175

FIGURE 11.3 Cross-sectional view of a FinFET.

Where η is the body-factor,  K  T  / q is the thermal voltage, q is the charge of

electron, K is the Boltzmann constant, T is the temperature.
In the case of an SOI FinFET, the body-factor η can be described by the follow-
ing expression [33]:

Coxfb  Csi
  1 (11.4)
Cgf  Cox  Csi   Coxfb  Cox  Coxfb 

Where Cox is the oxide capacitance, Csi is the bulk silicon capacitance, Cgf is the
gate to find capacitance, and Coxfb is the fine-to-bulk capacitance.
Injecting the body-factor of Equation 11.2 in Equation 11.1, we get an approxi-
mated solution for the subthreshold-swing (SS) in FinFET devices as:

1   Coxfb  Csi  K T
  Log 10    (11.5)
C gf  Cox  Csi   Coxfb  Cox  Coxfb  q
Table 11.3 presents the extracted subthreshold-swing parameter for the FinFET
devices.
Figure 11.4 illustrates the impact of varying the number of fins on the ON-current
of SOI FinFET. As the number of fins is increased from 1 to 3, the ON-current exhib-
its a threefold increase.
It should be noted that the SS parameters vary as a function of the fin’s width and
fin’s thickness, as described in Table. 11.4.

TABLE 11.3
Review of SS Parameters of FinFET
References [31] [33] [34] [35]
SS (mV/decade) 74.03 62.5 65 77
176 Circuit Design for Modern Applications

FIGURE 11.4 ON-current (ION) variation as a function of fins’ number, reproduced from
[31].

TABLE 11.4
SS of FinFETs with Different Fins
Geometrical Value SS (mV/decade)
parameter
WNF 30 63
45 56
80 71
150 72
TFIN 4 74
5 87.5
6 102
7 123.5

Table 11.4. Review on SS of FinFET with different fin width (WFIN) and thick-
ness (TFIN).

11.5.2 Tunnel Transistors
The Tunnel FET (TFET) is one of the best transistors for reducing leakage-current.
However, these types of components suffer from minor ON-current compared to the
classical MOSFET devices [28].
Figure 11.5 shows the 2D schematic view of the silicon/Tunnel FET under study.
Where LEXT is the source/drain extension length, TEXT is the source/drain thick-
ness, TOX is the gate-oxide thickness, LG is the gate length and TSI is the channel
thickness. The Vgs and Vds denote the gate-bias and drain-bias, respectively.
Figure 11.6, Shows the drain-voltage characteristics of tunnel double-gate transis-
tors for a week and higher value of the drain-bias (Vds = 0.1 and 1.0 V). Increasing
the drain-bias Vds from 0.1 to 1V, the vertical electrical field became strong. For a
smaller channel thickness (TSI = 5nm), the ON-current is equal to 0.87 and 1.8 mA,
respectively.
Advanced Semiconductor Devices 177

FIGURE 11.5 2D Schematics view of silicon/Tunnel FET.

FIGURE 11.6 Drain-current (Ids) against gate-bias (VGS) of TFET (Device parameters:
LG = 20 nm, LEXT = 20 nm, TOX = 2 nm, and TSI = 5 nm).

FIGURE 11.7 Impact of high-k gate dielectric (HfO2) on the transfer characteristics of
TFET (Device parameters: LG = 20 nm, LEXT = 20 nm, TOX = 2 nm, and TSI = 5 nm).

Moreover, various solutions have been proposed to enhance the ON-current of

TFETs. One such solution is the implementation of a high-κ gate dielectric, as illus-
trated in Figure 11.7, which depicts the impact of a high-κ gate dielectric (HfO2) on
the transfer characteristics of a transistor-field-effect-transistor (TFET). The device
parameters utilized in this illustration are as follows: length of gate (LG) = 20 nm,
length of channel (LEXT) = 20 nm, thickness of oxide (TOX) = 2 nm, and threshold
voltage (TSI) = 5 nm.

11.5.3 Nanosheet
Recently, nanosheet transistors have been proposed as a solid alternative to FinFET
technology for possible CMOS scaling down below 7 nm of technology nodes. The
stacked-nanosheet FETs have been proposed to increase the drivability of the current,
decrease the parasitic capacitances and reduce the short-channel effects [36–42].
178 Circuit Design for Modern Applications

FIGURE 11.8 Cross-sectional view of two channels stacked nanosheet FET.

FIGURE 11.9 Drain-current (Ids) with different drain-bias (Vds) in stacked Nanosheet at
LG = 16 nm, WNS = 14 nm TNS = 7 nm, TSP = 6 nm, and TPHY = 3.2 (HfO2).

The cross-sectional view of two channels stacked-gate nanosheet FET is pre-

sented in Figure 11.8, with WNS as the sheet’s width, TNS the sheet’s thickness,
TSP as the spacing between sheets, TPHY as the physical thickness of the high-k
dielectric. Moreover, the gate length is denoted by LG [42–45].
Figure 11.9 illustrates the drain-current variation in relation to the gate-bias volt-
age (Vgs) of the stacked-nanosheet FET depicted in Figure 11.8. The ON-current is
equal to 42 µA and the subthreshold-slope is more than 63 mV/decade.
Table 11.5 shows a comparison study on the ON-current (ION), OFF-current
(IOFF), ON-/OFF-current (ION/IOFF) ratio and subthreshold-slope (SS) of stacked-
nanosheet FET. The results indicate that these types of devices provide a great value
for ION and a good compromise on the ION/IOFF ratio. Moreover, the nanosheet
FETs exhibit higher values of SS parameters (> 63 mV/decade).

TABLE 11.5
Comparison of ION, IOFF, ION/IOFF Ratio, and SS
Parameter of Stacked Nanosheet FET
ION [µA/µm] ION/ ION ratio [A] SS (mV/decade) Reference
67 2.7 × 107 72 [39]
698 1.2 × 105 70.5 [40]
1408 1.38 × 105 72 [41]
799 2.5 × 107 70 [42]
Advanced Semiconductor Devices 179

11.6 CONCLUSIONS AND PERSPECTIVES

In this study, we conducted simulations on various structures aimed at achieving a
faster transition between the off-state and on-state compared to what is physically
achievable by MOSFETs. We introduced TFETs, Nanosheet, and FinFET structures
as potential alternatives to MOSFETs, considering the continuous reduction of the
subthreshold swing voltage slope. Through a comparative analysis, we found that
TFETs emerged as an excellent option, with potential drawbacks that appear to be
more manageable than those of its competitors [41–48].
FET tunneling, a device that utilizes band-to-band conduction tunneling, shows
promise in achieving a lower current and providing oscillation below the threshold
of 60 mV/dec [42, 43]. When compared to MOSFETs, TFETs offer the advantage of
generating higher driving currents as the supply voltage approaches 0.1 V. However,
TFETs do exhibit a low ON-current, which can be improved by implementing a
gated TFET. The additional gate in a gated TFET contributes to doubling the cur-
rent, thereby enhancing its performance.
In conclusion, our study demonstrates the potential of TFETs as a viable alterna-
tive to MOSFETs, offering faster transition times and improved driving currents at
lower supply voltages. Further research and development efforts should focus on
addressing the limitations of TFETs, particularly in terms of their low ON-current,
through the utilization of gated TFETs. This work opens up avenues for future inves-
tigations in the field of advanced semiconductor devices, paving the way for more
efficient and high-performance electronic components.
Future research may benefit from investigating novel materials, device archi-
tectures, and fabrication techniques that can enhance the performance of TFETs.
Additionally, investigating the integration of TFETs into practical circuit designs and
system-level applications would be valuable for assessing their real-world feasibility
and optimizing their performance characteristics, as summarized in Table 11.6. This
would allow for a comparison of the emerging MOSFET architectures, including
their respective advantages and disadvantages.
As shown in Table 11.7, an overview of the DC performance of NS FETs demon-
strates a comparison of devices with varying nanosheet widths (WNS), gate lengths
(LG), and channel materials. The table presents key parameters such as I_ON/I_OFF
ratios and subthreshold swing (SS) values for different configurations and materials.
As we have seen through the bibliographic study, different results of several archi-
tectures and structures have been presented. Among these structures and materials
presented, we cite Si, SiGe, simulations of TFETs, Nanosheet, and FinFET, which
had already demonstrated well before the start of this work, the possibility of reach-
ing slopes below the thermionic limit of 60 mV/dec at room temperature. However,
no demonstration had then succeeded in exceeding normalized currents (in μA/μm)
of the order of magnitude of unity. Faced with a PiN structure with slopes lower
than the limit of 60 mV/dec, the justification of the operation by band-to-band tun-
nel injection is not necessary. Meanwhile, the devices studied within the framework
have slopes higher than 60 mV/dec and currents much higher than the state of the art
of the time. It is, therefore, necessary to confirm that we are indeed in the presence
180 Circuit Design for Modern Applications

TABLE 11.6
Emerging MOSFET Architectures: Advantages and Disadvantages
Structures Advantages Disadvantages
Dual Planar Larger current Uniformity of silicon thickness
Grid Good channel control conduction Low silicon thickness
Absence of DIVSB effect Alignment of the two grids
FinFET Good control of the conduction channel Difficult lithograph
Manufacturing processes close to that of the Width uniformity
conventional MOSFET Small silicon film width
Self-alignment of grids Corner effect
Possibility of operation in symmetrical and
asymmetrical mode
GAA Excellent conduction channel control The manufacturing process is
Very reduced short channel effect with No not compatible with that of
corner effect the conventional MOSFET
Nanofil Excellent conduction channel control Need for small silicon diameter
MOSFET Very reduced short-channel effect High cost of production
Higher current Half-match issue

TABLE 11.7
An Overview of DC Performance of NS FET (WNS: Nanosheet Width, SS
Subthreshold-Swing, LG Gate Length)
LG WNS Channel ION
Ref (nm) (nm) materiel µA/µm ION/IOFF SSmV/dec
44 12 15 Si – 106 75
44 12 15 Si – 106 85
45 14 25 Si 290.5 – 68.10
45 14 50 Si 283.7 – 10.01
46 7 10 Si 68 2.6*107 71
47 60 135 SiGe 37.6 1.8*105 86

of TFETs and not of MOSFETs; we need to imagine and then carry out character-
izations, making it possible to differentiate the two injection mechanisms [48–56].
Many simulations have been performed with different materials in order to study
TFETs due to their electrical properties. These enthusiastic simulations of a TFET
performed on graphene indicate slopes at 0.19 mV/dec that would cause the blocking
transistor to saturate in less than 50 mV. But with VG = 0 V or a negative gate voltage,
a saturation of at least 100 millivolts has been found [49–66].
After the studies and simulations that we have done, we suggest developing TFETs
due to their multiple advantages. Some studies guess the application of negative
Advanced Semiconductor Devices 181

capacitance technology, according to the study by Wei Cao and Kaustav Banerjee
[51], whose analysis and conclusions provide invaluable NC-FET design guidance
that could not only prevent the further generation of scientifically misleading claims
but also avoid wasting millions of dollars in research and expenditures develop-
ment. Moreover, it could help identify a practical low-voltage operating device that
really operates NC. We will discuss the remaining topics in forthcoming chapters
and volumes.

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 12 Investigation of the
Challenges in Analog/
RF Circuit Design
for Millimeter Wave
Applications and
Possible Solutions
P. Sherly Arunodhayamary, G. Rajakumar,
M. Venkatesh, and A. Andrew Roobert

12.1 INTRODUCTION
This chapter discusses the challenges in CMOS-based circuit design for mmWave
range and THz range applications, and the possible solutions. The frequency thresh-
old at which CMOS technology encounters serious difficulties in radio frequency
(RF) circuit design is not constant; instead, it varies depending on a number of vari-
ables, including the demands of the particular application, circuit design methodolo-
gies, and technology nodes. The following broad observations can be made from the
literature. Up to 10 GHz of frequency the CMOS-based circuits can be designed with
reasonable effort and performance. After a certain frequency, CMOS technology
begins to exhibit notable difficulties; these difficulties usually peak around 30 GHz.
This is where the effects of noise, parasitics, and transistor performance restrictions
increase. From 30 GHz to 100 GHz, CMOS is frequently pushed to its boundar-
ies in the mmWave region, necessitating extremely sophisticated design methods
and cutting-edge technological nodes to attain satisfactory performance. Above 100
GHz, without major performance trade-offs, CMOS technology is widely regarded
as inadequate for many high-performance RF applications in the THz range. Hybrid
solutions or alternative technology are frequently chosen.
In this chapter, a three-stage low-noise amplifier designed for a 60 GHz applica-
tion has been taken as an example to discuss the issues faced in CMOS-based design.
As an alternate solution, the germanium source surrounding gate tunnel FET has

186 DOI: 10.1201/9781003483052-12

Investigation of the Challenges in Analog/RF Circuit Design 187

been designed and suggested based on the characteristics of the tunnel field effect
transistor (TFET).

12.2 DESIGN OF A THREE-STAGE V-BAND LOW-

NOISE AMPLIFIER FOR RF APPLICATIONS
This section presents a three-stage wireless HDMI receiver low-noise amplifier
(LNA). Inductive source degeneration effectively lowers the noise figure in the pro-
posed architecture. Other methods such as dual inductive peaking and stagger tun-
ing are also used. There is evidence of broadband operation between 56 GHz and 69
GHz. At 60 GHz, the LNA produces a noise figure of 4.08 dB and a gain of 33 dB.
It uses a 1.5 V supply and 90 nm CMOS technology to operate at 24.61 mW. The
design is done using the Cadence Virtuoso tool, while the simulation is carried out
using an RF specter.
In RF and microwave circuits, a three-stage cascoded LNA is a high-performance
amplifier architecture that is frequently employed to achieve low noise figures, high
gain, and wide bandwidth. Below is a thorough explanation of how it is configured
and functions:

12.2.1 Configuration Information
As shown in Figure 12.1, a cascoded pair, which consists of two transistors wired
in series, makes up each of the three phases. Whereas the upper transistor func-
tions as a common-gate (FET), the lower transistor functions as a common-source
(FET). The upper transistor increases the output impedance, enhancing gain and
bandwidth, while the lower transistor handles the primary amplification.
Since the noise figure of the first stage of the LNA has the biggest influence on the
overall LNA noise figure, it is optimized for low-noise performance as per Equation
12.1. Thus the inductive source degeneration is used to reduce the noise figure. Stages
2 and 3 are mainly concerned with boosting gain while preserving bandwidth and
stability. In addition to that, stage 3 focuses on the linearity of the LNA.

FIGURE 12.1 LNA circuit diagram.

188 Circuit Design for Modern Applications

 NF2  1 NF3  1  (12.1)

NFTot.  10 log10  NF1  
 Gain1 Gain2 
DC biasing makes sure every transistor is operating in its ideal range. To maintain
the transistor in saturation, FETs must have their gate-source voltage (Vgs) regulated
suitably. Biasing needs to be planned to provide thermal stability and reduce vari-
ances brought on by variations in manufacturing processes or temperature swings.
Resistors are used in biasing networks to set the proper voltages, and capacitors are
used to block DC signals while allowing AC signals to flow.
Input-Matching Network aligns the LNA’s input impedance with the source
impedance, which is typically 50 ohms. In order to maximize power transfer and
reduce reflections, this is essential. Usually makes use of a LC network or quarter-
wave transformer. The output matching network (OMN) matches the load impedance,
which is typically 50 ohms, to the output impedance of the LNA. This guarantees
effective signal transfer to the antenna or later stages. It consists of parts that are
frequently comparable to those in the input-matching network but are adjusted for
the properties of the output stage. Inter-stage matching is used to maintain signal
integrity and strength, the output impedance of each stage is matched to the input
impedance of the following stage.
In order to create resonant circuits that guarantee effective signal transfer across
a range of frequencies, these networks frequently contain capacitors and inductors.

12.2.2 Operation of the LNA

The first-stage transistor’s base, or gate, receives the input radio signal. The signal is
amplified by the common-source/emitter setup. Through the reduction of the Miller
effect (feedback capacitance), the cascode transistor in the first stage enhances the
bandwidth and raises the total gain. After going via an inter-stage matching network,
the first stage’s amplified signal moves on to the second stage, where it is amplified
even further. The procedure is repeated, with stage three offering further amplifica-
tion. This last phase keeps the noise performance intact while increasing the signal
to the required level.
The total noise figure is primarily influenced by the first stage. In order to reduce
noise contribution, low-noise transistors are used, and biasing and matching net-
works are adjusted. Because of the gain that the earlier stages supplied, the noise
added by the later stages is less pronounced. Achieving a wide bandwidth requires
careful consideration of the components that match the networks. The choice of
inductors and capacitors is made to provide wide passbands. Moreover, optimiza-
tion techniques like stagger tuning are used to increase the bandwidth. Thereafter,
we have tuned the multiple three stages to three nearby frequencies. Better isola-
tion between stages is a natural feature of the cascoded configuration, which lowers
the possibility of oscillations and feedback. The design of an LNA is difficult since
it must adhere to a number of specifications, including low noise figure (NF) and
­optimal gain.
Investigation of the Challenges in Analog/RF Circuit Design 189

12.2.3 Simulation Results and Discussion

The S-Parameter analysis results of the LNA are presented in Figure 12.2. The LNA
is considered as a two-port network. The input port is the source and the output port
is the load. The analysis shows, that 60 GHz, 4.08 dB of noise is considered moder-
ate. In order to preserve signal integrity and sensitivity in high-frequency applica-
tions, lower noise values are typically preferred. It can be difficult to obtain a low
noise figure at such high frequencies, though. This number shows that the signal is
moderately noisy due to the LNA.
The amount of the input signal that is reflected back to the source is indicated
by the input reflection coefficient (S11). With an S11 value of –12.55 dB, the LNA
is taking in roughly 94% of the power and reflecting back just about 6% of it. Given
that this is above the minimum allowable value of –10 dB, good input matching is
indicated. Over the frequency range of 57.7 GHz to 80 GHz, the design maintains
S11 below –10 dB, indicating good broadband matching. With a forward gain (S21)
of 33 dB, the input signal has been significantly amplified. Although this high gain
is useful for amplifying weak signals, oscillations, and distortions must be carefully
considered in order to ensure stability and linearity. The amount of the output signal
that is reflected back into the LNA is measured by the output return loss (S22). With
an S22 of 15.2 dB, the output is well-matched since only around 3% of the signal is
reflected. This is a positive outcome, indicating that the amplified signal is efficiently
delivered to the load via the LNA with little reflection.
A measure of linearity, the third-order input intercept point (IIP3) shows how
well the LNA manages strongly interfering signals. The comparatively low IIP3 of
–21 dB indicates that when the LNA is subjected to strong signals, it may cause
noticeable intermodulation distortion. This could lead to a decline in overall perfor-
mance, therefore it’s something to be concerned about, especially in settings with
strong interference signals (Table 12.1).

FIGURE 12.2 Simulation Results of the LNA. a). Noise Figure. b). Input return loss (S11). c).
Forward gain (S21). d). Output return loss (S22). e). Third-order input intercept point (IIP3).
190 Circuit Design for Modern Applications

TABLE 12.1
Comparison of the Proposed LNA with State-of-the-Art LNAs
Freq. S21 NF PDC IIP3
Ref Process Topology (GHz) (dB) (dB) (mW) (dBm)
Kim 65 3 Stage Common-Source 60 30 4.6 8.9 –26
et al.4
Lin 65 3 Stage Cascode 60 20.3 7.6 37.2 –11
et al.5
Wang 130 2 stage differential 60 20 9 7.2 –15
et al.6
This 90 3 stage cascode 60 33 4.08 24.61 –21
work

In this LNA, we have used 90 nm CMOS technology with ideal passive elements.
There are three possibilities to improve the above-mentioned parameters. Additional
optimization techniques can be used or lower technology nodes can be selected or
new active devices can be used.
When we consider the optimization techniques the noise figure can be optimized
by investigating optimization strategies like noise cancellation, employing transis-
tors with reduced noise, enhancing matching networks, or refining the biasing strat-
egy. The input matching can be improved by adjusting the input-matching network
to attain a higher S11 at the designated 60 GHz operating frequency, which will
guarantee less reflection and improved signal transfer. The linearity can be enhanced
by the strategies like linearization, improved biasing, or the use of feedback mecha-
nisms to improve linearity and raise the IIP3 value. To attain a well-balanced LNA
performance appropriate for the intended application, continuous iteration-based
optimization on the design while taking the trade-offs between gain, noise figure,
linearity, and matching into consideration will be helpful.
Another possible strategy to boost the efficiency of your LNA is to reduce the
CMOS size. Transistors that are smaller in size typically possess higher fT values,
which enable them to function at higher frequencies without much loss of stabil-
ity or gain. They have lower parasitic capacitances, which can enhance bandwidth
and lessen signal attenuation to improve high-frequency performance. Lower gate-
capacitance can result from smaller CMOS devices, which can increase transistor
switching speed. They have lower thermal noise. With less junction capacitance and
better control over the channel length, they can have lower nonlinear distortions,
which improves linearity and raises third-order intercept points (IIP3). Moreover,
they usually use less power, which is advantageous for battery-powered or energy-
efficient applications.
For the past three decades, CMOS devices have driven the semiconductor indus-
try due to the continuous growth of semiconductor processing and technology. Over
Investigation of the Challenges in Analog/RF Circuit Design 191

the years, the CMOS device's physical dimensions were reduced to nanometer scale
and further scaling is limited by short channel effects (SCE). To overcome such chal-
lenges, multi-gate devices are proposed which show excellent immunity to SCE and
yield better scalable operations. Still, these multi-gate devices suffer from DIBL and
threshold voltage roll-off effects discussed by Reddick et al. (1995). To overcome
the above problems, recently TFET was proposed which has gained wider signifi-
cance because of its low subthreshold slope and small leakage current. Moreover,
the conventional tunnel FET also suffers from low ON drive current and requires
abrupt junctions for tunneling. To overcome the fabrication challenges posed by the
MOS and TFET devices, a new transistor called halo-doped TFETs which over-
comes reverse short channel effects is proposed to achieve better ON and OFF states
reported by Wang et al. (2004).
Even though the halo doping device has better scalable performance than the
MOSFETs, still it suffers from the low subthreshold slope. To counter the above
challenges, the surrounding gate tunnel field effect transistor (SG-TFET) is pro-
posed, which exhibits a better subthreshold slope of 7 mV/decade and DIBL of 38
mV/V as compared to conventional TFET. Further, most of the research is carried
out investigating the analog performance metrics like transconductance (gm), unity-
gain cut-off frequency (f T ), output-conductance (gd ) and intrinsic gain (gm/gd ) for
the n-type and p-type triple material high-K surrounding gate TFET reported by
Zhang et al. (2006). The impact of geometric variability on the performance of gate-
stacked and silicon-based single halo-doped TM-SG-TFETs (Si-SH-TM-SG-TFETs)
is investigated and proposed for better performance. The effect of the triple material
gate (TMG) and channel engineering approach on the performance of Ge(SRC)-DH-
DD-TM-SG-TFET is studied.
In Tunnel FETs, current is generated by charge carriers entering channel from the
source through band-to-band tunneling and due to this phenomenon, Tunnel FETs
do not suffer from the limitations imposed on subthreshold swing like in conven-
tional MOSFETs. The influence of parameter fluctuations caused by process varia-
tions on the RF stability performance of germanium source dopingless tunnel FET
(DL-TFET) is reported by Kanchan Cecil et al. (2016). The influence of high-k mate-
rial on the RF stability performance of a double gate junctionless FET is studied
and proposed an optimized structure for better RF performance. Most of the studies
focused on analyzing the behavior of TM-SG-TFETs with and without high-k mate-
rials for improving the DC and analog performance but not on the stability aspects
of the device reported by Tirkey et al.20
In the following section, we have analyzed the RF stability performance of the
Ge(SRC)-DH-DD-TM-SG-TFET for Al2O3/TiO2 high-K dielectric material. Further,
the effect of geometrical variations toward the critical frequency is also analyzed
for proposing the optimized device. The second configuration describes the issues
and problem statements of the proposed structure. The third configuration describes
the RF stability performance of the Ge(SRC)-DH-DD-TM-SG-TFET for Al2O3/TiO2
high-K dielectric material
192 Circuit Design for Modern Applications

FIGURE 12.3 (a) Schematic representation of a germanium source dual halo dual dielectric
triple material surrounding gate tunnel field effect transistor. (b) 3D ATLAS TCAD device
simulator of the proposed device. (c) Silvaco ATLAS simulated mesh profile of Ge(SRC)-
DH-DD-TM-SG-TFET considered for simulation.

12.3 GERMANIUM SOURCE SURROUNDING GATE

TUNNEL FET FOR RF APPLICATIONS
Figure 12.3(a) Shows the schematic of the proposed Ge(SRC)-DH-DD-TM-SG-
TFET structure with dual halo and dual high-K (Al2O3/TiO2) dielectric material.
The modeling of the device is carried out using a 3D Silvaco ATLAS TCAD device
simulator. The device is composed of triple metals with different work functions
by using gate work function engineering techniques for tunneling phenomena to
take place. The device layer is halo-doped with a concentration of 1.2 × 1018cm–3.
Titanium dioxide and aluminum oxide used as dual dielectrics on either side of the
gate enables high fringing fields to penetrate into the device layer, thereby increasing
the ION. The 3D ATLAS TCAD device simulator of the proposed device is shown
in Figure 12.3(b). Silvaco ATLAS simulated mesh profile of Ge(SRC)-DH-DD-TM-
SG-TFET considered for simulation is depicted in Figure 12.3 (c).

12.3.1 RF Stability Performance of Ge(SRC)-DH-DD-TM-SG-TFET

The RF stability parameter depicts the capability of the transistor to operate in high-
frequency applications. This can be achieved by calculating the Stern stability factor
(K), which specifies whether the device is unconditionally stable or conditionally
stable. If K is greater than 1, then the transistor is unconditionally stable, otherwise,
it is conditionally stable, which leads to oscillations at some frequency. Equation
12.2 given in terms of Y parameters is used to calculate the K of a transistor.

2 Re(Y11 ) Re(Y22 )  Re(Y12 Y21 )

K (12.2)
| Y12 Y21 |
where, Y11 and Y22 are admittances, Y12 and Y21 are known as transfer admittance of
a two-port network.

Y11  2 (R gsC2 gs  R gd C2 gd )  j(Cgs  Cgd ) (12.3)

Investigation of the Challenges in Analog/RF Circuit Design 193

Y12   2 R gd C2 gd  jCgd (12.4)

Y21  gmi  2 R gd C2 gd  jCgd  gmi (12.5)

Y22  gdsi  j(Cgs  Cgd )  2 R gd C2 gd (12.6)

Substituting Equations 12.3 to 12.6 in Equation 12.2 will further simplify the K,
which is given by Equation 12.7,

(R gsgdsC2 gg  2R gd gm Cgg Cgd  C2 gg )

K (12.7)
Cgd 22gm C2 gg  g2 m

Critical frequency (f k) is one of the key RF performance parameters, specifying at

what frequency the device attains unconditionally stability. Substituting the K = 1 in
Equation 12.8 along with some approximations is simplified in Equation 12.9 which
is used to calculate the f k of the device in terms of various parameters.

fT U
fk  (12.8)
gdsgm R gs V  UV(gm R gd  1)
2

where, f T is the unity-gain cut-off frequency, which is one of the important metrics
of analog characteristics of the device, specifies the frequency at which the current
gain reaches unity and is expressed as,

gm
fT  (12.9)
2Cgg

Cgs
U= (12.10)
Cgg

Cgd
V= (12.11)
Cgg

Cgs  Cgsi  Cfext  Cfint (12.12)

Cgd  Cgdi  Cfext  Cfint (12.13)

The other parameters mentioned in Equation 12.8 are output-conductance (gds),

gate-source resistance (Rgs), gate-drain resistance (Rgd ), gate-capacitance (Cgg),
194 Circuit Design for Modern Applications

gate-source capacitance (Cgs) and gate-drain capacitance (Cgd ) without taking into
account of overlap capacitance.
The internal fringing field (Cfint) as well as the external fringing field (Cfext) is
expressed as

 WGe (SRC)  t Ge (SRC)   effox , Al2O3  TiO2  

Cfint   ln  1  sin    
3  Ge (SRC)
  2t effox , Al2O3  TiO2 2    (12.14)
2
((Vgs  VFB 2 f  Vds )/ 3 / 2 f
e

 2Weffox , Al2O3  TiO2  t gate 

Cfext   ln  1   (12.15)
 3   2 t ,
effox Al2 O3  TiO2  

Here, Ɛeffox,Al2O3-TiO2 and ƐGe(SRC) are dual high-K dielectric constants of gate oxide
and germanium source materials. Where W, tGe(SRC), teffox,Al2O3-TiO2 and tgate are germa-
nium width, germanium source thickness, effective oxide thickness, and gate mate-
rial thickness of titanium dioxide and aluminum oxide, respectively. Φf and VFB are
Fermi potential and flat band voltage, respectively.
The energy band profile of Ge(SRC)-DH-DD-TM-SG-TFET and Silicon-based
Single halo TM-SG-TFET in OFF state is presented in Figure 12. 4(a). The energy
gap between the valence band and conduction band is more, due to which tunneling
probability of charge carriers through the tunneling region is negligible. Hence, the
current flow in the device is small and is only due to the leakage current flowing in
the P+–I–N+ diode. The ON-energy band profile is shown in Figure 12.4(b), it clearly
shows that the narrow bandgap present between the channel and source, due to which
tunneling width (λ) is small, subsequently the tunneling rate of the electrons flowing
from source to channel is increased and thereby increasing the device ON current.

FIGURE 12.4 (a) Off-State Energy Band Profile (Vgs = 0 V and VDS = 1 V) and (b) On-State
Energy Band Profile (VGS = 1 V and VDS = 1 V) conditions For Ge(SRC)-DH-DD-TM-SG-
TFET as well as Si-SH-TM-SG-TFET at 1 nm.
Investigation of the Challenges in Analog/RF Circuit Design 195

It is reported that for TFET devices, ON current can be improved with the use of
high-k materials as gate dielectric. Even though the high-k gate dielectrics give bet-
ter device characteristics, but they also lead to dielectric/silicon interfacing defects
when they are placed over the silicon surface. These interface effects are taken into
consideration during the device simulation. TiO2 (Ɛr = 80) and Al2O3 (Ɛr = 9) are
the dual dielectric high-K materials considered for the simulations with an effective
oxide thickness of 2 nm.

12.3.2 Results and Discussion

The transconductance (gm) plays an important role in high-frequency applications
because it describes the device’s amplification capability. The transconductance
(gm) and transconductance generation factor (TGF V–1) is shown in Figure 12.5.
Transconductance (gm) is defined as the change of drain current with respect to a
change in gate-to-source voltage (VGS ). The peak of the transconductance should be
high enough at the bias point to achieve high-frequency applications. Ge(SRC)-DH-
DD-TM-SG-TFET shows a higher peak in transconductance and TGF V–1 as shown
in the plot. The transconductance increases very small in the linear region due to a
small variation of drain current and decreases in the saturation region because of
mobility degradation. The TGF or transconductance to drain current ratio (gm/Ids)
shows the efficiency of current to transconductance conversion.
The analog/RF performance is analyzed by RF Figure of Merits (FoM) param-
eters such as gd, gd/VGS, ft, and f max. Also, the reduced capacitance improves the
device’s RF applications. Figure 12.6. shows the comparison of gate-capacitance
(Cgg) and gate-to-drain capacitance (Cgd ) as a function of gate-to-source voltage
(Vgs) of Ge(SRC)-DH- DD-TM-SG-TFET and Si-SH-TM-SG-TFET. It is observed
that Cgg and Cgd of the proposed germanium source halo-doped TFET is less than
the silicon-based halo-doped TFET at the operation gate-to-source voltage (Vgs).
Due to the improved performance of f T, Cgg and gm with a high-k gate dielectric,

FIGURE 12.5 Plot of transconductance (gm) and transconductance generation factor (TGF
V–1) of Ge(SRC)-DH-DD-TM-SG-TFET and Si-SH-TM-SG-TFET at VDS = 1 V.
196 Circuit Design for Modern Applications

FIGURE 12.6 Plot of output transconductance (gd ) as a function of VDS for Ge(SRC)-DH-
DD-TM-SG-TFET and Si-SH-TM-SG-TFET at two fixed bias VGS = 0.4 V and 1 V.

TABLE 12.2
Performance metrics of a Ge(SRC)-DH-DD-TM-SG-TFET for Different
High-K Dielectric Materials at VCGS = VDS = 1V
High-k dielectric ION gm Cgg fT fk
materials (µA/µm) (µS) (fF) (GHz) (GHz)
SiO2 0.1 0.5 2.69E-01 2.6 8.5
Al2O3 0.5 3.09 3.75E-01 4.31 150
ZrO2 5.71 28.4 4.95E-01 24.5 270
TiO2 34.9 145 6.33E-01 150.7 330

Ge(SRC)-DH-DD-TM-SG-TFET with high-k gate material (TiO2) yielded higher f k

which is calculated using Equation 6.9 as compared to low-k gate material (Al2O3).
From Figure 12.4, f k is 150 GHz for low-k gate oxide material (Al2O3) and 330
GHz for high-k gate oxide material (TiO2). Various parameters which have an effect
on the stability and f k for various oxide materials are presented in Table 12.2.

t effox ,Al2O3 TiO2 t Ge (SRC) Ge (SRC)

Ge(SRC)  (12.16)
effox , Al2O3 TiO2

Figure 12.7(a and b) shows the plot of maximum frequency of oscillation (fmax) and
gain bandwidth product against gate-to-source voltage (Vgs). It is defined as the fre-
quency at which point the power gain is unity. The f max depends on the ft and Cgd
as shown in the above plot. To achieve high f max, ft should be high and parasitic
capacitance should be minimum. The proposed device Ge(SRC)-DH-DD-TM-SG-
TFET exhibits a higher peak in maximum frequency of oscillation compared to
Investigation of the Challenges in Analog/RF Circuit Design 197

FIGURE 12.7 Plot of (a) maximum frequency of oscillation and (b) product of gain band-
width for both a Ge(SRC)-DH-DD-TM-SG-TFET and a Si-SH-TM-SG-TFET at VDS = 1 V.

Si-SH-TM-SG-TFET. The tunneling process in TFET devices is greatly affected by

the variation of gate oxide thickness (teffox,Al2O3/TiO2), this effect is noticed due to the
variation of gate-capacitive coupling with a variation of effective oxide thickness.
As per WKB approximation, oxide thickness affects the tunneling probability by
modulating the tunneling width. Equation 12.16 gives the dependency of tunneling
width in terms of gate oxide thickness and other parameters. A thinner gate oxide
will reduce tunneling width (λ) and vice versa occur for thicker gate oxides. Through
simulation, it is also observed that irrespective of gate oxide materials, Ge(SRC)-
DH-DD-TM-SG-TFET exhibits improved ION with the scaling of the teffox,Al2O3/TiO2
and simulated values are shown in Table 6.3.

12.3.3 Possible Performance Improvements in LNA through Ge-SG-TFET

Germanium (Ge) has superior electron mobility in comparison to silicon, potentially
leading to reduced noise figures. The band-to-band tunneling mechanism used by
TFETs can lessen subthreshold swing and minimize thermal noise. This can greatly
enhance the LNA’s noise performance. Better electrostatic control over the chan-
nel is made possible by the surrounding gate structure, and this can result in more
accurate impedance matching. Ge-SG-TFETs’ high transconductance can lower the
input reflection. Germanium’s material qualities and the surrounding gate structure
can support greater drive currents, which raises the forward gain (S21). A high cur-
rent efficiency from the tunneling mechanism can lead to an increase in the LNA’s
total gain. Better output return loss can be achieved by enhancing the output match-
ing network with higher transconductance and better electrostatic control (S22).
By lowering reflections, the surrounding gate structure can produce stable output
characteristics. The third-order input intercept point (IIP3) can be enhanced by the
TFETs’ intrinsic tunneling process, which lowers some nonlinearities. Moreover,
germanium has better electrical characteristics than silicon, using it can further
improve linearity.
198 Circuit Design for Modern Applications

The difficulties in the Ge-SG-TFET-based LNA design and implementation also

need to be focused on. Compared to conventional silicon-based devices, Ge-SG-
TFETs are more difficult to construct, which could raise production costs and com-
plexity. It is necessary to make considerable changes to the fabrication methods in
order to incorporate these cutting-edge devices. It is essential to guarantee the long-
term stability of the device, particularly in high-frequency applications. To preserve
performance and stop deterioration over time, effective thermal management is
required. Currently, the process design kit is not directly available from the foundry.
Thus, the custom-designed transistor as discussed above is used as the library file or
an equivalent circuit or SPICE model or Verilog-A model in the circuit design tool
and the parameters are analyzed.

12.4 CONCLUSION
In this chapter, the design and optimization methods for a 60 GHz LNA have been
examined, with particular attention to important performance indicators like linear-
ity, noise figure, input reflection coefficient, forward gain, and output return loss. The
difficulties in designing high-frequency LNAs and methodical ways to solve them
using sophisticated circuit design and optimization techniques have been discussed.
In order to improve the performance of the LNA, we also investigated the possibility
of switching to lower nanometer (nm) technology nodes. Smaller technology nodes
have benefits like lower parasitic capacitances and faster electron mobility, but they
can have drawbacks like more flicker noise and process fluctuations. A strict layout
and sophisticated circuit design can help to minimize these problems and maximize
the advantages of lower nm technology.
Furthermore, we have investigated the influence of dual halo dual high-k dielec-
trics on the analog/RF stability performance of 40 nm channel Ge(SRC)-DH-DD-
TM-SG-TFET. From the simulation results, it is observed that the device with low-k
(Al2O3) dielectric attains stability at lower frequencies, but yields low ON current.
It is also noticed that high-k dielectric (TiO2) is responsible for obtaining lower fk.
In addition, the effect of geometrical variability toward fk is studied and results
show a decreasing trend with the increase in channel length, and effective gate oxide
thickness, but an increased trend for drain voltage. The practical elements of device
modeling and bringing it to the circuit simulation have been discussed.

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 13 Performance Analysis
of an Inner Gate
Vertical TFET
K. Kalai Selvi, K.S. Dhanalakshmi,
Sathashivam G, and K. Lakshmi Narayanan

13.1 INTRODUCTION
In the realm of semiconductor technology, the search for transistors that can oper-
ate efficiently at lower voltages while maintaining high performance continues to
drive innovation. The inner gate vertical tunnel field-effect transistor (IGV-TFET)
represents a promising advancement in this pursuit, offering potential benefits such
as reduced power consumption, enhanced speed, and improved reliability compared
to conventional metal oxide semiconductor field-effect transistors (MOSFET). This
chapter, “Performance Analysis of an Inner Gate Vertical TFET”, delves into the
fundamental principles, design methodologies, performance analysis, and potential
applications of IGV-TFETs. This introduction establishes the motivations, scope, and
objectives that guide the exploration of this novel transistor architecture. Traditional
MOSFET technology faces challenges as it scales down to nanometer dimensions,
including increased leakage currents and power dissipation. The emergence of
TFETs, leveraging quantum tunneling effects for transistor operation, offers a path-
way to overcoming these challenges by enabling operation at lower supply voltages
and reducing OFF-state leakage. This chapter seeks to contribute to the advancement
of semiconductor research [19] and development by providing a comprehensive over-
view of inner gate vertical TFET technology. By synthesizing theoretical insights
with practical applications, it aims to inspire researchers, engineers, and students
to explore and harness the full potential of this transformative transistor architec-
ture. “Performance Analysis of an Inner Gate Vertical TFET” represents a pivotal
exploration into the frontier of semiconductor technology, where innovative tran-
sistor architectures promise to redefine the capabilities of future electronic devices
[20–23]. Through this exploration, we aim to empower readers with knowledge and
insights that can drive innovation and contribute to the evolution of semiconductor
technology. Welcome to the journey of exploring Inner Gate Vertical TFETs and
their transformative potential in electronic design and applications.
Thermionic emission is used in a conventional MOSFET. It is a process of the
emission of electrons from the source region over a channel barrier to the drain on

DOI: 10.1201/9781003483052-13 201

202 Circuit Design for Modern Applications

the application of sufficient gate voltage [1]. MOSFETs suffer from a high subthresh-
old swing value of 60 mV/dec – the Boltzmann limit [2]. Subthreshold swing (SS)
is limited by thermionic emission. Subthreshold swing is one of the key parameters
measuring the turn-ON capability of the MOSFET. The higher the SS value, the
greater is the drive voltage needed to induce a change in drain current. This puts the
constraint on voltage scaling hence device scaling. The tunnel field-effect transistor
overcomes this constraint, it has SS < 60 mV/dec [3]. The basic structure of Tunnel
FET is a PIN diode with the source being a p-type material, channel intrinsic and
drain n-type material in contrast to MOSFET being a NPN transistor. TFET has
an asymmetric structure while MOSFET is symmetric. The mechanism of charge
transportation in TFET is governed by band-to-band tunneling (BTBT) [4]. Band-to-
band tunneling is a carrier injection process whereby the carrier transit from source
to channel is induced by applying a sufficient gate bias which lowers the barrier
between the valence band of the source and the conduction band of the channel.
Reducing the electrical thickness of the barrier in TFET enables electron flow rather
than lowering the barrier height in MOSFET. TFET can act as a P or N type depend-
ing on dominant carriers – holes or electrons respectively in the channel. Lateral FET
structures have reached their maximum scaling and have evolved as short-channel
devices, the increased functionalities in those devices have led to increased power
dissipation [5]. Short-channel effects occur when channel length roughly matches
the source and drain depletion widths [6]. Roll-off in threshold voltage and drain-
induced barrier lowering are the two main short-channel effects. Threshold voltage
rolls off – as channel length decreases, the voltage at which the transistor is switched
to ON-state changes [7]. This change can lead to variations in the transistor’s perfor-
mance and behavior. Drain-induced barrier lowering (DIBL) – refers to field penetra-
tion from the drain toward the source as drain voltage increases. Due to the reduced
barrier height at the drain, there is an injection of electrons from the source to the
drain without gate control [8]. In short-channel transistors, DIBL becomes more sig-
nificant, leading to increased leakage current. Mitigating the short-channel effect is
an important requirement in semiconductor technology advancement. Researchers
work on developing new materials, device structures, and fabrication methods to
overcome the challenges associated with the scaling of transistors while maintain-
ing reliability and performance. As per the recommendations of the International
Roadmap for Devices and Systems 2020 vertical structures can support increased
functionalities. Vertical Structures doesn’t suffer from the short-channel effect as it
has no limitation on channel length.
This chapter presents a Vertical TFET structure with an inner single gate in the
channel, high-k dielectric material HfO2 as gate oxide & low k SiO2 material in the
drain region.

13.2 DEVICE SCALING
The need for functionalities in devices has led to shrinkage or scaling of devices.
Reduction in device dimensions forced the engineers to reduce the voltage, and cur-
rent. The scaling of devices is classified as
Performance Analysis of an Inner Gate Vertical TFET 203

Constant field scaling or full scaling: In this type all the parameters of the
device such as physical and electrical parameters are scaled. Let us consider the
scaling factor as “S” whose value is greater than 1 (S > 1) now assumes all the
parameters of the device are scaled by scaling factor “S” then all parameters will get
changed to a reduced value. For example, if the original gate length is “L”, threshold
voltage Vth, current I, power dissipated Pd then after scaling the transformed values
are L’ = L/S, threshold voltage Vth’ = Vth/s, Current I’ = I/s, Power dissipated Pd’ =
Pd/s2, respectively.
Constant Voltage Scaling: This type of scaling reduces the physical parameters
of the device like the gate length, and applied electrical parameters are kept constant.
For example, if the original gate length is “L”, threshold voltage Vth, current I, power
dissipated Pd then after scaling the transformed values are L = L/S, threshold voltage
Vth’ = Vth, Current I’ = s*I, Power dissipated Pd’ = s*Pd, respectively. Constant voltage
scaling results in a short-channel effect in the field-effect transistor.
Lateral Scaling: In this scaling only the width of the channel is reduced. It’s
commonly called a gate shrink. The impact of this is an increase in the electric field
in the channel. A high electric field endows charge carriers with high energy. These
high-energy charge carriers can knock the electrons from the atoms and can damage
the device.
Some of the scaling difficulties are gate leakage current, depletion caused by
polysilicon gate, and short-channel effects. Gate leakage current arises due to thin
SiO2 used as dielectric materials. It can be alleviated by replacing SiO2 with high-
k materials that have sufficient thickness to resist leakage [9]. The depletion layer
formed in polysilicon on the application of sufficient bias increases the thickness of
the dielectric layer and affects the device characteristics like drain current. Metal
gates overcome the polysilicon depletion effect as it has high carrier density and a
depletion depth of only 0.5 Å [10]. Short-channel effects are predominant in struc-
tures that have been constructed in the lateral direction. A two-dimensional potential
distribution and a large electric field in the channel region are caused by drain and
gate bias in longitudinal and transverse directions, respectively, due to a reduction in
channel length. Due to the two-dimensional potential variation, the threshold voltage
is altered. This variation of the threshold voltage due to a reduction in channel length
affects the design of the device. Vertical structures have a channel length of more
than 50 nm [11]. Hence it does not suffer from short-channel effects.

13.3 NEEDS OF AN TUNNEL FET STRUCTURE

AND WORKING PRINCIPLE
Metal oxide semiconductors work on the principle of thermionic emission of elec-
trons where the energy barrier is controlled by the gate voltage, hence called field-
effect transistor. As MOSFET relies on thermionic emission, this mechanism puts
constraints on the subthreshold swing and ultra-sharp doping profiles are difficult to
achieve. Conventional MOSFETs suffer from high power consumption due to therm-
ionic emission. Different MOSFET structures like junctionless FET and Tunnel FET
have evolved to overcome this constraint. In Tunnel FET power consumption is kept
204 Circuit Design for Modern Applications

FIGURE 13.1 (A) Structure of a MOSFET.

FIGURE 13.1 (B) Structure of a Tunnel FET.

within limits due to the tunneling mechanism. Figs 13.1(a) and 1(b) illustrate the
structure of MOSFET and Tunnel FET respectively. When the driving voltage Vgs =
0 in a Tunnel FET, the valence band of the source and conduction band of the chan-
nel are not aligned in an off state, and the energy gap between them is sufficiently
large to prevent the charge flow, in contrast to, on condition when Vgs > Voff band
alignment occurs and the energy separation is reduced enabling the flow of charges
from source to channel. The probability of tunneling of electrons depends on the
height of the energy barrier and tunneling width. Reduction in height and width
of the energy barrier enhances the transportation of charges. The absence of band
alignment in the off state prevents the tunneling of charges. This in turn reduces
leakage current. The increase in drain current on the application of gate voltage is
quantified by subthreshold slope. Subthreshold slope’s counterpart is subthreshold
swing. Subthreshold swing is the gate voltage Vgs needed to alter the drain current by
a factor of 10 as shown in Equation 13.2. Subthreshold swing is measured in mV/dec.
SS < 60 mV/dec in Tunnel FET makes it feasible to reduce gate voltage, supply volt-
age, reduction in power consumption and enable scaling beyond 10 nm. Even though
the TFET has good switching characteristics it suffers from less ON-current. This
setback can be reduced by implanting a pocket in the source, using high-k dielectric
material, reducing oxide thickness, and using low bandgap materials.

13.4 LATERAL VS VERTICAL STRUCTURE

All MOSFET and Tunnel FET structures have been constructed as lateral structures.
Lateral structures have reached the scaling limits. The lateral structures of an inte-
grated circuit restrict the amount of transistors that can be built because they take
up a lot of space. Device scaling led to a reduction in gate length. Suppression of
gate length led to short-channel effects to continue scaling and follow Moore’s law
and to reduce short-channel effect vertical structures can be designed. By dictating
the current flow in a vertical direction, the area of the device is reduced in a lateral
Performance Analysis of an Inner Gate Vertical TFET 205

FIGURE 13.2 (A) Lateral FET structure.

FIGURE 13.2 (B) Vertical FET structure.

direction. This allows the integration of more transistors in the devices. Figures
13.2(a) and 2(b) show the FET structures both in lateral and vertical orientation
respectively. Fabrication of vertical structures is easy compared to lateral structures.

13.5 IMPACT OF CHANNEL LENGTH

Short-channel devices require less threshold voltage – gate voltage that turns on
the device. In short-channel devices, the conduction band maximum is less than in
long-channel devices. Hence the amount of Vgs supplied to push down the conduction
band in short-channel devices is less than the other one. This results in a change in
the threshold voltage. Leakage current arises from a lower threshold voltage since
off current is inversely correlated to length. As the length of the channel decreases,
the distance between the drain and channel decreases hence capacitance increases in
accordance with Equation 13.1.

C  q / V   0A / d (13.1)

q – is the charge on plates, ε0-free space permittivity, A – area of the plate, and d –
distance between plates of the capacitor. An increase in capacitance at the drain is
an undesirable phenomenon. So a long-channel device is one of the solutions for this.

13.6 STRUCTURE OF INNER GATE VERTICAL

TUNNEL FIELD-EFFECT TRANSISTOR
The cross-sectional view of a vertical TFET suggested in this chapter is depicted in
Figure 13.3. The proposed structure is an inner gate TFET structure with silicon as
206 Circuit Design for Modern Applications

FIGURE 13.3 Cross-sectional view of inner electrode vertical TFET structure.

the source, channel and drain material. High-k HfO2 (k = 25) is used as the dielectric
material in the channel region. In analogous to bipolar junction transistor source
being a supplier has a large area in FET, the drain region is reduced as it collects the
charges. To maximize depletion, a thin channel region is incorporated [12]. Double
gate structures are in existence due to the good control over the charges [13]. In con-
trast to a double gate, a single inner gate is used in the proposed structure as it acts
as a common gate of the entire region to provide better control over the channel. The
suggested TFET is an n-TFET with an n-type drain region, intrinsic (i) region, and
P-type source region.
The design values used in the simulation of the device are source dopant con-
centration – 5 × 10 ^ 20 cm– 3, drain concentration-1 × 10 ^ 18 cm– 3, and channel
concentration-1 × 10 ^ 16 cm– 3. The dimensions of the proposed structure are a
gate length of 50 nm, a source length of 50 nm, drain length of 28 nm. HfO2 of
3 nm thickness is used as a dielectric material. The device dimensions are listed
in Table 13.1. The performance of the suggested structure is examined in terms of
energy bands, different dielectric materials, inner vs outer gate, variation in work
function, input gate voltage, and DIBL.

TABLE 13.1
Device Parameter Dimensions Considered in Simulation
Parameters Dimension Concentration
Source length 50 nm 5 × 1020 cm– 3 (p-type)
Gate length 50 nm 1 × 1016 cm– 3 (p-type)
Channel length 50 nm
Drain region length 28 nm 1 × 1018 cm– 3 (n-type)
Dielectric (HfO2) 3 nm
Width of channel 20 nm
Performance Analysis of an Inner Gate Vertical TFET 207

The DC and AC characteristics of the proposed structure were examined using

the ATLAS Silvaco TCAD tool.

13.7 ENERGY BAND
Electrons orbiting the nucleus in an atom occupy specific discrete levels of energy
called energy levels. A large number of atoms makes up a solid material. Large
energy levels contributed due to the large number of atoms making up energy bands.
Two energy bands are present in solids-conduction and valence bands. The valence
band comprises low-energy electrons and the number of low-energy electrons is
more. In contrast, the conduction band comprises high-energy electrons and its quan-
tity is less at thermal equilibrium. Band-to-band tunneling relies on quantum theory.
Quantum theory describes how electrons behave as waves. A quantum wave will
not vanish when it hits a barrier; instead, its amplitude will drop exponentially. The
likelihood of discovering a particle inside the barrier drops as a result of the dimin-
ishing amplitude. The amplitude might not be zero on the other side if the barrier is
narrow. The likelihood that some of the particles may tunnel through the barrier is
finite. Figure 13.4 shows the tunneling effect.
Electrons in a TFET migrate from the valence band of the source to the conduc-
tion band of the channel due to the quantum tunneling phenomenon, provided that a
thin energy barrier separates the valence and conduction bands. Figure 13.5 displays
the energy band profile of the suggested device in both the on and off states. Charge
flow is inhibited by the tunneling energy barrier, which is wider in the off-state than
it is in the ON-state. The barrier width is reduced by the application of gate voltage,
causing tunneling.

13.8 IMPACT OF HIGH-K MATERIAL HFO2

The dielectric constant, denoted by the characters ε (epsilon) or k, is a fundamental
property of a material that describes its ability to store electrical energy in an elec-
tric field. Another name for it is relative permittivity. The dielectric constant is a
dimensionless quantity that says how a material responds to an applied electric field.
The capacitance of a capacitor is directly correlated with its dielectric constant. A
dielectric substance inserted between a capacitor’s plates causes the capacitance to

FIGURE 13.4 Tunneling effect. Image credits: Wikipedia.

208 Circuit Design for Modern Applications

FIGURE 13.5 Energy band profile in on and off state of the proposed device.

increase by a factor equal to the dielectric constant. Substances with a high dielec-
tric constant are often used in capacitors to increase their energy storage capacity
[14]. Mostly SiO2 has been used as a dielectric for MOSFET. The thickness of the
dielectric layer SiO2 was reduced to increase oxide capacitance to improve current.
However, SiO2 has lost its significance as the leakage current raised to 1 A/cm2
when its thickness was reduced to less than 1.5 nm. So, in search for thick and high
dielectric materials, it led to HfO2. It has a high dielectric constant (k = 25) greater
than SiO2 (3.9). The increased thickness doesn’t reduce the oxide capacitance as its
high-k value, hence high current can be obtained. The use of HfO2 enhances the
ON-current due to high charge holding capacity. ON-current of 10 –5A/μm and 10 –
7A/μm is obtained for HfO and SiO dielectrics in the gate, respectively. An increase
2 2
in current is required to obtain a low SS value. The electric field distribution is shown
in Figure 13.6 for SiO2 and HfO2 dielectric materials.

FIGURE 13.6 Electric field along the channel for inner electrode TFET with HfO2 and SiO2
dielectric material.
Performance Analysis of an Inner Gate Vertical TFET 209

13.9 IMPACT OF SIO2 IN THE DRAIN

One way to lessen gate oxide leakage is to use high-k materials. Since it has suffi-
cient thickness to prevent gate oxide tunneling. But at the drain region the unwanted
gate drain capacitance has to be lowered. For efficient depletion of charges a thin
channel is used in the device. New device structures are required to reduce leakage.
In the proposed device, drain thickness equivalent to channel thickness is designed
as charges directed in the channel region get collected in the drain. Insulators placed
in the drain region reduce the leakage. In this chapter, SiO2 is used as an insulator to
avoid leakage and helps in the collection of charges without scattering as the drain
area is reduced. As said low k material reduces the capacitance, and drain capaci-
tance can be lowered by using SiO2. The Off current obtained for SiO2 in the drain
region is in the order 10 ^ –18 A/µm whereas in the absence of an insulator it is 10
^ –5 A/µm. ON-current in the order of 10 ^ –5 A/µm is obtained for the proposed
device. A negligible amount of ON-current is obtained in the case of a large drain
area VTFET.

13.10 IMPACT OF EXTERIOR AND INNER GATE IN THE VTFET

In this chapter, a VTFET with inner gate was designed and compared with an exte-
rior gate VTFET. The VTFET structure with a single work function exterior gate has
a threshold voltage of 0.938 V [15]. The aims of designing nanostructures are not
only device scaling but also to obtain a reduced threshold voltage of 0.4–0.6 V, less
OFF-current and enhanced ON-current. The proposed structure has a threshold volt-
age of 0.45 V. The obtained threshold value implies that the inner gate requires less
drive voltage to turn on the device. Moreover, it uses a single gate to obtain control
over the channel.
According to Equation 13.2, subthreshold swing (SS) is the gate voltage needed to
cause a tenfold shift in drain current.

dVg
ss  (13.2)
d ln I d 
Vg being the gate voltage supplied, Id the drain current. SS is a key parameter measur-
ing the turn-ON capability of the MOSFET. The proposed design has a subthreshold
swing of 14 mV/dec. This has been accomplished by optimizing the design using
the inner gate to have an excellent channel control, compared to the exterior gate
VTFET having SS of 34.12 mV/dec [15].

13.11 EFFECT OF WORK FUNCTION VARIATION (WF)

Equation 13.3 describes the work function, which is the amount of energy needed to
remove an electron off the surface of a material and put it in a vacuum [16].

  Evac  EF (13.3)
210 Circuit Design for Modern Applications

EF is the Fermi energy and Evac is the vacuum energy level. The threshold voltage
of the FET is determined by the metal-semiconductor work function in accordance
with Equation (13.3). Reducing the work function difference between the semicon-
ductor and the gate reduces the threshold voltage. The voltage required to turn on
the FET is found in Equation 13.4. Threshold voltage can be controlled by a suitable
selection of metal gates.

Qss qN x (13.4)
Vth  MS   2F  a dmax
Cox C0 x
φMS work function difference between the metal gate and the channel and equal to
m  Si  F .
Qss – surface charge of the channel.

Cox – gate capacitance and equal to ε ox ε 0 .

tox

tox – gate oxide thickness.

kT  N a  , where N is the channel doping

φF Fermi potential, equal to ln   a
q  ni 
concentration.
xdmax maximum depletion width, for partially depleted devices equal to 4 SiF
qN a
Equation 13.4 works well for NMOS devices [16].
Owing to fabrication limitations, it is simpler to alter the metal gate’s work func-
tion than to alter the semiconductor’s dopant concentration. One easy and efficient
way to manage the voltage shift in FETs, a short-channel effect, is through work
function engineering. For NMOs, a FET metal work function close to 4.1 eV is cho-
sen, which is nearer to the conduction band energy of silicon and for PMOS it is 5.0
eV close to the valence band energy of silicon [17]. Hence less drive voltage will be
required to aid in device scaling. In the proposed device the work function values of
4.1, 4.3, 4.5, and 4.7 have been used in simulation and its impact on threshold volt-
age is exhibited in Figure 13.7. In the proposed device, a metal gate of optimal work
function 4.3 eV was used. Table 13.2 lists the different electrical parameter values for
work functions of 4.1, 4.3, 4.5, and 4.7.

13.12 TRANSFER CHARACTERISTICS
Transfer characteristics refer to variations of the device’s output-drain current in
response to changes in the input drive voltage. Figure 13.8. shows the transfer char-
acteristics of the proposed design. For a WF value of 4.1 that is close to the conduc-
tion band energy of silicon the threshold voltage (Vth = 0.25V) is less when compared
to WF of 4.7 (Vth = 0.85V). ON-current values decrease as work function difference
Performance Analysis of an Inner Gate Vertical TFET 211

FIGURE 13.7 Variation of work function-threshold voltage of an inner electrode VTFET.

TABLE 13.2
Simulation Outputs for Different Work Functions
Parameters/Work function 4.1 4.3 4.5 4.7
Threshold Voltage (V) 0.25 0.45 0.65 0.85
Subthreshold Swing (mv/dec) 38 14 14 14
IOFF (A/μm) 7.60E-12 1.80E-18 2.00E-18 2.00E-18
ION (A/μm) 3.15E-05 1.60E-05 5.00E-06 9.00E-07
ION/IOFF 4.00E-06 8.00E-12 2.00E-12 4.00E-11

FIGURE 13.8 Transfer characteristics Vgs vs Ids of the proposed device.

212 Circuit Design for Modern Applications

increases since more drive voltage is needed to turn on the device as illustrated in
Figure 13.8.

13.13 DRAIN-INDUCED BARRIER LOWERING

Devices with a short-channel (L < = 50 nm) experience field penetration. The deple-
tion zone at the drain approaches the source depletion as the drain voltage is raised.
This causes the potential barrier at the source to drop [18], which makes it easier for
the source to inject valence electrons over the decreased channel barrier and modi-
fies the threshold voltage.
The difference in threshold voltage divided by the difference in drain bias is the
definition of drain-induced barrier lowering.


DIBL  Vt  Vt
1 2
 / V
d2  Vd
1
 (13.4)

Where
Vt1 = threshold voltage at drain voltage Vd1
Vt2 = threshold voltage at drain voltage Vd2
The threshold voltage for the proposed structure is 0.04 and the same for drain
voltages of 0.5V and 3.0 V respectively. The DIBL value obtained is 3 mV/V. When
the distance between the source and the drain increases in long-channel devices (L
≥ 50 nm), the DIBL effect becomes insignificant.

CONCLUSION
Here, an inner gate VTFET is constructed, and several performance metrics are
assessed, including energy band, DIBL, SS, ION, and IOFF. When WF is 4.3 eV, the
simulation results show a significant BTBT rate. Additionally, the performance of
the VTFET is examined and compared with the current exterior gate VTFET to
determine the impact of the inner gate. TCAD simulations were used to produce
all of the results. A sharp subthreshold slope of 14 mv/decade can be reached with
the right device parameter adjustments. In addition, inner gate-VTFETs are used
to achieve the IOFF current of 10 ^ –18 A/µm and the ON-current ION of about 10 −5
A/μm. Low power circuits with better off current, switching, device scaling, and
short-channel effect can be designed using the suggested device.

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 14 Low-Power CNTFET-
Based Single-Ended
Write Driver Circuit
for SRAM Design
Aswini Valluri, Posani Vijaya Lakshmi,
and Avireni Srinivasulu

14.1 INTRODUCTION
VLSI designers have only utilized MOSFETs as an fundamental element in circuits
over the past few years. This is because the MOSFET-based circuit drains little
power, and it is even cheaper to fabricate [1, 2]. However, the increase in demand for
high chip density, high speed, and low power cannot be achieved by the process of
scaling. The MOS scaling leads to short channel effects, power dissipation and leak-
age current [3]. For the purpose of making future electronic gadgets much smaller,
smarter, and more efficient, it is critical to concentrate on a different device material.
A wide range of new material options for CMOS technology are thus being explored.
These include materials like carbon nanotube and silicon nanowire FET as well
as the more conventional FINFET and graphene FET. For overcoming the scaling
limit, carbon nanotube field-effect transistor (CNTFET) is chosen as a promising
replacement to the MOSFET for future electronics [4].
CNTFETs, are being studied for a broad range of uses, from large-scale con-
structions to nanometer-scale digital equipment. This is because of their exceptional
mechanical and physical qualities. Physicist S. Lijima discovered carbon nanotubes
by chance in 1991 while working on a project using carbonium. Graphite sheets are
rolled into nanoscale tubes called CNTs, which have excellent mechanical strength,
electrical conductivity, and chemical resistance. The transmission electron micro-
scope is the only way to see carbon nanotubes (CNTs), which are the tiniest known
nanomaterials.
One nanotube makes up a single-walled (SWCNT) and numerous nanotubes
make up a multiple-walled (MWCNT) respectively. The inter-layer spacing between
the nanotubes in MWCNTs is 0.34 nm [5]. CNTFETs consist of graphene sheets that
form the tubes which act as a channel in place of silicon. The graphene rolling as well
as the electrical properties of CNTFET is illustrated by the chiral vectors (n, m) [6].

DOI: 10.1201/9781003483052-14 215

216 Circuit Design for Modern Applications

FIGURE 14.1 CNTFET structure.

The value of a chiral vector (n, m) defines if the CNT is a metallic or semiconduct-
ing material. A Chiral vector is one that connects the centers of two hexagons that
determines the structure of a single-walled CNT. Metallic single-walled CNTs are
employed as on-chip interconnects, while semiconducting single-walled CNTs are
used in CNT-based devices as the channel [7–10]. CNTFETs exhibit various advan-
tages of high carrier mobility, good heat conduction, less quantum capacitance and
high transconductance.
Figure 14.1 depicts a typical CNTFET device construction. As a transistor chan-
nel, the CNT in the device may be altered by a gate. The drain and source of the
terminals of CNTFETs are highly doped, but the gate region can be non-doped.
The number of single-walled CNTs positioned adjacent to each other determines the
CNTFET gate width. The value of the pitch is established by computing the differ-
ence that exists between the axes of two successive SWCNTs. The CNTFET gate’s
width, and its diameter, which is based on the chirality vector, are calculated by
using Equations 14.1 and 14.2, respectively.

Wgate  Max  Wmin, M  Pitch  (14.1)

a
DCNT  m 2  n2  mn (14.2)

Where Wmin is the minimum width of a CNTFET gate and M is the number of single-
walled CNTs piled under the top of the gate.
A CNTFET device has the same structure, operation, and current–voltage (I–V)
properties as a normal MOSFET. Similar to the MOSFET devices, CNTFETs also
comprise both the N-type and P-type devices. CNTFET has a similar device size
with similar mobility over the MOSFETs. Therefore, transistor scaling is easily done
especially in complex circuits which require a huge number of transistors. As a result,
the drain current is practically zero at voltage levels (threshold voltage, which is the
smallest voltage that must be provided to turn the transistor “ON”). The transistor’s
threshold voltage is exceeded when the gate voltage increases. The CNTFET thresh-
old voltage can be calculated as a function of nanotube diameter using Equation 14.3.
Low-Power CNTFET-Based Single-Ended Write Driver Circuit 217

aV
VTH  (14.3)
3. q. DCNT
Where q is the charge of an electron, Vπ = 3.033eV and a = 2.49Å that represents the
CNT atomic distance.
The vector dependence of nanotube diameter results in a wide range of threshold
voltages for various (n, m). The chirality vector or the diameter can be used to adjust
the CNTFET threshold voltage. This makes CNTFET a more good alternative for
MOSFET-based devices.
Low-power applications play a vital role in the emerging SoCs in which SRAMs
are widely used by occupying almost 70% of the die area [11, 12]. Therefore, various
leakage reduction techniques were also designed [13] to control the overall power.
The design of SRAM with low power is a main perturb of implantable devices [14].
Less power consuming SRAMs are especially required for portable medical devices
like hearing aids and pacemakers. With the upswing of battery-operated devices
especially in biomedical implants, the lifetime of a battery draws attention as it may
cause difficulty for the patient to undergo surgery multiple times for its replacement.
This causes the patient to be affected mentally, physically and financially. Hence
the design of SRAM with low power consumption is very much required. Besides
power consumption, area tenancy also has a great benefit as an increase in area
yields inconvenience to the patients. Curtailing the power consumption and area
occupancy SRAM blocks in turn helps in improving the overall performance of
the SRAM design. For designing SRAM with less power consumption and reduced
transistor count, many circuit-level, technological and architectural approaches are
proposed. The architectural approach mainly includes peripheral circuits such as
sense amplifiers, Wordline Drivers, Decoders, and Write Drivers [15, 16] as they
occupy most of the portion of the SRAM chip. The recent proclamation [17] explores
that about 25% area of the SRAM macro-chip is being occupied by its peripheral
circuits. Many designs were implemented based on the concept of power reduction
and better performance of the peripheral circuits [18–20].
For instance, a Write Driver circuit drives its signals to a huge number of memory
cells for performing the write operation [21]. As the peripheral circuits also use a
large number of transistors for meeting the memory timing constraints, area occu-
pancy and power consumption should also be considered in their design. Therefore,
this chapter focuses on the design of a Write Driver circuit with reduced power and
transistor count which successively reduces the overall power consumption of the
on-chip SRAMs. It presents the modification of [22] resulting in the design of a
Single-Ended Write Driver circuit intended for single-ended SRAM cells.
Figure 14.2 shows the conventional type of 6T SRAM cell structure [23] which
stores one bit of information. Its design is simple enough and well-structured with
the two cross-coupled types of inverters and two access transistors which include
two PMOS and four NMOS. It also consists of a wordline (WL) and the two com-
plementary bitlines BL and BL1 for performing the corresponding operations.
Two storage nodes i.e., Q and Qbar are used to store the data of the core cell. The cell
works on three states such as read, write and hold. The write operation is performed
218 Circuit Design for Modern Applications

FIGURE 14.2 6T SRAM structure.

by enabling WL through which the two access transistors N1 and N2 are turned
ON. Now, the data that is to be written is given in the complementary form to the
bitlines BL and BL1. Thus, with the help of the two access transistors, the data is
inserted into the cell and stored in the nodes, i.e., Q and Qbar. The read operation
is also performed by enabling WL through which the two access transistors N1 and
N2 are turned ON and precharging the two bitlines to Vdd. At this moment, the data
accumulated in the storage nodes i.e., Q and Qbar, makes one of the two bitlines to
charge to Vdd and the other one to discharge to the ground. This results in a slight
voltage difference between the bitlines that is sensed by a sense amplifier that in turn
produces the actual data which is to be read that is accumulated in the storage node
Q. The Hold operation is performed by disabling WL through which the two pass
transistors, i.e., N1 and N2 are turned OFF breaking the connection between the cell
and the bitlines. In this case, the two cross-coupled inverters help to retain the data.
The rest of this chapter explains the importance of a Write Driver circuit whose
power consumption will be usually more due to the large power dissipation of two
bitlines. It explains the working of the existing design, elaborates the Modified Write
Driver circuit and presents the results and comparison of the designs.

14.2 EXISTING WRITE DRIVER CIRCUIT

The Write Driver is the circuit intended for performing the write operation. The
main function of a Write Driver is to write the correct data into the cell. Figure 14.3
shows the Existing Write Driver circuit with 12 transistors [22]. It consists of two
input signals namely write enable (WE) and data (D). WE is enabled in order to
transfer the data into the cell. Once WL is enabled, now based on the data given to
D, the bitlines will be charged or discharged respectively. Thus, the data enters into
the memory cell through the bitlines. When WE is disabled, the cell will be retained
with the previously stored values. For instance, if WE is made high and D is given
a high logic, then the BL will be charged to Vdd and BL1 will be discharged to the
ground. Similarly, if D is given a low logic, BL will be pulled toward the ground and
BL1 will be charged to Vdd.
Low-Power CNTFET-Based Single-Ended Write Driver Circuit 219

FIGURE 14.3 Existing Write Driver.

The work presented in this section is designed for the SRAM cells which use two
complementary types of bitlines BL and BL1 for performing the Write operation.
However, the involvement of two bitlines increases the bitline leakage, which further
increases the overall power consumption. However, as the SRAM array is considered
as a power-hungry block, the design of a bit-cell with less power is essential. This is
because of the reason that each and every column of a memory array will be con-
nected to a Write Driver. The power consumption of a write operation will be more
due to the large power dissipation of two bitlines. To lower the per consumption,
many Write drivers were designed [24] which led to the problem of area and bit-
cell’s instability. To achieve less power consumption, a single bitline is preferred to
carry out the write operation. The single bitline could reduce the power dissipation.
Thus, some researchers have proposed different designs of single-ended (SE) write
scheme which includes a single bitline only to perform the write operation. With
the help of the single bitline, data will be entered into the cell and stored in the stor-
age node Q. Several SRAM designs like 5T [25], 7T [26], 7T [27], 9T [28], 6T [29]
and 9T [30] are SE write assist structures. Therefore, it is much necessary to design
the Write Driver circuit also with a single bitline. The single bitline write drivers
function the same as that of the two bitline designs. The only difference is that in
case of two bitline designs, the data to be written into the cell is transferred through
the two complementary bitlines which upon entering into the cell stores in the two
complementary storage nodes. Whereas in the case of a SE scheme, the data to be
inserted into the cell is transferred through a single bitline which upon entering into
the cell stores in only one of the storage nodes while the other storage node stores its
complementary data due to the functionality of the cell. This can be achieved with
fewer transistors as it is not necessary to drive the two bitlines as mentioned in the
next section.

14.3 MODIFIED WRITE DRIVER CIRCUIT

This chapter thus modifies the Existing Write Driver (WD) circuit present in the
previous section by involving only a single bitline for the write operation as shown
220 Circuit Design for Modern Applications

FIGURE 14.4 Modified Write Driver.

in Figure 14.4. This design uses only six transistors. Similar to the existing design,
the modified one also uses two input signals: WE and the D. Enabling WE and
applying the data to be inserted into the memory cell to D, the write process will
be carried out successfully. When WE is enabled, and if D is given a low logic, BL
will be charged to Vdd and if D is given a high logic, BL will be pulled down toward
the ground. Thus, the data that is to be inserted will be transferred into the core cell
through the single bitline. When write-1 has to be passed to the core cell, the bitline
BL will be driven to Vdd which enters into the core cell through the access transistor
and gets accumulated in the storage node Q. Similarly, when write-0 has to be passed
to the core cell, the bitline BL will be pulled down to the ground which enters into
the core cell through the access transistor and gets accumulated in the storage node
Q. This helps in decreasing the bitline leakage of the memory cell by using a single
bitline instead of using two complementary bitlines. The usage of only six transistors
for designing the SE Write Driver circuit, also reduces the area of the SRAM chip
instead of using 12 transistors for the two bitlines design.

14.4 SIMULATION RESULTS AND DISCUSSION

The timing diagram of a CNTFET-based Write Driver is as shown in Figure 14.5
whose simulations are done in Cadence 32 nm technology at a 900 mv. As per the

FIGURE 14.5 Timing diagram of the Write Driver circuit.

Low-Power CNTFET-Based Single-Ended Write Driver Circuit 221

timing diagram, when the WE signal is enabled, and if the data input (D) is provided
with a high logic, WBL receives a logic high signal. Similarly, if the data input is
provided with a low logic, WBL receives a logic low signal. In the case if WE signal
is disabled then irrespective of the Data input values, WBL will continue with the
previously present logic signal. The Modified Write Driver circuit consumes less
power when compared to the existing one, since it uses only six transistors for its
design. Making use of only six transistors also reduces the area occupancy of the
SRAM chip. Since the Modified design is intended for the Write operation carried
on using a single bitline, the power consumed by charging and discharging of the
other bitline can be reduced. Also, the transistor count is reduced which leads to less
area occupancy. The essential parameters that are to be considered for analyzing the
performance of a Write Driver are its power consumption, delay, the power delay
product (PDP) and the area related to the transistor count. Since power consump-
tion and delay are the two main factors of recent requirements, the modified design
is analyzed for these concerns. The outcomes of the modified design are compared
with the existing ones as mentioned in the literature survey. Table 14.1 gives the
comparison results of the Modified Write Driver circuit in terms of relative param-
eters like power, delay, PDP, and number of transistors used to design the respective
circuits.
Figure 14.6 to Figure 14.8 presents the Modified Write Driver circuit in terms of
the parameters mentioned in Table 14.1 at discrete chirality values to have a clear

TABLE 14.1
Parameters Comparison
Existing WD Modified WD
Technology CNTFET(nm) 32 32
Supply Voltage (mV) 900 900
Power (pW) 113.17 79.63
Delay(us) 0.078 0.073
PDP(J) 8.827 × 10–18 5.812 × 10–18
No. of Transistors 12 6

FIGURE 14.6 Power comparison of Existing and Modified WD circuits at different chiral
values.
222 Circuit Design for Modern Applications

FIGURE 14.7 Delay comparison of an Existing and the Modified WD circuits at different
chiral values.

FIGURE 14.8 Power delay product (PDP) comparison of an Existing and the Modified WD
circuits at different chiral values.

idea of the performance of the design. It gives a clear picture of how the parameters
will be affected by a change in the chirality values. As the chirality value goes down,
better power consumption, delay and PDP achieved are observed (Figure 14.7).
Using the proposed Write Driver with a single bitline, SRAM architecture with
1k cells is implemented as shown in Figure 14.9. SRAM architecture consists of
a memory array and many peripheral devices such as a Wordline Driver, Write
Driver, sense amplifier, precharge circuit, column decoder and a row decoder. The

FIGURE 14.9 SRAM architecture with 1k cells.

Low-Power CNTFET-Based Single-Ended Write Driver Circuit 223

memory array of the architecture is implemented with 1024 cells with 32 rows and
32 columns.
Memory array which is the core block of any SRAM consists of a group of bit-
cells arranged in the pattern of rows and columns where each of the bit-cells is
used to store one bit of information. Each of the bit-cells always stores the data in a
complementary manner. It is designed generally with a collection of more bit-cells
arranged in the pattern of rows and columns. All the cells of each row partake in the
same wordline and all the cells of each column partake in the same pair of bitlines.
The length of an array always depends on the total number of bit-cells stored inside
it. Each cell of the array [31] consists of ten transistors.
The row and column peripherals used for its design along with the proposed
Write Driver are a sense amplifier [32], a Wordline Driver [33], a precharge circuit
and a decoder which helps in driving the read and the write operations of a SRAM
smoothly. A Wordline Driver is one which is responsible for driving a huge number
of bit-cells to perform the desired functionality. It enables the SRAM to execute the
read and write operations. Based on the requirement of executing the read or write
operation, the Wordline Driver helps in making it possible by enabling the required
one.
A decoder is one which provides address input to the wordlines of the core cell
of an array. The address input provided to the decoder decides which cell has to be
accessed. Since an array consists of rows and columns, two Decoders, i.e., row and
column Decoders are used to access a specific bit from the array.
The sense amplifier is one which is responsible for carrying out the read opera-
tion. Every column of the memory array is connected with a sense amplifier. It senses
and amplifies the small voltage difference evolved between the two complementary
types of bitlines of a selected column and produces the desired output, i.e., the data
stored in the core cell. A precharge circuit is one that is responsible for precharging
the two bitlines to Vdd before the commencement of read-and-hold operations.
Figure 14.10 and Figure 14.11 show the timing diagram of the Write and the
read operations respectively of SRAM. Figure 14.10 represents the occurrence of
write operation taking place with the involvement of all the peripheral devices of

FIGURE 14.10 Write cycle timing diagram.

224 Circuit Design for Modern Applications

FIGURE 14.11 Read cycle timing diagram.

the SRAM unit designed with the modified writer driver. Based on the inputs pro-
vided to the row and column Decoders, the bit-cell of a particular row and column
will be selected to proceed with the desired operation. The write operation com-
mences by asserting a logic-1 to the data input of the selected wordline driver. As the
write operation has to be commenced, WWL has to be asserted with a logic-1 and
RWL has to be asserted with a logic-0. However, enabling the WE and providing
the desired logic to the data input of the Write Driver, the bitline of the particular
bit-cell selected will be driven with it and thus the value enters into the memory. The
entered value will be thereby stored in the storage nodes of the cell, i.e., Q and Qbar.
As represented in Figure 14.10, the wordline that is made active through the decoder,
enables the performance of the write operation by storing the data in the storage
nodes with the help of bitlines based on the data given to the Write Driver.
Figure 14.11 represents the occurrence of read operation taking place with the
involvement of all the peripheral devices of the SRAM unit designed with the modi-
fied writer driver. The read operation commences by asserting a logic-0 to the data
input of the selected wordline Driver. For the read operation to commence, the sense
amplifier should be made active by asserting logic-1 to its enable input (SAEN).
Along with that, a precharge circuit should also be made active for precharging
the two bitlines to Vdd before the commencement of the read operation. As the
read operation has to be commenced, RWL should be asserted with a logic-1 and
WWL should be asserted with a logic-0, respectively. Now, based on the data that
is stored in the storage nodes, i.e., Q and Qbar., the two complementary bitlines
will be charged and discharged accordingly. Voltage difference thus aroused will be
observed by a sense amplifier which produces the output logic at Rout which is the
data that is to be read. Therefore, as indicated in Figure 14.11, the activated wordline
by the decoder enables it to execute the read operation relying on the data of storage
nodes with which the sense amplifier senses the voltage difference that is developed
in the bitlines and produces the data that is to be read.
Low-Power CNTFET-Based Single-Ended Write Driver Circuit 225

14.5 SUMMARY
This chapter specifically addresses the pressing requirement for fast-access, low-
power Static Random Access Memory (SRAM) in battery-operated systems, includ-
ing medical implantable devices. Due to the fact that SRAMs typically comprise
approximately 70% of the die area on System on Chips (SoCs), it is imperative to
optimize their design. The objective of this research is to develop a Single-Ended
Write Driver circuit that reduces the number of transistors and power consumption.
The proposed circuit accomplishes a 50% reduction in area occupancy by halving
the number of transistors in comparison to existing designs. The new design’s effi-
cacy is assessed in comparison to existing designs in terms of power consumption,
delay, and PDP. The proposed circuit exhibits substantial enhancements in perfor-
mance and efficiency when implemented with 32 nm carbon nanotube field-effect
transistor (CNTFET) technology at 900 mV using Cadence.

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 15 Electron Mobility Models
and Subthreshold
Swing for Modern
Semiconductors
Shiromani Balmukund Rahi and Young Suh Song

15.1 INTRODUCTION TO SUBTHRESHOLD SWING

In the ever-evolving landscape of semiconductor technology, the quest for higher
performance and lower power consumption drives continuous innovation in device
design and modeling. Among the crucial parameters influencing transistor operation,
electron mobility and subthreshold swing play pivotal roles in determining device
efficiency and speed. This chapter, “Electron Mobility Models and Subthreshold
Swing for Modern Semiconductors”, delves into the fundamental principles,
advanced modeling techniques, and practical implications of these critical aspects
in contemporary semiconductor devices. This preface introduces the motivations,
scope, and objectives that guide the exploration of electron mobility models and
subthreshold swing in modern semiconductor research. As semiconductor devices
scale down to nanometer dimensions, traditional CMOS technology faces inherent
challenges such as increased leakage currents and limited gate control over channel
charges. Understanding and accurately modeling electron mobility, which dictates
how quickly electrons move through the semiconductor material under an applied
electric field, is essential for optimizing device performance and minimizing power
consumption. Subthreshold swing, another crucial parameter, directly impacts the
energy efficiency of transistors during their off-state operation. Innovations in mod-
eling and design methodologies focused on reducing subthreshold swing are critical
for achieving low-power operation, which is increasingly demanded in applications
ranging from mobile electronics to data centers.
This chapter seeks to contribute to the advancement of semiconductor research
by providing a comprehensive overview of electron mobility models and subthresh-
old swing in modern semiconductor devices. By bridging theoretical insights with
practical applications, it aims to inspire researchers, engineers, and students to
explore and innovate in these critical areas of semiconductor technology. “Electron
Mobility Models and Subthreshold Swing for Modern Semiconductors” represents

228 DOI: 10.1201/9781003483052-15

Electron Mobility Models and Subthreshold Swing 229

a foundational exploration into the forefront of semiconductor physics and device

engineering. Through this comprehensive examination, we aim to empower readers
with knowledge and insights that can drive innovation and shape the future of elec-
tronic devices. We try to cover all these contents, remaining will be covered in the
forthcoming chapters or in the next volume of this book.Welcome to the exploration
of electron mobility and subthreshold swing in modern semiconductor technology.
Subthreshold swing is a crucial parameter in semiconductor devices that gauges
how efficiently a transistor transitions from an OFF-state to an ON-state when func-
tioning in the subthreshold region, typically near or below the threshold voltage [1].
In simpler terms, it measures the transistor’s effectiveness in switching on and off
with low input voltages [2].
The significance of subthreshold swing in semiconductor devices is multifaceted
and pivotal for several reasons. First, it directly impacts device power consump-
tion, particularly in low-power applications like portable electronics and IoT devices
[3]. A lower subthreshold swing enables transistors to function more efficiently at
reduced supply voltages, resulting in decreased power usage and extended battery
life. Second, subthreshold swing influences circuit speed and performance, espe-
cially in ultra-low-power designs. A lower subthreshold swing facilitates quicker
switching times and enhanced response in digital circuits, essential for achieving
rapid data processing while maintaining energy efficiency [4]. Additionally, sub-
threshold swing plays a significant role in overall energy efficiency for integrated
circuits. By minimizing subthreshold swing, designers can optimize the balance
between performance and power consumption, leading to energy-efficient designs
that meet the requirements of modern computing and communication systems.
The concept of “subthreshold swing” could be understood by the following
Equation 15.1–5 and Figure 15.1. In Equations 15.1–5, VG, ID, Vth, VDS, μn, W, L, T,
and k stand for gate voltage, drain current, threshold voltage, drain voltage, electron
mobility, width, length, temperature, and Boltzmann constant [5–7].

FIGURE 15.1 Illustration describing the basic structure of MOSFET. Conventionally, SiO2
had been adopted for gate dielectric material, but HfO2 with SiO2 interfacial layershavebeen
adopted for recent MOSFET designs.
230 Circuit Design for Modern Applications

dVG
SS  (15.1)
d  loglog I D 

I D   n  W / L  Cox  VG  Vth  0.5VDS  VDS (15.2)

SS   ln10  *  dVG  /  dlnI D    ln10  * 1 / m  kT / q  (15.3)

SS   kT / q  2.3 1  CD / Cox  (15.4)

SS  60 mV 1  CD / Cox  (15.5)

As explained in Equation 15.1, the subthreshold swing (SS) could be explained by the
change in gate voltage according to the change in log(ID). As described earlier, this
SS value needs to be decreased in most cases, because low SS means that the same
current-change could be achieved by a small gate voltage change. Normally, a lower
SS value in transistor design enables low power consumption in transistors.
Equation 15.2 shows the drain current, especially under the linear region. This
could be derived by utilizing Taylor series expansion. Equations 15.3–15.5 show
the overall simplification for subthreshold swing. As shown in Equation 15.5, the
subthreshold swing of “silicon-channel devices” normally has a higher value than
60 mV under temperature of 300 K, because CD and Cox are normally positive values
[5–7].
So far, the concept of “subthreshold swing” has been explained “mathematically”.
However, for a more easy and intuitive understanding, the figure with equations is
shown in Figure15.2. Let’s simply think about the following three cases.
In Table 15.1, when it comes to case A, when the gate voltage changes 1 V (from 0
V to 1 V), log(ID) changes only 1 (from –6 to –5). Then, according to Equation 15.1,

FIGURE 15.2 Graph shows the concept of subthreshold swing.

Electron Mobility Models and Subthreshold Swing 231

TABLE 15.1
ThreePossible Cases for
Transistor’s Characteristic
Characteristics
Case A ID = 10 A (when VG = 0 V)
–6

ID = 10–5A (when VG = 1 V)
Case B ID = 10–6A (when VG = 0 V)
ID = 10–4A (when VG = 1 V)
Case C ID = 10–6A (when VG = 0 V)
ID = 10–3A (when VG = 1 V)

the subthreshold swing for case A is 1 V/dec = 1000 mV/dec. Normally, for “sub-
threshold swing”, many engineers use the unit of [mV/dec] for easy understanding.
On the other hand, when it comes to case B, when the gate voltage changes 1 V
(from 0 V to 1 V), log(ID) changes 2 (from –6 to –4). Then, according to Equation
15.1, the subthreshold swing for case A is 1 / 2 = 0.5 V/dec = 500 mV/dec.
However, when it comes to case C, when the gate voltage changes 1 V (from 0
V to 1 V), log(ID) changes 3 (from –6 to –3). Then, according to Equation 15.1, the
s15.ubthreshold swing for case A is 1 / 3 = 0.3 V/dec = 333 mV/dec. Considering the
fact that a lower subthreshold swing value is normally desirable for transistor design,
case C might be the most promising case.

15.2 INTRODUCTION TO ELECTRON MOBILITY

15.2.1 Basic Concept of Electron Mobility
Electron mobility refers to a fundamental property of materials, particularly semi-
conductors, that describes the ease with which electrons can move through the mate-
rial when subjected to an electric field. It is a measure of the speed at which electrons
drift in response to an applied electric field and is denoted by the symbol μ [8–10].
Electron mobility is a critical parameter in understanding and designing semicon-
ductor devices [9].
In practical terms, electron mobility quantifies how fast electrons can move
through a material under the influence of an electric field [10]. It is an essential
characteristic because it directly influences the performance of electronic devices
such as transistors. Higher electron mobility implies that electrons can move more
quickly, which can lead to faster device switching speeds and improved overall
device performance.
Electron mobility is influenced by various factors, including the material’s crystal
structure, temperature, doping levels, and the presence of impurities or defects [11].
For example, materials with a well-ordered crystal lattice and fewer impurities tend
to exhibit higher electron mobility. Conversely, factors like scattering due to lattice
imperfections or impurity atoms can reduce electron mobility.
232 Circuit Design for Modern Applications

In semiconductor physics, electron mobility is typically measured in units of cen-

timeters squared per volt-second (cm²/Vs) [12]. It is an important parameter used in
the design and optimization of semiconductor devices such as transistors, diodes,
and integrated circuits [13]. Understanding and controlling electron mobility are key
aspects of semiconductor technology that contribute to the development of faster,
more efficient, and reliable electronic devices.

15.2.2 Importance of Electron Mobility in Semiconductor Devices

Electron mobility is a crucial factor influencing the effectiveness and functionality
of semiconductor devices, making it a vital parameter in both semiconductor physics
and device engineering. The significance of electron mobility lies in its direct influ-
ence on the operational properties and effectiveness of various electronic compo-
nents. The importance of electron mobility canbe understood inTable 15.2.

15.3 ELECTRON MOBILITY MODELS

15.3.1 Classical Mobility Models (Drift–Diffusion
Model, Einstein Relation)
Classical mobility models like the drift–diffusion model and Einstein relation are
fundamental principles in the fields of semiconductor physics and electronic engi-
neering, offering valuable insights into the behavior of charge carriers such as elec-
trons as they navigate through semiconductor materials in the presence of electric
and thermal fields.
The drift–diffusion model delineates the movement of charge carriers within
semiconductors through two primary mechanisms: drift and diffusion. Drift sig-
nifies the directed motion of carriers under the influence of an electric field, akin
to particles moving under a force’s effect. Conversely, diffusion accounts for the
random thermal motion of carriers, causing them to disperse from areas of high
concentration to lower ones.
By combining these drift and diffusion processes, the drift–diffusion model com-
prehensively explains the overall transport of carriers in semiconductor devices like
diodes and transistors. This model proves particularly beneficial for understanding
how the interplay of electric fields and carrier concentrations affects device function-
ality and performance.
On the other hand, the Einstein relation establishes a critical link between carrier
mobility and diffusion coefficient under thermal equilibrium conditions in semicon-
ductors. It states that the product of carrier mobility (μ) and elementary charge (e) is
equal to the diffusion coefficient (D) multiplied by the thermal voltage (kT), where k
represents the Boltzmann constant and T signifies absolute temperature. This math-
ematical relationship provides a bridge between the broader-scale transport prop-
erties (mobility) and the microscopic thermal properties (diffusion coefficient) of
carriers in semiconductors [14–16]. There have been various researches which show
the importance of temperature-engineering, so that the electron mobility could be
improved [17–21].
Electron Mobility Models and Subthreshold Swing 233

TABLE 15.2
The Significance of the Electron Mobility
Category Explanation
Speed of Electron Electron mobility directly impacts how rapidly electrons can traverse a
Movement semiconductor material when subjected to an electric field. Higher electron
mobility results in faster electron drift speeds, which are crucial for
achieving high-speed operations in electronic circuits. For example, in
transistors, increased electron mobility facilitates faster switching, leading
to improved device performance in terms of speed and response time.
Device Performance The mobility of charge carriers, such as electrons, significantly affects the
overall performance of semiconductor devices. In fundamental electronic
components like field-effect transistors (FETs), electron mobility
determines the efficiency of channel conductivity and the speed at which
the transistor can transition between its on and off states. Improved
electron mobility contributes to lower resistance and decreased power
consumption, resulting in more energy-efficient devices with superior
overall performance.
Power Consumption Electron mobility plays a critical role in determining the power efficiency of
semiconductor devices. Enhanced mobility allows electrons to move with
greater freedom and reduced resistance, leading to lower power dissipation
during device operation. This aspect is particularly crucial in low-power
applications such as mobile devices, IoT sensors, and battery-operated
systems, where minimizing power consumption is essential for extending
battery life and enhancing energy efficiency.
Material and Device Semiconductor materials exhibiting higher electron mobility are preferred
Optimization for fabricating high-performance devices, especially in applications
requiring high frequencies and swift operations. Engineers and researchers
focus on optimizing material characteristics and device structures to
enhance electron mobility, resulting in the development of advanced
semiconductor technologies with enhanced performance attributes.
Technology As semiconductor technology evolves and device dimensions shrink, the
Advancements importance of electron mobility becomes even more pronounced. Scaling
down device sizes can introduce challenges such as increased resistance
and reduced carrier mobility. Hence, ongoing exploration of innovative
techniques and materials is crucial to maintaining or improving electron
mobility while scaling down semiconductor devices to meet the evolving
demands of next-generation electronics.
In summary, electron mobility serves as a foundational element that drives
the design, performance, and energy efficiency of semiconductor devices.
Efforts aimed at understanding and optimizing electron mobility are
essential for advancing semiconductor technology and creating state-of-
the-art electronic systems with enhanced functionality and superior
performance characteristics.
234 Circuit Design for Modern Applications

The Einstein relation finds extensive application in semiconductor physics for

analyzing carrier transport behaviors and in the realm of device modeling and simu-
lation to comprehend how mobility influences crucial device characteristics such
as conductivity and current flow. Overall, these classical mobility models serve as
foundational tools for studying and optimizing semiconductor devices and circuits
in electronic systems [22].

15.3.2 Advanced Mobility Models (Velocity Saturation

Model, Lattice Scattering Model)
Advanced mobility models such as the velocity saturation model and lattice scatter-
ing model are pivotal concepts in semiconductor physics and electronic engineer-
ing, extending beyond the classical drift–diffusion model to capture more nuanced
behaviors of charge carriers in semiconductor materials [23–25]. Normally, there are
two representative advanced mobility models – the velocity saturation model and the
lattice scattering model.
The velocity saturation model is an advanced mobility model that addresses the
phenomenon of carrier velocity saturation in high-electric-field conditions. In tra-
ditional models like the drift–diffusion model, it’s assumed that carrier velocity
increases linearly with electric field strength. However, in reality, as the electric field
strength becomes very high, carriers start to experience velocity saturation, where
their velocity reaches a maximum limit despite further increases in the electric field
[26–29].
This saturation occurs due to the carrier’s limited time to accelerate between scat-
tering events, such as collisions with phonons or impurities in the crystal lattice. The
velocity saturation model introduces a saturation velocity term to account for this
behavior, allowing for more accurate predictions of carrier transport in high-field
regions, such as in high-voltage devices or devices with small dimensions where
electric fields can be intense.
The lattice scattering model is another advanced mobility model that focuses
on the scattering mechanisms encountered by charge carriers as they interact with
the crystal lattice of the semiconductor material. In semiconductor crystals, lattice
vibrations (phonons) can interact with carriers, leading to scattering events that
affect their mobility.
The lattice scattering model considers various types of lattice scattering mecha-
nisms, such as acoustic phonon scattering, optical phonon scattering, and alloy scat-
tering. These mechanisms introduce momentum changes and energy loss to carriers
during their transport, influencing their mobility characteristics. By incorporating
these scattering processes into the mobility model, researchers and engineers can
better understand and predict the mobility behavior of carriers under different tem-
peratures, doping, and material conditions.
Both the velocity saturation model and lattice scattering model represent advance-
ments beyond the simplistic assumptions of classical mobility models. They pro-
vide deeper insights into the complex behaviors of charge carriers in semiconductor
Electron Mobility Models and Subthreshold Swing 235

materials, essential for designing and optimizing high-performance semiconductor

devices such as high-speed transistors, integrated circuits, and advanced electronic
systems.

15.3.3 Modern Electron Mobility Model.

In addition to the above-mentioned mobility models, there are a couple of recent
electron mobility models. For easy understanding, these models are briefly explained
in Table 15.3 with Table 15.4. Specifically, the sophisticated electron mobility model
tends to have more time complexity, and it has been a well-known fact that the tem-
perature dependence mobility model has high time complexity. For example, con-
centration and temperature-dependent models have high time complexity.

TABLE 15.3
The Explanation of the Modern Electron Mobility Model
Name of model Explanation
Concentration and temperature- Caughey-Thomas formula. Usually applied for the temperature
dependent model from 77K to 450K.
Concentration dependent Si and GaAs mobility model under 300K.
Watt model The transverse field model is applied to surface nodes only.
Modified Watt More sophisticated Watt model. This model usually applies to
non-surface nodes. This model also utilizes E⊥ effects. Good for
modeling planar MOSFET.
Tasch model This model includes the dependence of the transverse field.
However, these models are not good for 3D MOSFET such as
FinFET and GAA MOSFET. This model requires a very fine grid.
Parallel electric field dependence This model utilizes the velocity saturation effect.
model
Carrier–carrier scattering This model is also called the Dorkel–Leturq model. This model
considers the dependence of n, N, and T. This model is usually
used when carrier concentration is very high.

TABLE 15.4
Intrinsic Electron and Hole Mobility in Different Channel Materials
(Under 300 K)
Si Ge InAs InSb GaAs
Electron mobility (cm V s )
2 –1 –1 1600 3900 40,000 77,000 9200
Hole mobility 430 1900 500 850 400
Bandgap (eV) 1.12 0.66 0.36 0.17 1.4
Dielectric constant 11.9 16 14.8 17.7 12.4
236 Circuit Design for Modern Applications

15.4 IMPACT OF MOBILITY ON TRANSISTOR

SPEED AND POWER CONSUMPTION
The mobility of charge carriers within semiconductor devices significantly impacts
both transistor speed and power consumption. Enhanced carrier mobility often
results in faster transistor operation and reduced power usage. This outcome stems
from the fact that carriers with higher mobility can swiftly respond to an applied
electric field, leading to quicker switching times and minimized operational delays.
Moreover, increased carrier mobility enables transistors to achieve comparable
performance levels at lower operating voltages. This is particularly advantageous
considering that power dissipation in CMOS circuits is directly proportional to the
square of the supply voltage. By leveraging higher mobility to maintain performance
while decreasing the supply voltage, substantial reductions in power consumption
can be achieved, thereby promoting the development of energy-efficient electronic
systems.
Furthermore, mobility influences subthreshold behavior and leakage currents in
semiconductor devices. Subthreshold behavior pertains to a transistor’s functional-
ity when the applied voltage is below its threshold voltage for full activation. In this
operational range, carrier mobility plays a pivotal role in determining how effec-
tively carriers can navigate the channel, even under weak electric fields.
Optimized mobility can enhance subthreshold behavior by facilitating more effi-
cient carrier flow under low electric fields, thereby contributing to a lower subthresh-
old swing. Lower subthreshold swings are desirable as they enable better control
over transistor states and help in reducing leakage currents, particularly subthreshold
leakage, which is a significant contributor to power consumption in modern semi-
conductor devices.
Considering the relationship between mobility and device reliability, it is essential
to note that while higher carrier mobility can boost device performance, it may also
introduce reliability challenges in specific scenarios. For instance, elevated electric
fields associated with enhanced mobility can lead to hot carrier effects, potentially
impacting the device’s long-term reliability.
Additionally, mobility influences how process variations and aging effects affect
device performance. Variations in carrier mobility across devices or within the same
device due to manufacturing disparities can impact circuit behavior and overall reli-
ability. Hence, engineers need to carefully consider mobility-related factors during
device design and reliability assessments to ensure the development of robust and
durable semiconductor devices.

15.5 HIGH-MOBILITY CHANNEL MATERIALS

(III-V COMPOUNDS, GE, SIGE)
High-mobility channel materials, including III-V compounds, germanium (Ge), and
silicon-germanium (SiGe), are instrumental in propelling semiconductor technol-
ogy forward and elevating the performance of electronic devices. These materials
Electron Mobility Models and Subthreshold Swing 237

TABLE 15.5
High Mobility Channel Materials
Material Explanation
III-V Semiconductor materials known as III-V compounds are created from elements in
Compounds group III (such as gallium, aluminum, and indium) and group V (such as nitrogen,
phosphorus, arsenic, and antimony) of the periodic table. Their exceptional
electron mobility results from specific crystal structures and band alignments. III-V
compounds like gallium arsenide (GaAs), indium phosphide (InP), and gallium
nitride (GaN) are extensively utilized in high-frequency and high-speed electronic
devices. GaAs, in particular, arerenowned for theirremarkable electron mobility
and find widespread use in microwave devices, high-speed transistors, and
optoelectronics.
Germanium Germanium stands out as a semiconductor material with higher intrinsic carrier
(Ge) mobility than silicon, owing to its narrower bandgap. This characteristic makes it
particularly suitable for applications requiring enhanced carrier mobility, such as in
high-speed transistors and detectors. Ge-based materials are frequently
incorporated in complementary metal-oxide-semiconductor (CMOS) technology to
boost transistor performance. Ge channels within CMOS devices contribute to
improved electron and hole mobility, resulting in faster switching speeds and lower
power consumption compared to pure silicon counterparts.
Silicon- SiGe represents a hybrid semiconductor material combining silicon and germanium,
Germanium offering increased carrier mobility over pure silicon while remaining compatible
(SiGe) with existing silicon-based fabrication processes. SiGe is commonly employed to
fabricate strained silicon layers in CMOS technology, deliberately distorting the
lattice structure to enhance carrier mobility. The adoption of strained silicon
technology with SiGe layers has been pivotal in achieving significant performance
enhancements in modern integrated circuits, particularly in terms of speed, power
efficiency, and overall device functionality.

possess superior carrier mobility compared to conventional silicon (Si), making

them highly sought-after across a range of semiconductor applications. The detailed
explanation for high-mobility channel materials is shown in Table 15.5.

15.6 CONCLUSION
This chapter has explained the concept of subthreshold swing and electron mobility
with some mathematical equations and figures. All in all, even though there have
been various electron mobility models, each model has its own strengths and weak-
nesses. By utilizing various electron mobility models, it is expected that scientists
and engineers will be able to design and develop next-generation designs. The con-
cept of electron mobility and subthreshold swing isimportant for understanding the
main characteristics and behaviors of transistors.
238 Circuit Design for Modern Applications

Acknowledgment
In this chapter, the knowledge in previous research has been widely utilized, and the
sources of information arelisted inthe reference format (e.g., [1, 2], …). The author
would like to sincerely thank the authors who have put their sincere effort into pub-
lishing many articles and research related to this chapter.

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 16 Multiple-Gate MOSFET
Model Implemented
in Analog Circuits
for Simulations and
Co-Design Applications
Ismahan Mahdi, Billel Smaani, and
Mohamed Salah Benlatreche

16.1 INTRODUCTION
Since the invention of the first transistor, the semiconductor industry has always
aimed at improving the electrical performance of the produced ICs. This is achieved
only by reducing the size of the transistors, as well as by increasing the number of
integrated transistors into the CMOS chips technology [1]. According to the ITRS
predictions, the physical grid length of MOSFETs can be reduced up to 5–6 nm [2].
However, adverse effects, especially short-channel effects (SCEs), are the main obsta-
cle to this reduction and this trend toward miniaturization. The DG MOSFET has
been chosen as one of the best candidates for replacing the conventional MOSFETS
in the manufacture of very large-scale CMOS circuits (VLSI) [3, 4]. Indeed, the DG
MOSFET has several advantages, for example, the low grid current, a high current,
excellent control of short-channel effects, and a slope below the near-ideal threshold
[5]. On the other hand, DG MOSFET’s compact transistor models are very useful for
circuit simulation and analysis. A compact model is a mathematical description of
the electrical behavior of a device. A compact model thus provides a bridge between
the transistor level and the circuit level, providing a way to analyze transistors and
establish more complex circuits in circuit simulators, such as SPICE [6].
In the literature, the compact modeling of a double-grid TMOS is done in two
ways: implicit or explicit. In the first case, the model uses an iterative calculation
procedure [7, 8]. In the second case, this type of model does not use iterative calcula-
tion [9]. However, explicit models of simple analytical formulation are most suitable
for circuit simulation. In this part, we present a compact modeling of a DG MOSFET
with a low-doped channel. For this, we adopt a basic physical approach that describes
the static and dynamic behavior of the device using analytical expressions of simple

DOI: 10.1201/9781003483052-16 241

242 Circuit Design for Modern Applications

formulations adequate for the simulation of circuits. The model is validated for a
long-channel double-grid TMOS, as well as for the short channel. Effects such as
DIBL, VT Roll-off, and degraded mobility are taken into account. To validate the
obtained results from the compact modeling, we compare these with those obtained
from a digital simulation done with the commercial software SILVACO-TCAD.
In this chapter, we will be devoted to the implementation of the DG MOSFET
compact model in the Verilog-AMS hardware description language. We will per-
form a time analysis and simulation of circuits based on a DG MOSFET, such as
the Colpitts oscillator and the passive charge inverter, using the SMASH circuit
simulator.

16.2 PRESENTATION OF THE CONSIDERED DEVICE

Figure 16.1 shows the architecture of the device in question. It is a weakly doped and
symmetrical MOS double-grid transistor. The technological parameters of this tran-
sistor are the length of the channel L, the thickness of the oxide tox , and the height
of the silicon tsi . Vgs is the voltage applied to the two grids and Vds is the tension
applied in the drain.
So we consider a DG MOS transistor with a N low-doped silicon channel
N A  1.1014 cm 3 . The source and drain regions are heavily doped N D  5.1021 cm 3
and a mid-gap grid metal. We consider two cases of canal length: a long channel
L = 1µm and a short channel L = 60m . The thickness of silicon varies between 20
and 25 nm, and an oxide density tox of 2 nm [9]. The drain current is then calculated
using the drift–diffusion transport model.

16.3 DESCRIPTION OF THE COMPACT ANALYTICAL MODEL

The rapid progress in the performance of the circuits in CMOS technology is linked,
on the one hand, to the development of new structures, such as the SOI MOSFET
multi-grids, and on the other, it is related to the realization and design of increasingly
efficient circuits. However, circuit designers need compact models for multi-grid
MOS devices for the design and simulation of circuits as well as for the implemen-
tation of chip-on systems [1, 10]. These models must inform the circuit designer
about the physical-electric and technological aspects of the component. All this
in an analytically compact, simple and suitable way for precise circuit simulation.

FIGURE 16.1 Considered structure of the double-grid TMOS (symmetric)

Multiple-Gate MOSFET Model Implemented in Analog Circuits 243

Considering a N-type DG MOSFET, we can ignore the contribution of holes in the

charge transportation process, and then the Poisson equation is written considering
only electron density [11]:

d 2 q.n
 (16.1)
dy 2 µsi
Φ is the electrostatic potential, n the electron density, ε si is the permissiveness of
silicon and q is the elementary charge of electrons. According to Boltzmann's statis-
tic, the electron density n can be defined as [12]:

   Vch 
n  n i .exp   (16.2)
 t 
 t ( K .T / q) is the unit of thermodynamic voltage, ni corresponds to the intrinsic
density of carriers in silicon and Vch is the potential of Fermi’s quasi-level. By replac-
ing the solution of Equation 16.2 with Equation 16.1, the Poisson equation is rewrit-
ten as follows :

d 2 q.ni    Vch 
 .exp   (16.3)
dy 2
µsi  t 
The unbounded integral of Equation 16.3, leads to the solution of the following elec-
trical field [13]:

2.q.ni . t
E . exp  (  Vch ) /  t   C1 (16.4)
 si
C1 is the constant of integration.
Through Equation 16.4, the surface potential  s    y  tsi / 2  can be expressed
as follows:

 Qg2 
 s  Vch   t .ln   C1  (16.5)
 si
2 . .q. .n
t i 
Qg corresponds to the grid charge density.
The application of Gauss’s law to the grid oxide interface leads to the following
expression [14]:

Qg
Vgs   MS   s  (16.6)
Cox
Cox is the capacity of grid oxide and  MS is the difference of output work between
grid metal and silicon. By replacing the solution of Equation 16.5 with Equation
16.6, we get :
244 Circuit Design for Modern Applications

Qg  Qg2 
Vgs   MS  Vch    t .ln   C1  (16.7)
Cox  2. si .q. t .ni 
with C1  Qg / q.ni .(tsi / 2)
The grid charge density Qg can be calculated using the Gauss law [15]:

d
Qg   si . (16.8)
dy y  tsi / 2

Since this device is a double-grid MOS transistor, we have two grid charge densities.
The mobile charge density Qm can then be calculated according to [16]:

Qm  2.Qg (16.9)

Then, by normalizing the voltage relative to Φ t and the charge relative to 4.Cox .Φ t
[13, 17], the Equation 16.7 is rewritten as:

 C 
vg  vch  vto  4.qg  ln  qg   ln 1  qg . ox  (16.10)
 Csi 

 
vto   MS  ln q.n i .tsi / 8.Cox . t
corresponds to the threshold voltage in the
case of a long-channel DG MOSFET and Csi is the capacity of silicon.
Equation 16.10 that we have just obtained is a primordial equation that connects
tensions, charge density, and different capacities. This implicit equation will allow,
by solving it, to calculate the density of mobile charge. We will discuss this in detail
in the following paragraphs.

16.3.1 The Drain Current

According to the drift-diffusion transport model, the drain current is obtained through
the integration of the mobile charge density from the source to the drain [14]:

W V ds
I ds  .  Qm .dVch (16.11)
L 0
µ is the mobility of electrons and W the width of the device.
Using Equations 16.8, 16.9, and 16.11, the standard drain current expression is as
follows [17]:

 2
 
i    qmd  qms   2.  qmd  qms   2.  Csi / Cox  .ln 1   qmd  qms  . Cox / 2.C 
Csi 

(16.12)
Multiple-Gate MOSFET Model Implemented in Analog Circuits 245

FIGURE 16.2 Organigram describing the main steps of iterative charge calculation using
the Newton-Raphson method

The final drain current can then be calculated after denormalization of the solution
of the Equation 16.12 by the factor 4.µ.Cox t2 . W / L  .

16.3.2 Calculation of Mobile Charge Density

16.3.2.1 Iterative Calculation
Simply, the mobile charge density is calculated by the iterative calculation of the grid
charge density applied to Equation 16.10, using the Newton-Raphson method [18], as
shown in the organizational chart in Figure 16.2.
Figure 16.2, represents the organogram of the main steps of the iterative calcu-
lation of the charge density. So we start with the definition of the initial charge as
well as the technological and physical parameters of the component. Then, for each
iteration (from 1 to n), the charge and absolute error are calculated. The charge cal-
culation is based on the nonlinear Equation 16.10 and its derivative, as well as the
use of the main formula of Newton-Raphson. When the error is very small (error test
for each iteration), so it converges, this subsequently allows for the calculation of the
total mobile charge density and drain current.
Figure 16.3(b) shows the curve of the mobile charge density (normalized) based
on the grid voltage Vgs . This charge density is calculated iteratively, for Vds equals
to 1 V and Vgs varies from 0 to 1.4 V. We can see the logical evolution of the mobile
charge density as well as the drain current. The latter allows for a predictable behav-
ioral drain current from low to high inversion (Figure 16.3 (a)).
However, at the level of circuit simulation an iterative model is not adequate.
Indeed, an electrical circuit can contain a large number of transistors, and iterative
calculation of charge, potential and other parameters takes a prohibitive calculation
time.
246 Circuit Design for Modern Applications

FIGURE 16.3 Variation of drain current based on grid voltage for a long-channel DG MOS
(a); variation of the standardized mobile charge density based on the long-Channel DG MOS
grid tension (b), for Vds=1 V

16.3.2.2 Direct Calculation
To solve the problem of iterative calculation, the mobile charge density must be
explicitly calculated. This is in the linear regime and in the saturation one.
For v( vg  vch  vto ), α(Cox / Csi ) and q(= qg ) , Equation 16.10 is rewritten as
follows [19]:

v  4.q  ln  q 1  .q   (16.13)

Charge Density in the Saturation Regime

In this operating regime, the inversion charge density is significant (q >> 1). Taylor's
series development (in 1st order) of the term ln  q 1 .q   around q = qt , gives [20]:

 q  qt .  q  qt  
ln  q 1  .q    ln  qt 1  .qt    2.    (16.14)
 q  qt 2  .  q  qt  
After injection of Equation 16.14 into Equation 16.13 and rearrangement, a 2nd-
order equation is obtained as follows:

4.q 2   4.qt  a  b  v  .q  [qt (b  a  v)]  0 (16.15)

2.(1  2..qt )
with a  and b  ln  qt (1  .qt ) 
1  .qt
The solution of Equation 16.15, is then obtained:

 2 
 va b   va b 
q0  1 / 2.   qt     qt   2a.qt  (16.16)
 4   4  
 
Multiple-Gate MOSFET Model Implemented in Analog Circuits 247

By replacing the solution of Equation 16.16 in the term ln  q 1 .q   of Equation
16.13, the grid charge density in the saturation regime qgS is then calculated directly
via the following solution:

 
qgS  1 / 4. v  ln  q0 . 1  .q0   (16.17)

Charge Density in Linear Regime

In the linear operating regime, the inversion charge density q is weak. For this pur-
pose, the first term on the right side of Equation 16.13 can be ignored, and the equa-
tion may be rewritten as follows [19]:

v  ln q  1 / FW (ln q) (16.18)

1
with FW (ln q)  and  ln q  ln q  ln qt .
4.qt exp( ln q)  ln(1  .q.exp( ln q))

Taylor's serial development of FW (ln q) around  ln q  0 leads to the following

expression [20]:

 qt  4  (1  4.qt )  
1
FW (ln q)  . 1   ln q 
4.qt  ln(1  .qt )  (1  .qt ).(4.qt  ln(1  .qt )) 


(16.19)

By replacing the solution of Equation 16.19 with Equation 16.18, we get the following
one (after arrangement):

1 2  ln qt  v   v.ln qt 
.ln q   1   .ln q   a  v    0 (16.20)
b  b   b 
a(1  .qt )
with a  4.qt  ln(1  .qt ) and b  .
qt  4.(1  )   
The solution of Equation 16.20 is given by [19]:

  
q0  exp 1 / 2. v  (b  ln qt )  [v  (b  ln qt )]2  4ab   (16.21)
  
248 Circuit Design for Modern Applications

FIGURE 16.4 Variation of the normalized mobile charge density based on grid voltage,
comparison between iterative (red) and direct (black) calculations, for Vds=1 V

Thus, by replacing the solution of Equation 16.21 with the expression

v  4.q0  ln  q. 1  .q   of Equation 16.13, we will able to have the charge density
expression of the grid in a linear regime qgL :

exp(v  4q0 )
qgL  (16.22)
1 / 2  1 / 4  .exp(v  4q0 )
In Figure 16.4, we compare the mobile charge density calculated directly with that
obtained by the iterative charge calculation using the Newton-Raphson method, for a
constant drain voltage Vds = 1V and a grid voltage Vgs varies from 0 to 1.4 V. It can
clearly be seen that the charge density obtained with the iterative calculation is in
good harmony with that obtained through the direct one.

16.4 Short Channel Effects

From the 2D Poisson equation, then, considering the parabolic approximation of the
electrostatic potential in the vertical direction (with d  / dy y t / 2  0 ), the electro-
si
static potential can be expressed by [21, 22]:

ox  s ( x)  (Vgs  V fb )   ( x)  (Vgs  V fb ) 2

 ( x, y )   s ( x )  . . y  ox . s .y
 si tox  si tox .tsi
(16.23)

with V fb is the flat-band voltage.

The surface potential Φ s ( x) is defined by [22]:

1   t 
 s ( x)  .  c ( x)  ox . si .(Vgs  V fb )  (16.24)
ox tsi  4 . t 
1 . si ox
4. si tox
where Φ c ( x) is the electrostatic potential at the center of the silicon channel. The
latter is written as [16]:
Multiple-Gate MOSFET Model Implemented in Analog Circuits 249

 c ( x)  Vgs   MS
x  Lx
sinh   sinh  
 Vbi   F  Vds  Vgs   MS  .  l   V    V   .  l 
L
 bi F gs MS 
L
sinh   sinh  
 
l l 
(16.25)

With:
Vbi is the drain-channel and source-canal junction voltage.

  si .t si .tox   .t 
l 1  ox si   is the natural length of a DG MOSFET [22].
 2.ox  4. si .tox  
 

Φ cmin is the minimum electrostatic potential. The latter can be evaluated via
d  c ( x) / dx x  L / 2 .
Taking into account the latter expression and Equation 16.25, Φ cmin is written as:

 L 
sinh  
 c min  Vgs   MS   2. Vbi   F  Vgs   MS   Vds  .  2.l  (16.26)
L
sinh  
l 
The threshold voltage of the short channel device can be defined as the grid voltage
Vgs for which Φ cmin of Equation 16.26 equals  to  vto . t [23].
We can determine the threshold voltage of the DG MOSFET for short channels
according to [16]:

 L 
sinh  
vto   2.  vbi   F   vds  .  2.l 
L
sinh  
vth  l  (16.27)
 L 
sinh  
1  2.  2.l 
L
sinh  
l 
where vto is the normalized threshold voltage of the long-channel device.

16.4.1 Threshold Voltage Deviation Due to

DIBL Effect and to VT Roll-off
Simply analytically, the DIBL effect and the V T Roll-off represent the shift ∆vth
between the threshold voltage of the short-channel device vth and that vto of the
long-channel device [15]:
250 Circuit Design for Modern Applications

vth  vto  vth (28)

By replacing Equation 16.27 with Equation 16.28, we get the voltage shift ∆vth (after
arrangement and approximation) [16]:

vth   .  2.  vbi   F  vto   vds  (29)

with   exp   L / 2.l  .

16.4.2 Degradation of Mobility
The degradation of mobility related to the transversal and longitudinal electric field
is given by the following expression [14]:

T
eff  (30)

1 T
L
Where:
µT is transversal field mobility.
µ L is lateral field mobility.
By applying the definition of saturation of the operating carrier speed and mobil-
ity and lateral field, µ L can be written in a simplified way, such as:

 1
 L  sat (31)
 ds 
t
L
with ν sat corresponds to the saturation rate of the carriers.
Transversal field mobility is given by [16]:

0
T  (32)
Eeff
1
E0
Where:
µ0 corresponds to the mobility of low electric field carriers, the latter is consid-
ered as an adjustment parameter.
 
Eeff  q g .4.Cox .UT /  si is the effective electric field.

By replacing the solution of the Equations 16.31 and 16.32 in Equation 16.30, the
final expression of mobility is written as follows:
Multiple-Gate MOSFET Model Implemented in Analog Circuits 251

T
eff  (33)
 ds t
1  T . .
L  sat

16.5 INTRINSIC CAPACITORS
The intrinsic capacitors of the transistor can be defined as the deviation of the charge
relative to the voltage applied to the different terminals [24]:

Qx Qx
C xy    (16.34)
Vy x y
Vy x y

where x, y = G, S , D (grid, source, and drain).

Since we consider the symmetrical operation mode (Figure 16.1), the double-grid
TMOS can be considered as a three-terminal device. The equivalent scheme of the
device including intrinsic capacitors is as follows [25]:
Figure 16.5, represents the equivalent circuit of symmetric DG MOSFET. With
Csg , C gs , C gg , Cdg , C gd , Css , Csd , Cdd , Cds , g m , are, respectively, the capacitors:
source–grid, grid–source, grid–grid, drain–grid, grid–drain, source–source,
source–drain, drain–drain, drain–source, and grid transconductance.
Based on the previously calculated mobile charge density, and based on the EKV
model [17], from the works of F. Prégaldiny, F. Krummenacher, J - M. Sallese et
al. [26, 27], the intrinsic capacitors are calculated in a direct manner following the
expressions represented in the Table 16.1.
Where:
Cox _ T (= 2.W .L.Cox ) is the total capacitor of the oxide.
 f ( 1 / 4  i f 0 ) and  r ( 1 / 4  ir 0 ) are variables derived from the EKV
model developed for the "bulk" MOSFET [17].

FIGURE 16.5 Equivalent circuit of the dual-grid TMOS in symmetrical operation mode
taking into account intrinsic capacitors.
252 Circuit Design for Modern Applications

TABLE 16.1
Analytical Expressions of the Intrinsic Capacitors of the Dual-Grid TMOS in
Symmetrical Operation Mode.
Capacity Analytical expressions
Drain-grid
 4  3  6  3  28  2   10  2  15   
 f r f r f f r 
 
 2
22    10  2 
 f r r 
C  1 / 15.C
dg ox _ T  3 
     
 f r 
  
 
 
Source-grid
 4  3  6  3  28  2   10  2  15  
 r f r f r f r 
 
 2
22.   10  2 
 r f f 
C  1 / 15.C
sg ox _ T  3 
   
  f  r 
   
 
 

Drain-source  
 (2   1)  (  2   2  3   ) 
f f r f r 
C  2 / 15.C .
ds ox _ T  3 
     
   
 f r

Source-drain  
 (2   1)  (  2   2  3   ) 
 r f r f r 
C  2 / 15.C . 
sd ox _ T  3
     
   
 f r

Grid-grid C C C
gg sg dg

Grid-source C  C C C
gs sd ds sg

Grid-drain C C C C
gd sd ds dg

Drain-drain C  C C
dd dg ds

Source-source C  C C
ss sg sd
Multiple-Gate MOSFET Model Implemented in Analog Circuits 253

FIGURE 16.6 Variation of drain current depending on the drain voltage of the long-channel
DG MOSFET for different grid tensions. Line: model; dots: digital simulation.

16.6 RESULTS AND DISCUSSIONS

16.6.1 Validation: Model vs. Digital Simulation
In order to verify the accuracy and precision of the results obtained from the com-
pact analytical modeling of the double-grid TMOS, we compare these with those
obtained through the digital simulation of the transistor. In our case, we use the
ATLAS tool of the marketed software SILVACO-TCAD for digital simulation (2D)
of a DG MOSFET [28]. The validation of the results of the compact modeling of the
double-grid TMOS allows, on the one hand, to verify the accuracy of the model. On
the other hand, to move toward the use of the model in simulation and circuit design
[29, 30].
In Figure 16.6, we compare the modeled drain current with the drain current
calculated through the numerical simulation of the long-channel device. For Vds
varied from 0.0 V to 1.4 V, and Vgs = 0.8 V to 1.2 V and 1.4 V, the results that we
have obtained by compact modeling present a good precision compared to the results
of the numerical simulation carried out by SILVACO-TCAD.
In Figure 16.7, the modeled drain current is compared with that obtained by the
digital simulation of the short-channel device L = 60nm . We see that the shift due
to the DIBL effect and the VT Roll-off is well included. The current of the model
coincides with the results of the digital simulation both in the case of long- and short-
channel devices.

FIGURE 16.7 Variation of drain current depending on the drain voltage of the short-chan-
nel DG MOSFET (Semi-Log scale). Line: model; symbols: digital simulation
254 Circuit Design for Modern Applications

FIGURE 16.8 Variation of grid-grid capacity depending on grid voltage. Line: model; sym-
bols: digital simulation.

In order to validate the modeling results that describe the dynamic appearance of
the component, we compare grid capacity (main capacity C gg  Csg  Cdg ) with
the digital simulation of the component. According to Figure 16.8, a good agreement
is also achieved in the case of the grid capacity of a DG MOSFET equal to 300 nm
in length.

16.6.2 Drain Current Analysis and Influence

of Technological Parameters

Figure 16.9, shows the variation of the modeled current according to the tensions
applied on the grid Vgs and the drain Vds , for a device of canal length 1µm , width
fixed to W = 1µm and constant mobility µ = 1000cm 2 / V .s .
In Figure 16.10, we present the influence of double-grid TMOS technological
parameters, such as silicon channel length and oxide thickness. We can see that
the reduction in length ( L = 1.0 : 0.6µm ) (Figure 16.10(a)) and oxide thickness
( tox = 2.0 : 1.5µm ) (Figure 16.10(b)) are accompanied by an increase in drain current
and the current Ion .

16.6.3 Mobility Degradation Effect

Figure 16.11 shows the variation of drain current based on grid voltage for 100nm
channel length double-grid TMOS, a thickness of 25 nm for silicon and 2 nm for the

FIGURE 16.9 Transfer features (a); output features (b), for a long-channel DG MOSFET
Multiple-Gate MOSFET Model Implemented in Analog Circuits 255

FIGURE 16.10 Transfer characteristics for DG MOSFET: influence of canal length

L = 1.0 : 0.6µm (a); influence on oxide thickness tox = 2.0 : 1.5µm (b)

FIGURE 16.11 Influence of the mobility degradation effect on the transfer characteristic of
the double-grid TMOS.

oxide. From this figure, we can see the effect of the degradation of mobility under
the influence of the transversal and lateral electric fields. This degradation is essen-
tially reflected in the reduction of the drain current and especially the current Ion.
In the case of constant mobility Ion( µ0) = 0.0136 A , as in the effective mobil-
ity Ion( µeff ) = 0.0105 A .

16.7. APPLICATION: CIRCUITS SIMULATION

In this part, we will perform simulations and especially a time analysis of circuits
based on double-grid TMOS. For this, we implement the model in a hardware
description language (HDL), in our case the Verilog-AMS. The Verilog-AMS code
is then inserted into the HDL simulation stream of the SMASH circuit simulator.

16.7.1 HDL Simulation Flow Description

Generally, the main steps of a SMASH circuit simulator HDL simulation are divided
into three parts [31]. This is as shown in the organigram in Figure 16.12:
Figure 16.12 shows the organogram of the main steps of the HDL simulation fol-
lowed by SMASH. In the first part, HDL templates are compiled into binary shared
256 Circuit Design for Modern Applications

FIGURE 16.12 Organigram describing the main steps of HDL simulation in the SMASH
environment.

libraries; then they are added to the main catalog. The second part is devoted to the
development and linking of each example of the model to the design hierarchy. The
development is carried out by loading the modules into the design hierarchy, link-
ing each example to its ports, and solving hierarchical references. The last part is
reserved for the simulation and execution of the elaborated design.

16.7.2 Model Implementation in Verilog-AMS Language

In order to use the DG MOSFET compact model in the HDL simulation flow, the
model must be implemented in a hardware description language (HDL), such as
Verilog-AMS or VHDL-AMs [32, 33]. Indeed, the implementation of the models in
HDL language allows the direct use of the latter by different circuit simulators, such
as SMASH, SPECTRE, ELDO, etc.
Verilog-AMS is one of the most widely used hardware description languages. In
addition, this language is very suitable for compact modeling, it acts as an interface
between the circuit simulator and the compact device model [29, 30]. In addition,
the Verilog-AMS combines Verilog-HDL and Verilog-A into a single Mixed Signal/
HDL language. One of the unique features of Verilog-AMS is that it provides the
automatic insertion of interface elements so that analog and digital models can be
directly interconnected even if their terminal types are not compatible [33].
We have implemented the DG MOSFET model in the Verilog-AMS language. In
the SMASH circuit simulator, the code of the model (module) is in the form of a file
(input file) with the extension “.VAMS”. It is then executed through a file extension
“.CIR” which describes the circuit, interconnections, circuit elements as well as the
control instructions required for the simulation of circuits.
Figure 16.13 shows the execution results of the Verilog-AMS code of the DG
MOSFET model in the SMASH circuit simulator. The obtained results are in the
form of transfer characteristics (Figure 16.13(a)) and outputs (Figure 16.13(b)). The
results are valid from the low to the high reversal regime thus for different voltages
of grid Vgs and drain Vds.
Multiple-Gate MOSFET Model Implemented in Analog Circuits 257

FIGURE 16.13 Transfer characteristics for different drain voltages Vds (a); output charac-
teristic for different grid voltages Vgs (b), for a long-channel DG MOSFET (L = 1 µm, tox = 2
nm and tsi = 25 nm).

16.7.3 The Colpitts Oscillator Based on Dual-Grid Nanometric TMOS

16.7.3.1 Operation and Oscillation Conditions
Oscillators are electronic circuits that generate periodic signals at constant or vari-
able frequencies. This is from a continuous source of energy. This type of circuit has
many applications in communications systems, such as signal modulation and gen-
erating a reference frequency [34]. The Colpitts oscillator is one of the most widely
used sinus oscillators. Indeed, it has several advantages such as frequency stability,
low energy consumption and good noise performance. In addition, this type of oscil-
lator is widely used (in practice) in high frequencies.
The Colpitts oscillator can be considered to be a locked system that is divided
into two parts: an active circuit which is an amplifier based on an active component,
such as the double-grid TMOS, and a passive circuit that uses passive components,
like inductions and capacities (LC) [35]. In a closed loop, the active circuit is respon-
sible for achieving the stability of the signals by saturation and amplification as well
as compensating for the losses of the resonant part. However, the passive circuit is
responsible for the selection and stabilization of oscillation frequencies. The active
circuit is counter-reacted by the passive circuit which is an LC circuit performed in
a bridge to the mass (often called a resonator circuit).
In general, in a closed loop this system generates oscillations only when the
Barkhausen criterion is verified [34]:

G ( jw).H ( jw) = 1 (16.35)

arg G ( jw).H ( jw)  0  2k k  N (16.36)

258 Circuit Design for Modern Applications

Where:
G ( jw) is the transfer function of the oscillator active element
H ( jw) is the transfer function of the passive reaction cell
The oscillations are obtained initially if the loop gain is much higher than the
unit G ( jw).H ( jw)  1 . This gain is then returned to the unit when the oscillations
are established.
In the general case, the frequency of the signal generated by the Colpitts oscillator
depends on the passive components of the resonator circuit (two capacities and one
induction).

16.7.3.2 Presentation of the Considered Circuit

Figure 16.14 shows the scheme of the oscillator, it being a Colpitts-type oscillator
with an LC resonator circuit. L A represents a shock induction. CA is a bonding capac-
ity; CB and CD are disconnecting capacities. The resonator circuit consists of two
capacities CRA, CRB, and the induction L RA. Vdd is the continuous polarization voltage.
The values of the passive components are given in Table 16.2. The polarization ele-
ments were chosen to assume an operating point in the linear regime.

16.7.3.3 Time Analysis and Stability

Based on the DG MOSFET model implemented in the Verilog-AMS language, we
will perform simulations to make a time analysis of the Colpitts oscillator. For that,
we use the SMASH circuit simulator (Mixed-Mode).
The time simulation allows one to obtain the transitory behavior of the oscillator
in question, it also allows one to visualize the evolution of the output signal of the
Colpitts oscillator based on the DG MOSFET according to the time (Figure 16.15).
In the figure below, we can clearly see the fast stability of the entertained oscillations
generated by the oscillator, which begins after the instant t ≈ 194 ns. The frequency
of the generated signal is almost equal to 0.17 GHz and the signal amplitude is 7 V
(hill to hill).
In oscillators, the frequency of the generated signal is a crucial parameter. In
the case of the Colpitts oscillator the oscillation frequency can be calculated
1 1  1 1 
by: f osc  . . 
2 LRA  CRA CRB 

FIGURE 16.14 Scheme of the considered circuit: Colpitts oscillator

Multiple-Gate MOSFET Model Implemented in Analog Circuits 259

TABLE 16.2
Values of the components of the considered circuit
Resistances (Ω) Capacities (F) Inductances (H)
RA RB RC RD CA CB CD CRA CRB LA LRA
75K 120K 50 50 5n 10n 10n 3p 2p 30n 1µ

FIGURE 16.15 Evolution of the output voltage depending on the time of the Colpitts
oscillator.

Theoretically, the oscillator in question generates oscillations with a fre-

quency equal to 1.43 GHz. The difference between the recorded frequency (0.17
GHz) and the theoretical one (1.43 GHz), lies in the fact that in the equation
1 1  1 1 
f osc  . .  , the calculation does not take into account the
2 LRA  CRA CRB 
polarization impedance. In reality, the resistances RA and RB put in parallel with
the induction LRA thus reducing the value of the generated frequency.

16.7.3.4 Impact of the Reduction of the Component’s Technological

Parameters on the Circuit Time Response
The impact of the time response variation of the establishment of the entertained
oscillations of the Colpitts oscillators is analyzed through the temporal simulation of
the circuit and the time-based analysis of the output signal. This analysis is carried
out for different technological parameters of the double-grid TMOS, such as channel
length L and oxide thickness tox .
In Figure 16.16, we present the influence of the reduction in the length of the
channel L = 2, 1.5, and 1 µm. While the impact of the oxide thickness tox = 2 and 1.5
nm of a DG MOSFET is highlighted in Figure 16.17. We can therefore see that the
more the channel length and the oxide thickness of the DG MOS are reduced, the
shorter the time response and the establishment of entertained oscillations. This is
related to the variation in the quantity of the charge and the current of the transistor,
thus modifying the gain of the latter. As expected, the reduction of technological
parameters of the considered double-grid TMOS at the level of the oscillator allows
for the optimization of the temporal response of the Colpitts oscillating circuit and
therefore its speed. This also reduces the circuit size of the considered oscillator
260 Circuit Design for Modern Applications

FIGURE 16.16 Impact of the channel length L, with tox = 2nm, tsi = 25nm, W = 1µm.

FIGURE 16.17 Impact of oxide thickness tox, with L = 1µm et tsi = 25nm, W = 1µm

based on the dual-grid TMOS architecture, and makes the DG MOS an excellent
candidate for the realization of RF oscillator circuits.

16.8 The Double-Grid Nanometric TMOS-Based Passive Charge Inverter

16.8.1 Considered Inverter Circuit
Another circuit application is the simulation and the study of a passive charge
inverter [36], which is a key element in electronic applications. The circuit of the
Multiple-Gate MOSFET Model Implemented in Analog Circuits 261

FIGURE 16.18 Inverter circuit scheme with passive charge and based on symmetrical DG
MOSFET.

FIGURE 16.19 Evolution of the output voltage of the passive charge inverter.

passive charge inverter is shown in Figure 16.18. R A is a resistance of 1 KΩ. The

symmetrical DG MOS is described using the model's Verilog-AMS code, in the
same way as the Colpitts oscillator.

16.8.2 Temporal Simulation and Performance Analysis

The temporal simulation of the passive charge inverter allows the evolution of the
output voltage depending on the input signal (Figure 16.19). Through this figure,
we can see the right behavior of the inverter. That is, when the transistor is locked,
the output of the inverter is in the ON-state (≈ Vdd). In the case that the transistor
is passing, a current circulates and generates a voltage drop at the ends of the resis-
tance, and the output of the inverter is then in the OFF-state.
Figure 16.20 shows the result of the time simulation of the inverter for a rectangu-
lar input signal of an amplitude equal to 5 V. It can be seen that the output signal is
quite the opposite of the input signal. Moreover, we can see the speed and linearity
of this type of inverter based on DG MOS (no signal distortion and no delay in set-
ting time).

FIGURE 16.20 Inverter temporal simulation: input signal (a); output signal (b).
262 Circuit Design for Modern Applications

16.9 CONCLUSION
In the first part of this chapter, we presented a compact modeling of DG MOSFET
nanometric, this modeling is based on a basic physical approach. The static and
dynamic behavior of the double-grid TMOS is well described for both long- and
short-channel devices. The short-channel DG MOS modeling was made possible by
taking into account short-channel effects, such as DIBL, V T Roll-off and the effect
of the degradation of carrier mobility.
In order to calculate the charge density, we performed an iterative charge calcula-
tion using the Newton-Raphson method. The problem of iterative charge calcula-
tion is then solved, through a direct calculation procedure built on the Taylor series
development of the “charge” function. The results are validated by digital simula-
tions obtained with the ATLAS tool of the marketed SILVACO-TCAD software.
The results obtained are consistent with those of the digital simulation.
In the second part of this chapter, we aimed at a “circuit” application of the devel-
oped model. For this, we implemented the nanometric DG MOSFET model in a
hardware description language, which is Verilog-AMS. We then analyzed the per-
formance of the device under consideration through the time simulation of the cir-
cuits based on DG MOSFET, such as the Colpitts oscillator and the passive charge
inverter.
For this, we used the SMASH circuit simulator. The results of the “circuits” simu-
lation show the reliability and effectiveness of the Verilog-AMS code of the devel-
oped model. The use of the model in industrial applications, such as the development
of new integrated circuit architectures, may be considered.

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36. J. Goguet, “Contribution à la modélisation physique et électrique compacte du transis-
tor à nanotube”, PhD thesis, Bordeaux 1 University France, 2009.
 17 Design of an Impedance
Attenuated Control
Loop for Flipped
Voltage Follower-Based
Output-Capacitor-
Less LDO Regulators
Shri Antaryami Panigrahi

17.1 INTRODUCTION TO LDO VOLTAGE REGULATORS

Output capacitor-less LDO regulators (Silva, 2020) are preferable choices for deliv-
ering DC power at absolute accuracy and speed, compared to integrated converters
(Martinez et al., 2022). As per the requirement of an operating mode, i.e., low-power
or normal mode or sleep mode, a block in an SoC may demand varieties of current
levels within some time constraints (Benini et al., 2000). In this scenario, designing
capacitor-less LDOs with a low quiescent current budget and fast transient response
that can maintain the same performance for varieties of capacitive loads are key
to the performance of the entire SoC. When it comes to implementation, an SoC
exploits the low voltage and high-speed operation offered by the lower technology
nodes so as to increase the efficiency and bring down the dynamic power. This can
germinate other challenges such as the need for very low drop-out voltages, poor
line and load regulation, inability to drive a wide range of loads, etc. This trade-off
between low quiescent current and fast time domain response that can support a
wide range of loads along with other specifications, makes the design of LDO fairly
complex. The key motivation for this research is to analyze the existing approaches
based on their driving capacity, response time, and quiescent current, eventually
designing a highly stable, fast transient response LDO regulator with good figure of
merit (FoM) to cater for the need of SoCs.
Observation of Table 17.1 leads to the fact that wide BW leads to faster load regu-
lation, while fast slewing (Bu et al., 2017) at the gate node of the pass transistor leads
to a fast recovery time of the LDO. The slew rate limitation with respect to GBW
leads to the germination of notable voltage spikes during the sharp load transitions.

DOI: 10.1201/9781003483052-17 265

266 Circuit Design for Modern Applications

TABLE 17.1
Conventional PMOS vs Flipped Voltage Follower-Based LDO
Key Parameters Expressions FVF-based PMOS-based LDO
Line Regulation ∆Vout/∆VLine 1/Av,O
Load Regulation ∆Vout/∆Iout Zout ≃ 1/A_v,O Gm,P
Response time t_R 1/BW,CL + Cpar..VG/I_SR
Power supply rejection PSR_DC Av,O

On the other hand, line regulation, and regulation accuracy are dictated by the loop
gain (Milliken et al., 2007), but the intrinsic gain offered by the implemented gain
stages is usually very low in the recent CMOS technologies. So the pursuit of gain
can be achieved with the cascaded gain stages, but they can harm the bandwidth,
because of the occurrence of few high-impedance nodes in the loop. Impedance
modulation can be employed to reduce the impedance of such particular nodes to
improve the BW and subsequently response time to the sharp transients. On the
other hand, low output impedance (Zout) is desirable for an LDO to have better load
regulation. A flipped voltage follower (Man et al., 2008; Lu et al., 2016) based LDO
offers potentially low Zout to meet the specifications regarding the DC load regula-
tion and supply ripple rejection. A flipped voltage follower (FVF) stage can sustain
the stability issue pertaining to large capacitive loads offered by the SoC.
So an analysis of the control loop is necessary to design fast response LDOs,
which is presented in Section 17.2, followed by the discussion on impedance modu-
lation techniques. Conditional stabilities of the various techniques are investigated
through theoretical explanations. An impedance modulation scheme is proposed and
the performance is analyzed in Section 17.3 along with the comparison of the con-
ventional buffers with the same power. The stability of the proposed LDO assisted
by the proposed impedance modulator is presented in Section 17.3.6. A detailed
study of regulation characteristics of the proposed LDO is discussed in Section 17.4,
through simulations.

17.2 CONTROL LOOP OF FLIPPED VOLTAGE

FOLLOWER-BASED LDO
The FVF stage usually behaves as a single pole system for output capacitor-less-
based LDO designs. The low output impedance offered by an FVF stage can ease
the stability issue of the regulating loop, but the amount of loop gain it contributes
is not enough for a proper DC line regulation and supply ripple rejection. So addi-
tional gain blocks can be assisted by the conventional FVF stage (Man et al., 2008)
for quenching gain aspects. This leads to stability overheads at a variety of loading
conditions, and hence impedance modulation at critical nodes is essential in FVF-
based design of LDO, in bringing down the impedance offered by a typical node.
The reduced node impedance usually alleviates the associated poles and improves
Design of an Impedance Attenuated Control Loop 267

FIGURE 17.1 FVF-based LDO regulator circuit: a. Control loop, b. Poles occuring in
s-plane.

the phase margin, i.e., in the absence of impedance modulation the pole ωp,G wors-
ens the phase margin (PM) which is explained in Figure 17.1. The voltage buffers
(Al-Shyoukh et al., 2007) have been deployed as a key modulator that sets the gate
node of the pass transistor (MP) apart from the high-impedance nodes of the gain
blocks. The regulation specifications are duly controlled by these gain stages. The
parasitic Cgs,P of the orders of 10’s of pFs at the gate of the MP transistor impacts
the stability if it is acting non-dominant pole (ωp,G) Impedance modulation is a key
mechanism to enhance the loop bandwidth. The loop gain of the control loop of the
FVF-based LDO can be expressed approximately as the product of the transfer func-
tion of individual stages forming the loop, which is represented as:

TFopen  s   TFgain  s   TFImp  s   TFf vf  s  (17.1)

The stability of such a control loop can be evaluated with the help of two famous
approaches (Ogata, 2010): (1) the Routh-Hurwitz criterion, and (2) the Root–Locus
method. The characteristics equation can be considered for the evaluation of absolute
stability from the first approach. The control loop may have several loops, where
each loop needs to stabilize across the load variations. The recent impedance modu-
lation mechanisms employed in the FVF-based LDOs are listed here and analyzed
for stability in the section following.

17.3 IMPEDANCE MODULATION FOR ENHANCEMENT

OF STABILITY AND BANDWIDTH
The source follower, which usually precedes the PMOS power stage, acts as the
intermediate stage of the control loop. It not only deals with the stability of the over-
all LDO, but also handles the large signal slewing at the gate node of the pass tran-
sistor. In this context, a class A voltage buffer implemented with a source follower
can offer output resistance (Rout) of 1 //gm and a gain of ≤ 1 V/V. The Rout can be
made effectively smaller at the cost of quiescent current, to push the ωp,G away from
the operating bandwidth. For applications where LDO has to drive fairly large loads
(nFs of CL), the output node if not dominant, may contribute a non-dominant pole to
the overall control loop; which certainly impacts PM; so large quiescent current may
be necessary to improve stability.
268 Circuit Design for Modern Applications

FIGURE 17.2 Recent approaches employed for impedance attenuation in the FVF based
LDO: (a) Source follower (Chen and Leung, 2010), (b) Super source follower1 (Huang et al.,
2019), (Ma et al., 2019) (c) Super source follower2 (Choi et al., 2019), (Chang et al., 2014) (d)
Super source follower3 (Cai et al., 2020), (e) Adaptive Voltage Follower (Antaryami, 2022),
(f) Enhanced Super Source Follower (Antaryami, 2022) (g) Voltage combiner (Antaryami,
2022).

17.3.1 Control Loop with a Source Follower (SF)

The output DC resistance (Rout) offered by an SF stage (Figure 17.2(a)) is the inverse
of gm2 of M2. An enhanced stability can be achieved for an SF stage with modula-
tion of Rout, by raising the quiescent current IB1 for a specified size of M1 or by
raising the size of M1 at a specified quiescent power dissipation. The former method
leads to an increase in quiescent power, while the latter one escalates the parasitic
capacitance offered at the gate node of the FVF stage. An NMOS-based voltage buf-
fer can boost the slewing aspects of MP to counter the load transients compared to
PMOS-based SF. The loop gain of the control loop with SF as the impedance modu-
lator can be written by taking a cue from Equation 17.1 as;

 gm1Ro, 2   1   gmP Ro, 2 

   TFopen1 s        1  sRo, f Co, f  (17.2)

 1  s  Ro, 2C 2    1  sRo, sf Co, G   

FIGURE 17.3 Simulation summary ZOut of the buffers used for impedance attenuation.
Design of an Impedance Attenuated Control Loop 269

FIGURE 17.4 Signal flow graph of FVF-based LDO with SF as the impedance attenuator.

The stability can be achieved by ensuring the inequality described by the following
equation evaluated by the Routh-Hurwitz criterion:

 1  1 1  1 1   1 1 1 
    .   p 2  p, G  p, out 
 p , out   p 2  p , G   p 2  p ,G   
(17.3)
 1 1 1 
 ADC  p 2 . p, G . p, out 
 

The poles ωp,out represents the pole at the output node of the LDO, ωp,G is the pole
at the gate node of MP, ωp2 is the pole at the node “v2” as shown in Figure 17.4.

17.3.2 Control Loop with Super Source Follower (SSF) as

Impedance Attenuation (Liu and Chen, 2020)
Unlike the SF stage discussed in the previous section; an SSF stage (Figure 17.2(b))
enhances the Rout by gm3.rds3, because of the presence of current sink transistor
M3. However, the DC level shift contributed by the SSF stage is the same as that of
the SF stage, as both of the circuits have a PMOS in source follower action. In an
SSF1, the Rout is enhanced with the employment of single feedback through M3; but
in the SSF2 (Figure 17.2(c)), the DC output current is decreased by the deployment
of dual feedback path, i.e., through M3 and M4–M5 to enhance output resistance
(Choi et al., 2019). It essentially enhances the loop gain of the basic SF. This imped-
ance modulation scheme is applied by (Liu and Chen, 2020), along with another gain
enhancement loop through an error amplifier. The loop gain of the control loop with
SSF as the impedance modulator can be written by breaking both of the feedback
loops, i.e., the β(s) once broken can work as a load to the output of the LDO. By look-
ing at Figure 17.5 the loop gain can be written as:

FIGURE 17.5 Signal flow graph with SSF as the impedance attenuator.
270 Circuit Design for Modern Applications

 gm, EA.Ro, EA gm1Ro, 2   1 

TFopen 2  s     
 1  s  Ro, EAC , oEA  1  s  Ro, 2C 2    1  sRo, ssf Co, G 
(17.4)
 gmP Ro, 2 
 
 1  sRo, f Co, f 
where Ro,ssf represents the output impedance (DC) of the super source follower
stage.
The conditional stability for the control loop is evaluated by the expression as:

 1 1  1 1   1 1  1 1 
       
 p, out p, G  pEA p, 2    p 2 p, EA  p, G p, out  
(17.5)
 1 1 1 1  1 1 1 1 
     
 p, G p 2 p, EA p, out   p 2 p, G p, out p, EA 

17.3.3 Enhanced Super Source Follower (ESSF) Based

Control Loop (Antaryami, 2022)
Impedance attenuation can also be improved with cascaded versions of the PMOS
and NMOS source followers. The signal flow graph of the control loop with this
impedance modulation technique resembles the conventional SF-based design as
shown in Figure 17.4. The transfer functions of the impedance modulation stage can
be represented as:

 A _ inv.gm5  ASF .gm6 

H_ESSF  s   
1  sz1
 (17.6)
 A _ SF .gm6  1  sp1, SF 
Where z1 (left half plane zero) is derived as:

 p1, SF p1, inv  Ainv.gm5  ASF .gm6  

z1    (17.7)
 Ainv.gm5p1, inv  ASF .gm6p1, sf 
which is located outside the loop BW owing to the presence of a big positive quan-
tity in the denominator of Equation 17.4. The buffer offers Zout of 42.5 Ω up to 100
MHz, beyond which it shows an inductive effect caused by Cgs6 which hardly both-
ers the loop BW (Figure 17.6).

FIGURE 17.6 Signal flow graph of the LDO with voltage combiner-based impedance
attenuation.
Design of an Impedance Attenuated Control Loop 271

The loop gain of the control loop with ESSF as the impedance modulator can be
written as:

 gm1Ro, 2   1   gmP Ro, 2 

TFopen3  s        1  sRo, f Co, f 
 1  s  Ro, 2C 2    1  sRo, essf Co, G   
(17.8)

where Ro,essf represents the output impedance (DC) of the enhanced super source
follower stage.

17.3.4 Adaptive Voltage Follower: AVF-Based Impedance

Modulation (Antaryami, 2022)
The open loop gain of the NMOS-based SF stage is enhanced with the help of a
current mirror, i.e., the closed loop output resistance ROut,cl = ROut/(1 + βA) signifi-
cantly low impedance to push the ωp,G outside the UGB of the control loop.
The transfer function in Laplace’s domain can be expressed as;

 s 
1
H_Buf 
 ACS .gm5  ASF .gm6   z1

 (17.9)
ASF .gm6  1 s 
 p1, SF 
 
Where z1 (left half plane zero) is derived from Equation 17.9 as:

 p1, CG p1, CS  A _ CS .gm5  ACG.gm6  

z1    (17.10)
 A _ CS .gm5p1, CS  ACG.gm6p1,CG 
The LHP zero ωz1
improves the loop stability by increasing the PM. The pole at the output of the
AVF stage is presented as:

Av, CGgm6  gds, 6  7

p , Z  p , G  (17.11)
CZ  CG, P
where CZ is the buffer capacitance lumped at the Z node i.e., CZ = C,AVF and the
equivalent conductance gds,6−7 = gds,6 + gds,7. The zero contributed formed of the
feed-forward paths by the Cgs6 and Cgd7:

Av, CGgm6  Av, CGgm5

z , Z   (17.12)
Cgs 6  Cgd 5
This AVF stage offers a very low Zout of 42.5 Ω up to 100 MHz of loop band-
width. The comparison of all the buffers is already shown in Figure 17.3. Table 17.2
272 Circuit Design for Modern Applications

TABLE 17.2
Node Impedance Offered by the Voltage Buffers
Buffer Circuit High Zout Nodes Low Zout Node
SF [Figure 17.2(a)] Input Output
SSF [Figure 17.2 (b)] Input, Drain of M2 Output
VC [Figure 17.2 (e)] Gate of M5, Gate of M6 Output
AVF [(Antaryami, 2022) Drain of M2 Output
ESSF [(Antaryami, 2022)] NA Output, Drain of M2
This work Input Output

compares its basic features with the conventional source followers. The open loop
gain AVF stage as the impedance modulator can be written as:

 gm1Ro, 2   1   gmP Ro, 2 

TFopen 4  s       (17.13)
 1  s  Ro, 2C 2    1  sRo, avf Co, G   1  sRo, f Co, f 
The relative stability for the LDO with AVF in the control loop can be written as that
of the SF stage, mentioned in Section 17.3.1.

17.3.5 Control Loop with Voltage Combiner (VC)

as the Impedance Modulator

Although the stability can be improved with compensation; bandwidth can be lim-
ited, which will cause a slow response while tackling the large load current transients.
Feature of contributing to the gain along with stability, i.e., low output impedance
(≃ 1/(gm,cs + gmb,cs)) helps in isolating ωp,G makes voltage combiner (Povoa et al.,
2019) in Figure 17.2(e) as an alternative impedance modulation scheme. It can pro-
vide ⩾ 1 V/V of gain with proper bias, which can certainly improve the loop gain. It
can be fed with a common source stage (CS) and a common gate stage (CG) to take
advantage of splitting and combining the control loop, which can provide additional
degrees of freedom.
The transfer functions of such a stage can be represented as:

 s 
Av, CSgm7  Av, CGgm6  1 
H_VC   z1  (17.14)
Av, CGgm6  1 s 
  p1, CG 
 
The LHP zero Z1 improves PM and the pole ωp,G can be expressed as;
ωp,Z = ωp,G = Av,cg gm6 + g
The LHP zero Z1 improves PM and the pole ωp,G can be expressed as:
Design of an Impedance Attenuated Control Loop 273

Av, CG gm6  gds, 6  7

p , Z  p , G  (17.15)
CZ  CG, P
A zero is formed of the in-phase path leading to the output node of the buffer,
expressed as:

Av, CGgm6  Av, CSgm7

z , vc   (17.16)
Cgs 6  Cgd 7
The loop gain of the control loop with ESSF as the impedance modulator can be
written as:

 gm, EA.Ro, EA gm1Ro, 2   1 

TFopen5  s     
 1  s  Ro, EAC , oEA  1  s  Ro, 2C 2    1  sRo, vc Co, G 
(17.17)
 gmP Ro, 2 
 
 1  sRo, f Co, f 
where Ro,VC is the output resistance of the voltage combiner stage. The conditional
stability can also be evaluated with the help of Routh-Hurwitz criterion as men-
tioned in the previous subsections. To ensure the stability of all loading conditions,
a compensation scheme is employed in the proposed LDO. Miller’s compensation
with nulling zero is implemented with a resistor Rm, Cm2 to appoint the ωp,X as the
dominant pole.

17.3.6 Proposed Feed-forward Based Impedance Modulator

The preceding gain blocks in the VC-based impedance modulation mechanism
make the control loop a lot more complex, unlike the SF-based impedance modula-
tion. This complexity question arises mainly because of so many poles contributed
by the presence of multiple low-power gain blocks. Maintaining the symmetry in
slewing is a challenging task, which can be controlled with the help of a current
mirror-based feed-forward mechanism, which can certainly improve regulation dur-
ing load transients. So a current mirror-based feed-forward stage is preceded by the
NMOS source follower. The signal flow graph of the proposed attenuator is shown
in Figure 17.7. We can infer the relative stability by writing the open loop transfer
function, which is expressed as:

FIGURE 17.7 Signal flow graph of the proposed impedance attenuation mechanism.
274 Circuit Design for Modern Applications

 1  gm3 / gm4  1 
H_IA  s   gm6.  || rds5   .gm5  || rds5  (17.18)
 gm6  1  s   gm6 
 
  p , ND1 
 gm3   s 
  .gm5  gm6  1  
 gm4  z 2 
 . (17.19)
gm6  1 s 
  p , ND1 

Where ωpND1 is the non-dominant pole of the gain stage preceding the M5 transis-
tor and ωpND is the non-dominant pole contributed by the impedance attenuator
itself which is usually a high-frequency pole and gets canceled by the in-built zero
ωz2 formed by feed-forward path provided by M6.

1
ZOut, SF  s   (17.20 a)
gm1  gmb1  1 / rds, B  1 / rds,1  sC _ SF

1
Zout , IA  s   (17.20 b)
gm6  gmb6  1 / rds, 5  1 / rds, 6  sC _ IA
The loop gain for the proposed impedance attenuator (in Figure 17.3) can be found
by splitting the feedback loop at the folding node of the FVF stage and loading the
folding node with a similar environment as discussed in Man et al. (2008) written
with the help of the Figure 17.4 as:

Av11  s / z1 AvIA 1  s / z 2  Afvf 1  s / z3

Tloop | LDO  s   . . (17.21)
1  s / pD 1  s / pND1 1  s / pOut
If we compare each of the impedance modulation schemes discussed above, it can be
inferred that the relative stability is primarily evaluated with an initial assumption
of the static nature of the poles associated with the high-impedance nodes within
the loop. However, it is not always the case, as some nodes may be dynamic in
nature owing to their association with the output node. But for an FVF-based LDO,
the output is always kept at low output impedance for all possible loading condi-
tions, which is intrinsically a low impedance stage. As far as design for stability is
concerned these conditions can be achieved either at the cost of increased quiescent
current usage or with the help of suitable methods of frequency compensation. For
the proposed work, the frequency compensation method is employed to maintain the
absolute stability intact, which is presented in the following section.

17.4 FVF-BASED LDO REGULATOR WITH

PROPOSED IMPEDANCE MODULATOR
This mechanism is implemented by steering the output voltage of the cascode gain
stage through a non-inverting gain stage formed by the NMOS current mirror. The
Design of an Impedance Attenuated Control Loop 275

FIGURE 17.8 Proposed LDO regulator with the Impedance modulator and slew enhance-
ment circuit.

current mirror with M4 and M5 transistors provides an additional feed-forward stage

leading to the gate node of the pass transistor. It can be suitably used to cancel the
undesired non-dominant poles in the control loop. The mechanism also eliminates
the need for another transistor stack typically used for PMOS source follower action,
which was used in the attenuators discussed in the AVF-based and ESSF-based
impedance attenuators.
This supports low supply voltage requirements, however it may add up to the
overall PSR characteristics of the LDO. The PSR response can be minimized with
cancellation circuitry if needed. The circuit diagram of the proposed LDO is shown
in Figure 17.8.
The output capacitor-less FVF LDO uses a control voltage generator as discussed
in Lu et al. (2015) to drive the VC signal on MC1 transistors of Figure 17.3. The
power transistor is sized to 2 m/250 nm, and the bias current sums up to 40 uA at
the no-load condition.
The LDO with the impedance modulator discussed above is designed in 45 nm
CMOS technology with Vth0,n = 0.469 V for the NMOS, Vth0,p = –0.418 V for the
PMOS. Two on-chip capacitors Cm1 = 2pF, Cm2 = 50pF are used for maintaining
unconditional stability
even at worst case loading, i.e., light load current and as high as 1nF of capacitive
load conditions along with a nulling resistor Rm = 5k Ω. The load current drive var-
ies from 0 µA (during light load) to 30 mA (during heavy load). The DC line voltage
regulation characteristics of the LDO are shown in Figure 17.9, which shows the
regulation starts at 1.1 V and maintains an output of 1.06 V up to 2.0 V for various

FIGURE 17.9 Simulated Line regulation characteristics of the LDO regulator.

276 Circuit Design for Modern Applications

FIGURE 17.10 Simulated transient response of LDO for CL variations, along with their
edge responses (bottom left: falling edge, bottom right: rising edge).

load current conditions. The DC variation at 100 µA is around ± 2 mV from the

regulated value of 1.05 V obtained at 1.13 V, whereas the variation at IL,max of 25
mA is approximately ±5 mV. The loading capacity of the LDO is simulated in Figure
17.10 with 0 pF, 200 pF, and 1nF for load current transitions from 0 µA to 30 mA
with 1ns edge. The recovery time is well within 5 ns even for 1nF CL, although a 1%
settling time is around 25 ns. Thanks to the impedance modulator and the transient
improvement circuit which helps in obtaining the fast response time and 1% settling
time respectively 104 ps and 31.6 ns respectively from the LDO, i.e., for a heavily
capacitive load as 1 nF applications such as programmable memories. The compari-
son of the existing works for time domain analysis is presented in Figure 17.11, i.e.,
the adaptive voltage follower-based LDO shown in Figure 17.2a, conventional source
follower-based LDO in Figure 17.2b, the super source follower-based LDO shown in
Figure 17.2c is proceeded with a similar gain stage in Figure 17.2a for a fair com-
parison. Overshoot and undershoot of 51.5 mV/49.5 mV is observed for the proposed
work compared to the adaptive voltage follower-based LDO in Figure 17.2. a, but the
∆VOut of the former is within 6mV, whereas the latter has around 14.3 mV.
The response time calculation is quantified (Hazucha et al., 2005) as:

VOut
Tr  C  (17.22)
I L ,max

FIGURE 17.11 Simulated transient response of LDO across impedance mechanisms.

Design of an Impedance Attenuated Control Loop 277

IQ
FoM  Tr  (17.23)
I L ,max
where C happens to be the total on-chip capacitance used, ∆VOut refers to the maxi-
mum deviation in VOut, IL,max is the maximum output current drive and IQ is the
quiescent current. In this work, a recovery time of 104 ps is attained for a 1 ns sharp
transient in load current, owing to the impedance modulation used in the control
loop at 200 pF load. Table 17.3 gives a detailed comparison of the proposed LDO
with respect to recent works. It can be observed that though the work of Huang et
al. (2019) presents the second-best FoM, but edge time of the transients, quiescent
current usage, and integrable capacitors are not considered for the FoM. Whereas the
work presented by Liu and Chen (2020) has limited IL,max, and edge time for the
load transients are pretty slow, i.e., 100 ns, which hardly fits into the IoT applications
with fast dormant to active transition times.

17.4.1 Stability and Compensation

The primary LDO circuit along with the slew enhancer circuit, the current sink
transistor, the feed-forward capacitor C f and the control voltage generator circuit
makes it a multi-loop architecture. So the primary loop of the LDO involving the
impedance modulator can help in dealing with the non-dominant pole ω p ,G , but
other non-dominant poles such as the pole at the “X” node, the mirror pole at the
“V3” node in Figure 17.7 can also come close during high loading (IL) conditions
toward the dominant pole. The capacitor C f can add up to 2 pF to the X node, form-
ing a potential pole. So a foolproof compensation scheme is employed to deal with
the stability against the varying loads and PVT variations. The Rm resistor of 4 kΩ,
and Cm2 of 40 pF are chosen for the compensation.

17.4.2 Transient Discussions
The load may demand current varying over several orders, i.e., 100µA to 10 mA
within a very short interval of time i.e., of the orders of 100 ns as the system require-
ments. This fact can be explained simply by considering the large signal slewing
behavior of the LDO, under such transients. However, the overall droop of the out-
put-regulated voltage is a complex phenomena involving phase margin, immediate
response management during overshoot/undershoots, etc., which is beyond the intui-
tive modeling required here.
The output node of the LDO falls to a sharp negative value, for which the slew
enhancement circuit is added. This circuit adds an alternative fast response path to
control the slewing of the gate node of the MP transistor unlike the path through M2
→ M3 →M4 → M5 which adds multiple pole-zero leading to a slow responding gate
node.
278 Circuit Design for Modern Applications

TABLE 17.3
Comparison of Performance with the Literature
(Lu (Cai (Tan (Koay (Huang
et al., et al., et al., et al., et al.,
Parameters This work 2015) 2020) 2014) 2013) 2019)
Impedance
Attenuation VC-based SF ESSF NA NA SSF
Technology 45 nm 65 nm 65 nm 65 nm 180 nm 65 nm
Vin (V) 1.2 1.2 1.2 1.2 1.8 1.3
Vout (V) 1.05 1.0 1.0 1.0 1.0 0.6–1.1
Iq (µA) 40–70 50–90 27–82 50–93 13.2 50–190
IL,max (mA) 30 mA 10 mA 50 mA 10 mA 50 mA 50 mA
On-Chip cap (pF) 52 144 300 153 10 122.5
Line reg. (mV/V) 8 37.1 NA 8.89 217 1
T_edge (s) 1n 0.2n 0.8n 100n NA 2n
Tr (s) 104p 1.75n 1.95n 9.44p 77p 6.28p
C_L (F) 0p-1n NA 300p 10p-10n 10p-100n 0-2n
FoM (Hazucha, 2005) 0.2496ps 8.75ps 7.995p 0.004ps 20.32ps 0.0238ps

17.5 CONCLUSION
The control loop of the flipped voltage follower-based LDO is analyzed by consider-
ing several recent topologies to improve the response time. Impedance modulation
techniques conventionally employed in the control loops are simulated for the same
power and compared against each other. A feed-forward architecture-based imped-
ance modulator is proposed to tackle the bandwidth bottleneck of the loop. An FVF-
based output capacitor-less LDO regulator is designed with the proposed impedance
modulator in PTM 45 nm CMOS technology. The LDO shows a competitive FoM
against the recent works, which makes it suitable for optimal voltage regulation in
SoC applications.

BIBLIOGRAPHY
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 18 III-V Material-Based Lateral
Beyond Silicon

and Vertical HEMTs for High-

Power and High-Speed
Switching Applications
Danielraj A, Saravana Kumar R,
Sanjoy Deb, and Balakrishnan R

18.1 INTRODUCTION
The most significant growth in the field of electronics is the transistor; when the first
transistor was created, transistor-based technological innovations quickly gained
traction in the marketplace. Compared to germanium (Ge), a competitor semicon-
ductor, silicon (Si) has been used in transistors since 1960 due to its availability in
nature. In Figure 18.1, Gordon Moore, an Intel co-founder, proposed “Moore’s law”
in early 1965, which states that a silicon chip’s transistor count doubles every 18
months. In order to lower the number of transistors in a circuit, researchers worked
on a number of logical technologies.
CMOS technology is one of the most studied and used technologies. The first
silicon-based MOSFET was developed in the 1980s, paving avenues for the develop-
ment of CMOS devices. A key player in the semiconductor business, CMOS delivers
unique characteristics that enhance logic properties while reducing the size of the
device. Therefore, Si-CMOS scaling technologies offer excellent density, reduced
power consumption, fast switching speed, and improved device performance. Dae
Hyun and Del Alamo [1] and Kim, Kim, and Del Alamo [2] addressed a number of
limitations on down-scaling in relation to CMOS technology over time. Addressing
the essential challenge of transistor scaling without compromising its physical quali-
ties is necessary. In recent years, researchers have primarily focused on reducing
the IC’s transistor size. CMOS standard logic technology has experienced scaling
restrictions due to the short-channel effects of the lithography process due to static
and dynamic energy dissipation during switching. The thermal effects of a gate
length below 5 nm will also restrict the growth of CMOS technology. Researchers
predict that additional Si-based field-effect transistors (FETs) and CMOS develop-
ments will soon reach a fundamental down-scaling limit. Scholars speculate that

DOI: 10.1201/9781003483052-18 281

282 Circuit Design for Modern Applications

FIGURE 18.1 Transistor count every two years, followed by Moore’s law.

Moore’s law may have already reached its inevitable conclusion. Thus, instead of
concentrating on Si, researchers are trying to find other channel materials with sub-
stantially higher carrier transport velocities. The usage of innovative semiconductor
channel materials with higher transport capacities over Si allows for further device
scalability.
Si FETs might eventually be replaced by devices based on III-V, 2D, or carbon
nanotube materials due to their higher mobility and ability to be fabricated at an
ultra-scale. In the manufacture of transistors, GaN-based III-N compound semicon-
ductors have the potential to surpass silicon as one of the most inventive new chan-
nel materials. GaN HEMTs based on III-N material used in power electronics and
high-speed switching applications are the main focus of this development. GaN-
based HEMTs provide a number of benefits over silicon (Si)-based transistors, [3]
including higher critical electric field strength and high-electron-mobility, especially
III-N semiconductors. HEMTs have a high potential for high-speed and high-power
capabilities.
Electrical power is essential to our everyday lives and has been a major force
behind human progress. Because they regulate and transform electric currents, volt-
ages, or power electronics are essential components of power consumption. They
are widely used in consumer goods, energy harvesting, and applications, including
motor drives, power converters, switching power supply, and power inverters. Power
devices are a major part of various operating domains like consumer electronics,
hybrid vehicles, military, motor drivers, aerospace, etc. A power conditioner is one
of the important parts of power electronics, which is made up of several semicon-
ductor devices operating in switch mode, where the gate driver controls the devices’
transitions between the “OFF” and “ON” states. An ideal switch should have a full
voltage drop across it and no leakage current when it is switched “OFF”. It should not
have a voltage drop across it when turned “ON”. The truth is that the power devices
show an ON-state resistance (RON) and a leakage current—the breakdown voltage
(Vbr) under common bias, limiting the voltage across it. Therefore, a low RON and
high Vbr are important characteristics of high-power devices that can be achieved to
Beyond Silicon 283

maximize energy efficiency and minimize conversion losses. Gallium nitride (GaN)
has also become a more desirable material in the past ten years for semiconduc-
tor device fabrication. The cost, manufacturing feasibility, high-electron-mobility,
strong OFF-state breakdown voltage, and low noise are important factors that must
be taken into account. III-nitrides HEMT as a power-switching device can address
the problems stated by its large and direct bandgap. The range of the bandgap is 0.9
eV–6.2 eV.

18.2 III-V GAN DEVICES

The most recent advancement in nanodevice manufacturing opens the door to the
possible use of III-N semiconductor devices in high power, good gate control, and
high-speed applications. Compared to conventional silicon, III-N semiconductor
devices exhibit high-electron-mobility and unique characteristics. Furthermore,
III-V group materials are combined to form binary (GaN), ternary (AlxGa1–xN), and
quaternary (AlxGa1–xAsyP1–y) components to improve the better device performance.
III-V nitrides, which are focused on in this work, exhibit high sheet carrier con-
centration, wider bandgap, good electron mobility, low thermal impedance, and high
breakdown field [4]; chemical inertness, thermal stability, and radiation resistance
are further advantages of III-nitride materials, making them more stable. GaN is
the most common wide bandgap material utilized today, and GaN has bandgaps of
3.4 electronvolts (eV), whereas silicon is 1.1 eV. The material properties of GaN and
their associated device are given in Table 18.1. It has a built-in electric field due to
polarizations like spontaneous and piezoelectric. The necessity of energy conser-
vation in today’s environment and the large array of applications, like high-power
devices, have sparked the interest of researchers in the field of nitride-based devices
in recent years. The GaN devices applications in power electronics applications [5]
are represented in Figure 18.2.
In particular, the significance of III-N-based FETs is in the effective transmis-
sion of electric power at high temperatures and low-loss energy conversion. One of
the objectives is to develop GaN-based switches that operate fast and effectively at
high-power levels. In general, GaN devices have high power-handling capabilities.

TABLE 18.1
The Material Properties of GaN and Their Associated Materials
Thermal Saturated
Bandgap Breakdown Conductivity Mobility Velocity
Material Energy (eV) Field (MV/cm) (W/cm*K) (cm2/V*s) (*107 cm/s)
Si 1.1 1.5 1.5 1300 1.0
GaAs 1.4 0.5 0.5 6000 1.3
SiC 3.2 4.9 4.9 600 2.0
GaN 3.4 > 3.0 2.3 ~ 2000* 2.7
284 Circuit Design for Modern Applications

FIGURE 18.2 GaN devices applications in power electronics.

18.3 HIGH-ELECTRON-MOBILITY TRANSISTORS
HEMT is a type of field-effect transistor in which the channel is a heterojunction
rather than a doped area. As Seen in Figure 18.3, a heterostructure is a combina-
tion of III-N compound semiconductors with different lattice constants and band-
gaps. While forming the heterostructure, the lattice mismatch between the lower and
higher bandgap material must be minimal; otherwise, defects in the heterointerface
will be created. Defects in the crystal lattice have an impact on the device’s electri-
cal performance and must therefore be avoided [6]. These days, GaN HEMTs are a
popular and widely utilized device. They exploit the enhanced transport, breakdown,
and thermal stability of undoped GaN in addition to its high bandgap discontinuity
in the heterostructures. Figure 18.3 shows the lattice orientation of an III-N hetero-
junction, which creates a large bandgap discontinuity.
When two bandgap materials are combined, the energy bands bend until the
device reaches equilibrium. To this extent, electrons in the wide bandgap material
are depleted and accumulate in the lower bandgap material under equilibrium con-
ditions. The 2DEG is formed right beneath the heterojunction at the narrow and

FIGURE 18.3 Band energy diagram of AlGaN/GaN HEMT.

Beyond Silicon 285

wider bandgap materials interface, in which the carriers are accumulated and allow
for higher electron mobility. This is due to carrier diffusion from a wider bandgap
(heavily doped) region to a low bandgap (lightly doped) region, which could be fur-
ther improved using the bandgap engineering technique. Javorka [7] defines the car-
rier conductivity of 2D well-formed in HEMT.

  qns (18.1)

where µ, ns, and q, are the electron mobility, carrier concentration and charge of an
electron. The primary goal of a heterojunction device is to achieve a rapid bandgap
shift, which takes to the potential of a wider quantum well.
Figure 18.4 represents the basic structure of HEMT. The main layers of this struc-
ture are

• Barrier layer
• Buffer layer
• Channel layer
• Substrate

Barrier layer: This layer determines the resistance of the conduction channel.
It is always a wider bandgap than the channel.
Channel layer: The channel material should have a lower bandgap than the
barrier. The width and length of the channel layers can control the device’s
overall performance.
Buffer layer: The insertion of the buffer layer is determined by the substrate
material and the type of epitaxial growth technique used.
Substrate: Generally, the substrate acts as a heat sink from the package.

The alignment of source–drain, gate and other layers is shown in Figure 18.4 along
with a 2DEG formation. Even with a “0” gate voltage, a small current flows in the
2DEG channel. The source and the drain potential difference varies when the posi-
tive gate voltage is applied, resulting in a high flow of current, but the gate controls

FIGURE 18.4 Basic HEMT structure.

286 Circuit Design for Modern Applications

the current flow. High drain current (Id, sat) can be achieved by increasing ns con-
centration. As a result of the increased ns concentration, the 2DEG supplies more
carriers from source to drain.

18.3.1 AlGaN/GaN HEMT
The AlGaN/GaN heterostructure is formed when a barrier is built on a compara-
tively thick GaN layer. In conventional III-N devices, a doped layer is necessary to
form a 2DEG; however, in AlGaN/GaN, where polarization fields generate a chan-
nel, doping is not necessary to form a 2DEG with a very high electron concentration.
The heterojunction interface’s band offset or band discontinuity causes electrons to
accumulate below the Fermi level, which raises the 2DEG in these devices. As per
Figure 18.5, the electron attempted to drift from higher to lower bandgap surfaces.
In the process of growing AlGaN and GaN layers on top of one another to form a
heterojunction, mechanical strain, stress, and lattice mismatch cause polarizations,
namely piezoelectric and spontaneous polarization, in the atoms at the interface.
Electrons that tend to compensate for this positive charge by forming a 2DEG in
the quantum well at the heterostructure interface will fall under the Fermi level, as
shown in Figure 18.5 [2].
By modifying Al content in the alloy of AlxGa1–xN, it is possible to modify the
bandgap of III-N materials. The mole fraction “x” is often tuned to be less than
0.18–0.3 [8].

18.3.2 Lateral and Vertical Topology GaN HEMT Transistors

There are currently two topologies for GaN-based power transistors under con-
sideration: vertical and lateral structures. The AlGaN/GaN HEMT, depicted in
Figure 18.6, has the most promising lateral shape because it allows current to flow
laterally within the device. It makes use of an AlGaN/GaN heterostructure inter-
face-formed 2DEG. Strong piezoelectric and spontaneous polarization in III-nitride
materials give rise to an AlGaN/GaN structure with a high sheet carrier density [9].
AlGaN/GaN structure also shows low ON-resistance and strong electron mobility
(2000 cm2/Vs) [9].

FIGURE 18.5 On the left, the energy band of the hetero interface. In the right band, the
energy level heterostructure after equalization Fermi levels, which creates well.
Beyond Silicon 287

FIGURE 18.6 Basic lateral AlGaN/GaN HEMT structure.

The metal-insulator-semiconductor HEMT (MIS-HEMT) is an HEMT in which

the design combines the advantages of the metal oxide structure. In addition to con-
ventional HEMT, an insulator layer is added below the gate in MIS-HEMT, which
reduces the terminal leakage current, achieves high 2DEG, has a high breakdown
voltage and improves threshold voltage compared to Schottky HEMT structures.
Compared to lateral HEMT days, nowadays, a vertical topology is very nominal
for achieving low RON and high VBR [10]. Therefore, it has recently received much
attention. However, vertical GaN HEMT devices are still in the early stages. The
most commonly investigated vertical structure to date is the current aperture vertical
electron transistor (CAVET), which was initially demonstrated for a dispersion-free
performance described by [10] and shown in Figure 18.7. The device controls the
current flow along the 2DEG using an AlGaN/GaN structure. Current can only flow
through vertically through the drain because of the p-GaN current blocking layer
(CBL). Compared to GaN lateral topology HEMTs, more and more significant struc-
tural variations have been documented for GaN vertical topology power devices,
owing to the fact that research in this sector is still in its early stages.
In typically lateral devices, the presence of a 2DEG in the channel assures low
switching losses and low conduction losses. Compared to the GaN substrate used in
the vertical structure, the Later structure substrate Si is cheaper.

FIGURE 18.7 A GaN vertical MOSFET.

288 Circuit Design for Modern Applications

FIGURE 18.8 Normally-ON AlGaN/GaN HEMT structure.

18.3.3 Normally-ON HEMT
GaN HEMT is a depletion-mode device. The general structure of Normally-ON
GaN HEMT is shown in Figure 18.8. Passivation prevents surface degradation and
reduces trap states, ensuring improved overall performance.
GaN capacitors (GaN cap) play a crucial role in GaN HEMT circuits, providing
high-frequency filtering and energy storage. They minimize signal distortion and
optimize power efficiency.
The GaN channel facilitates high-electron-mobility, allowing it to operate at
higher frequencies with superior power density compared to traditional technologies.
GaN HEMT technology excels in power electronics applications, offering
high efficiency and reduced energy losses. The combination of passivation, GaN
capacitors, and a high-mobility GaN channel results in enhanced reliability and
performance.
GaN HEMT offers advantages like faster response times and simplified circuit
design. However, this characteristic brings drawbacks, notably increased power con-
sumption in applications favoring a normally-OFF state. Additional circuitry, such
as gate biasing, is required to control the device and prevent continuous power flow.
In power-switching applications, the normally-ON nature poses challenges for safety
and efficiency, necessitating strategies to ensure secure turn-OFF. Ongoing research
focuses on addressing these challenges and optimizing normally-ON GaN HEMTs.

18.3.4 Normally-OFF p-GaN Structure

Figure 18.9 shows the p-GaN structure for a normally-OFF device in HEMT tech-
nology. This technology involves utilizing a p-type gallium nitride layer to create a

FIGURE 18.9 Normally-OFF p-GaN AlGaN/GaN HEMT structure.

Beyond Silicon 289

barrier that prevents electron conduction with no applied voltage. The p-GaN layer
allows for normally-OFF operation, enabling enhanced safety and power efficiency
in certain applications. The absence of a continuous current flow when the device is
in its default state contributes to reduced power consumption and improved overall
energy efficiency.
However, drawbacks include the complexity of fabricating and optimizing the
p-GaN layer, potential challenges in achieving high-electron-mobility, and device
performance challenges. Additionally, the normally-OFF characteristic may intro-
duce increased switching losses during operation, affecting the efficiency of power-
switching applications. Balancing these factors is essential in maximizing the
benefits of the p-GaN structure for e-mode HEMT devices.

18.3.5 MIS-HEMT Structure
The metal-insulator-semiconductor HEMT (MIS-HEMT) structure features a thin
insulating layer between the gate electrode and the semiconductor channel, offer-
ing improved gate control and reduced gate leakage, as shown in Figure 18.10.
Advantages of the MIS-HEMT structure over p-GaN include enhanced gate control
precision, leading to lower OFF-state leakage current and improved overall power
efficiency.
The insulating layer in MIS-HEMTs contributes to better isolation between the
gate and channel, reducing the impact of parasitic capacitances and enhancing high-
frequency performance. MIS-HEMTs typically exhibit superior gate reliability, as
the insulator helps prevent gate degradation over time, resulting in enhanced device
longevity. MIS-HEMTs may offer improved scalability compared to p-GaN struc-
tures, making them suitable for advanced semiconductor processes and miniaturized
electronic devices.
The enhanced gate controllability of MIS-HEMTs enables precise modulation of
the electron channel, leading to better control over device switching characteristics
and reduced susceptibility to temperature variations. In summary, the MIS-HEMT
structure provides advantages over p-GaN configurations, including improved
gate control precision, reduced leakage current, enhanced high-frequency perfor-
mance, superior gate reliability, scalability, and precise modulation of switching
characteristics.

FIGURE 18.10 AlGaN/GaN MIS-HEMT.

290 Circuit Design for Modern Applications

18.4 DESIGN REARRANGEMENT OF GAN HEMT DEVICES

Enhancement AlGaN/GaN HEMT devices with low leakage current, low material
interface defect, high package density, and high breakdown voltage are required for
use in high-power, high-speed commercial applications. The following elements
need to be taken into account when constructing an AlGaN/GaN HEMT for high-
power uses.

18.4.1 Breakdown Voltage
One of the most vital design considerations for high-power transistors is the break-
down voltage. Existing devices attain much lower breakdown voltages than the theo-
retical limits. Thus, it is necessary to consider how to achieve a high breakdown
voltage of more than 1000 V without growing the device’s size.

18.4.2 ON-State Resistance
Like OFF-state breakdown voltage, ON-state resistance (RON) is also one of the acute
figures of merit for high-power devices. RON should be kept as low as possible to
minimize the size and cost. In addition, low RON lowers heat loss in the device, which
cuts the costs of additional cooling systems and heat sinks.

18.4.3 Normally-OFF
Since most GaN HEMT devices operate in depletion mode, high-power applications
prefer to use transistors in enhancement mode, which delivers better performance for
device driving and control circuit design.

18.4.4 Current Collapse Phenomenon

In conventional HEMT devices, a peak electric field at the edge of the gate at the
side of the drain causes surface leakage current due to the high field. With this,
electrons are often trapped because of surface traps and built negatively charged
regions (virtual gate), producing the current collapse during a switching transient.
This phenomenon affects the device performance at a high frequency by limiting the
device output power.

18.5 LATERAL TOPOLOGY TWO-FIELD PLATE ALGAN/GAN HEMT

Researchers are implementing different methods to achieve e-mode GaN HEMT
devices by changing the material mole fraction to reduce lattice mismatch in the
channel region, introducing a p-doped gate, high Al content channels, gate recess
engineering [6], recessed gate etching techniques [11], p-doping cap layer [12] and
adopting metal-insulator-semiconductor HEMT.
Beyond Silicon 291

However, the reported AlGaN/GaN-based devices have disadvantages such as

reduced ION, increase in terminal leakage currents, and high breakdown voltage Vbr.
Hence, to increase the performance of AlGaN/GaN HEMTs, achieving a positive
VT with low-power consumption, circuit simplicity, low ON-state resistance RON,
and fail-safe requirements is crucial. The objective of this chapter is to analyze the
device performance of the Two-field plate AlGaN/GaN HEMT device, with +ve VT
attained by effective gate recess engineering and PNT layer. The two-field plate tech-
nique is implemented to reduce device parasitic capacitance. The proposed device is
analyzed by iterating the gate recess depth Ddepth, gate length Lg and gate to source
length Lsg.

18.5.1 Device Geometry Description

Figure 18.11 represents the cross-sectional view of a 2-Field Plate (2FP) AlGaN/
GaN HEMT device to exhibit positive threshold voltage. The device is built on a
Si substrate. On top of the substrate, the AlGaN buffer layer, followed by the GaN
channel layer, AlGaN spacer layer, AlGaN barrier layer, and Thin GaN cap layer,
are arranged from below upwards. In between the barrier and spacer, the AlGaN
Piezoneutralization layer is used to provide VT uniformity. On the top, on both sides
of the gate, the device consists of a passivation layer. The field plate is attached to the
gate and extended toward the drain. Gate length Lg is varied, with field plate exten-
sion of LFP. It also has a GaN cap layer. The second field plate with length is between
the gate and drain to reduce the distance to achieve low gate capacitance. On top of
the 2FP AlGaN/GaN HEMT device, the source, and drain are formed.
The Piezoneutralization layer [13] provides better control over threshold voltage
in GaN devices. The PNT layer concentration is Al0.07Ga0.93N, which is less than that
of the barrier and spacer layers. The PNT layer with different AlGaN compositions
cancels the intervening polarization charges and gives a flat-band condition under

FIGURE 18.11 Proposed 2FP GaN HEMT device schematic cross-sectional view with
Piezoneutralization layer (PNT) and additional field plate.
292 Circuit Design for Modern Applications

FIGURE 18.12 Conduction band profile versus depth in μm for 2FP GaN HEMT compared
with convention HEMT device.

the gate. Consequently, these parameters can adjust VT. The devices experience a
reduction in the carrier with a decrease in AlGaN thickness. An increase in the gate
depth of the device can adjust the VT of the AlGaN/GaN HEMT device to +ve. The
gate depth modification in HEMT reduces the thickness of the buffer beneath the
gate, which reduces the 2-DEG concentration in the device. The disruption expe-
rienced by the 2DEG will shift the device’s VT in the +ve direction. Figure 18.12
shows band energy versus device depth for conventional AlGaN/GaN HEMT and
DFP AlGaN/GaN HEMT. The device also experiences an upward shift in 2DEG
formation. AlGaN layer thickness can be decreased by an increase in Ddepth of the
device along with preciously increasing gate length. The disturbance experienced by
2-DEG will move the VT of the HEMT in a positive direction.
Figure 18.13 shows DC characteristics, i.e., drain to source current Id vs gate to
source voltage Vgs. Simulation results of conventional HEMT structure in [10] and
proposed DFP AlGaN/GaN HEMT show enhancement in performance of the pro-
posed device in terms of drain current and by achieving e-mode operation. Results
are taken by varying gate length Lg, with constant gate recess penetration depth

FIGURE 18.13 Variation of ON-current current and threshold voltage characteristics mea-
sured with varying Lg, for proposed 2FP AlGaN/GaN HEMT.
Beyond Silicon 293

FIGURE 18.14 Breakdown voltage (Vbr) of proposed 2FP HEMT device with different
addition field plate length (LFP2).

Ddepth and fixed source-to-gate length Lsg. The device records the best saturation
drain current as Lg decreases. The device records maximum VT at maximum Lg. An
increase in Lg increases the resistance value, which improves the controlling ability
of the gate to channel, thereby increasing VT to the positive side.
Figure 18.14 shows the breakdown characteristics of the proposed device, with
the ideal dimension device achieving a breakdown voltage (Vbr) of 400 V. Schottky
contact at the source and drain suppression carrier injection in the source leads to
less leakage current during high voltage on the source side. Hence, the breakdown
voltage of the lateral HEMT becomes higher. The device’s performance has been
further enhanced by increasing the distance of the additional field plate. Figure 18.14
depicts the OFF-state breakdown voltage of the proposed device at different field
plate lengths. Enhancement in breakdown voltage for an increase in LFP2 is wit-
nessed, and maximum breakdown voltage (Vbr) 400 V is achieved at minimal LFP2.
Further increase in field plate length affects other parameters like drain current (Id)
and threshold voltage (VT) to a large extent.
Two-field plate HEMTs are designed, and performance parameters are observed.
Maximum threshold voltage is observed for maximum Lsg and maximum Ddepth at
a gate bias of 25 V. The PNT layer improved the device’s gate controllability. The
device with an additional field plate ensures even field distribution, and the peak
electric field is reduced with a recessed gate, which ensures substantial improvement
in RON. +ve VT is achieved without any give and take in RON and Id. Varying Lsg,
Ddepth, and Lg derives the proposed device’s ideal structure dimension.

18.6 VERTICAL TOPOLOGY CAVET ALGAN/GAN HEMT

Vertical devices are favored over lateral devices in order to improve device per-
formance, as previously indicated, coupled with high-current/voltage ratings and
a reduction in power losses. Because of the complicated construction of the CBL,
vertical HEMTs were previously addressed for being difficult to fabricate. However,
294 Circuit Design for Modern Applications

in recent works by numerous researchers, the structures of vertical HEMTs have

been successfully manufactured using methods such as molecular beam epitaxy, ion
implantation, and MOCVD to renew the structure [14]. Current aperture, vertical
trench MOSFET, and vertical electron transistor (CAVET) are the most widely used
notable gate structures in vertical topology devices [15].
One of the best structures is the vertical topology CAVET AlGaN/GaN HEMT
structure. In the device, the drain and source are in the same plane, and in the device,
a drift zone with n-type is employed to hold high voltage. Current travels from source
to drain horizontally. Although CAVET devices are typically depletion-mode devices,
e-mode devices are a superior choice for high-power devices when it comes to switch-
ing speed and safety (Ji et al., 2018b). In order to achieve e-mode in AlGaN/GaN
HEMT structures, approaches such as recessed gate techniques [16], field plate [17],
cascade CAVET, and current blocking layer engineering have been implemented.
An analysis has been conducted on a new type of Δ-shaped gate vertical topology
AlGaN/GaN MIS-HEMTs on (0001) c-plane GaN semi-polar substrate. In place of
a sidewall layer inversion, a 2DEG channel is used at the interface in this vertical
GaN with Si3N4 insulated structure. From the bottom of the device, a current spread-
ing GaN layer strongly doped with n+, a drift GaN layer weakly doped with n–, a
boron CBL, and a top contact layer with n+ GaN are used. However, in scaled-down
gate-length devices, the current leakage, short channel, and current collapse have an
impact on the device’s performance and reliability. In order to counteract the effects
of OFF-state leakage currents and short-channel devices, compensatory doping
with either carbon (C) (Oka et al., 2014) or magnesium (Mg) was employed. Lower
conductivity and hole mobility are the results of increased ionized-impurity disper-
sion caused by the greater active concentration of magnesium doping (Subramanian
et al., 2020) [17].
Furthermore, the results published to date clearly demonstrate that the low growth
temperature and pressure of carbon doping in Ga-interstitial sites in GaN leads to
mediocrity in the epitaxy, which is the cause of the current collapse through deep-
level electron trapping. It has been proven that dopants such as boron (B) are effec-
tive in raising the device operating voltage and lowering leakage current in both
RF and power-switching HEMT devices [16]. This chapter analyses the effects of
varying the thickness of B-CBL and boron doping (B) integration in GaN CBL for
vertical CAVET AlGaN/GaN HEMT. In light of this feature, a different p-type dop-
ant to magnesium and calcium could be considered.

18.6.1 Device Description
AlGaN/GaN CAVETs are a promising option for modern industrial applications due
to their greater performance in comparison to high-power switching SiC devices
[18]. Figure 18.15 depicts the structure of the device. It is composed of a UID-GaN
channel, an AlGaN barrier layer, and an n+ GaN cap. It also has a n-type GaN sub-
strate layer, a boron-doped CBL and a n-GaN drift layer. Furthermore, the source
contacts and p-GaN CBL are aligned. Together with the source-to-gate separation,
Lsg, the gate dielectric with Si3N4 thickness (tSi3N4) and gate depth penetration depth
(tpenetration) are adjusted for optimization. A negative fixed charge (with a density
Beyond Silicon 295

FIGURE 18.15 E-mode Vertical topology CAVET device structure view with a boron-
doped GaN CBL used for numerical device simulation.

magnitude of about 1013 cm-2) is present at the Si3N4/GaN contact. Electrodes are
formed on the devices’ top and bottom by the source and drain [19].
The conduction band energy versus depth in the device is shown in Figure 18.16.
A shift in the band diagram is created in the sidewall of the device at the AlGaN/
GaN vertical topology MIS-HEMT junctions. It is confirmed that lower polarization
charges, as opposed to typical (0001) c-plane charges, cause an upward shift in the
AlGaN/GaN heterojunction (Shrestha et al., 2015a). At Vds = 10 V, a distinct band
bending is seen at the AlGaN/GaN junction, and the simulation results show a maxi-
mum sheet carrier density.
The Ids–Vds characteristics of AlGaN/GaN vertical MIS-HEMT devices with
tSi3N4 of 40 nm and tpenetration of 0.8 µm are displayed in Figure 18.17. These devices
have maximum drain currents (Ids, sat) of 1000 A/cm–2. At the higher voltage level, the
suggested device produces a maximum drain current density [20].
The DC transfer characteristics (Ids–Vgs) of the Vertical topology MIS-HEMT,
evaluated at Vds = 10 V, are displayed in Figure 18.18 for a range of gate depth

FIGURE 18.16 Sheet carrier density (ns) and profile of conduction band versus position
along the channel in μm extracted at Vds = 10 V for vertical topology CAVET AlGaN/GaN
MIS-HEMT.
296 Circuit Design for Modern Applications

FIGURE 18.17 Simulated mentioned in symbols and experimental mentioned in solid lines
transfer characteristics for C-doped and Mg-doped vertical topology CAVET AlGaN HEMT
compared with vertical AlGaN barrier HEMT of boron (B)-doped.

FIGURE 18.18 Variation of Drain current vs drain–source voltage characteristics at con-

stant tSi3N4 and tpenetration and Vgs for vertical topology vertical topology AlGaN MIS-HEMT.

penetration depths variations. As the recessed penetration depth increases, the satu-
ration drain current Ids of the device increase. The Ids improve with a decrease in
device tSi3N4 and tpenetration.
Breakdown voltage characteristics (VBR, OFF) in relation to drain voltage (Vds) are
displayed in Figure 18.19. According to [17], the breakdown voltage criterion is the
Vds at which a 1 mA/mm drain current Ids is recorded, with Vgs= 0 V. When the criti-
cal electric field (Ec) and Lgd of vertical topology CAVET MIS-HEMTs alter, there is
a linear shift in the breakdown voltage-band ratio (VBR, OFF).
FOMs factors such as maximum frequency (fmax) and cut-off frequency (f T) are
investigated with respect to change in tSi3N4 and tpenetration in Figure 18.20. Whereas
fmax is the maximum available power gain transit frequency, cut-off frequency (f T) is
measured when the current gain is at unity. The former is a crucial variable that is
measured in digital applications with significant swing and speed. The latter is taken
Beyond Silicon 297

FIGURE 18.19 Breakdown voltage (VBR, OFF) versus Ids and ground substrate for different
tpenetration, with constant tSi3N4.

FIGURE 18.20 Maximum frequency of oscillation and cut-off frequency versus gate volt-
age Vgs with different tSi3N4 and tpenetration at Vds = 10 V.

into account while optimizing high-frequency amplifiers. According to, these two
FOMs are as follows:
A study of the b-doped vertical CAVET structure with different recess penetra-
tion depths was conducted while taking the Cgg into account in relation to the gate-
channel distance. A movement in the VT is seen, as expected, and when penetration
decreases, gm rises. The absence of charge control in larger layers is evident in Figure
18.20. The tpenetration does not have a high impact on f T and fmax, but significantly
for VT and gm. As penetration decreases, Cgg rises to offset the increase in gm [21],
thereby resulting in a constant f T and fmax. The highest frequency (f T) in Figure 18.20
is 5 GHz, while the maximum and fmax are recorded at Vds = 10 V for minimum tpen-
etration of and maximum tSi3N4. It is observed from Equations (18.2) and (18.3), where
Cgg is inversely proportional to f T and fmax, a rise in tSi3N4 results in a decrease in Cgg.
On the other hand, f T and fmax rise in response to a reduction in Cgg.
298 Circuit Design for Modern Applications

FIGURE 18.21 Block diagram of a DC-to-DC boost converter circuit that used vertical
CAVET AlGaN MIS-HEMT as a switch.

The study presents the demonstration and observation of Boron-doped GaN

CAVET vertical topology AlGaN/GaN HEMTs. The breakdown voltage is as high as
1500 V at a gate bias of 0 V at minimum tB–CBL thickness. The device has a consistent
distribution of electric field, and the gate corner exhibits a significantly lower electric
field, which substantially improves VBR, OFF, and RON. The high threshold voltage
of around 6V and good ION/IOFF current ratio with enhancement-mode operation is
achieved. RON is not affected and recorded a minimum of 1.24 mΩ.cm2.
The device under test (DUT) was taken into consideration and examined with
the boost converter circuit and it is represented in Figure 18.21. The vertical CAVET
HEMT act as a power switch, the Schottky barrier diode (SBD) as a rectifying ele-
ment, a load resistor, capacitors act as filters, and the inductor serves as a storage
element that makes up the circuit for the boost converter. As a circuit element, a
SiC diode is employed to guarantee a zero recovery current with superior switching
properties. Mixed-mode technology computer-aided design (TCAD) simulations are
used to perform the computations. Because of the energy released from the inductor,
the load is seen to reach double the input voltage during the switch-OFF interval, and
an observed 65% rise in output voltage is noted. These findings demonstrate the sug-
gested vertical topology GaN power transistors are highly suitable for high-power,
low-cost, and low-loss switching applications.

18.7 CONCLUSION
In conclusion, this book chapter presents a comprehensive exploration of two dis-
tinct high-electron-mobility transistor (HEMT) structures 2FP AlGaN/GaN HEMT
with a PNT layer and Vertical AlGaN/GaN CAVET MIS-HEMTs. The 2FP HEMT,
incorporating a PNT layer, showcases improved gate controllability and even electric
field distribution, leading to a substantial reduction in ON-resistance (RON). With
enhancement-mode operation achieved without compromising RON and drain current
(Id), the proposed device, particularly at its ideal dimensions, proves highly suit-
able for low-cost, high-current, high-voltage, and high-frequency power electron-
ics applications. On the other hand, the vertical HEMT with B-doped GaN CBL
and CAVET structure demonstrates impressive breakdown voltage characteristics
and an even electric field distribution. The depth variations in the gate corner fur-
ther enhance performance, yielding significant improvements in breakdown voltage
Beyond Silicon 299

(VBR), OFF-state current (IOFF), and ON-resistance (RON). With its capability for
enhancement-mode operation and a high ION/IOFF current ratio, the Vertical HEMT
stands out as a promising choice for low-cost, power electronics and low-loss switch-
ing applications. These findings collectively contribute valuable insights into the
design and performance optimization of advanced HEMT structures for diverse
power electronics applications.

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 19 Advanced Compound
Semiconductor Based
Heterostructure
Devices for Next
Generation Electronics
Saravana Kumar R, Leeban Moses M,
Lino L, and Papanasam E

19.1 INTRODUCTION: BACKGROUND AND DRIVING FORCES

Silicon, the workhorse of the semiconductor industry, has been the preferred mate-
rial due to its affordability and compatibility with native oxides, crucial for the devel-
opment of CMOS technology. However, the journey to shrink transistor size is not
without its hurdles. As transistors get smaller, the increased gate density boosts oper-
ating frequency but also leads to short-channel effects that raise off-state leakage
current and limit practical standby power. Despite reducing the oxide semiconductor
thickness for improved gate control, gate-leakage current escalates, making it chal-
lenging to achieve optimal ON-currents and OFF-currents at lower supply voltages.
The importance of capacitance and parasitic resistance in transistors further compli-
cates device scaling. These challenges underscore the need for alternative materials,
a need that both industry and academia are actively addressing. Among these alter-
natives, III–V compound semiconductors are emerging as a promising option for
future power applications [1]. Figure 19.1 presents the III–V semiconductor materials
in the periodic table, a testament to their potential.
HEMTs, or high electron mobility transistors, are a type of transistor made from
a combination of different semiconductor materials. These materials form a hetero-
junction, a junction between two different materials, where a continuous energy level
is created by aligning the conduction and valence bands. The HEMT is made of a
material with a wide energy gap that has been enriched with electrons in the con-
duction band. This material interacts with a material with a smaller energy gap and
lower energy conduction band states. This difference causes electrons to move from
the wide energy gap material to the nearby narrow energy gap material, changing
the potential and creating an electric field. Figure 19.2 represents the energy band

DOI: 10.1201/9781003483052-19 301

302 Circuit Design for Modern Applications

FIGURE 19.1 III–V combination semiconductor materials.

FIGURE 19.2 Energy band diagram of a HEMT device.

diagram of HEMT device in a thermal equilibrium condition. When equilibrium

is reached, a process similar to a p–n junction is sustained by the resulting electric
field, which pushes electrons back into the wide energy gap material’s conduction
band.
HEMTs are a type of semiconductor device with superior switching speed due
to the presence of excess majority charge carriers in the undoped narrow bandgap
material. This material also boasts excellent electron mobility because it lacks donor
atoms, which reduces scattering. The HEMT’s intriguing feature is its ability to con-
trol the management of band discontinuities, which determines the type of carriers
that enter and exit the device. The formation of a plate at the boundary between the
two zones within the narrow bandgap material creates a conducting channel in the
HEMT, making it essential to its operation (Figure 19.2).
HEMTs are devices that utilize different materials, such as GaAs, GaN, and InP,
and offer distinct properties tailored for specific applications. GaAs-based HEMTs,
for instance, leverage gallium arsenide to achieve high-speed and high-frequency
performance. These transistors are composed of several layers, such as the GaAs
substrate, GaAs buffer layer, AlGaAs barrier layer, and GaAs or InGaAs channel
layer. The AlGaAs barrier layer confines electron carriers, facilitating rapid elec-
tron mobility known as high electron mobility. Furthermore, the formation of a
two-dimensional electron gas layer enhances electron transport, ensuring efficient
operation and high-frequency performance [2]. GaAs-based HEMTs are the pre-
ferred choice for applications that demand high-performance amplification and sig-
nal processing, characterized by low noise, high gain, and low power consumption.
Advanced Compound Semiconductor Based Heterostructure Devices 303

19.2 INDIUM PHOSPHIDE-BASED HEMT DEVICES

FOR HIGH-FREQUENCY APPLICATIONS
Indium phosphide (InP)-based HEMTs are known for their unique properties and
are widely used in high-performance signal processing applications. These transis-
tors utilize InP as their primary material and have a typical structure consisting of
an InP substrate, an InP buffer layer, and an InGaAs or InAlAs barrier layer. The
barrier layer effectively confines electron carriers in the channel, taking advantage of
InP’s high electron mobility and allowing for smooth electron movement through the
channel. InP-based HEMTs generate a layer between the channel and barrier, which
is responsible for rapid electron transport, making them efficient for high-power and
frequency applications. Their low noise, high gain, terahertz frequency range and
robust power handling capabilities make them ideal for various applications and it is
represented in Figure 19.3.
An InP multi-layered heterostructure design consisting of several critical layers
is represented in Figure 19.4. The cap layer, which is a thin film heavily doped for
enhanced conductivity, sits atop the barrier layer to impede oxidation and main-
tain device integrity. The barrier layer exhibits a wider bandgap than the channel to
increase the channel-insulator distance, which reduces scattering effects for better
carrier mobility. To further enhance channel mobility, a targeted portion of the bar-
rier layer receives localized doping (unlike full-layer doping) for precise carrier con-
finement and minimal resistance, known as the delta doping layer. The incorporation
of a spacer layer also helps to reduce scattering effects, optimizing channel perfor-
mance [3]. The low-bandgap channel layer forms a potential well and acts as the con-
ducting path for the device. To ensure efficient operation, the buffer layer guarantees

FIGURE 19.3 Terahertz frequency range applications.

FIGURE 19.4 InP-based HEMT device structure.

304 Circuit Design for Modern Applications

FIGURE 19.5 Relationship between RF performance of the device along with barrier and
gate length.

compatibility between the substrate and the device material. The substrate acts as the
structural foundation, providing mechanical support and facilitating heat dissipation
for thermal management.
InP-based HEMT device performance, for both DC and RF applications, can
be optimized by carefully tuning the barrier, channel, and gate length thicknesses.
Thicker barriers improve drain current by distancing channel electrons from surface
traps but reduce gate controllability and RF performance, which is represented in
Figure 19.5. Short gate lengths enhance transconductance and enable high-frequency
operation, but exacerbate short-channel effects. Increasing channel thickness can
potentially boost drain current and mobility. The trade-offs between these param-
eters are visually represented in the attached figure, where gate length reduction
initially improves RF performance until limited by short-channel effects. Similarly,
the figure depicts the influence of barrier and gate length on overall RF performance.
While short gate lengths can be beneficial, balancing them with barrier thickness
and potentially optimizing channel thickness is crucial for achieving optimal
performance.

19.3 GALLIUM NITRIDE BASED HEMT DEVICES FOR

HIGH-POWER AND FREQUENCY APPLICATIONS
GaN-based HEMT devices utilize GaN as the primary material to achieve optimal
performance. The typical structure of a HEMT includes a substrate, an AlGaN buf-
fer layer, an AlGaN or InAlN barrier layer, and a GaN or InGaN channel layer.
The barrier layer effectively contains electron carriers within the channel, allow-
ing for smooth electron movement. A special layer known as 2DEG is generated
concerning the channel and barrier layers to ensure rapid operation and outstanding
extraordinary frequency performance. GaN HEMTs are ideal for elevated power and
frequency applications such as power amplifiers, wireless communication, and radar
systems, thanks to their high electron mobility. These transistors also offer notable
advantages like improved VBD, power density, and thermal conductivity, making
them suitable for demanding applications [4].
Pseudomorphic HEMTs are electronic components that regulate the electron flow
between source and drain terminals through gate voltage manipulation. They use
a pseudomorphic structure to enhance electron mobility, resulting in faster trans-
port and superior performance at high frequencies. PHEMTs are ideal for low-noise
amplifiers in radio frequency systems due to their low noise figure, making them
Advanced Compound Semiconductor Based Heterostructure Devices 305

perfect for microwave and millimeter-wave applications. Going beyond PHEMTs,

mHEMTs (metamorphic HEMTs) introduce a buffer layer between materials with
different lattice constants, allowing optimization through indium concentration
adjustments in the channel. This flexibility caters to various performance charac-
teristics like low noise or high gain. In contrast, induced HEMTs enable the tuning
of electron densities using a top gate, unlike modulation-doped HEMTs. Induced
HEMTs do not have a doped layer, which significantly enhances electron mobility
compared to modulation-doped counterparts.

19.4 SPONTANEOUS POLARIZATION AND PIEZOELECTRIC

POLARIZATION OF ALGAN/GAN-HEMT
GaN HEMTs are important electronic devices used in high-frequency and high-
power applications. These devices rely on two polarization effects: spontaneous
and piezoelectric. Spontaneous polarization is a naturally occurring phenomenon
that happens due to an inherent imbalance in the crystal structure of the materials
used in HEMTs. GaN’s wurtzite structure is inherently polar because of differences
in the nitrogen and gallium atoms. This causes charges to accumulate at opposite
ends, creating an electric field that affects electron distribution and transport in the
HEMT. On the other hand, piezoelectric polarization occurs when the crystal lattice
is strained. In AlGaN/GaN HEMTs, the AlGaN and GaN layers have different lat-
tice structures, causing strain and a piezoelectric effect [5]. This effect, influenced by
aluminum in the AlGaN layer, creates an electric field that affects charge distribu-
tion and carrier movement in the device. Both spontaneous and piezoelectric polar-
ization influence electron distribution and overall device performance. Therefore,
engineers need to manage these effects during the design and fabrication stages to
optimize the HEMT for specific applications. By doing so, they can ensure better
efficiency and reliability of the device.

19.4.1 GaN-HEMT Device with the Addition of Different Layers

The basic structure of a GaN-based HEMT device is represented in Figure 19.6. The
performance of AlGaN/GaN HEMTs is often limited by current collapse and cur-
rent dispersion. The cause of current collapse is the existence of slow-acting trapping

FIGURE 19.6 HEMT Device structures with different layers.

306 Circuit Design for Modern Applications

states between the gate and drain, induced by surface defects. These defects act as
electron traps, forming a charge layer that depletes the channel between the gate and
drain in regions of high electric field. During large signal RF operation, the trapping
states exhibit a short time constant, impeding the modulation of the channel charge,
and resulting in a reduction of RF current swing and output power. However, the
application of suitable dielectric materials, like Si3N4, to passivate the HEMT sur-
face can significantly mitigate this detrimental effect. Passivation eliminates surface
effects that impose limitations on RF current and breakdown voltages of the devices
[6]. The introduction of a passivation layer atop the AlGaN barrier layer plays a
crucial role in preventing external polarization and reducing the peak electric field
at the drain end of the gate region, thereby reducing noise interference and cross-
talk. To prevent current collapse at high drain-source voltage and minimize parasitic
capacitances, a Si3N4 passivation layer is implemented across the device surface.
The incorporation of the Si3N4 dielectric layer between the gate and AlGaN layer
enhances the gate-channel distance, ultimately refining control over the threshold
voltage. However, increasing the thickness of the Si3N4 layer results in a rise in VT
and a reduction in gate capacitance, leading to a decrease in transconductance.
The selection of the gate insulator plays a crucial role in the design of high-
power switching III-nitride metal-insulator-semiconductor HEMT devices. HfAlOx
emerges as a promising alternative by combining the high dielectric constant of
HfO2 with the substantial barrier height and excellent thermal stability of Al2O3.
It presents low gate-leakage current, high channel carrier density, and resistance to
self-heating effects. The incorporation of an Al2O3 layer serves to diminish parasitic
capacitance [7]. A 40 nm HfO2 passivation layer is also implemented to minimize
parasitic capacitances. The high dielectric constant of this passivation layer plays a
crucial role in alleviating dispersion effects and enhancing the transport properties.
Although using a thin passivation layer may slightly reduce the operating frequency
range due to the larger dielectric constant of Si3N4, it proves effective in mitigating
buffer leakage current and minimizing gate-leakage current.
Research teams are investigating MOS-HEMTs and exploring various oxide
layers such as SiO2, Al2O3, HfO2, MgCaO, and Al2O3 to enhance device perfor-
mance by minimizing gate-leakage currents. To address gate-leakage, a dielectric
layer is employed beneath the gate, comprising SiO2, Sc2O3, Al2O3, or Ga2O3.
Incorporating a dielectric layer in DCMOSHEMT enhances performance compared
to DCHEMT by reducing the effective gate-source capacitance and gate-leakage
current [8]. Increasing the gate thickness can lead to diminished control over the
lower channel, resulting in a decrease in peak transconductance.
To minimize gate-leakage current and counteract scattering effects, an AlN
spacer layer with wide-bandgap properties is utilized. This spacer layer confines
more electrons in the channel and alleviates the impact of gate-leakage current [7].
A second GaN spacer layer transforms the device into a normally OFF transistor
by inducing a negative polarization at the upper interface of the channel, depleting
it of electrons when no gate voltage is applied. AlGaN buffer layers confine elec-
trons in the conduction channel by preventing electron penetration into the buffer
at high drain-source voltages, a phenomenon known as the punch-through effect.
However, thick AlGaN buffers exhibit lower thermal conductivity compared to GaN
Advanced Compound Semiconductor Based Heterostructure Devices 307

buffers. Fe-doped GaN buffers require a larger gate-drain distance to achieve the
same breakdown voltage as GaN buffers. Carbon-doped GaN buffers effectively
reduce leakage current by acting as deep acceptor-like traps.

19.4.2 GaN HEMT Device on Different Substrates

GaN HEMTs are particularly well-suited for such uses due to their exceptional
electric field capabilities and high maximum speed. Traditionally, GaN HEMTs
have been made using epitaxial layers grown on different substrate types, a process
known as hetero-epitaxial growth. However, using substrates with different lattice
structures during this growth process leads to crystal defects, or threading disloca-
tions, which can potentially impact the characteristics of the transistors by acting as
electron traps. This can limit the density of the plate charge, which in turn raises the
dynamic on-resistance. Additionally, the AlGaN/GaN heterostructures, with their
high density of threading dislocations, exhibit notable gate-leakage currents [9].
Silicon (Si) is a cost-effective and widely available substrate material for various
applications. However, using Si as a substrate for GaN presents certain challenges.
The larger lattice mismatch between Si and GaN can lead to increased dislocation
density or microcracks in the GaN layer. Additionally, Si’s lower resistivity contrib-
utes to higher substrate leakage and a reduced breakdown voltage. Due to the lower
resistivity of Si substrates and the intrinsic conductivity channel across the boundary
between III-nitride and Si, fabricating RF GaN HEMTs on Si may result in increased
RF impairments. Attempts to mitigate this issue involve using high resistive (HR)
Si substrates, albeit at a higher cost and potential drawbacks in the development of
elevated strain GaN due to increased bowing issues. The cost and limitations asso-
ciated with HR Si substrates constrain the production of these devices on larger Si
substrates.
The suitability of different substrates for GaN-HEMT varies based on their lat-
tice mismatch with GaN. SiC substrates, with a lower lattice mismatch (3.4%), are
considered more suitable than others. SiC also has a wider bandgap (3.5 eV) and
minimal substrate leakage current. Although epitaxial layer flaws at the GaN and
SiC interface cause problems with thermal performance, AlGaN HEMTs on SiC
substrate have shown impressive power densities. Diamond substrates reduce the
self-heating effect and enhance reliability but encounter challenges due to the large
lattice mismatch (11%). Sapphire is another commonly used substrate for GaN epi-
taxy, but GaN stability on sapphire is generally weaker than on Si under high-drain
bias conditions. Benefits of homoepitaxy, or the development of GaN layers on GaN
substrates, include an incredibly thin channel layer that is ideal for high-frequency
functioning with a minimal gate length and a relatively low defect density. Current
collapse in GaN HEMTs is decreased by AlGaN/GaN layers produced on GaN sub-
strates, which show either reduced reverse leakage currents or excellent electron
mobility. Following proton irradiation, metal-insulator-semiconductor HEMTs on
GaN substrates demonstrate reduced deterioration in both current flow and dynamic
characteristics [10]. Recently, remarkable results have been achieved with outstand-
ing high-power-added efficiency by using GaN substrates with decreased silicon
contamination at the layer interface.
308 Circuit Design for Modern Applications

FIGURE 19.7 HEMT device structures with different representations of field plates.

19.5 GAN-HEMT DEVICE WITH FIELD PLATE CONFIGURATION

The field plate (FP) technique in HEMT device structures is represented in Figure 19.7
reduces the current collapse, improves device reliability, and enhances gate-to-drain
capacitance. By dividing the peak electric field at the drain-side edge of the gate, this
approach decreases drain current by significantly reducing the mobility of carriers.
By adjusting the lengths of the gate FP toward the drain side, the devices exhibit
improved breakdown performance while maintaining stable transconductance with
minor deviations. This variation in FP length reduces the electric field distribution at
the drain-edge side, which reduces self-heating effects due to reduced carrier mobil-
ity and drain current. Consequently, the breakdown voltage of the device improves
[11]. The increase in FP length significantly boosts breakdown voltage, there might
be a slight degradation in transconductance. However, this trade-off is deemed
acceptable given the substantial improvement in breakdown voltage.
The Discrete FP GaN-HEMT device structure represented in Figure 19.7 has a
unique arrangement of FPs within the device structure. This arrangement reduces
the total area of the field plate, resulting in a decrease in the device’s parasitic capaci-
tance. In traditional Continuous FP HEMTs, although breakdown voltage improves,
the trade-off is an increase in parasitic capacitance, which subsequently reduces the
cutoff frequency of the device. The Discrete FP approach is used to increase VBD
without affecting the device’s RF performance. In addition to supporting the VBD
process and uniformly spreading the electric field throughout the channel without
raising the parasitic capacitance of the device, the discrete FP HEMT exhibits a posi-
tive temperature coefficient [12]. The discrete FP lowers the peak electric field under
the gate area by generating electric field peaks on both sides. This lowers parasitic
capacitance and suppresses the total gate capacitance.
The VBD of the device is improved by extending the FP, but the gate-drain and
gate-source capacitances are also increased and are represented in Figure 19.8. In
order to widen the depletion zone and replace the single-peak electric field with
numerous peaks, the micro-FP structure in HEMTs consists of a drain FP, a source
FP, and several micro gate FPs. In typical HEMTs, an electric field peak is formed
when potential lines collect on the drain side due to the shortening of the depletion
Advanced Compound Semiconductor Based Heterostructure Devices 309

FIGURE 19.8 Representation of breakdown voltages for different field plate structures.

area at the drain-side gate edge caused by an increase in bias. On the other hand,
HEMTs, including micro-FPs, show reduced electron concentration in the vicinity
of the drain-side gate edge, leading to a longer depletion area and a more consistent
potential distribution [13]. This results in three-to-three areas with high potential
line density: the edge of the micro gate FPs, the drain region, and the edge of the
drain FP. Consequently, HEMTs with micro-FPs demonstrate uniform electric field
distribution and with an improved VBD.
The source–drain FP has a greater drain current than the other FP designs when
the electrons are entirely drained because of the peak electric field below the drain
FP. Due to its improved surface field distribution, the gate FP exhibits a greater
breakdown voltage than conventional FP approaches, which results in substantial
enhancements in the breakdown voltage of the HEMT. Although the source FP can
be used to increase breakdown voltage, the gate FP usually performs better due to its
shared structure for improvement [14]. The variation in drain current with respect to
the field plate structures is represented in Figure 19.9.

FIGURE 19.9 Representation of drain current of HEMT with different field plate structures.
310 Circuit Design for Modern Applications

FIGURE 19.10 HEMT device structures with different representations of back-barrier.

19.6 GAN-HEMT DEVICE WITH BACK-BARRIER LAYER

In AlGaN HEMT device structures, the inclusion of a back-barrier (BB) helps to
combat short-channel effects and improve carrier confinement in the channel. The
back-barrier design enhances the confinement of carriers, which prevents excessive
electron injection into the buffer region. This reduction in injected carriers expands
the overall performance of the device. It’s crucial to remember, though, that large
concentrations of aluminum (Al) in the back-barrier might cause strain, which raises
the number of dislocations in the channel layer. To further reduce device leakage
current, it may potentially form an additional quantum well at the junction of the
buffer layer and the AlGaN BB which is represented in Figure 19.10. The back-
barrier is made with a reduced Al alloy and has an adequate thickness to reduce
channel layer flaws in order to avoid these problems. One important aspect influenc-
ing device performance is the thickness of the BB layer [15]. A thicker barrier layer
increases the channel’s sheet charge density, which raises the carrier concentration
there. However, decreasing the BB thickness shortens the time between the gate and
the channel, leading to a higher induced electric field.
Utilizing an InAlN-BB with highly confined layers has demonstrated significant
improvements in gm and f T. The InAlN layer is an excellent choice for the back-
barrier in N-polar devices due to its lattice-matched composition. When a surface
is subjected to a negative voltage, electrons that travel through the upper interface
channel are effectively trapped within the second interface located at the InN/GaN
bottom cap. This confinement mechanism prevents the electrons from spreading into
the buffer region. This aids in the control of buffer leakage current. Lattice-matched
heterostructures utilizing InAlN back-barriers showcase strong polarization, good
thermal stability, and high drain current density. However, limited miscibility, phase
separation, compositional heterogeneity, and the existence of trenches in the material
due to displacement imperfections in the GaN buffer offer challenges to the develop-
ment of excellent ternary InAlN [8]. Increasing the width of the barrier enhances
both spontaneous and piezoelectric polarization charge, leading to higher values of
transconductance and improved drain current density. On the other hand, when the
Advanced Compound Semiconductor Based Heterostructure Devices 311

thickness of the barrier is decreased, it enhances the gate’s control over the channel.
This increased control makes the device highly responsive and enables a significant
improvement in the amplitude of the high-frequency input power swing during the
turn-ON process.
To improve HEMT performance, an AlGaN back-barrier structure is used. This
structure helps to reduce leakage current and enhance electron confinement. The
amount of aluminum (Al) in the AlxGa1–xN back-barriers affects the device’s perfor-
mance. A higher Al content results in a deeper and narrower conduction band dis-
continuity, which reduces device leakage. However, if the Al content exceeds 10%, it
can lead to lower thermal conductivity due to alloy scattering. Therefore, optimizing
the Al content is critical to achieve low leakage and a positive threshold voltage in
HEMTs. By increasing the “x” value (Al content) from 0% to 7%, electron confine-
ment is improved, but the sheet carrier density of the 2DEG is decreased [15]. This
indicates effective prevention of electron spillover to the buffer at high drain-source
voltage. Additionally, a thinner BB layer leads to a shorter channel-to-gate distance,
which raises the generated electric field represented in Figure 19.11.
The AlxGa1–xN back-barrier has a reduced DIBL due to reduced output conduc-
tance at small gate lengths. Moreover, introducing p-type doping in the BB can reduce
the peak electric field, which increases the breakdown voltage by approximately 11%
while maintaining the maximum drain current density represented in Figure 19.12.
The improved electron confinement in the AlxGa1–xN BB is attributed to the negative
polarization at the GaN/AlxGa1–xN interface. This polarization-induced electric field
raises the conduction band edge, creating a potential barrier against carrier diffu-
sion and enhancing electron confinement. The use of AlInN back-barriers allows for
adjustments in material composition, eliminating lattice-mismatch-related defects.
Compared to conventional AlGaN back-barriers (with Al content less than 10%),
the higher energy bandgap of AlInN back-barriers enhances carrier confinement
[16]. However, achieving high-quality AlInN layers can be challenging. It is crucial
to optimize growth conditions to maintain good interfacial quality, as lower-quality

FIGURE 19.11 Representation of drain current of HEMT with different back-barrier

materials.
312 Circuit Design for Modern Applications

FIGURE 19.12 Representation of gm of HEMT with different back-barrier materials.

interfaces can adversely affect the heterostructure properties. The inclusion of AlInN
back-barriers enhances the confinement of carriers, thereby reducing their scattering
with carbon impurities found in the underlying buffer layer. This improvement helps
minimize the leakage flow of carriers into the semi-insulating GaN buffer layer.
HEMTs that use AlInGaN quaternary alloys as back-barrier materials offer tunabil-
ity in the bandgap, lattice parameter, and polarization. The narrower immiscibility
of quaternary alloys compared to other materials allows for higher mobility and sat-
isfactory transport properties. The higher back-barrier height provided by AlInGaN
back-barriers improves electron confinement in the channel and minimizes electron
spreading into the GaN buffer represented in Figure 19.12.
Incorporating an InGaN back-barrier beneath the AlGaN layer can enhance elec-
tron confinement and improve device performance. InGaN facilitates the growth
of high-quality materials with fewer traps, which contributes to improved interface
and surface smoothness. The inclusion of a back-barrier leads to heightened trans-
conductance, as electron confinement is enhanced, enabling better modulation of
electrons by the gate voltage, especially at high drain voltage. However, an observed
decrease in transconductance occurs with an increase in the mole fraction of InGaN
[12]. The increased concentration of electrons in the channel is the cause of this
decrease in gm, which makes it more difficult for the gate to modulate such a con-
centration and diminishes its control over the channel represented in Figure 19.13.
The introduction of an InGaN back-barrier leads to a significant shift in the thresh-
old voltage toward the positive side, effectively mitigating the short-channel effect.
In single-channel devices, the incorporation of an InGaN back-barrier introduces a
slightly increased threshold voltage at lower drain-to-source voltages, although the
impact is minimal [17].
Conversely, in double-channel devices, the upper channel displays a smaller nega-
tive threshold voltage compared to the lower channel, primarily due to its stronger
interaction with the gate. This disparity in threshold voltage results in higher trans-
conductance and an expanded range of the gate-to-source voltage swing. These vari-
ations in threshold voltage offer additional benefits for circuit design enhancements.
Advanced Compound Semiconductor Based Heterostructure Devices 313

FIGURE 19.13 Representation of ft of HEMT with different back-barrier materials.

The inclusion of a ternary compound, such as BGaN, offers improved electron con-
finement within the channel and enhances the electrical resistivity of the buffer layer.
The BGaN BB enhances electron confinement in the two-dimensional electron gas
by creating an electrostatic barrier beneath the channel layer [18]. By increasing the
boron concentration, the electron confinement is further enhanced as it renders the
electrostatic barrier more resistive, making it difficult for electrons to escape the
channel. This improvement in resistivity within the buffer layer leads to enhanced
DC characteristics and higher operating frequencies, facilitating electron confine-
ment and concentration at the AlGaN/GaN interface represented in Figure 19.13.

19.7 GAN-HEMT DEVICE WITH DIFFERENT CHANNELS

A GaN-based HEMT is a type of three-terminal device that uses electrons for cur-
rent conduction. The electrons pass through a channel formed at the interface of
AlGaN and GaN, with the electric field applied through a gate that controls the num-
ber of electrons in the channel. The channel is formed due to polarization effects and
discrepancies in energy levels between the barrier and channel layers, which incor-
porates spontaneous and piezoelectric charges impacting band structure and electron
quantity in the channel represented in Figure 19.14. As the gate voltage is applied,
electrons transfer from the higher energy barrier to the channel, influencing source
resistance and transconductance. The speed of electrons in the channel depends on
the electric field and mobility at low fields. The current in the linear region corre-
lates with the electric field as electron speed aligns with the field. The energy level
of the conduction band decreases along the channel length, further decreasing with
increased channel thickness, indicating a rise in average electron speed and drain
current.
However, reduced channel thickness diminishes gate control and introduces inter-
ference from vertical electric fields in double-gate structures. In devices with thicker
GaN channels, enhanced carrier mobility, particularly in the low carrier concentra-
tion regime, is notable due to reduced Coulomb scattering from trapped charges near
314 Circuit Design for Modern Applications

FIGURE 19.14 HEMT device structures with different representations of channel layers.

FIGURE 19.15 Representation of drain current of HEMT with different channel conditions.

the AlGaN/GaN interface, enhancing crystalline quality represented in Figure 19.15.

Thicker GaN channels exhibit higher carrier mobility maxima, lower trap density,
and improved overall device performance. In contrast, devices with thinner undoped
channels with enhancements in carbon doping demonstrate effective electron con-
finement in the buffer layer, exhibit low leakage current and suffer from pronounced
trapping effects. Thicker channels alleviate trapping effects but compromise electron
confinement, especially with shorter gate lengths.
As the thickness of the channel decreases in a HEMT, electron mobility is
impacted by additional scattering arising from the interface and alloy in the back-
barrier layer. This interface scattering results in a reduction in the effective velocity
of electrons as the channel becomes thinner. At elevated current levels, gain com-
pression occurs due to the degradation of electron velocity caused by interface scat-
tering. Reducing sheet resistance is crucial in heterostructure research, impacting
HEMT linearity and maximum frequency by increasing parasitic access resistance
[19]. The double-channel technology, utilizing two channels, proves a promising
approach to increase carrier density without adversely affecting mobility, thereby
Advanced Compound Semiconductor Based Heterostructure Devices 315

FIGURE 19.16 Representation of breakdown voltages of HEMT with different Channel

conditions.

reducing sheet resistance and leading to enhanced drain current, output power, and
device linearity.
The allocation of electrons between the upper and lower channels relies on the
thickness of the upper GaN channel layer. The breakdown voltages of HEMT with
different channel conditions are represented in Figure 19.16. Initially, the bottom
channel becomes active, followed by the activation of the upper channel as the
gate bias is increased. When the upper channel is operational, the lower channel
is shielded from gate control, leading to saturation of the two-dimensional electron
gas in the bottom channel. By connecting the two channels in the access region with
the high-mobility lower channel at the gate region, a low resistance (Ron) can be
achieved. The separation between the two channels influences resonance intensity,
with smaller separations enhancing coupling and intensifying resonance.
In the room temperature non-resonant detection mode, the detector’s response
signal is primarily influenced by the barrier layer’s thickness and the distance
between the two channels. A thicker barrier provides a higher 2DEG density but
reduces gate control capability. The barrier height between the two channels is deter-
mined by their distance, with a smaller distance resulting in a lower barrier height
and increased tunneling probability. At low gate-source voltage (Vgs), neither the
upper nor the lower channel conducts [13]. With increasing Vgs, a 2DEG forms in the
triangular barrier between the channels, and as Vgs continues to rise, both channels
conduct, leading to an increase in tunneling probability and carrier transfer from
the bottom channel to the upper channel. This results in the formation of a vertical
built-in electric field between the two channels, with a direction from top to bottom.

19.8 GAN-HEMT DEVICE WITH DIFFERENT GATE STRUCTURES

The width of the gate in a HEMT device structure is crucial for the speed of electron
movement and the device’s operating frequency. Reducing the gate width is a com-
mon strategy, but it can increase gate resistance and negatively impact high-frequency
316 Circuit Design for Modern Applications

characteristics and noise figures. To overcome these challenges, a T-shaped gate con-
figuration, also known as a mushroom gate, has been proposed. This configuration
features preserving the advantage of a short-channel while reducing gate resistance
for efficient high-frequency operation. The T-gate structure is widely accepted as
the standard gate structure since it reduces gate access resistance and extrinsic gate
capacitances, with the gate positioned closer to the source than the drain to enhance
breakdown voltage.
Hot-electron generation and degradation in GaN HEMTs are influenced by fac-
tors such as carrier concentration, electric field distribution, temperature, and buf-
fer compensation species. Strategies to prevent these effects include reducing the
peak electric field or increasing electron energy loss through scattering. Reliability
enhancement techniques often focus on minimizing the peak electric field by adjust-
ing gate placement, but this may increase access region resistance and impact DC
performance [20]. Field-plated devices are employed in power switching and low-
frequency wireless applications, yet they are still susceptible to hot-electron-induced
degradation. Dual-gate HEMTs have been proposed for high-frequency and high
breakdown voltage applications, but they come with trade-offs like reduced cutoff
frequency and the need for complex contact padding and biasing circuitry. Another
alternative is the pi-shaped single-gate structure, aiming to improve GaN-HEMT
reliability while maintaining DC and RF performance and is represented in Figure
19.17. This gate layout alters electron transport and reduces the high electric field
by preventing excessive hot-electron generation. The pi-shaped gate facilitates a
two-step process for electron acceleration, allowing for energy loss or thermaliza-
tion between steps to avoid excessive kinetic energy accumulation and hot-electron
issues. The recessed Δ-shaped gate formation creates a channel layer at the AlGaN
and GaN junction, forming a single-channel path for electrical conduction [19]. This
reduces resistance and increases conductivity. The vertical GaN structure operates
similarly to traditional lateral GaN HEMTs, with the gate voltage controlling the
formation and conduction of the single channel. Optimizing the depth and thickness
of the passivation layer provides better control over the threshold voltage.

FIGURE 19.17 Representation of drain current of HEMT with different gate Structures.
Advanced Compound Semiconductor Based Heterostructure Devices 317

FIGURE 19.18 Representation of breakdown voltages of HEMT with different gate

structures.

To address the issue of initially induced single-channel carriers from the BB, a P+
Mg-doped InGaN cap layer was added beneath the gate in AlGaN/GaN HEMTs. In
typical devices, the lower channel density in the InGaN layer, due to its low growth
temperature, makes the single-channel activation easier compared to p-GaN. The P+
InGaN cap layer counters polarization-induced charges in the AlGaN layer, leading
to a normally-OFF operation [14]. Conventional HEMTs without an InGaN cap layer
result in a normally-ON operation due to a single-channel forming at the AlGaN
interface. Introducing a P-InGaN layer only in the gate region aims to reduce source
parasitic resistance, even in a normally-OFF operation, eliminating the need for gate
recess etching that could impact the device threshold voltage.
The incorporation of a high-quality GaN cap with dopant material as boron
beneath the gate has demonstrated effectiveness in reducing leakage current and
minimizing carrier trapping effects. In comparison to the GaN cap with a dopant
material such as Magnesium, the GaN layer with a dopant material such as boron
offers improved device performance, including lower leakage current, enhanced cur-
rent density, and better transconductance and are represented in Figure 19.18. A GaN
layer with dopant material such as boron that has higher resistivity increases the
electrostatic barrier, while its passivation effect reduces the probability of carrier
trapping. GaN layer with dopant material such as boron also addresses surface state
issues, restricts gate tunneling current, and increases the on/off current ratio [16].
Moreover, it increases resistivity and decreases defect-related effects. Carbon-doped
GaN faces challenges in crystal growth due to low temperatures.

19.9 CONCLUSION
Various techniques, such as material engineering, source/drain engineering, and gate
engineering, have been employed in the construction of InP-based HEMTs. These
advancements offer advantages compared to GaAs, Silicon, and SiGe semiconduc-
tor technologies, leveraging inherent characteristics like high electron mobility,
318 Circuit Design for Modern Applications

high thermal conductivity, and low voltage operation. In high-frequency applica-

tions where low noise and speed are crucial, InP HEMTs present significant benefits.
These applications encompass areas such as millimeter-wave, terahertz, radar, and
satellite communication. GaN HEMTs offer distinct characteristics and a wide band
gap that make them highly suitable for RF and high-power applications. The larger
bandgap of GaN enables its effective utilization in various devices such as RF ampli-
fiers, power converters, wireless power transfer devices, and monolithic microwave
integrated circuits (MMICs). Additionally, GaN exhibits a higher breakdown field
and drain current, further enhancing its performance. To address challenges asso-
ciated with GaN HEMTs, several structural solutions have been developed. These
solutions involve implementing techniques such as trenches, surface passivation,
variable field plates, cap layers in the gate structure, gate recesses, incorporating
a back-barrier, and utilizing different barrier layers. Through these advancements,
issues related to high peak electric fields, breakdown voltages, leakage currents, and
current collapse in GaN HEMTs can be mitigated.

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GaN HEMT using discrete field plate technique for high power and high frequency
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20 GaN HEMT-Based
Power Amplifiers
Advancements and
Applications
T Venish Kumar, R Karthick, C Nandhini,
M Annalakshmi, and R Rajesh Kanna

20.1 INTRODUCTION
There is a growing need for powerful amplifiers with high power and frequency in
several industries such as wireless communication, military uses, communication
via satellite, and television broadcasting. The market demand for lower power con-
sumption and better throughput is driven by the constant growth in data rates and the
rising user base in mobile communications [1]. These requirements have been fur-
ther heightened by the transition from the fourth generation (4G) to the forthcoming
5th generation (5G) wireless communication, impacting various sectors including
robotics, healthcare, autos, education, agriculture, and others.
The significance of power amplifiers in radio transmissions is crucial since they
serve as controlling devices in the transmitter output stage and significantly influ-
ence system parameters such as efficiency, linearity, and gain. The adoption of
solid-state power amplifiers is a substantial change resulting from rapid progress in
solid-state device technology, replacing vacuum tube microwave devices. Efficiency
is of utmost importance in applications such as base stations, since the utilization
of highly efficient power amplifiers can effectively minimize power dissipation and
alleviate the requirement for intricate and costly cooling systems [2].
Significant advancements have been made in semiconductor technology with the
aim of enhancing efficiency and performance, resulting in the birth of diverse power
amplifier topologies. The introduction of gallium nitride (GaN) high electron mobil-
ity transistors (HEMTs) has been a significant milestone in the field. Silicon nitride
(GaN) has garnered significant attention as a potential contender for power ampli-
fiers due to its unique crystalline structures and remarkable material characteristics.
The emergence of power amplifiers based on GaN HEMT has resulted in notable
progress that surpasses previous semiconductor technologies, providing enhanced
efficiency, gain, and thermal performance.

320 DOI: 10.1201/9781003483052-20

GaN HEMT-Based Power Amplifiers 321

TABLE 20.1
Properties of Different Compound Semiconductors
Properties Si SiC GaAs GaN
Bandgap (Eg, eV) 1.12 3.2 1.4 3.4
Breakdown field (Ebr, mV/cm) 0.3 3.5 0.4 3.3
Electron mobility (µn, cm²/V s) 1500 650 8500 2000
Saturation Electron Drift Velocity (vsat, cm/s) 107 2.7 × 107 1.2 × 107 2.5 × 107
Transit Frequency (fT, GHz) 20 20 150 150
Thermal conductivity (K, W/m°C) 150 450 550 130

The AlGaN/GaN HEMT provides a three-dimensional representation of GaN,

highlighting the heterojunction between AlGaN and GaN, resulting in the formation
of a two-dimensional electron gas (2DEG). The characteristics of GaN, such as its
elevated electron mobility, broad bandgap energy, and elevated breakdown voltage,
render it exceptionally well-suited for applications requiring high power and high
frequency [3]. The features are succinctly outlined in Table 20.1, highlighting the
superior efficiency, gain, and thermal performance of GaN.
This chapter examines the complexities of GaN HEMT-based power ampli-
fiers, investigating their structure, progress, and utilization in different industries.
GaN possesses specific features that make it a crucial facilitator in the dynamic
field of high-power and high-frequency amplification. These advantages are effec-
tively utilized in many applications such as RF microwave integrated circuits, power
amplifiers, switches, and low noise amplifiers [4–8]. Furthermore, the chapter exam-
ines methods for improving efficiency and linearity, tactics for managing thermal
conditions, and the advancement of GaN monolithic microwave combined circuits
(MMICs) [9, 10].
This chapter endeavors to offer significant insights into the improvements and
different uses of power amplifiers based on GaN HEMT through a comprehensive
examination. The unique characteristics of gallium nitride (GaN) HEMTs highlight
their exceptional performance in diverse electrical applications. GaN, with a band-
gap of around 3.4 eV, allows for functioning at high temperatures and has a high
breakdown voltage. This is important for applications that need to withstand high
voltages [11]. GaN high-entropy metal triboelectric nanotubes (HEMTs) exhibit
remarkable electron mobility, generally nearing 1000 cm²/Vs, which enables effi-
cient electron transport and makes them very suitable for high-frequency appli-
cations [12]. Furthermore, the exceptional thermal conductivity of GaN, which is
around 1.3 W/(cm•K), plays a significant role in facilitating efficient heat drainage,
hence impacting the thermal stability of GaN HEMTs. The homogeneity of the
bandgap throughout the material is crucial in maintaining consistent electrical char-
acteristics, which is essential for ensuring the dependable and predictable operation
322 Circuit Design for Modern Applications

of devices [13]. GaN high-entropy metal triboelectric nanotubes (HEMTs) demon-

strate a notable power density, frequently attaining values in the range of several
Watts per square millimeter. Additionally, they possess a low specific ON-resistance
(Ron), typically quantified in milliohms per square millimeter, which contributes to
improved power efficiency and diminished heat generation [14, 15]. GaN HEMTs
demonstrate resilience in managing high voltage levels, as seen by their breakdown
voltage above 600 V [16]. In addition, it has been shown that GaN HEMTs exhibit a
significant cut-off frequency (fT) that extends into the gigahertz range, hence show-
ing their capacity to function effectively at elevated frequencies [17]. The combi-
nation of these distinct quantitative qualities establishes GaN HEMTs as essential
elements in high-frequency communication systems, power amplifiers, and various
power electronics applications, demonstrating their significant contribution to the
advancement of semiconductor technology.
In electronic systems, power amplifiers play a crucial role by increasing the ampli-
tude of electrical impulses, which is a vital function in signal processing. Amplifiers
play a crucial role in situations when there is a need to enhance weak input signals in
order to facilitate efficient transmission or subsequent processing. Power amplifiers
serve a crucial role in guaranteeing signal resilience in a wide range of applications,
including audio systems and RF communication. In the signal processing chain,
the amplification step is commonly carried out following low-power stages, during
which the amplified signal is readied for later stages. Achieving desirable perfor-
mance metrics in many electronic devices and systems necessitates the improvement
of signal strength [1].
Various categories of power amplifiers provide unique operational attributes,
enabling designers to select the most suitable option according to individual appli-
cation needs. The most prevalent amplifier classes are Class A, Class B, Class AB,
Class C, and Class D, each possessing distinct advantages and trade-offs. Class
A amplifiers exhibit a notable degree of linearity, but at the expense of efficiency.
Conversely, Class D amplifiers employ pulse-width modulation to achieve great
efficiency, rendering them well-suited for digital audio applications. The selection
of amplifier classification is contingent upon various criteria, including power effi-
ciency, linearity, and the particular requirements of the given application [2].
Efficiency, linearity, and output power are crucial factors to be taken into account
while designing a power amplifier. Efficiency, which can be described as the propor-
tion of output power to input power, plays a critical role in the reduction of power
wastage, particularly in devices that rely on battery power. Linearity is a crucial
attribute in applications where maintaining signal fidelity is of utmost importance,
as it guarantees accurate signal replication without the introduction of distortions.
Meanwhile, the capacity to generate power is crucial for operating devices with dif-
ferent levels of resistance, such as speakers or antennas, which allows for wider sig-
nal coverage and range. The attainment of equilibrium among these variables poses
a formidable obstacle in the realm of power amplifier design, necessitating meticu-
lous deliberation in the choice of amplifier category and design parameters to cater
to the distinct demands of each application [3].
GaN HEMT-Based Power Amplifiers 323

20.2 GAN HEMT TECHNIQUES

20.2.1 Advancements in GaN HEMT Fabrication Techniques
GaN HEMT technology has witnessed substantial progress in fabrication techniques,
contributing to enhanced device performance. State-of-the-art substrate materials,
particularly silicon carbide (SiC) and sapphire, have demonstrated improved ther-
mal conductivity and compatibility with GaN, leading to better heat dissipation and
increased reliability [18]. Additionally, advancements in epitaxial growth techniques,
such as metal-organic chemical vapor deposition (MOCVD) and molecular beam
epitaxy (MBE), have enabled precise control over material properties, resulting in
high-quality GaN layers with reduced defects [19]. These improvements in substrate
technology and epitaxial growth have paved the way for the fabrication of smaller
and more intricate GaN HEMT devices through enhanced lithography and etching
processes, fostering increased integration density and improved efficiency [20].

20.2.2 Performance Enhancements and Key Breakthroughs

in GaN HEMT Technology

GaN HEMTs have achieved notable performance enhancements and technological

breakthroughs, positioning them as leading semiconductor devices. Characterized
by high electron mobility, GaN HEMTs enable fast switching speeds and low on-
resistance, crucial for applications like high-frequency communication systems and
power electronics [21–25]. The high-power density and efficiency of GaN HEMTs
surpass traditional semiconductor technologies, such as silicon (Si), making them
well-suited for power amplifiers and radar systems [26]. Breakthroughs in design
and fabrication have led to improved breakdown voltages, enhancing device reliabil-
ity, while the wide bandgap of GaN allows for operation at elevated temperatures and
voltages [27]. These advancements collectively contribute to the widespread adop-
tion of GaN HEMTs in various high-performance applications.

20.2.3 Comparison with Other Semiconductor Technologies

In comparison with other semiconductor technologies, GaN HEMTs stand out for
their superior characteristics. When compared to silicon (Si), GaN HEMTs offer
higher electron mobility and excel in high-frequency applications. The wide band-
gap of GaN, in contrast to gallium arsenide (GaAs), results in higher breakdown
voltages and better thermal stability, making GaN HEMTs suitable for high-power
applications [28]. While SiC is also a wide-bandgap material, it is often preferred for
high-power and high-temperature applications, complementing the strengths of GaN
HEMTs. These distinctions highlight the versatility and performance advantages of
GaN HEMT technology in the semiconductor landscape [29].
To achieve higher power density, the utilization of gallium nitride high elec-
tron mobility transistors (GaN HEMTs) is essential, as they enable increased con-
verter efficiency, allowing for a departure from thermal limitations. A key benefit
324 Circuit Design for Modern Applications

FIGURE 20.1 The curve depicts the potential enhancements in efficiency achievable by
employing 600 V/190 mΩ GaN HEMTs instead of 500 V/140 mΩ Si MOSFETs.

of GaN is the significantly reduced output charge (QOSS), enabling Zero Voltage
Switching (ZVS) with lower magnetization current. This reduction in conduction
losses in switches and transformers contributes to an overall efficiency improvement.
Moreover, the lower gate charge in GaN results in diminished losses associated
with gate driving. Importantly, GaN HEMTs outperform superjunction MOSFETs
by exhibiting lower losses related to the charging/discharging of COSS capacitance
during ZVS. Consequently, the efficiency of the entire system can be enhanced by
approximately 0.4% at full load across the entire input voltage range, as depicted in
Figure 20.1.

20.3 GAN HEMT POWER AMPLIFIER DESIGN CONSIDERATIONS

20.3.1 Biasing and Thermal Considerations for GaN HEMTs
When designing power amplifiers using GaN HEMTs, it is essential to consider
appropriate biasing and temperature control [30]. GaN HEMTs have a high degree
of sensitivity to variations in temperature, and their ability to perform may be nega-
tively impacted if not properly regulated. It is crucial to establish a biasing strat-
egy that is both reliable and efficient in order to guarantee the best operation of
the device. This entails the meticulous identification of bias sites and the consistent
maintenance of bias conditions across diverse operational settings. In addition, effi-
cient thermal management is crucial for dispersing the heat produced during opera-
tion. This requires the implementation of sophisticated heat sinks, thermal vias, and
other cooling methods to avoid overheating and guarantee the power amplifier’s
long-term dependability [31].
To attain a small signal gain exceeding 26 dB, meticulous attention was given
to factors such as mismatch, propagation loss, process variation, and the greatest
achievable gain (MAG) of transistors. To address these factors, the design decision
was made to implement a three-stage, common-source architecture. The careful
consideration of the cell’s peripheral was of utmost importance, as it involved evalu-
ating the compromises between larger transistors that yield greater output power
(Pout) and the difficulties in achieving broadband matching due to reduced optimum
impedance, resulting in heightened loss.
GaN HEMT-Based Power Amplifiers 325

Although larger transistors have the potential to achieve a greater Pout, their
lower optimum impedance makes broadband matching more complex, leading to
increased loss. The potential influence of supplementary parasitics on the transi-
tion rate (fT) and the highest oscillation frequency (fmax) may result in heightened
energy consumption and diminished power-added efficiency (PAE). As a result, the
deliberate choice was made to reduce the total gate width (TGW) of the output stage
cell in order to satisfy the 1 W Psat criterion.
The process of selecting the optimal gate width for energy cell implementations
required evaluating three different combinations, following the guidelines provided
in the foundry design handbook. The objective was to uphold the precision of the
model while utilizing a unit gate width (UGW) of at least 100 ± m and a maximum
of eight gate fingers (NGF). An eight-finger HEMT was selected as the final option
after considering a cautious staging ratio of 1:2. In order to mitigate the soft compres-
sion phenomenon observed in GaN-based devices, the dimensions of the first stage
cell were slightly increased to 50 ò 2 µm. This modification resulted in an enhanced
linear driving capability while having minimal impact on the final power-to-energy
ratio (PAE). Figures 20.2 and 20.3 depict the power amplifier topology, Interstage
matching network (ISMN), fT, fmax, and terminal resistances of three unit cells
with distinct fingers but similar TGWs under nominal bias conditions. These figures
offer valuable insights into the inherent trade-offs involved in the design consider-
ations [31].

FIGURE 20.2 Block diagram of multistage power amplifier.

FIGURE 20.3 Schematic of interstage matching network.

326 Circuit Design for Modern Applications

20.3.2 Stability Analysis and Considerations for Power Amplifier Design

Stability is a critical aspect of power amplifier design to prevent issues such as
oscillations and ensure reliable and consistent performance [31]. Stability analysis
involves examining the interaction between the GaN HEMT, the load, and the feed-
back network. The use of stability circles or the Rollett stability factor can aid in
evaluating the stability margins of the amplifier. Implementing techniques such as
source and load-pull analysis during the design phase can help identify potential
instability regions and guide the selection of appropriate biasing and matching net-
works. Additionally, the incorporation of stabilizing elements, such as resistive or
reactive components in strategic locations, can improve stability without sacrificing
performance [32]. It is crucial to strike a balance between achieving high gain and
efficiency while maintaining stability throughout the desired operating range.
Active GaN devices have a significant inherent advantage, which makes them
more prone to self-oscillation and increases the likelihood of circuit failures. Hence,
it is imperative to guarantee the initial grounding of all chosen power cells. Figure
20.4 depicts two prevalent stabilization techniques employed at the input of the tran-
sistor in order to mitigate power dissipation. The implementation of a parallel RC
network featuring reactive/resistive lossy MN guarantees stability within the desired
frequency range. Additionally, the integration of a series connection consisting of a
restoring stability resistor, Rp, and choke of the inductor, Lp (or the microstrip line,
TLp), into the gate bias branch is intended to improve stability at lower frequencies.
This configuration emulates the behavior of a closed circuit for the amplifier chain.
To prevent potential instability, it is crucial to carefully consider the self-resonant
frequencies (fSR) of the MIM a capacitor, Cs, particularly if fSR is either within or
outside the operating band. The fSR of Cs may be shifted to lower frequencies due
to electromagnetic coupling from the environment. In order to tackle this issue, it is
possible to divide Cs into two distinct-shaped capacitors that are linked in parallel
on both sides of Rs. This configuration effectively reduces the parasitic inductance
associated with the capacitor plates. The symmetrical arrangement of the layout
enhances the consistency of signal transmission and facilitates the attainment of
input balancing for the transistor.
The simplified hybrid model depicted in Figure 20.5 is used to compute the chan-
nel resistance (Ri) and depletion capacitance (Cgs) in order to assess the influence of

FIGURE 20.4 Schematic of stabilization circuit.

GaN HEMT-Based Power Amplifiers 327

FIGURE 20.5 Simple equivalent circuit for HEMT.

the R–C stabilizing network on matching bandwidth. By excluding the insignificant

Cgd, every cell is seen as a bilateral two-port network, where the input impedance,
Zin, can be expressed as an array of Ri and Cgs. If the input capacitance of a stable
HEMT is observed from point A as Zins, then:

1
Zins   Zin (20.1)
1
 jCs
Rs
The quality factors, Q of Zins (i.e., Qins) and Q of Zin (i.e., Qin), are defined as:

1  2 R 2Cs  Cs  Cgs 
Qins  Qin (20.2)
Rs
1   RsCs  
2

Ri
1
Qin = (20.3)
RiCs
Qins
The ratio is given by:
Qin
Qins 1  R Cs  Cs  Cgs 
2 2
 (20.4)
Qin Rs
1   RsCs  
2

Ri
At f0, the quality factor Qin is 1.7, and Qins is larger than Qin when RsCs > 10 –11. After
integrating a parallel RC network, there is a potential reduction in the maximum
attainable bandwidth, which could be a trade-off for considerations related to gain.
Nevertheless, when considering a frequency range of 10 GHz that is designed cau-
tiously, there exists a significant opportunity to achieve a harmonious equilibrium
among security, connectivity, and gain. According to Equation 20.2, the output stage
cell utilizes a stabilization network including 2 equal 0.68 pF capacitors connected
together with a 30 Ω resistor. This configuration yields a Qins value of 2.24. The
series of parasitic inductance, indicated by the C–R–C framework, is reduced by half
from 21.2–9.6 pH relative to the typical R–C arrangement by putting the reactance
values of X slopes from Figure 20.6 at the FSR into Equation 20.5. As a result, the
frequency of fSR rises to 44.6 GHz [33].
328 Circuit Design for Modern Applications

FIGURE 20.6 The reactance and frequency in a parallel RC and C–R–C stabilization
network.

FIGURE 20.7 Compares stability factor (a) and maximum gain (b) versus frequency for
R–C network, no stabilization network, and parallel R–C with series R–TL stabilization.

X  1
| fSR  2  L   (20.5)
f  C
The analysis of Figure 20.7 demonstrates that the lack of a stability network, simulta-
neous R–C system, and serial R–C network with R–TL all exhibit a continuous Rollett
instability factor (K) over 1 across the majority of the bandwidth. Additionally, the
gain loss remains small, measuring less than 0.9 dB. Although there is instability at
wavelengths below 1 gigahertz, this issue can be effectively addressed by taking into
account the inherent losses and filtering abilities of all R–C networks.
GaN HEMT-Based Power Amplifiers 329

20.3.3 Impedance Matching Techniques Considerations

Achieving optimal impedance matching is pivotal for maximizing power transfer
efficiency in GaN HEMT-based power amplifiers, ensuring precise alignment with
source and load impedances. Commonly, transmission line-based matching net-
works, such as microstrip or coplanar waveguides, are employed for effective imped-
ance transformation. Advanced techniques, including the strategic use of lumped
elements, transmission line transformers, or matching networks with reactive
components, contribute to fine-tuning impedance across a broad frequency range.
Meticulous attention to impedance matching minimizes signal reflections, thereby
optimizing the overall efficiency of the power amplifier [34]. In RF and microwave
circuit design, determining the optimal impedance domain and crafting an equivalent
large-signal output matching model is vital. Defined specifications, encompassing
operating frequency, power levels, and efficiency, guide this process. Large-signal
output matching, which accounts for the nonlinear behavior of active devices, is
of paramount importance. Techniques like load-pull analysis, S-parameters, and
the Smith Chart provide valuable insights for visualizing impedance variations.
Here, the reflection coefficient and insertion loss along with frequency response is
depicted in Figure 20.8. Passive components are intricately designed, with a focus
on transforming load impedance for maximum power transfer. The iterative refine-
ment of the design, informed by practical implementation, simulation, and feedback,
ensures the final product meets stringent performance specifications. The utilization
of advanced simulation tools and precision measurement equipment plays a pivotal
role in this comprehensive design approach.

FIGURE 20.8 (a) The reflection coefficient and (b) insertion loss along with frequency
response.
330 Circuit Design for Modern Applications

FIGURE 20.9 Input impedance in power stage with respect to frequency, (a) real part, (b)
imaginary part.

Regarding the interstage matching network, complexities arose from the non-
conjugate matching of optimum load and source impedances to their respective
transistors. To overcome this challenge, a dedicated optimization loop technique
was implemented, aligning the input impedance of the power stage and the out-
put impedance of the driver. The matching network underwent meticulous optimi-
zation to account for real and imaginary impedances in both directions. Despite
encountering limitations in impedance transformation from the input to the output
impedance of the power stage, as evidenced by variations versus frequency shown
in Figure 20.9, the design process demonstrated a strategic and adaptive approach to
overcome such challenges.

20.4 CONCLUSIONS
In conclusion, the design considerations for GaN HEMT-based power amplifi-
ers involve critical aspects such as biasing, thermal management, stability, and
impedance matching. Proper biasing and effective thermal control are imperative
for optimal GaN HEMT performance, considering their sensitivity to temperature
fluctuations. The use of a three-stage, common-source layout effectively tackles
issues pertaining to mismatch, propagation loss, process variation, and the maxi-
mum attainable gain (MAG) of transistors. Careful selection of unit cell parameters,
including periphery and gate width, is essential to balance trade-offs between output
power, broadband matching, and optimal impedance.
GaN HEMT-Based Power Amplifiers 331

Stability analysis is crucial to prevent issues like self-oscillation, especially with

the intrinsic gain of GaN devices. Stabilization measures, such as parallel RC net-
works and series connections of stabilizing resistors and inductors, enhance stabil-
ity without sacrificing performance. Attention to the self-resonant frequencies of
capacitors is essential, and strategies like splitting capacitors contribute to signal
transmission consistency.
The impact of stabilization networks on matching bandwidth is quantified, reveal-
ing trade-offs between stability, bandwidth, and gain. Despite potential reductions
in bandwidth, a well-balanced approach ensures stability within a conservatively
designed bandwidth of 10 GHz. The output stage utilizes a stabilization network
with capacitors and resistors, resulting in increased self-resonant frequencies and
improved stability.
Achieving optimal impedance matching is fundamental for power transfer effi-
ciency, and the interstage matching network is optimized through a dedicated loop
technique. Despite challenges in impedance transformation, the design process dem-
onstrates adaptability and strategic decision-making.
In summary, a comprehensive approach to GaN HEMT power amplifier design
considers biasing, thermal management, stability, and impedance matching, dem-
onstrating a strategic balance between performance parameters to meet stringent
specifications.

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 21 New Approaches for
Modeling Nanoscale
Junctionless FETs
Device and Circuit-Level
Performance Assessment
H. Ferhati, T. Berghout, and F. Djeffal

21.1 INTRODUCTION
Over the past few decades, MOSFETs (Metal Oxide Semiconductor Field Effect
Transistors) have been the key driving force behind the semiconductor indus-
try, serving as the foundational element of integrated circuits [1–5]. MOSFETs
are now a microelectronics foundation, they are more popular as smaller devices
with higher performance, and their application in electronic circuits is expanding
[2–7]. The device architecture and operating principle have remained practically
unchanged to this day, but its physical dimensions have continued to decrease [4–8].
The International Technological Roadmap for Semiconductors (ITRS) forecasted
that miniaturizing traditional MOSFET devices would reach its limit in 2017 [9].
Basically, reducing the size of components is not the best solution to guarantee better
performance, while maintaining low manufacturing costs [10–14]. Parasitic effects
such as high OFF-state current, degraded subthreshold behavior, drain induced bar-
rier lowering (DIBL) and noise effects appear and increase with the reduction of
the transistor dimensions [12–15]. This decline in electrical performance is primar-
ily related to weak control of the channel electrostatic field. The development of
the semiconductor industry requires fulfilling several criteria including producing
even smaller electronic devices, faster transit times, and reliable and cost-effective
devices. Accordingly, the industry has encountered great changes, moving from
microelectronics to nanoelectronics [16–20]. Thus, alternative solutions to con-
ventional MOSFET are proposed for future technological nodes. In this context,
Junctionless strategy and multiple gate (MG) designs including double gate, FinFET
or well-known as GAA (Gate-All-Around) have offered new pathways for extend-
ing the miniaturization 2026 [18–23]. Therefore, these multi-gate structures have
attracted significant interest among researchers due to their potential in developing
high-performance nanoelectronic integrated circuits (ICs) [22–26]. This is mainly

334 DOI: 10.1201/9781003483052-21

New Approaches for Modeling Nanoscale Junctionless FETs 335

due to their capability of offering better electrostatic control of the channel and
reduced parasitic currents [25]. Despite these advantages, various challenges regard-
ing commutation speed, power loss, device reliability and processing complexity
still persist, making continuous miniaturization extremely difficult [26]. Therefore,
the emergence of novel design strategies is still required to keep up with Moore’s law
evolution. Following this direction, several architectures including, dual material
gate (DMG), gate stack, underlap, doping engineering, heterostructured channel and
T-shaped devices have been investigated for overcoming common problems associ-
ated with MG MOSFET devices [27–32]. Moreover, graphene-based nanoscale JL
transistors have been widely investigated to achieve high derived current capability
and improved switching behavior [33–36]. However, the use of 2-D materials has
various drawbacks including noise effects and complicated manufacturing process-
ing. Also, the rise in leakage current reduces device reliability and power consump-
tion also increases. Thus, these technologies have led to achieving enhanced analog/
RF performances, but the adaptation of these architectures for future technological
nodes still remains a real challenge.
In traditional nanoscale MG MOSFETs, the ion implantation method is employed
to create source/drain (S/D) areas, resulting in a random distribution of dopant atoms
[37]. This phenomenon results in doping gradients between the channel and S/D
extremities with a typical distance value of about 3 nm/dec. Besides, the use of heav-
ily doped S/D regions imposes high-temperature thermal treatment to achieve acti-
vation of dopants in semiconductor film. This process can consequently cause dopant
atoms to spread sideways from S/D regions into the device channel, hindering the
formation of sharp junctions at the interface between the source/channel and drain/
channel. As a potential solution to these problems, junctionless (JL) technology is
one of the most intriguing strategies being continuously explored due to its versatil-
ity in design, low cost and capability for mitigating technological issues associated
with conventional devices [38–40]. It involves utilizing a uniformly n-type doped
channel without P–N junctions [38]. This strategy has enabled avoiding the elabo-
ration of abrupt junctions, which is considered as a serious problem for nanoscale
devices as is above-outlined. Accordingly, the research interest is turned toward the
development of new high-performance cost-effective nanoscale MG JL MOSFET
devices [41–43]. In this regard, several studies confirmed the capability of JL tech-
nology for the realization of GAA MOSFET devices with improved performances.
Despite the technological benefits of the JL-based devices, suppressing metallurgi-
cal junctions has affected the device-derived current capability, the commutation
speed and power consumption. These issues have conducted research to introduce
applied design strategies commonly used to enhance conventional MG MOSFET
device performance. This includes gate engineering, alternative high-κ gate dielec-
tric, engineered doping profiles, S/D extensions and alternative III–V-material build-
ing blocks [43–49]. However, further improvements should be achieved to make JL
GAA MOSFET devices highly competitive with conventional nanoscale MOSFET
devices in terms of device performance.
Silicon-based alloys, with adjustable band gaps below 1.1 eV, high carrier mobil-
ity, and compatibility with CMOS technology, have emerged as potential alternative
336 Circuit Design for Modern Applications

materials for designing MG MOSFET devices with high analog/RF performance

[50–54]. Within this framework, to enhance ON-state current and Ion/Ioff ratio of
JL GAA MOSFETs, in addition to increasing the switching speed of the device,
Si(1–x)Snx and SixGe(1–x) binary alloys have successfully met all the previously
mentioned criteria [52–56]. Therefore, the purpose of this chapter is to explore the
application of these Si-based binary alloys in improving GAA JL MOSFET devices.
In this setting, nanoscale MG MOSFET designers still face the problem of the opti-
mization of subthreshold properties (SS and Ioff current), drive current (Ion current)
and ambipolarity effect, in order to develop high-performance ICs with improved
FoMs relative to the traditional silicon-based MG MOSFETs. In this perspective,
SiSn and SiGe GAA JL MOSFET devices are optimized using the particle swarm
optimization (PSO) technique and the appropriate Si-based binary alloys are suc-
cessfully selected.

21.2 DEVICE DESIGN AND MODELS

This section delineates a three-stage research framework primarily centered on the
development of Si-based binary alloy GAA JL MOSFET devices. Initially, we intro-
duce the device structure and the conceptual fabrication processes, incorporating
the utilization of SiGe and SiSn compounds. Subsequently, we delve into a com-
prehensive discussion of the operational mechanism of the scrutinized JL device.
Finally, we introduce the analytical modeling approach employed to evaluate device
performance.

21.2.1 GAA JL MOSFET Structure

The foundational aspect of GAA JL MOSFET is based on the incorporation of SiGe
and SiSn binary alloys into the source, drain, and channel areas. The primary objec-
tive is to explore how incorporating alternative materials in the channel, source,
and drain regions can improve device performance and minimize parasitic currents.
Figure 21.1(a) illustrates the schematic structure of GAA JL MOSFET under investi-
gation, Si, SiGe, and SiSn as material building blocks in (a), (b), and (c). The devices
are composed of heavily doped Si and silicon-based alloy ultrathin films. These
films are equipped with a surrounding gate to control the channel’s electrostatic
characteristics and establish Ohmic electrodes. The mole fraction (xGe and xSn)
of the suggested Si binary alloys (SiGe and SiSn) can induce significant changes
concerning the device transport mechanism and performance of JL transistors. The
same doping level is considered for the S/channel/D structure. This can lead to an
altogether different operating mechanism in the JL transistor device compared to the
traditional MOSFET one. The investigated nanoscale device is taken with a short
channel length (L) and an ultrathin gate-oxide thickness (tox). Besides, SiO2 mate-
rial is suggested for the gate-oxide regions and the surrounding gate is taken with
highly doped polycrystalline silicon (Poly-Si) for which the work function value is
first fixed at the value of 4.8 eV. Design parameters of GAA JL MOSFET devices
based on Si, SiGe and SiSn channels are summarized in Table 21.1. The concentration
New Approaches for Modeling Nanoscale Junctionless FETs 337

FIGURE 21.1 (a) Cross-sectional view of the investigated GAA JL MOSFET devices based
on Si and SiGe, SiSn binary alloy. (b) Concept of the fabrication processing of the studied
GAA JL MOSFET with Si-based binary alloys.

TABLE 21.1
Design Parameters of the Analyzed GAA JL MOSFET Devices with Si-Based
Binary Alloys
SiGe DG GAA JL
Design Parameter Notation SiSn GAA JL MOSFET MOSFET
Oxide thickness tox 4 nm 4 nm
Drain n+-doping ND 1018 cm–3 1018 cm–3
Source n+-doping NS 1018 cm–3 1018 cm–3
Channel doping Nch 1018 cm–3 1018 cm–3
Gate work function Фm 4.6 eV 4.6 eV
Sn mole fraction xSn [0, 0.5] [0, 0.5]
Ge mole fraction xGe – [0, 1]
Channel raduis R 10 nm 10 nm
Channel length L 80 nm 80 nm

within SiSn alloy is confined to a specified range, i.e., [0, 0.4], where experimentally,
the maximum achievable Sn mole fraction is around 44% using several crystalliza-
tion techniques as reported in [57–58].
The described GAA JL MOSFET structure can be elaborated following numer-
ous fabrication steps. Accordingly, Figure 21.1(b) depicts the concept fabrication
process of the investigated junctionless transistor based on Si binary alloy build-
ing blocks. Basically, a freestanding vertical nanowire base should be elaborated
to fabricate the GAA JL MOSFET device [59–62]. In this context, the SiSn and
SiGe films can be deposited on the Silicon-On-insulator (SOI) structure using the
chemical vapor deposition (CVD) technique. Thereafter, the freestanding vertical
338 Circuit Design for Modern Applications

nanowire can be fabricated by depositing a hard nitride mask and photo-resist and
then using the deep reactive ion etch (DRIE) process to get SiGe and SiSn pillar
structures [62]. The pillar radius can be suitably reduced by a self-limited oxidation
process [62]. Then the nitride layer can be removed using a wet etching method.
After achieving the vertical nanowire of SiGe or SiSn, the next step consists of the
doping process, where the ion implantation technique using arsenic dopant followed
by rapid thermal annealing (RTA) process can be exploited for the realization of
highly doped nanowire. High doping concentration can be achieved by well control-
ling the ion implantation doping process. Afterwards, isolation oxide can be grown
to separate the gate and base regions as depicted in Figure 21.1 (b). After that, the
dry thermal growth method can be employed to form SiO2 gate oxide around the
nanowire. Subsequently, the surrounded gate can be formed by depositing α-Si film
using the LPCVD technique followed by an ion implementation process and thermal
treatment to develop the poly-Si gate [62]. To tailor the gate length of the transistor,
the RIE process can be exploited to remove the gate isolation oxide and poly-Si as
shown in Figure 21.1 (b), keeping the poly-silicon around the desired gate length.
Finally, the chemical mechanical polishing (CMP) method and contact holes can be
patterned, etched and then metalized to form the source, drain and gate electrodes as
illustrated in Figure 21.1 (b).

21.2.2 Operating Mechanism
Indeed, the operational mechanism of JL devices differs significantly from that of
conventional inversion mode (IM) MOSFET. In addition, The JL device functions
based on the drift-diffusion mechanism while the gate voltage modulates the elec-
trostatic behavior in the channel, leading to the transition from OFF to ON states.
Figure 21.2 illustrates the change in drain current concerning the gate voltage in rela-
tion to the conventional GAA JL MOSFET device. Accordingly, the OFF-state of
the transistor is attained when the channel is completely depleted. This operational

FIGURE 21.2 Ids –Vgs characteristics of the Si GAA JL MOSFET obtained from the experi-
mental work and numerical simulation.
New Approaches for Modeling Nanoscale Junctionless FETs 339

mode arises from the significant disparity in the work function between the gate and
the channel material. In the OFF-state, the drain bias applied is distributed across
the depleted channel, resulting in heightened series resistance and consequently, a
low drain current. The shift from a fully depleted channel to a partially depleted one
under applied voltage signifies the device threshold voltage. During this state, the
current initiates its flow at the GAA MOSFET channel center, leading to avoiding
the degradation of carrier mobility, which is considered the main benefit of depletion-
based JL MOSFET with respect to conventional (IM) devices. In this framework,
the introduction of Si-based binary alloys like SiGe and SiSn would influence the
device threshold voltage, where the compound composition can change the transition
between the fully and partially depleted operating modes. Continuing to elevate the
gate bias to reach the flat-band voltage renders the entire channel conductive, leading
to the occurrence of the accumulation operating mode, as depicted in Figure 21.2.
Accordingly, carriers will accumulate at the oxide/channel interface and the current
saturates by further increasing the gate voltage.

21.2.3 Modeling Approach
The analyzed device is suggested with Si-based binary alloys (SiGe and SiSn), where
the elaboration of the device from a technological viewpoint can be easily made
by developing SiGe or SiSn thin films on the SOI platform. From Figure 21.1, the
parameter r denotes the cylindrical channel radius and Nch refers to the doping level
of the considered SiGe and SiSn channel. To model the device operating mechanism,
Poisson’s formula is modified to fit a problem with 1 D, where the lower limit of
channel length is fixed at 60 nm. Besides, the channel radius is limited to 10 nm, thus
quantum confinement effects are ignored [63].
The conventional expression for Poisson’s formula in cylindrical coordinates can
be presented as:

d 2 1 d  qN ch    (r )  V  
   exp    1 (21.1)
dr 2 r dr  al   Vt  
where q is the electron charge,   r  refers to electrostatic potential in SiGe of SiSn
channel body, ε al represents Si-based compound (SiGe, SiSn) permittivity, Vt is the
thermal voltage and V denotes the source to drain potential shift.
A parabolic profile for the channel potential is considered. Besides, boundary
conditions assuming a constant electrostatic potential of Ψ 0 and zero electric field
at the channel center are given by

 (0)   0 (21.2a)

d
0 (21.2b)
dr r 0
340 Circuit Design for Modern Applications

Therefore, the electrostatic potential can be expressed as

 s  0 2
 (r )  r  0 (21.3)
R2
with Ψ s denoting the surface potential at the channel/SiO2 boundary.
To compute the mobile charge, it is necessary to apply Gauss’s theorem at the
interface of the channel (SiGe, SiSn) and SiO2. Consequently, the association between
the potential and the mobile charge is expressed as:

d Qm  Q fix
 (21.4)
dr rR  si

With Qm and Q fix referring respectively to the mobile and the fixed charges. In this
framework, the fixed charge can be estimated from Q fix = 2qN ch R / 2. Subsequently,
employing Gauss theorem as defined in the aforementioned equation around the
proposed (SiGe, SiSn) channel and accounting for the boundary conditions, we can
derive an implicit equation for the mobile charge density, given by:

 R  Qm  Q fix  
1  exp  
 2 alVt
Qm  Q fixQi   exp   s  V  (21.5)
Qm  Q fix  V 
 t 

With Qi  2 alVt / R.
Conversely, we can deduce the connection between the surface potential Ψ s and
the applied gate voltage Vgs as:

d Qm  Q fix
  Cox Vgs  V fb   s  (21.6)
dr rR  al

Thus, Ψ s can be demonstrated as in the following formula

Qm  Q fix
 s  Vgs  V fb  (21.7)
Cox

where Vgs and Vfb denote the gate and the flat-band voltages, the oxide capacitance
( Cox ) can be estimated from Cox  ox /  R ln 1  tox / R   with εox is the oxide per-
mittivity. In this context, the Si-based alloy composition can modulate this electronic
parameter ( ϕms ), which can in turn the device’s flat-band characteristics. Likewise,
the doping level of the considered SiSn and SiGe channels can also modify the flat-
band voltage and thus the transition from the partially depleted working to the accu-
mulation modes. Consequently, the flat-band voltages of both SiGe and SiSn-based
JL transistors (VfSiGe, VfSiSn) can be estimated from the following expressions
New Approaches for Modeling Nanoscale Junctionless FETs 341

  N ch 
V fbSiGe  ms1  Vt ln  
  ni 
 (21.8)
V fbSiSn  ms 2  Vt ln  N ch 
  n 
 i 
with

ms1  m  Eg SiGe   SiGe


ms 2  m  Eg SiSn   SiSn
where VfbSiGe and VfbSiGn represent the SiGe and SiSn flat-band voltages, mainly
depending on the variation of the material bandgap (Eg) and electron affinity (χ)
when the elemental composition is varied [57–58].
To formulate a concise model for the drain current, it is essential to estimate the
channel charge Qm. In this context, the Lambert function LW(z) [63] can offer an
alternative solution with an explicit form for the channel charge Qm. Thus, utiliz-
ing Equations 21.5 and the Lambert function, an analytical expression for the total
mobile charge can be derived as:

   Q fix  Qm1 (V )   
 1  exp    
 K   Qi 
Qm (V )  CoxVt LW  exp   i V    (21.9a)
CoxVt Qm1 (V )  Q fix
 
 
 
The Lambert function expression, LW(z), is provided as:

 ln 1  ln 1  z   
LW  z   ln 1  z  1   (21.9b)
 2  ln 1  z  
 

  Q fix  Qm 2 (V )  
 exp   
K Qi
Qm1 (V )  Qe LW 
 Qe

Qm 2 (V )  Q fix
 i  
 exp  V 

(21.9c)
 
 
and

 K 
Qm 2 (V )  CoxVt LW  exp   i V  / 2   (21.9d)
 CoxVt 
with

K = Q fixQi
342 Circuit Design for Modern Applications

Qi CoxVt
Qe 
Qi  CoxVt
The potential  i V  with i = 1, 2 depends on the material used in the channel, where
i = 1 corresponds to the SiGe compound and i = 2 is related to the SiSn channel.

  Qi 
1 V    Vgs  V fbSiGe  V 
  Cox 
 (21.10)
  Qi 
 2 V    Vgs  V fbSiSn  C  V 
  ox 
The drift-diffusion model governs the transport mechanism of suggested GAA JL
MOSFET based on Si-based binary alloys for each value of Vgs. Thus, the drain cur-
rent can be calculated utilizing the following equation:

Vds
R nVt
I ds 
L  Q dV
0
m (21.11)

With µ n is the channel mobility depending on the material used in the channel as
well as the elemental composition. Upon evaluating the integral in Equation 21.11,
we derive a concise analytical expression for the drain current I ds .

R nVt
I ds   F (0)  F (Vds )  (21.12)
L

Qm (V ) 2  Qi  CoxVt    Q (V )  Q fix 
F (V )   2Qm (V )  CQm (V ) ln 1  exp  m  
2CoxVt Qi   2CQi 

 
 
 Qm (V )  Q fix 
Q fix ln 
  Qm (V )  Q fix   
 2Qi  exp    1 
 
  2Qi   
(21.13)

To assess the accuracy of the developed compact analytical model based on the
drift-diffusion transport mechanism, the Si GAA JL MOSFET design reported in
the experimental work [61] is simulated taking the same geometrical and physical
parameters. In this perspective, Ids–Vgs characteristic and those reported in [61]
are compared in Figure 21.2. The curves illustrate a notable concordance between
the analytical outcomes and the experimental data. The adopted modeling frame-
work effectively reproduces the experimental results, affirming its suitability for
New Approaches for Modeling Nanoscale Junctionless FETs 343

examining the impact of incorporating Si-based binary compounds on JL transistor

performances. This serves as the primary goal of the following section in the chapter.

21.3 SI-BASED BINARY ALLOYS GAA JL MOSFET ANALYSIS

For performance evaluation of investigated Si-based binary alloys GAA JL MOSFET,
the output and transfer characteristics associated with the devices based on Si, SiGe,
and SiSn material building blocks are extracted using the developed model and then
illustrated in Figure 21.3. From the latter, we can notice the improved electrical
behavior of Si-based binary alloys GAA JL MOSFET devices in comparison to the
conventional Si-based device. In addition, the introduction of SiSn and SiGe materi-
als allows modulating the threshold voltage, thus leading to better control of device
commutation properties. Besides, this also reduces parasitic effects associated with
the device. Figure 21.3(a) shows also that current conduction in the JL device is
controlled by the channel/gate junction as in a MOSFET. The threshold voltage is
achieved when the partially depleted operating mode is reached. Afterwards, further
increasing the gate voltage to achieve the flat-band condition, gives rise to the accu-
mulation current. On the other hand, the output characteristics of the investigated
devices demonstrate that improved drain current can be achieved by considering
SiSn and SiGe materials, where a high drain current of 0.45 mA is recorded. This
can be primarily attributed to the utilization of Si-based binary alloys in offering
enhanced carrier mobility and improved transport characteristics. It can be also
observed from Figure 21.3(b) that the proposed SiSn GAA JL MOSFET device
exhibits a higher drain current as compared to the SiGe-based device. This can be
attributed to its better control of the channel electrostatic behavior and thereby its
transport mechanism is improved. Furthermore, it can be seen from Figure 21.3(b)
that, at higher drain voltages, the drain influence on current conduction in saturation
reduces, and JL GAA MOSFET exhibit lower output conductance (gds) than that of
the inversion mode device, whose output transconductance is reported to be 200 μS/
um. A lower output conductance associated with SiSn and SiGe GAA JL MOSFET
devices can avoid complexity such as inverter-gate and cascode implementation and
required biasing power in analog designs.

FIGURE 21.3 (a) Ids–Vgs curves of the Si DG TFET obtained from the experimental work
and numerical simulation. (b) Output characteristics of the analyzed Si, SiSn and SiGe GAA
JL MOSFET devices.
344 Circuit Design for Modern Applications

FIGURE 21.4 Variation of ION/IOFF ratio as a function of (a) Ge concentration and (b) Sn
mole fraction for both proposed transistors based on SiGe and SiSn material building blocks,
respectively.

After bringing evidence that using Si-based binary alloys can offer new path-
ways for improving and modulating the performance and transport mechanism of
GAA JL MOSFET device, it seems of paramount importance to analyze the influ-
ence of the Ge containing (xGe) and the Sn concentration (xSn) in both SiGe and
SiSn, respectively, on the device performance. To achieve this, Figure 21.4(a) and (b)
illustrate the fluctuation of the drain current concerning Ge and Sn mole fractions,
respectively. The Sn mole fraction in SiSn alloy is varied from 0% to 44%, which is
considered as the limit for the elaboration of stable SiSn thin film with good crystal-
linity and reduced defects [57–58]. As observed in Figure 21.4(a), the scrutinized
SiGe GAA JL MOSFET device exhibits higher performance with respect to the con-
ventional Si-based device. In addition, the ON-to-OFF current ratio increases with
the Ge mole fraction increase. This is mainly ascribed to the effect of the Ge level in
SiGe on the threshold voltage, modulating the transport mechanism of the transis-
tor. In addition, increasing the Ge concentration leads to improved carrier mobility,
contributing to the ON-state current enhancement. On the other hand, Figure 21.4(b)
demonstrates the complex behavior of SiSn GAA JL MOSFET devices. In other
words, the ON-to-OFF current ratio decreases with rising Sn concentration in the
SiSn channel to reach the lowest value of xSn = 15%. Thereafter, the Sn containing
increase over the latter critical value leads to an exponential increase of the ION/
IOFF ratio as shown in Figure 21.4(b). This complex behavior can be explained by
the effect of SiSn binary alloy in inducing significant changes regarding the gate/
oxide/channel electronic structure and the lateral carrier transport from the source
to the drain. The discrepancies regarding the electrical behavior between both GAA
JL MOSFET devices based on SiGe and SiSn material can be explained by the dif-
ference between the materials’ electronic properties when the elemental composition
is varied. In the case of SiGe material, the increase of Ge content induces bandgap
lowering and the material affinity is slightly influenced, where χ Si0.1Ge0.9 = 4.01 eV
and χ Si = 4.01 eV. On the other hand, the variation of Sn concentration decreases
the bandgap and induces significant changes in the conduction band position, lead-
ing to a higher variation of the electron affinity ( χ Si0.6 Sn0.4 = 4.23 eV and χ Si = 4.01
eV). This behavior can significantly modulate the flat-band and threshold voltages.
The maximum transconductance and cut-off frequency of the examined JL devices,
utilizing SiGe and SiSn binary alloys, are identified for various concentrations of Ge
New Approaches for Modeling Nanoscale Junctionless FETs 345

FIGURE 21.5 Variation of transconductance and cut-off frequency vs (a) Ge concentra-

tion and (b) Sn mole fraction for both proposed transistors with SiGe and SiSn channels,
respectively.

and Sn. This is depicted in Figure 21.5(a) and (b), respectively. The latter figure
shows that the investigated GAA JL MOSFET devices with SiSn and SiGe material
building blocks offer improved transconductance and cut-off frequency when com-
pared to the conventional Si-based design. When Ge and Sn mole fractions increase,
it can be seen from Figure 21.5 that the transconductance has dissimilar tendencies
for both devices based on SiGe and SiSn. The increase of Ge content results in the
cut-off frequency increase in the range of xGe = [0,0.8] and then decreases for high
Ge concentration over 0.8 and for pure Ge-based devices. Alternatively, raising the
Sn level in the SiSn channel can improve both transconductance and cut-off fre-
quency. These discrepancies regarding device performance are related to the dif-
ferences concerning the electronic and electrical properties of both SiGe and SiSn
materials as it is above-outlined. Hence, a careful attention should be paid to the Ge
and Sn amounts used in GAA JL MOSFET devices for analog/RF applications for
which the maximum transconductance is highly required. In addition, other design
parameters such as the oxide thickness, the channel radius, the doping concentra-
tion and the gate work function also should be carefully selected, having a great
influence on device performance. Therefore, new optimization approaches should
be implemented to identify the suitable design parameters and Si-based binary alloy
composition that can offer the highest performances. This perspective will be thor-
oughly investigated in the next section of the chapter.

21.4 PSO DEVICE OPTIMIZATION

In the past several years, a wide range of scientific fields, including engineering,
biomedicine, economics, material science, renewable energy, and environmental
monitoring, have faced significant obstacles in their attempts to tackle numerous
real-life global optimization problems [64]. Within this framework, traditional local
optimization methods encounter several challenges in addressing global optimiza-
tion issues [64–66]. The primary factor impacting conventional methods is their
susceptibility to being entrapped in local optima solutions [67]. Moreover, precisely
solving the optimization problems in a reasonable amount of time appears to be
exceedingly challenging. However, global optimization techniques can be useful in
346 Circuit Design for Modern Applications

resolving these problems [65–67]. From this standpoint, modern artificial intelli-
gence approaches, including genetic algorithm (GA), and PSO metaheuristic tech-
niques, have garnered significant attention. The latter method, initially introduced
by Eberhart and Kennedy [68], emulates the metaphor of natural social behavior,
such as bird flocking. In this regard, the primary advantage of this approach lies in
its straightforward mechanism and ability to identify optimal solutions for a diverse
array of complex mathematical problems. These unique properties demonstrate the
usefulness of PSO for studying and optimizing a wide range of innovative micro and
nanoelectronic devices [69–71]. Due to its simplicity and versatility, the PSO-based
approach for global optimization can be very useful in studying and optimizing the
proposed GAA JL MOSFET device performance based on SiGe and SiSn binary
compounds. It offers new pathways to identify the optimized design, providing the
highest possible performance (Figure 21.7).
Fundamentally, PSO-based methodology employs random processes to minimize
a defined fitness function, enabling easy identification of global solutions to a given
problem. Additionally, the optimal position of each particle in the swarm and the

FIGURE 21.6 (a) Flowchart of the adopted PSO-based optimization framework. (b) Fitness
function versus the generation number of the performed PSO global search process.

FIGURE 21.7 Schematic of the basic circuit configuration of an inverter gate using the
optimized SiGe and SiSn-based transistors.
New Approaches for Modeling Nanoscale Junctionless FETs 347

collective best positioning of the particle group can influence the selection of poten-
tial particles. Alternatively, the group of particles to which a particle is topologically
connected is commonly referred to as a neighborhood, which is divided into two
categories: local best particles and global best particles. Consequently, each particle
in the swarm can exchange information with every particle in its vicinity. Moreover,
to modify and update the position and velocity of the recommended particles, equa-
tions inspired by bird-swarming behavioral models can be utilized, as outlined in the
following formulas.

Vi k 1  wVi k  s1h1k ( pijk  Z ik )  s2h2k ( gijk  Z ik ) (21.13 a)

Z ik 1  Z ik  Vi k 1 with i  1...m (21.13 b)

where m is to the swarm size, Vi k and Z ik refers to the particle velocity and position,
while gijk and pijk represent respectively, the best positioning of the particle group
and the best position of each particle in the swarm, s1 and s2 are the cognitive and
social acceleration factors; h1 and h2 are random numbers considered in the specific
range of [0,1]. To balance the global search process the inertia weight (w) is applied.
The proposed PSO-based optimization framework is represented by the flowchart
shown in Figure 21.6(a). Observing this flowchart, the main objective is to determine
the optimized GAA JL MOSFET based on SiSn and SiGe binary alloys. To do so,
various geometrical (r, tox, and L), electrical (Vgs and Vds), electronic (ϕm ) , and
physical (Nch, xGe, xSn) should be optimized to minimize the objective function.
The latter is formulated based on satisfying several criteria related to the device’s
RF/analog performances. The fitness function is defined as follows:

1 1 1
F ( X )  w1 ( )  w2 ( )  w3 ( ) (21.14)
ION / I OFF ratio gm fc
The objective function is represented by the weighted sum approach method with wi
(i = 1 – 3) are a weighting factor taken equal to 1/3. This representation is suggested
to reduce the optimization problem to a mono-objective one, where the current ratio,
transconductance and cut-off frequency can be maximized equally. In Equation 21.9
the parameter X denotes a victor defining the GAA JL MOSFET design parameters.
The PSO is conducted by considering 50 particles in the swarm, 400 maximum
generations, resulting in optimization error for the stopping criterion being infinitesi-
mal. After carrying out PSO computation, Figure 21.6(b) shows the fitness function
versus the generation number for both optimized devices based on SiSn and SiGe
alloys. We can see that PSO has allowed minimizing the objective function, thus
maximizing the device performance criteria (current ratio, gm, and fc). In addition,
quiet stabilization is achieved after 500 generations for both investigated JL tran-
sistors. The optimized design parameters for both investigated GAA JL MOSFET
based on SiSn and SiGe compounds and the associated performance parameters are
recapitulated in Table 21.2. It can be demonstrated that highly improved device per-
formances are achieved thanks to the use of the PSO optimization framework. The
optimized Sn and Ge contents of 42% and 83% are successfully selected through
348 Circuit Design for Modern Applications

TABLE 21.2
Performance comparison between the conventional Si GAA JL MOSFET
device and the optimized ones with SiGe and SiSn binary compounds.
Si GAA JL Optimized SiGe Optimized SiSn GAA
Symbol MOSFET design GAA JL MOSFET JL MOSFET
Design variables: ​ ​ ​
Channel length L (nm) 80 65 70
Oxide thickness tox (nm) 4 3 3.5
Channel radius R (nm) 10 8 9
Channel doping Nch (cm–3) N-type 1 × 1018 N-type 4 × 1018 N-type 2 × 1018
Drain voltage Vds(V) 0.5 0.6 0.6
Gate workfunction Фm (eV) 4.6 4.5 4.45
Ge mole fraction (%) – 0.83 –
Sn mole fraction (%) – – 0.42
Gate oxide material SiO2 SiO2 SiO2
Performance parameters: ​ ​ ​
Transconductance (µS) 7.2 32 49
ION/IOFF ratio (dB) 34.5 145.4 187.5
Cut-off-frequency (GHz) 43 57 92

the proposed PSO method. The optimized transistor based on SiSn exhibits highly
improved performance parameters as compared to that of the SiGe-based one. This
metaheuristic technique has promoted wider possibilities to select the appropriate
device parameters that can contribute to providing the highest RF/analog perfor-
mances as compared to the Si-based device.

21.5 CIRCUIT-LEVEL ANALYSIS
In this section, we show a circuit-level investigation of an inverter circuit build-
ing block designed with the optimized GAA JL MOSFET based on SiSn and SiGe
alloys. The optimized devices with the resulting design parameters provided in Table
21.2 are used. Figure 21.7 depicts the basic circuit configuration, which is an inverter
using a load resistance. The latter is set to the value of 10 kΩ, and the voltage is
taken with a value of 2 V. The circuit is analyzed using TCAD simulation based on
mixed-mode available in Silvaco numerical software [75]. In this context, all simu-
lations take into account room temperature circumstances. Furthermore, physical
models commonly used for nanoscale devices are taken into account. So, the effects
of temperature, transverse field and doping on carrier mobility are included by using
the CVT model established by Lombardi et al. [75]. Parallel electric fields may affect
carrier mobility, hence the FLDMOB model is taken into account. The SRH state-
ment is included to account for the Shockley–Read–Hall recombination model. The
bandgap narrowing effects by activating the BGN parameter should be accounted for
by the use of JL technology requiring a heavily doped semiconductor.
New Approaches for Modeling Nanoscale Junctionless FETs 349

FIGURE 21.8 Output voltage characteristics obtained from inverter-gate circuits based on
the optimized GAA JL MOSFETs with SiGe and SiSn cmpounds compared to that of the
conventional Si-based device.

The voltage characteristics of the analyzed circuits based on the optimized

GAA JL MOSFET devices based on SiSn and SiGe material building blocks are
extracted and compared to the conventional Si-based device in Figure 21.8 using
similar geometry. It can be observed that suitable switching characteristics can be
achieved by considering the optimized devices. The optimized devices show shifted
threshold voltage due to the use of SiSn and SiGe compounds. Moreover, GAA JL
MOSFETs based on SiSn and SiGe materials demonstrate an improved transition
from ON-to-OFF states due to their enhanced transconductance behavior. In addi-
tion, the implementation of the optimized SiSn and SiGe-based JL transistors can
mitigate noise effects as demonstrated by Figure 21.8, where at OFF-state the output
voltage approximately equals to 2 V proving the reduced noise margin effects. These
enhancements can be explained by the reduced parasitic current and enhanced trans-
conductance (gm) associated with the optimized GAA JL MOSFETs. Therefore,
we believe that the present investigation can highlight new directions for the use of
S-binary alloys to design novel optimized GAA JL MOSFETs highly suitable for
future nanoelectronic applications.

21.6 CONCLUSIONS
A new GAA JL MOSFET designs based on SiGe and SnSi binary alloys are pro-
posed in this work. The analytical drain current model of the analyzed GAA JL
MOSFET device is developed to study the analog/RF performances of the device.
The operating mechanism of the proposed SiSn and SiGe GAA JL MOSFET designs
is studied and thoroughly discussed. The influence of the Sn and Ge concentrations
350 Circuit Design for Modern Applications

on the transistor performance is investigated. It is revealed that the use of Si-based

binary alloys can improve the device performance by modulating the transport char-
acteristics of the device, where improved ON-to-OFF current ratio and transconduc-
tance are achieved. PSO optimization framework is then implemented to optimize
SiSn and SiGe GAA JL MOSFETs and boost their performances by selecting appro-
priate Sn and Ge contents and design parameters. It is demonstrated from the opti-
mization results that high-performance GAA JL MOSFET can be designed using the
adopted PSO approach, showing great promise for boosting the device performance
and reducing noise effects. The optimized devices based on SiSn and SiGe binary
compounds are then implemented in a basic circuit configuration of inverter with
load resistance. The voltage output characteristics show the improved commutation
and low noise effects of the optimized devices with appropriate Sn and Ge con-
taining. Therefore, the optimized JL transistor designs using SiSn and SiGe alloys
can provide a new pathway toward achieving high RF/analog performance with low
parasitic effects, which can be highly suitable for FET-based nanoelectronic circuits.

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22 Survey of Machine
Learning-Augmented
TCAD Algorithms for
Modeling GaN HEMTs
Niketa Sharma, Yogendra Gupta, Vinay Kanungo,
Amit Kumar Sharma, and Ashish Sharma

22.1 INTRODUCTION
In recent years, the semiconductor industry has witnessed a remarkable paradigm
shift, driven by the increasing demand for high-performance electronic devices.
Among these, HEMTs have emerged as promising candidates for power amplifiers,
microwave applications, and high-frequency devices [1–5]. However, the complex
physics governing the behavior of these devices poses significant challenges in their
accurate modeling and simulation [6].
Traditionally, TCAD tools have been employed to simulate the performance of
semiconductor devices by solving intricate mathematical models describing their
physical processes. Despite the advancements in TCAD methodologies, accurately
capturing the behavior of GaN HEMTs remains a formidable task due to the inherent
complexities, non-linearities, and material-related challenges associated with these
devices.
To overcome these hurdles, a growing trend in the semiconductor community
involves the integration of ML techniques with TCAD algorithms [7]. This syn-
ergy aims to leverage the predictive power of ML models to enhance the accuracy
and efficiency of device simulations. The incorporation of TCAD and ML not only
addresses the limitations of traditional modeling approaches but also opens new
avenues for optimizing device performance and design.
This chapter presents a comprehensive survey of the state-of-the-art in machine
learning-augmented TCAD algorithms for the modeling of GaN HEMTs. Through
an exhaustive exploration of recent research endeavors, we delve into the diverse
methodologies, applications, and outcomes of integrating ML techniques into TCAD
workflows. By critically evaluating the strengths and limitations of these hybrid
approaches, we aim to provide researchers, practitioners, and industry professionals
with valuable insights into the evolving landscape of semiconductor device model-
ing. In the subsequent sections, we will discuss key ML concepts applied to TCAD,

DOI: 10.1201/9781003483052-22 353

354 Circuit Design for Modern Applications

highlight notable advancements in GaN HEMT modeling, and analyze the impact of
these innovations on the semiconductor industry. As we navigate through the intri-
cacies of this interdisciplinary field, our goal is to illuminate the current trends,
challenges, and future prospects that lie at the intersection of machine learning and
TCAD for AlGaN/GaN HEMTs. Finally in the last section, we will give a brief sum-
mary, and show some prospects in this field.

22.2 BACKGROUND
As technology continues to advance, the abundance of data has become a signifi-
cant resource, and effective data analysis techniques play a crucial role in shaping
emerging technologies. One prominent technique for data analysis and modeling is
machine learning, which Murphy [8] defines as a set of methods capable of automati-
cally detecting patterns in data and using these patterns to predict future data. In the
realm of semiconductor device modeling, Silvaco-ATLAS is employed to simulate
device characteristics [9].
The modeling of semiconductor devices requires a mapping algorithm, facilitat-
ing the estimation of device current based on node voltages and device parameters.
Traditional semiconductor device modeling approaches aim to comprehend the
physical phenomena of the device, typically covering one region of device operation
[10–11]. However, this creates challenges in modeling transitions between regions. In
contrast, black-box modeling techniques provide models for all components, often
expressed as mathematical equations linking terminal voltages and node current [12].
These models capture the electro-physical behavior of the device in relation to char-
acteristics like geometry, biasing, temperature variations, and process variations [13].
Semiconductor device models serve as a crucial link between designers and
manufacturing foundries, allowing simulation of device circuits before fabrication.
Schneider and Galup-Montoro emphasize the importance of an accurate device
model for computer-aided circuit simulation, enabling parametric design space
exploration and analysis prior to fabrication. The accuracy of the device model
enhances productivity and time-to-market.
Figure 22.1 illustrates the classification of semiconductor device models into two
types: those for device design and analysis, and those for circuit simulations (com-
pact models).

FIGURE 22.1 Semiconductor device model classification.

Survey of Machine Learning-Augmented TCAD Algorithms 355

TCAD models, specifically designed for device design and analysis, offer high
accuracy but are hindered by large memory usage and long computation times.
For circuit design and functional verification, faster compact models are required.
Guidelines by Tsividis and Andrews [14] highlight the attributes of good compact
models, emphasizing continuity, physical accuracy, and adherence to semiconductor
device characteristics. To be concise, the following outlines key attributes:

1. Semiconductor models must align with the characteristics inherent in semi-

conductor devices, encompassing factors such as current–voltage (I–V),
transconductance, electron mobility, electric field, electron concentration,
leakage currents, as well as intrinsic and extrinsic capacitances.
2. It is imperative that all models, encompassing charges, currents, and
their derivatives, maintain continuity concerning each terminal voltage.
Commercial circuit simulators frequently employ nonlinear Kirchhoff’s
current law (KCL) and the Newton–Raphson method, relying on lineariza-
tion that demands continuous derivatives for efficient operations.
3. The model’s outcomes should exhibit physical coherence, faithfully repro-
ducing real-world devices. Any results should steer clear of non-physical
phenomena, such as negative transconductance or capacitances, ensuring a
meaningful representation of semiconductor behavior.
Models are expected to be generalizable, considering a wide range of
effects to ensure accuracy across diverse input conditions. They inherently
involve a trade-off between accuracy and simplicity, with complex models
offering greater predictive power but posing challenges in understanding
and analysis.

22.3 CHALLENGES
Explaining the common challenges encountered in semiconductor device modeling,
this discussion utilizes HEMT technology as a representative example. GaN semi-
conductor devices exhibit significant properties in comparison to their silicon (Si)
and silicon carbide (SiC) counterparts, offering the potential to replace widely used
Si power devices. Sensors based on wide-bandgap semiconductors possess several
advantages, including operation at high temperatures, high chemical stability, and
resilience to ionizing radiation. Despite these advantages, technical barriers hinder
their widespread adoption by the biosensor community, thus limiting the commer-
cialization of GaN-based biosensors [4, 15].
The initial step in understanding the biosensing capabilities of various GaN
devices, which differ in structures, designs, and packaging, is crucial. However, the
conventional semiconductor device physics methodology poses practical challenges
for the biosensor community due to the intricate nature of novel GaN device model-
ing. Existing models, owing to their complexity and the time-intensive analytical
procedures involved, are inadequate for validating all applications and cannot serve
as a universal model for all GaN biosensing devices currently in existence [16–19].
356 Circuit Design for Modern Applications

FIGURE 22.2 Standard flow of machine learning.

To address this limitation, machine learning techniques were employed to design

GaN simulation models that accurately replicate the actual devices. Precision in
capturing effects necessitates additional TCAD simulations. As emphasized earlier,
the effectiveness of integrated circuit design and verification heavily relies on the
availability of accurate device models. Scaling of devices to capture higher-order
effects requires complex models capable of accommodating various scaling-induced
effects, underscoring the importance of a thorough understanding of device physics.
This underscores the necessity of physics-based modeling for its superior accuracy
compared to alternative methods.
Similar efforts are essential when modeling new semiconductor devices, given
that the physical foundation of these devices may differ from existing ones. While
some existing intellectual property, such as model source codes and test benches,
may be utilized, the process of making new models accessible to the designer com-
munity remains time-consuming (Figure 22.2).

22.4 BASIC PRINCIPLE OF MACHINE LEARNING ALGORITHMS

The objective of machine learning is to enhance the performance of machines in
tasks without relying on explicit programming. To accomplish this objective, a series
of steps must be followed. Initially, data collection and preparation are essential.
Subsequently, the selection of a training model or algorithm is crucial. Following
that, an evaluation of the model is necessary to facilitate hyperparameter tuning and
enable accurate predictions [20].

• In supervised learning, the algorithm is trained using labeled examples to

develop a model. This model is then applied to address similar problems
with unlabeled data. The most common applications of supervised learning
are found in classification problems.
• Unsupervised learning involves training the algorithm with unlabeled data,
aiming to identify patterns or extract features from the dataset. Clustering
problems are commonly addressed using unsupervised learning algorithms.
• Reinforcement learning revolves around a machine learning algorithm
interacting with a dynamic environment while pursuing goals. In this
approach, the algorithm takes actions without immediate evaluation from a
teacher, with a classic example being the self-driving car.
Survey of Machine Learning-Augmented TCAD Algorithms 357

Prior to delving into the diverse applications of machine learning within the field of
semiconductor devices, it is essential to provide a summary of the various descrip-
tors, algorithms, and databases employed in materials informatics.

22.4.1 Databases
Semiconductor device’s application of machine learning primarily revolves around
supervised learning. The effectiveness of these approaches is predominantly contin-
gent on the quantity and calibers of accessible data, posing a significant hurdle in
material informatics. A notable issue arises with target features requiring expensive
experimental determination, such as breakdown voltage, threshold voltage, C–V, and
I–V characteristics.
For databases and materials informatics to flourish, it is imperative to adopt a
FAIR approach to data [21]. This involves adhering to the four principles: findabil-
ity, accessibility, interoperability, and repurposability [22]. Essentially, individuals
across diverse disciplines should be capable of locating and retrieving data, along
with its associated metadata, in a universally accepted format. This ensures the ver-
satility of the data for various applications.

22.4.2 Features
A crucial element within a machine learning algorithm lies in how the data is effec-
tively represented. In the realm of material science, features must possess the capa-
bility to encompass all pertinent information, enabling the differentiation between
various atomic or crystal environments [23]. The process itself, referred to as feature
extraction or engineering, may range from simple tasks like determining atomic
numbers to more intricate transformations such as expanding radial distribution
functions (RDFs) on a specific basis. Alternatively, it might involve aggregations
based on statistics, such as averaging over features or calculating their maximum
values. The extent of processing required is heavily contingent on the algorithm
employed. In the case of methods like deep learning, feature extraction can be con-
sidered an integral part of the model [24]. The optimal choice for representation
hinges on the target quantity and the diversity of the occurrence space. It is essential
to note that the costs associated with feature extraction and evaluating the target
quantity should never be comparable for completeness.

22.4.3 Data Preparation
Machine learning fundamentally involves statistical learning, typically rooted in sta-
tistical learning theory. As the name suggests, statistical learning acquires statistical
insights from extensive data sets. Specifically, it operates on the assumption that
an underlying, unidentified statistical distribution exists for all data, with each data
point independently generated from this distribution. This assumption is commonly
referred to as independent identically distributed (IID). Given this premise, the pri-
mary objective of ML is to uncover the concealed statistical distribution, aiming to
358 Circuit Design for Modern Applications

identify a distribution that closely approximates the hidden one. The resulting ML
model serves as a representation of the discovered statistical distribution.
Given these principles, the significance of data preparation cannot be overstated.
The data must adhere to three crucial conditions: (1) suitability for training the target
model, necessitating transformations if the raw data is unsuitable; (2) adequacy for
revealing the underlying rules and facilitating effective model training; and (3) a
faithful representation of the hidden statistical distribution.
In the realm of material science, several high-quality databases, including
Material Project [25], C2DB [26], AFlow [27–28], GDB-13 [29], QM9 [30], etc.,
have already been utilized in ML studies. Simultaneously, researchers are actively
involved in constructing additional databases through high-throughput computation
and ML [31–34] methodologies. An intriguing approach involves extracting data
from numerous online papers using text mining and natural language processing
technologies [35]. In cases where no suitable ML-ready database exists for material
science, researchers must undertake the task of generating their own data.
TCAD data generated for various parameters is employed in the application of
machine learning algorithms for prediction and modeling purposes. The process
flow and implementation strategy are illustrated in Figure 22.3. Data preprocessing,
as outlined in [36], involves importing necessary libraries and cleaning the data. The
data is then standardized using the z-score [37], ensuring a mean value of 0 and a
standard deviation of 1, as depicted in Equation (22.1).

z
 x  µ (22.1)

Following the definition of input features and output labels, the Scikit-learn library
[38] is utilized to implement machine learning algorithms. Subsequently, the panda’s
data frame [39] is employed to split the dataset into training and test sets. Eighty
percent of the data is allocated for training and model building, while the remaining

FIGURE 22.3 Process flow diagram of development, prediction, and validation of a

machine learning model.
Survey of Machine Learning-Augmented TCAD Algorithms 359

20% is used for evaluating the test set. The models are then assessed based on the
coefficient of determination.

22.5 MACHINE LEARNING MODELING OF GAN HEMT DEVICES

The utilization of commercial TCAD tools in simulations not only demands users
with extensive expertise in physics and simulations but also suffers from draw-
backs in terms of time efficiency and convergence. Simulations based on time dif-
ference (TD), or Monte Carlo (MC) methods are particularly time-consuming and
exhibit poor convergence. Additionally, the complex coupling effects arising from
the stacked structure and 2D distribution of charges, along with the consideration
of background carriers, traps, and interface states in AlGaN/GaN HEMT, further
magnify the limitations of the conventional TCAD method [40, 41]. Due to these
challenges, there is an amplified deficiency in the conventional TCAD method.
Furthermore, the absence of presented physical analytical models capable of effec-
tively characterizing the correlation between structural parameters and off-state
performance underscores the difficulty in accurately characterizing off-state perfor-
mance. Nevertheless, the recent advancements in machine learning (ML) methods
offer a promising avenue for accurately forecasting the performance of these devices,
eliminating the need for reliance on physical-based models [42–44]. In the pres-
ent era, machine learning (ML) techniques are utilized for the anticipation of key
parameters, such as breakdown voltage (BV) and on-resistance (Ron) [45]. However,
the exploration into the intricate relationship between the structural parameters of an
AlGaN/GaN HEMT and the off-state I–V curve, as well as breakdown performance,
remains inconclusive. A thorough examination is presented regarding the application
of machine learning for modeling and designing gallium nitride high electron mobil-
ity transistors (GaN HEMTs).

22.5.1 Thermal Modeling of the GaN HEMT Device

This work presents a study on nonlinear data modeling for the output characteristics
of a GaN-based HEMT device across a broad temperature range. The study utilizes
the machine learning regression technique, specifically the decision tree (DT) [46].
The algorithm mentioned is widely employed for “inductive inference”, aiming to
approximate the target function. In this method, each node represents a test on a
variable, with branches indicating test outcomes, and the classification variables’
costs positioned at the tree’s leaves. Utilizing training examples, this algorithm con-
structs a classification model that delineates the relationship between “classes” and
“attributes”. Once trained, the model can effectively classify new, unfamiliar cases.
Decision tree models offer resilience to noisy data and are adept at learning disjunc-
tive expressions.
Simulation utilized a singular gate finger device with a unit gate width of 100 μm,
as illustrated in Figure 22.4. The epitaxial configuration consisted of a 25 nm Al0.25
Ga0.75N layer, a 2.7 μm GaN buffer, and an AlN layer atop a sapphire substrate.
360 Circuit Design for Modern Applications

FIGURE 22.4 Schematic diagram of AlGaN/GaN HEMT structure.

The device’s specifications included a gate length (LG) of 1 μm, a source-to-gate

length (LSG) of 1 μm, and a gate-to-drain length (LGD) of 2 μm. To train the machine
learning models, a dataset is employed, incorporating variations in gate-to-source
voltage (Vgs) and temperature spanning from 300 to 600 K. Temperatures exceeding
300 K are utilized to evaluate the model’s ability to extrapolate beyond the input
range. The decision tree algorithm goes through a process known as “hyperparam-
eters optimization”, which refines three key parameters: MinParentSize, set to 1,
MaxNumSplits, set to 2000, and NumVariablesToSample, set to 3.
The output curves illustrate the characteristics of the GaN HEMT device. These
curves are depicted in Figure 22.5 and cover a temperature range of 300 to 600 K,
with an applied voltage between the gate and source set at +2 V. The data extracted
from the decision tree model is compared with simulated outcomes. This process
yields a mean-squared error of 5.32 × 10 –8. Further exploration includes studying the
temperature dependence of the maximum Ids and gm of various HEMTs. Figure 22.6
displays the transconductance (gm) versus gate–source voltage (Vgs) for drain bias Vds
= +10 V of the simulated AlGaN/GaN HEMT.
Observations reveal a 52% reduction in Ids with a temperature increase from 300
to 600 K.
The gate bias, ranging from −6 to 2 V for each drain bias, attains peak current
density at Vgs = +2 V, Vds = +10 V @ 300 K, reaching a current density of 0.84 A/
mm. These estimations reveal a mean-squared error of 2.17 × 10 –6. The attributes
predicted using the decision tree algorithm closely align with those simulated.

FIGURE 22.5 Comparison of Ids at distinct temperatures (300–600 K) at Vgs = +2 V [46].

Survey of Machine Learning-Augmented TCAD Algorithms 361

FIGURE 22.6 Comparison of transconductance at different Temp (300–600 K) at Vds =

+5V [46].

22.5.2 Artificial Neural Network-Based Assessment of Off-

State Performance in an AlGaN/GaN Device
This work presents an in-depth exploration of the application of machine learning
in the modeling and design of power devices, encompassing lateral diode, LDMOS,
IGBT, and GaN HEMT [47]. In contrast to TCAD simulation, the ML-based approach
demonstrates significant potential and efficiency in simulating performance curves
without encountering convergence issues.
Artificial neural networks (ANNs) are utilized to measure the off-state current
in gallium nitride high electron mobility transistor semiconductor devices due to
their capability to effectively capture complex, nonlinear relationships within datas-
ets. GaN HEMT devices often exhibit intricate behavior, especially in off-state con-
ditions, which can be challenging to model accurately using traditional analytical
methods. ANNs excel in handling such complexities by learning from data patterns
and relationships, making them suitable for tasks like off-state current measurement
in GaN HEMT devices. By training an ANN with data representing various off-
state conditions and corresponding current measurements, the network can learn
the underlying patterns and correlations. Once trained, the ANN can accurately pre-
dict the off-state current for new conditions, providing valuable insights into device
behavior without relying solely on complex analytical models or empirical testing.
This approach offers a more efficient and reliable means of assessing off-state cur-
rent in GaN HEMT devices, contributing to their characterization and optimization
for various applications.
There are generally two types of ML frameworks that can be employed for per-
formance curve simulation.

Single-Stage Method: Illustrated in Figure 22.7, this approach takes the

device’s structural and bias parameters as input.
Table 22.1 provides essential material characteristics of GaN for the sim-
ulation. In contrast to conventional lateral power devices based on Si, the
off-state breakdown performance of GaN-based power devices is impacted
by various 2D effects concurrently. This collective influence of 2D cou-
pling is not solely dictated by the structural parameters of the devices but
362 Circuit Design for Modern Applications

FIGURE 22.7 Flow of modeling of electrical performance using machine learning (ML)
through an artificial neural network (ANN) based approach.

TABLE 22.1
The Basic Material Properties of GaN
Property GaN
Bandage (eV) 3.4
Critical electric field (MV/cm) 3.3
Thermal conductivity (W/(cm·K)) 1.3
Electron carrier mobility (cm2/(V·s)) 2000
Electron saturation velocity (107 cm/s) 2.5

is also influenced by unconventional or unclear 2D physical mechanisms.

Consequently, this gives rise to a distinct off-state characteristic in the
AlGaN/GaN HEMT.
The ML-based model then produces the corresponding electric perfor-
mance curve, essentially functioning as a TCAD simulator. The results in
Figure 22.8 depict the off-state I–V curves of the GaN HEMT [47], accu-
rately simulated using this method. However, a drawback is the time-con-
suming nature of the training and simulation processes, particularly when
dealing with massive amounts of data for I–V curves.
Two-Stage Method: The two-stage approach employs a compact model to
succinctly describe I–V curves using a minimal set of parameters. In this

FIGURE 22.8 Off-state curve of GaN HEMT based on single-stage method [47].
Survey of Machine Learning-Augmented TCAD Algorithms 363

FIGURE 22.9 A method combining physical-model and ANN-based modeling flow to cre-
ate electrical performance curves using ML.

method [48], illustrated in Figure 22.9, structural parameters serve as inputs

during ML-based training and simulation, while compact model param-
eters function as outputs.
Essentially, this approach combines automated tools for extracting com-
pact model parameters. Figures 22.10(a) and (b) depict ML-based simula-
tions of GaN HEMT and IGBT using the two-stage technique, respectively.
GaN HEMT utilizes ASM, while IGBT employs HENFER compact
models. Notably, the ANN-based method within the two-stage approach
achieves high accuracy in simulating on-state curves for various types of
power devices.
Despite the traditionally laborious and time-intensive nature of conven-
tional approaches, there is evidence suggesting that ML-based modeling
and design methods are increasingly recognized as efficient alternatives.
Nevertheless, there remains room for improvement in the broader adoption
of these models, focusing on areas such as data optimization, model visu-
alization, reusability, and the development of more finely tuned artificial
structures. The successful integration of ML applications in semiconductor
power devices serves as a promising indicator for the expanded utilization
of ML in various modeling and design domains.

22.5.3 Large-Signal ANN Modeling

In this study, authors [49] introduce a novel approach to optimize the modeling
flow for millimeter-wave GaN HEMTs using artificial neural networks (ANNs).

FIGURE 22.10 On-state curve of (a) GaN HEMT and (b) IGBT based on two-stage meth-
ods [48].
364 Circuit Design for Modern Applications

Our methodology involves the creation of an ANN model that specifically cap-
tures the characteristics of a current source while mitigating the influence of low
noise. Parasitic elements are identified from the S-parameters at various bias points
utilizing small-signal equivalent circuits. To minimize noise effects, these para-
sitic elements are then represented by nonlinear functions. Additionally, we derive
resistances and inductances from the discrete data points located near the load line,
thereby augmenting the precision of our model.
The artificial neural network model effectively analyzes the I–V characteristics
influenced by current collapse. It also considers short-channel effects. Additionally,
it examines the S-parameters within the millimeter-wave frequency range. The
depicted large-signal model for millimeter-wave GaN HEMTs can be observed in
Figure 22.11 [49]. Capacitances (Cgs, Cgd, Cds) were represented using nonlinear func-
tions, while only the current sources at the core were simulated using an ANN.
These models necessitate the computation of built-in potentials Vgsi, Vgdi, and Vdsi.
Figure 22.12 depicts the I–V waveforms obtained from measurements and simu-
lations conducted using both artificial neural networks and conventional compact
models.
The ANN model accurately captures the measured Ids waveforms, showcasing its
robust modeling capabilities. In contrast, the conventional compact model exhibits

FIGURE 22.11 Large-signal ANN model for millimeter-wave GaN HEMTs.

FIGURE 22.12 I–V characteristics of (a) ANN model with (b) Compact model [49].
Survey of Machine Learning-Augmented TCAD Algorithms 365

significant discrepancies from the measured data. These findings underscore the
efficacy of ANN in modeling complex systems. The artificial neural network has
effectively replicated I-V waveforms with remarkable precision, surpassing the capa-
bilities of traditional compact models.

22.5.4 ML-based Statistical Approach for Threshold Voltage

Detection in Recessed Gate AlGaN/GaN MIS-HEMTs
Among the different neural networks used to implement ML, an artificial neural
network-based approach provides a good prediction owing to its learning and error
correction capability, making it particularly adept at modeling various processes
affecting output electrical characteristics, such as VTH, in metal-insulator-semicon-
ductor (MIS)-HEMTs. Despite its predictive power, comprehending the individual
impacts of different processes on VTH remains challenging due to ANN acting as a
black box and lacking transparency.
The Tikhonov regularization method offers distinct advantages for measuring
threshold voltages in GaN HEMT semiconductor devices. By incorporating regu-
larization techniques, Tikhonov regularization effectively mitigates the effects of
noise and measurement errors inherent in experimental data, enhancing the accuracy
and reliability of threshold voltage determination. This method leverages a balance
between fitting the data and controlling model complexity, thus reducing the risk
of overfitting and providing robust estimates of threshold voltages. Additionally,
Tikhonov regularization can accommodate limited and noisy datasets common in
semiconductor device characterization, making it particularly suitable for accurately
assessing threshold voltages in GaN HEMTs.
This study utilizes a machine learning-driven Tikhonov regularization method
to evaluate the impact of the process on VTH in recessed gate MIS-HEMTs. It also
involves devising a straightforward analytical formula that integrates multiple input
features, including recessed depth, dielectric, cleaning, and plasma treatment, facili-
tating the optimization and prediction of device characteristics [50]. Figure 22.13
illustrates the layout of the recessed gate AlGaN/GaN MIS-HEMTs. The processing
steps involve manufacturing Si (111) wafers through an Au-free CMOS-compatible
process. This process begins with an AlN nucleation layer, followed by a GaN buffer,
a 15-nm Al0.25 Ga0.75N barrier, and a 3-nm GaN cap. The aim is to mitigate 2DEG-
induced adverse effects on system integration and safety.

FIGURE 22.13 Schematic of recessed gate MIS-HEMTs.

366 Circuit Design for Modern Applications

FIGURE 22.14 Flowchart of a ML-based TR method to model the VTH [50].

The schematic flow shown in Figure 22.14 illustrates the processing splits
employed as input features in the machine learning model to correlate with the out-
put feature, VTH. However, traditional linear regression-based ML techniques present
difficulties in assessing the individual impacts of input parameters due to potential
overfitting. In contrast, Tikhonov regularization (TR) methodology provides advan-
tages by integrating a penalty term (λω2) in the cost function (yi–yi,prediction) [51, 52] to
regulate insignificant input features. In this research, the TR approach was executed
using the Scikit-learn library [53].
The modeling outcomes of ML-based TR and ANN approaches are compared
in (Figure 22.15). The ML-based TR method demonstrates comparable results to
ANN, with ML-based TR offering the advantage of deriving analytical equations to
understand process impacts, which is not achievable with ANN.

FIGURE 22.15 Comparison of results from testing data using (a) and (c) TR approach and
(b) and (d) ANN, where the ANN utilized three hidden layers (32, 16, and 8 neurons, respec-
tively) with implementation through TensorFlow and Keras packages [50].
Survey of Machine Learning-Augmented TCAD Algorithms 367

In summary, this work presents the pioneering use of a ML-based TR method-

ology to comprehensively develop and analyze the influence of process dependen-
cies on VTH in recessed gate GaN-based MIS-HEMTs. It showcases the successful
generation of a multivariable analytical equation from the ML-based TR approach,
demonstrating good agreement between analytical and measured VTH results across
19 distinct processing splits, and offering insights into process optimization through
coefficient analysis, indicating a promising avenue for enhancing performance
in GaN-based technologies. The modeling outcomes of ML-based TR and ANN
approaches are compared in Figure 22.15.

22.6 SUMMARY AND PROSPECTS

The chapter provides an overview of machine learning-augmented TCAD algo-
rithms for modeling GaN HEMTs. It begins by explaining the importance of accu-
rate device modeling in the design and optimization of GaN HEMTs for various
applications such as biosensing, power electronics and wireless communication.
Traditional TCAD simulations face challenges in accurately capturing complex
physical phenomena and device behavior, especially in GaN-based devices due to
their unique material properties.
To address these challenges, machine learning techniques have been integrated
into TCAD workflows to improve model accuracy and computational efficiency. The
chapter discusses various machine learning approaches, including ANNs, support
vector machines, and decision trees, and their applications in different aspects of
GaN HEMT modeling such as parameter extraction, model calibration, and device
optimization. Case studies and examples are provided to illustrate the effectiveness
of machine learning-augmented TCAD algorithms in improving model accuracy
and reducing simulation time.
The chapter concludes by highlighting future research directions and potential
advancements in machine learning-augmented TCAD algorithms for GaN HEMT
modeling. One potential area for future exploration is the development of hybrid
modeling approaches that combine physics-based TCAD simulations with machine
learning techniques to leverage the strengths of both methodologies. Additionally,
there is a need for further investigation into the integration of uncertainty quantifica-
tion techniques into machine learning-augmented TCAD workflows to assess model
reliability and robustness.
Furthermore, the scalability of machine learning-augmented TCAD algorithms
for large-scale device simulations and optimization tasks remains an important
research challenge. Future efforts should focus on developing scalable machine
learning techniques and parallel computing strategies to enable efficient modeling of
complex GaN HEMT structures and circuits. Moreover, the application of machine
learning-augmented TCAD algorithms could be extended to other semiconductor
materials and device technologies beyond GaN HEMTs, opening up new opportu-
nities for innovation in device design and optimization. Overall, the integration of
machine learning with TCAD holds great promise for advancing the state-of-the-art
in semiconductor device modeling and design.
368 Circuit Design for Modern Applications

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23 Implementation of
Modified Dual-Coupled
Linear Congruential
Generator with
Parallel Prefix Adder
Hima Bindu Katikala and Gajula Ramana Murthy

23.1 INTRODUCTION
In a time when digital communication is widely used, data transmission security has
become crucial. Data secrecy and integrity are frequently dependent on how reliable
pseudo-random bit-generating techniques are. These pieces serve as the foundation
for secure communication protocols, encryption techniques, and other applications
where randomization is necessary for security.
A crucial factor among the several approaches currently in use for producing
pseudo-random bits is the effectiveness of the underlying arithmetic operations. In
particular, the silicon area, power consumption, and performance of these generators
are influenced by the design and optimization of the adders [16]. The need for more
compact, dependable, and effective pseudo-random bit generators is only going to
increase as technology develops.
In this chapter, a Parallel Prefix Adder and a modified dual-coupled linear con-
gruential generator are implemented. The goal is to improve pseudo-random bit-
generating efficiency by taking into account important factors like area, delay, and
power consumption. The goal of the suggested model is to maximize memory use
while preserving or enhancing the functionality of current topologies. Different
methods of VLSI architecture design and performance improvements have been
studied in the literature [18–20].
The proposed adder’s performance is thoroughly analyzed in this chapter through
extensive parametric simulations performed using the Xilinx tool. The outcomes
show notable gains, presenting a strong argument for the use of this novel strategy in
a variety of applications requiring the creation of pseudo-random bits. In addition to
making a significant contribution to the field of secure data transmission, this work

DOI: 10.1201/9781003483052-23 371

372 Circuit Design for Modern Applications

FIGURE 23.1 Basic architecture of the IoT model.

creates new opportunities for study and advancement in the areas of digital circuit
design and optimization.
Security of data in many applications has become increasingly complicated,
and the protection of personal information on the internet is becoming increasingly
important. Huge volumes of data being sent across the internet to millions of com-
ponents could cause privacy concerns. Figure 23.1 illustrates the basic architecture
Internet-of-Things (IoT) model comprising a device/sensor, cloud server and end-
user [1–2]. The user may collect data in real time at numerous collection frequencies
thanks to the device layer. It is made up of a collection of wireless sensor devices
connected to the internet, data-collecting circuits, and communication protocols to
send data to nearby or remote storage locations for additional processing. The data
gathered from the sensors is stored in the cloud layer where it is processed further,
removing noise, features extracted, and massaged data. There are several ways to
represent the end-user layer, which is made up of the recipient user. Security and
privacy issues are present in smart gadgets, which is cause for concern. Added sub-
layers or subsystems inside the confines of these three layers to guarantee the deci-
sion-supporting system’s resilience
The IoT has enormous promise across a range of industries, but its whole com-
munication infrastructure has security flaws and puts end users at risk of losing their
privacy. The technologies employed in the IoT for information relay from one appli-
cation to another include security flaws that are the primary cause of certain secu-
rity problems impacting the entire evolving IoT system. The critical component for
security in IoT systems is the pseudo-random bit generator (PRBG). The major goal
of this research is to improve PRBG’s performance using the dual-coupled LCG
method and to make the PRBG more efficient. The constituent of IoT-based devices
that manage user personal information is the pseudo-random bit generator. So the
internet is secure for apps using it and data protection for IoT-based devices has
become more complex these days. Due to the initial delay of the clock, occupied
area, randomness, performance, and other constraints, the largest bit size of a PRBG
VLSI model is difficult. It is challenging to achieve a high bit-rate, cryptographi-
cally safe, significant key size PRBG because of hardware constraints, which need
an effective VLSI design in regards to area, delay, and power. “PRBG is random if
it passes 15 census test cases of the National Institute of Standards and Technology
(NIST)” [3]. Pseudo-random bits can be produced using various techniques. linear
Implementation of Modified Dual-Coupled Linear Congruential Generator 373

feedback shift register, coupled linear congruential generator (CLCG), and dual-cou-
pled LCG, Blum–Blum–Shub (BBS) generator, linear congruential generator (LCG)
are various linear congruential generators [4].
The most straightforward method is the linear feedback shift register (LFSR). It
occupies less space and is less complicated in terms of hardware. It does not pass
randomization tests because of its linear structure. The pseudo-random bits are gen-
erated using LFSRs, which are N-bit counters. In an N-bit LFSR has an output of
(2n–1) sequences [7].
One of the proven encrypted pseudo-random generators is the BBS generator,
which is based on the quadratic exponent and was introduced by Lenore Blum,
Manuel Blum, and Michael Shub. The enormous unique primes P and Q, which
determine both the maximum duration period and the linear difficulty of generating
patterns, are crucial to the security of the BBS generator. With π (= 2pq) denoting
the maximum duration period, the linear complexity of the BBS generator is ≥ π/2.
This indicates that the prediction’s difficulty is linearly related to the longest pos-
sible sequence length. A modulo n (= pq) and a squaring operator must be carried
out for each bit to be generated, which complicates the physical design of the BBS
generator. “A specific prime number is measured by the hardware implementation
and performs modulo of the largest prime numbers” [8–11].
For generating pseudo-random bit sequences an algorithm is proposed by Blum
and Shub. Let us consider the bit sequence (b1, b2, … , bl ) with a length of l:

1. Consider the two primes P and Q that contain two random bits, equivalent
to three modulo 4

2. P   2 p1  1   4 p2  3

and Q   2q1  1   4q2  3

where p1, p2, q1, q2 are prime numbers
3. Proceed N as P*Q
4. Choose a seed (random number) that ensures gcd (s, N) = 1 in the interval
{1, N−1}.
5. Compute x0 ←s 2 mod N.
6. For i from 1 to l do the following:
xi ←xi2–1mod N.
bi ← xi mod 2 (least significant bit of xi)
Bi ← xi mod 2log n (extracting the [log n] bit from xi).
7. The output binary sequence is b1, b2, …, bl.
and the binary block sequence is B1, B2, … , Bl each having log (n) bits.
Where n = [1+ log2 N].

Montgomery generator is the most effective modular architecture as in Figure 23.2

used in BBS for multiplication purposes. Nevertheless, it has one drawback: when
the modulus’s bit size increases, latency also rises.
374 Circuit Design for Modern Applications

FIGURE 23.2 Montgomery multiplication BBS generator.

A well-liked and often employed technique for generating random numbers is the
linear congruential generator.

X n 1   aX n  c  mod m

Where parameters are defined as m – modulus, a – multiplier with a range of {2,3,

…, m – 1}, c – increments are to be chosen wisely to avoid the bit repetition (choosing
c = 0). LCG block utilizes operators like multiplier, adder, comparator and subtrac-
tor as in Figure 23.3. To simplify the execution the subtractor and comparator are
removed using a technique known as word length reduction. However the LCG total
period can never be greater than modulus m, it can be improved.
A comparator and parallel combination of two LCGs make up a coupled linear
Congruential generator [13]. CLCG has a higher level of security when compared to
one LCG. Sequences have a periodic form, according to the CLCG discrete Fourier
transform test it contains two inequality comparisons [14].
Dual-CLCG initially creates pseudo-random bits that have 2n + 5 clocks of clock
latency, and two clocks after generating output Dual-CLCG needs a (2n – 1) num-
ber of flip flops to create patterns of n-bit. However, the statistical randomness tests
were generated for Dual-CLCG given failed results, and the maximum sequence
length was not reached [14]. There are numerous different types of adder topologies
in VLSI technology. Fundamental topologies of adders include ripple carry adders,
carry-increment adders, carry-skip adders, and parallel prefix adders. Parallel prefix
adders will be utilized in place of the three-operand modulo carry-save adder.

FIGURE 23.3 LCG block diagram.

Implementation of Modified Dual-Coupled Linear Congruential Generator 375

FIGURE 23.4 Straight forward Dual-CLCG.

23.2 DUAL-CLCG RANDOM GENERATOR

When compared to prior techniques, the convention method generates more effec-
tive pseudo-random bits. As shown in Figure 23.4, the PRBG architecture consists
of two comparators which are of n-bit, dual-coupled LCGs, and XOR gate. In com-
parison to the conventional approach [5], the architecture of the novel PRBG method
is based on straightforward LCG.
The mechanism for generating pseudo-random numbers or bits is the LCG. An
LCG is designed using a three-operand modulo, 2N carry-save-adder, N-bit register,
N-bit 2*1 multiplexer, and logical shifter, as given in Figure 23.5. The footprint of
LCG is smaller, whereas the hardware is simpler. Due to its linearity, it does not pass
randomization tests, as it is easier to predict the next sequence after some time.
Processed Dual-CLCG random bit generator algorithmic Equation 23.1 is as fol-
lows [5],

“xi  1  a1* xi  b1mod 2n

yi  1  a 2* yi  b2mod 2n

pi  1  a3* pi  b3mod 2n

qi  1  a 4* qi  b4mod 2n” (23.1)

FIGURE 23.5 Algorithmic flowchart of LCG.

376 Circuit Design for Modern Applications

The parameter value is rewritten as a  2r  1, where the value of r is in between 2n

(1 < r < 2n). The modified LCG equation is given in Equation 23.2,

 
xi  1  a1* xi  1 mod 2n   2r1  1 xi  1 mod 2n

 
  2r1* xi  xi  b1 mod 2n

(23.2)

The XOR gate is employed to ensure that the outcome of the pseudo-random bit
generator is as efficient as possible. The XOR gate’s output is as follows in Equation
23.3:

“Zi   Bi  Ci  mod 2  Bi ^Ci

Bi  1, if xi  1  yi  1

= 0, else

and Ci  1, if pi  1  qi  1

=0 (23.3)

A typical addition operation of carry-save adder will be performed by using a full

adder and its execution will be done in two stages as in Figure 23.6. A series of full
adders is constructed in the first phase, which executes an addition operation on
every bit that generates a sum and also carries bits. The final stage which helps to
determine the end sum is the ripple carry adder.
The area consumed and critical path for the series full adder is given in
Equation 23.4,

“ Area, A3CSA   2n  1 AFA   2n  1  2 Ax  3 AG ”

Critical path, T3CSA  nTFA  3Tx  2  n  1 TG (23.4)

FIGURE 23.6 The block diagram of a series full adder.

Implementation of Modified Dual-Coupled Linear Congruential Generator 377

FIGURE 23.7 Gate-level diagram of a 2-bit comparator.

Comparison of two LCG outputs is done using magnitude comparators. The block
diagram consists of a magnitude comparator constructed employing logic gates. The
magnitude comparator executes two operations on two inputs: less than or equal to
and greater than. The construction of a two-input gate-level comparator is illustrated
in Figure 23.7.

23.3 PARALLEL PREFIX ADDER STRUCTURE

Parallel prefix architectures as depicted in Figure 23.8 are used as high-performance
adders since delays & width are directly proportional [12].
PPA usually includes three stages

• • Pre-computation
• • Prefix stage
• • Final computation

23.3.1 Pre-Computation
Equations 23.5 and 23.6 are used to calculate, propagate and generate the supplied
inputs during the pre-computation stage.

Pi  Ai  Bi (23.5)

Gi = Ai.Bi (23.6)

FIGURE 23.8 Parallel prefix structure with a carry-save notation.

378 Circuit Design for Modern Applications

23.3.2 Prefix Stage
The group generates/propagates signals that are calculated for each bit in the prefix
stage using the provided formulas. Equation 23.7 ordered pair is produced by the
black cell (BC), whereas the left signal is produced by the gray cell (GC) [12].

“ gL, PL  0  gR, pR    gL  pLgR  pLpR  (23.7)

Gi : k  Gi : j  Pi : j.G j 1:k (23.8)

Pi : k  Pi : j.Pj 1:k ” (23.9)

Equations 23.8 and 23.9 [13] can be written more practically utilizing the Brent and
Kung-denoted by symbol “o”. It serves exactly the similar purpose as a black cell.
Gi : k : Pi : k   Gi : j : Pi : j  o  G j 1:k : Pj 1:k  (23.20)
The rules for creating prefix structures will be developed with the aid of the “o”
operation as in Equation 23.10.

23.3.3 Final Computation
The result of the final calculation is the sum and carry-out as in Equations 23.11 and
23.12

Si  Pi . Gi 1:1 (23.11)

Cout  Gn:1 (23.12)

Here, “–1” represents the carry-input position. Different groups of generate/propa-

gate signals may be used to achieve the same correct carries. Different prefix archi-
tectures can be developed based on various methods of grouping the generated and
propagated signals. The definitions of the cells BC and GC utilized in prefix struc-
tures are shown in Figure 23.9.

23.4 HAN CARLSON ADDER

This section explains how to implement the Han Carlson adder (HCA) topology in
place of a three-operand modulo carry-save adder. The same conventional adder is
replaced with the Han Carlson adder to examine the performance of the existing
architecture. In place of three input additional circuits, a two two-input adder circuit
is required for the design and generation of pseudo-random bits. The Brent Kung
Adder’s complexity is lowered by the HCA, a parallel prefix tree adder [6]. As seen
in Figure 23.10, this adder features a hybrid design that combines phases from the
Implementation of Modified Dual-Coupled Linear Congruential Generator 379

FIGURE 23.9 Black and gray cell logic definitions.

FIGURE 23.10 Han Carlson adder.

Brent Kung Adder and the Kogge Stone Adder. Carry-merge operations are only
applicable on even bits in this adder. The prefix tree is used to transmit the P and G
signals for odd bits, which are then merged once more with the signals for even bits
at the very end to provide precise carry bits. By not adding extra steps to its carry-
merge path, the complexity and overall expense of designing an HCA are decreased.

23.5 SIMULATION RESULTS
Figure 23.11 displays the simulation outcomes of a modified dual-coupled LCG used
as a PRBG of 8 bits.

FIGURE 23.11 8-bit modified PRBG using a Han Carlson adder.

380 Circuit Design for Modern Applications

TABLE 23.1
Comparıson Table Usıng Modıfıed Dual-CLCG for Dıfferent Types of Adders
in PRBG
Total
Area Memory
(No of Usage
Sno Adder Type Delay (ns) Frequency (MHz) LUTs) (kilobytes)
1 Ripple carry 3.822 261.643 99 601,672
adder
2 Carry-save 3.427 330.036 89 601,360
adder
3 Han Carlson Adder 3.090 286.532 69 601,424

The comparative analysis of different adder types [15] in terms of delay, frequency,
area, and total memory are discussed below. The overall design output values are
given. The design’s area, memory, and frequency are calculated by synthesizing the
code. Table 23.1 lists the practical results of the number of LUTs, memory, and delay.
Han Carlson adder in a dual-coupled generator occupies minimum area (LUTs) and
delay rather than the three-operand modulo ripple carry-adder as shown in Figure
23.12. Apart from this, the proposed adder can be used to improve the performance
of the memory units [17]. As discussed in the literature [21, 22], advanced transistors
[23, 24] will further improve the performance of the adder.
Both static and dynamic power are calculated by using the Vivado tool. The
amount of power used when a device or circuit is not in use is calculated as static
power. The consumption of power by a device that has inputs that are active is
referred to as dynamic power. Table 23.2 lists the practical outcomes of power.

FIGURE 23.12 Delay and area (LUTs) of different types of adders.

Implementation of Modified Dual-Coupled Linear Congruential Generator 381

TABLE 23.2
Power Analysis
Dynamic power Static power Total power
S. No. Adder type (µW) (µW) (µW)
1 Ripple carry adder 3.151 0.200 3.351
2 Carry-skip adder 2.941 0.190 3.131
3 Han Carlson 2.596 0.176 2.772

23.6 CONCLUSION
Significant advantages have been demonstrated in the generation of pseudo-random
bits with reduced power consumption and decreased area occupancy through the
implementation of the Han Carlson adder in place of conventional adders, including
the dual-CLGA, carry-save adder, and ripple carry-adder. The design has demon-
strated enhancements in power efficiency, memory, area, and speed by employing
the Xilinx ISE 14.7 utility for parameter calculation. These benefits are further vali-
dated through comparative simulations with Verilog-HDL prototypes and Artix-7
simulators. The Han Carlson adder is a promising candidate for cryptographic
applications that require secure data processing with minimal resource utilization
due to its superior performance in minimizing power and area. This novel method
improves the efficacy and effectiveness of cryptographic systems, thereby facilitat-
ing the development of more sophisticated and secure data-handling technologies.

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Index
2-bit comparator, 377 Carbon-doped GaN buffer, 307
2D and 3D structures, 168, 169 Cascoded, 187, 188
2DEG, 284, 285, 286, 287, 292, 294 CAVET, 287, 293, 294, 295, 296, 297, 298
Channel layer, 285, 291
Accurate, 137, 138, 139, 146, 147 Circuit design, 170
AKI (acute kidney injury), 139, 146 Circuit simulator, 241, 242, 255, 256, 258, 262
Al2O3, 197 CMOS, 97, 98, 122, 123, 125, 126, 127
AlGaAs barrier layer, 302 CMOS chips technology, 241
AlGaN back-barrier, 311 CMOS inverter, 1, 7–8, 10–13, 15
AlGaN/GaN HEMT, 284, 286, 287, 288, 290, CMOS technology, 75, 87, 186, 187, 190, 275,
291, 292, 293, 294, 298, 321 278, 281, 301, 335
AlGaN/GaN, 2, 7, 8, 10, 13, 16, 17, 18 CNTFET, 48, 49, 150, 151, 153, 154, 215, 216,
AlInGaN back-barrier, 312 217, 220, 221, 223, 225, 226, 227
AlN spacer layer, 306 Colpitts oscillator, 242, 257, 258, 259, 261,
Aluminum oxide, 192 262, 264
Amplifier, 120, 121, 123, 124, 131 Column decoder, 222, 223, 224
Analog circuit, 241, 262 Common amplifier classes, (322)
ARDUINO IDE, 145 Common-source architecture, (324)
Area, 92, 93, 94, 96, 97, 98, 99, 100, 101 Compact model, 241, 242, 253, 256, 262, 263
Artificial neural network, 9, 11, 12, 18 Compact modeling, 342
AVDD (analog voltage digital domain), 141, Comparative analysis chart, 100, 101
142, 143 Comparison, 190, 343, 348
Compensation, 273, 274, 277
Back-barrier, 310, 311, 312, 313 Complementary metal-oxide-semiconductor, 37,
Band to band tunneling, 202, 207 38, 39, 40, 41, 43, 45, 46, 47
Bandgap, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, Compound, 236, 237
235, 237, 283, 284, 285, 286, 318 Compound semiconductors, 282, 284
Bandwidth, 125, 126, 127, 129–133 Computer architecture, 87
Barrier layer, 285, 291, 294 Conduction losses, (324)
Battery-powered devices, (322) Constant field scaling or full scaling, 203
BBS, 373, 374 Constant mobility, 254, 255
BCI, 66 Constant voltage scaling, 203
Biasing, (324) Contemporary circuit design, 48, 52
BiCMOS, 49, 50, 51, 52, 57, 70 Control loop, 266, 267, 270, 271
Binary alloy, 336, 337, 339, 342, 343, 346, 347, Cost-effective, 146
348, 349, 350 Coupled linear congruential generator, 371, 373,
Bitcells, 223 374, 375, 377, 379, 381, 382
Bitline leakage, 219, 220, 226 C–R–C structure, (328)
Blocking layer, 287, 294 Current collapse, 290, 294, 305, 306, 307,
Blynk, 140, 141, 145 308, 318
Breakdown voltage, 282, 283, 287, 290, 291, 293, Current mirror, 127
296, 297, 298, 306, 307, 308, 309, 311,
315, 316, 317, 318, 319 Dark silicon, 77
Broad frequency range, (329) Data (D), 218
Buffer layer, 285, 291 Data preparation, 6, 17
Database, 5, 6, 17
Cache memory, 82 DC and RF applications, 304
Cadence 32 nm technology, 220 Decision tree, 8, 15, 18
Cadence Virtuoso, 187 Decoder functionality, 223
Calibration, 145, 146, 147 Delay, 92, 93, 94, 96, 97, 98, 99, 100, 101, 221,
Cap layer, 303, 318 222, 225, 371, 372, 380

383
384 Index

Delay impact on frequency, 34 Frequency range and power dissipation, 27

Delay stages, 26 Full adder, 376
Device optimization, 233
Device performance, 231, 233, 236 GAA MOSFET, 335, 336, 339, 343
DIBL effect, 249, 253 GaAs buffer layer, 302
Dielectric constant, 207, 235 GaAs substrate, 302
Dielectric, 294 Gain, 121, 124, 130, 131
Dielectric layer, 306 Gallium Arsenide (GaAs)-based HEMTs, 302
Digital communication, 147 Gallium nitride (GaN), (321)
Digital simulation, 242, 253, 254, 262 Gallium nitride (GaN)-based HEMT, 304, 305,
DIP (dual in-line package), 144 314, 319
Discrete FP, 308 Gallium nitride high electron mobility transistor
Dominant pole, 273, 277 (GaN HEMT), 320
Double Grid MOSFET, 242, 244, 253, 255, 262 GaN HEMT-based power amplifiers, 320
Double-channel device, 312 GaN HEMTs, 1, 2, 7, 11, 12, 14, 15, 16, 17, 18
Drain current, 8, 172, 177, 178, 242, 244, 245, GaN monolithic microwave integrated circuits
246, 254, 255, 304, 308, 309, 310, 311, (MMICS), (321)
313, 314, 315, 318, 319, 338, 339, 341, GaN substrate, 287, 294, 307, 319
342, 343, 344 Gate leakage current, 203, 301, 306, 307, 310,
Drain induced barrier lowering, 202, 212 311, 314, 317, 318
DRAM, 75 Gate recess, 290, 291, 292, 317, 318
Drift-diffusion model, 232, 234 Gate region, 306, 315, 317
Dual dielectric, 195 Gate-bias (VGS), 169, 170, 171, 176, 177, 178
Dual planar grid, 180 Gate-capacitance, 193
Dual-CLCG random generator, 375 Gate-drain capacitance, 194
Dual-gate HEMTs, 316 Gate-source capacitance, 194
Dual-grid TMOS, 251, 252, 260 Gate-source capacitances, 308
Dynamic power, 97, 100, 380, 381 Gate-source voltage, 188, 340, 342, 347
Germanium, 236, 237
Effective thermal control, (330) GNRFET, 48
Einstein relation, 232, 234 Graph, 140, 145
Electron mobility, 228, 229, 231, 232, 233, 235, Grid capacity, 254
237, 283, 285, 286 Grid voltage, 245, 246, 248, 254, 257
Electrostatic potential, 243, 248, 249
Elevated breakdown voltage, (321) Han Carlson adder, 378, 379, 380, 381
Elevated temperatures, (323) HDL simulation, 255, 256
Elevated voltages, (321) Healthcare, 137, 138, 139, 140, 147, 148
Energy band, 194 Heat sinks, (324)
Enhanced reliability, (323) Heterojunction, (321)
Environmental influence on frequency, 29 Heterostructure, 16
Epitaxial growth techniques, (323) High cut-off frequencies, (322)
High electron mobility, (320), (323)
Fast switching speed, (323) High-electron-mobility transistor (HEMTs), 298
Fault-tolerant inverter, 15 High electron mobility transistors (HEMTs), 301,
Fe-doped GaN buffer, 307 302, 304
Feedback loop, 269, 274 High power density, (323)
Feedback network, (326) High-speed switching, 281, 282
Field plate (FP) technique, 308 Hole mobility, 235, 237
Field plate, 290, 291 HX711 ADC (half of X 711 analog to digital
Field-effect transistors (FETs), 281 converter), 138, 140, 146, 147
Figure of merit (FoM), 33 Hybrid cache, 85
FinFET, 48, 49, 168, 169, 176 Hysteresis, 146
Five-stage single-ended oscillator, 30
Flipped voltage follower, 265, 266 ICU (intensive care unit), 138, 139
Forward gain, 189 III-V compound semiconductors, 301
Frequency control, 25, 30, 31 III-V GaN devices, 283
Index 385

Impact on speed and power consumption, 24, 29 Low power VLSI, 92

Impedance, 187, 188, 197, Low voltage, 42, 44
Impedance attenuation, 268, 270, 273
Impedance matching, (329) Machine learning, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11,
InAlN back barrier, 310 13, 14, 15, 16, 17, 18
Indium phosphide (InP)-based HEMTs, 303 Magnetic Tunnel Junction, 80
Induced HEMTs, 305 Main memory, 77
Inductive peaking, 187 Matching networks, (326)
Inductive source degeneration, 187 Maximum available gain (MAG), (324)
InGaAs channel layer, 302 Maximum oscillation frequency (fmax), (325)
InGaN back-barrier, 312 Memory array, 219, 222, 223, 226
InGaN cap layer, 317 Memory wall, 78
Inherent trade-offs, (325) Memristor, 58, 59, 60, 61, 64
Input impedance, 125, 127, 130, 131 MEMS, 56, 57
Input-Matching Network, 188 Metaheuristic, 346, 348
Input return loss, 189 Metal-organic chemical vapor deposition
Input terminal, 125 (MOCVD), (323)
Integrated Circuit, 75, 120, 121, 122 Metamorphic HEMTs, 305
Integration, 121, 122, 124, 125, 126, 131 Microwave circuits, 187
Inter-Stage Matching Network, (330) Miller effect, 188
Interface, 124, 130 MIS-HEMT, 287, 289, 294, 295, 296, 298
Interstage matching network (ISMN), (325) mL/h (milliliters per hour), 139, 140
Intrinsic gain, (331) mmWave, 186
Inverter gate, 343, 348, 349, 350 Mobile charge density, 244, 245, 246, 248, 251
IoT, 48, 50, 69, 138, 140, 141, 147, 148, 149 Mobility degradation effect, 255
IoT model, 372 Modern semiconductor, 228, 229, 236
Isolation transistor, 3, 7, 16–17 Modified watt, 235
I-V- 3, 5, 7, 10, 12 Molecular beam epitaxy (MBE), (323)
Montgomery multiplication, 374
Junctionless FET, 337, 338, 339, 340, 342, 343, MOSFET, 3–4, 8, 11, 241, 242, 245, 249, 251,
344, 345, 346, 347, 348, 349, 350 259, 262, 281, 287, 294
Multi-valued logic, 151, 152
Khaled Hayatleh, 37 Multicore system, 77
Multigate JL FETs, 334, 335, 336
Ladner-Fischer Adder, 95, 96, 97, 98, 99, Multiplexer, 155, 156, 157, 158, 159, 160, 161,
100, 101 162, 375
Large-signal output matching, (329) Multiplier, 154
Lateral field mobility, 250, 251
Lateral Scaling, 203 Nabil Yassine, 37
Lattice mismatch, 284, 286, 290 Nanoelectronic circuits, 334, 350
Leakage current, 75 Nanoelectronics, 334, 346, 349, 350
Linear congruential generator, 371, 373, 374, 375, Nanoscale, 335, 336, 348
377, 379, 381, 382 Nanosheet devices, 169, 177, 178, 179, 180
Linear feedback shift register, 373 Neural networks, 9, 11, 12, 13, 18
Linear regime, 246, 247, 248, 258 Newton-Raphson method, 245, 248, 262
Load cell, 137, 138, 140, 141, 142, 143, 144, 145, NMOS, 97
146, 147, 148 NMOS quad model, 5–6
Load transient, 268, 273, 277 NMOS transistor, 3, 5–7, 11–12
Load-pull analysis, (326) No-linear regime, 258
Loads, 265, 266, 267, 277 Node MCU ESP8266 (Node Microcontroller
Logic signals, 221 Unit Espressif 8266), 138, 140, 141,
Loop gain, 258 142, 144, 146, 149
Low-noise amplifier, 187 Noise, 37, 40, 41, 44, 45, 46, 47
Lower gate charge, (324) Noise figure, 189
Low Output Capacitance, (320) Normally-OFF transistor, 317
Low power Adder, 92 Normally-OFF, 288, 289
386 Index

On-chip oscillator, 142, 143, 147 Precharge functionality, 222, 223, 224
ON-Resistance (Ron), (322) Pre-computation, 93, 94
ON-state resistance, 282, 290, 291 Prefix-computation, 93, 94
Operating frequency, 29 Propagation delay, 1, 9–10, 12, 15–18, 150, 164
Operating points, 40, 41, 46, 47 Pseudo-random bit generator, 371, 372, 376
Optimization, 336, 345, 347, 348, 350 Pseudo-random bits, 371, 372, 373, 374, 375,
Oscillation frequency, 26, 27, 30, 258 378, 381
Output matching network, 188, 197 Pseudomorphic HEMTs, 304
Output return loss, 189 PSO, 336, 345, 346, 347, 348, 350
Output voltage, 349 Pulse-width modulation, (322)
Overshoot, 276, 277
Quad logic (QL), 4
p-doped gate, 290 Quad transistor (QT), 5, 13, 15
p-GaN, 287, 288, 289, 294 Quad transistor (QT) logic, 5
Parallel Prefix Adder Structure, 377 Quantum-dot cellular automata, 61
Parallel Prefix Adders, 92, 93, 98 Quantum Effects, 169, 171, 172
Parallel RC network, (331) Quantum theory, 207
Parasitic capacitance, 289, 291, 306, 308 Quaternary logic, 152
Pass transistor logic, 92, 97, 98, 101, 265, Quaternary multiplier, 155, 156, 157, 158, 159,
267, 275 160, 162
Passive components, 257, 258
PCB, 48 Radio frequency, 186
PD_SCK (Programmer Data Synchronous Rajasekhar Nagulapalli, 37
Clock), 143, 144 Random bit generation, 381, 382
Penetration depth, 292, 294, 296, 297 Read operation, 218, 223, 224
Performance of different stage oscillators, 33 Real time, 140, 145
Peripheral devices, 222, 223, 224 Recessed gate, 13, 15, 18
Phase margin (PM), 44, 267, 277 Reduced output charge (QOSS), (324)
Phase noise, 27 Reduced thermal resistance, (330)
Phase noise and figure of merit (FoM), 33 Reduce power dissipation, (320)
Photonics, 58, 67, 68, 69 Reliability, 122, 132
Physical Unclonable Functions (PUFs), 29 Reliable, 137
Piezoelectric, 283, 286 Response time, 265, 266, 276, 278
Piezoelectric polarization, 305, 310 RF Applications, 186, 187, 192, 195
Pi-shaped gate, 316 RF microwave integrated circuits, (321)
PMOS, 97 Ring oscillator, 29
PMOS transistor, 3–7, 13 Roll-off in threshold voltage, 202
Polarization, 283, 286, 291, 295 Routh-Hurwitz criterion, 267, 269, 273
Polarization impedance, 259 Row decoder, 222
Positive feedback, 29, 30 RTL schematic view, 95, 96, 99, 100
Post-computation, 93, 94
Power, 92, 93, 96, 97, 98, 99, 100, 101 Sapphire, 307, (323) S-parameters, (329)
Power-added efficiency (PAE), (325) Saturation regime, 246, 247
Power amplifiers, (322) Scattering, 231, 234, 235
Power consumption, 29, 122, 123, 125, 126, 127, SCE, 241
129, 132, 217, 218, 219, 221, 222, 225, Schottky HEMT, 287
228, 229, 230, 233, 236, 237 Self-bias, 42, 43
Power-delay product (PDP), 150, 164 Self-resonant frequency, (326), (331)
Power delay product (PDP), 221, 222 Semiconductor device model, 1, 2, 3, 15, 16
Power dissipation, 150, 164 Semiconductor technology, (320)
Power-down control, 143, 144 Sense amplifier, 217, 218, 222, 223, 224, 226
Power efficiency, (322) Sense amplifier operation, 217, 218, 222, 223,
Power spectral density (PSD), 45, 46 224, 226
Power supply rejection ratio (PSRR), 44, 45, 46 Sensor, 122, 124, 129, 130, 131
Power transfer efficiency, (331) Sensors, 141, 147, 148
Power wall, 77 Serial clock, 143, 144
Precharge circuit, 222, 223, 224 Seven-stage single-ended oscillator, 31
Index 387

Short channel effect, 191, 202, 241, 301, 304, TFETs (tunnel field-effect transistors), 177,
310, 334 179, 180
SiC substrate, 307 T-gate, 316, 319
Si substrate, 291, 307 Thermal conductivity, (323)
Si3N4, 294, 295, 296, 297 Si3N4 passivation Thermal management strategies, (321)
layer, 306 Thermal Modeling, 10, 18
Silicon carbide (SiC), (323) Thermal vias, (324)
Silicon-germanium 236 Third order input intercept point, 189
Silicon Germanium, 334, 335, 336, 337, 338, 339, Three-stage single-ended oscillator, 25, 26, 27
340, 341, 342, 343, 344, 345, 346, 347, Threshold voltage, 5, 13, 18, 249, 287, 291, 292,
348, 349, 350 293, 298
Silicon tin, 334, 335, 336, 337, 338, 339, 340, THz, 186
341, 342, 343, 344, 345, 346, 347, 348, Tikhonov regularization, 13, 14
349, 350 Timing diagram, 220, 221, 223, 224
Silvaco-ATLAS, 2 TiO2, 197
SILVACO-TCAD, 242, 253, 262 Titanium dioxide, 192
Simulated result, 95, 96, 99, 189, 220 Torque, 147
Single bitline, 219, 220, 221, 222, 226 Total gate width (TGW), (325)
Single event upset (SEU), 2 Transconductance, 3, 8, 9, 195, 304, 306, 308,
Single-stage method, 9, 10 310, 312, 313, 317
Slewing, 265, 267, 268, 273, 277 Transfer characteristics, 210
Small-signal gain, (324) Transfer function, 258
SMASH circuit simulator, 242, 255, 256, 262 Transistor count, 217, 221
SMD (surface mount device), 144 Transistor scaling, 216
SoC, 265, 278 Transversal field mobility, 250, 255
SOI, 53, 54, 55, 56, 57, 58, 70 Triple Modular Redundancy (TMR), 4
Solid-state device technology, (320) Tunnel FET, 202, 203
Solid-state power amplifiers, (320) Two-dimensional electron gas, 302, 313, 315, 321
Source follower, 267, 268, 269, 270, 271, 272, Two-stage method, 10, 11
273, 275, 276
Spartan 3E FPGA, 97, 98, 100 Unilateral two-port network, (327)
Spontaneous polarization, 305
SRAM, 75 VAVDD (Variable Analog Supply Voltage Drain
SRAM architecture, 222 Drain), 142
SRAM chip area, 217, 220, 221 Velocity saturation, 234, 235
Stability, 273, 274, 275, 277 Verilog-AMS, 242, 255, 256, 258, 261, 262
Stacked nanosheet FET, 178 VLSI, 371, 372, 374, 381, 382
Stagger tuning, 188, Voltage combiner, 268, 270, 272
Static power, 97, 100 Voltage control, 30, 31
Storage node (Q), 217, 218, 219, 220, 224
Strain gauge, 141, 147 Wide bandgap, (323)
STT-MRAM, 74, 75, 80 Wi-Fi (Wireless Fidelity), 137, 141, 145, 148
Subthreshold swing, 169, 172, 173, 174, 175, 179, Wordline Driver, 217, 222, 223, 224
180, 204, 209, 228, 229, 230, 231, 236 Work function, 209
Summary report, 96, 97, 100 Write Driver (WD) circuit, 219
Superior thermal stability, (323) Write enable (WE), 218
Superjunction MOSFET, (324) Write operation, 217, 218, 219, 221, 223, 224
Supply voltage impact, 32
Xilinx, 96, 98, 100
Tasch model, 235 XOR gate, 375, 376
TCAD , 192, 348
TCAD algorithms, 1, 15 Yield rate, 122
TCAD simulation, 4, 9, 15
Technology schematic view, 96, 99, 100 Zero offset, 146
Temperature, 124, 126, 130, 132 Zero Voltage Switching (ZVS), (324)
TFET, 187, 191, 192, 194, 195, 196, 197, 198, 343 Δ-shaped gate, 294, 316, 319
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