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Design and Implementation of Single Precision Floating-point Arithmetic Logic

Unit for RISC Processor on FPGA

Conference Paper · May 2023

DOI: 10.1109/MI-STA57575.2023.10169623

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 2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and
Computer Engineering (MI-STA), Benghazi, Libya 21-23 May 2023.

Design and Implementation of Single Precision

Floating-point Arithmetic Logic Unit for RISC
Processor on FPGA
2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA) | 979-8-3503-1989-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/MI-STA57575.2023.10169623

1st Noor Alhuda Saad Adela 2nd Amani Najeeb Ben Yousuf 3rd Mohamed Muftah Eljhani
Department of Computer Engineering Department of Computer Engineering Department of Computer Engineering
University of Tripoli University of Tripoli University of Tripoli
Tripoli, Libya Tripoli, Libya Tripoli, Libya
[email protected] [email protected] [email protected]

Abstract— The main purpose of conducting this research is to based on a 32-bit general-purpose four-stage pipeline processor
design and implement a single precision floating-point arithmetic equipped with a floating-point unit. The processor includes a
logic unit (ALU) that considered as a part of the math coprocessor. comprehensive collection of instructions, programs, and data
The main advantage of floating-point representation is that it can memory, general-purpose registers, and an arithmetic logic unit
support more values than fixed-point and integer representations. that can perform single-precision floating-point arithmetic
Summation, Subtraction, multiplication and division are calculations [4]. Designing high-performance arithmetic
arithmetic functions in these calculations. In this floating-point hardware has always been a sought-after challenge because
unit, input must be provided in IEEE-754 format, which is 32 microprocessors and signal processors are widely used. The
single precision floating point values. The application of This
Arithmetic and Logic Unit, which controls the speed of
arithmetic unit is located in the math coprocessor. Commonly
processor operations, is a crucial component of microprocessors.
referred to as reduced instruction set computation (RISC)
processor. In this processor, for a signal processing, a value with Simple arithmetic calculations are performed by standalone
high accuracy is required and as it is an iterative process, the circuitry on modern CPUs. Adding on-chip memory or cache to
calculation should be as fast as possible. A fixed-point and integer fast arithmetic hardware allows processors to reduce latency
central processing unit (CPU) can't meet the requirements. The associated with data access from main memory, resulting in a
floating-point representation can calculate very large or very significant boost in performance [5]. CPUs and GPUs nowadays
small process quickly and accurately. The system designed, come equipped with processors that can accommodate multiple
verified and implemented with Verilog hardware description and robust ALUs. Typically, the ALU is responsible for
language using Intel Altera software tools. performing various mathematical, logical, and decision-making
computations as part of the final processing stage by the
Keywords—: Floating point, IEEE-754, ALU, FPGA Design, processor. Arithmetic operations such as addition, subtraction,
Verilog Hardware Description Language and incrementing, as well as logic operations like AND, OR,
XOR, and NOT, are all executed by the ALU[6]Floating point
I. INTRODUCTION operations are widely utilized in various sectors due to their wide
RISC is a microprocessor design approach that emphasizes dynamic range, simple operation rules, and high precision.
simplicity and ease of use. While it may not be as efficient for There is an increasing need for high-speed hardware floating
complex calculations that require a single, complicated point arithmetic units to fulfill the demand for high-speed data
instruction to execute, it excels at tasks that can be broken down signal processing and scientific procedures. Additionally, the
into multiple simple operations. This makes RISC processors use of floating-point arithmetic operations is increasing in
ideal for use in pipelining applications[1] [2]. With the commercial, financial, and internet-based applications [7]. The
increasing complexity of devices, integrated microprocessors floating point representation is a widely used method to
must provide high performance, while still maintaining low represent real numbers in scientific notation. It uses a sliding
power consumption and a small form factor. This has become window mechanism to adjust the precision according to the
essential for daily activities, as computers and mobile phones number's scale, making it capable of representing extremely
have become indispensable tools. However, with the growing large or small numbers, ranging from 1,000,000,000,000 to
complexity of these products, there is a greater need for 0.000000000000001. To implement floating point arithmetic on
processing power while still maintaining battery life. Recent reconfigurable hardware, such as FPGAs, is challenging due to
trends have shown that RISC processors have overtaken CISC the complex algorithms. Therefore, we aim to construct a
processor architecture. The advantage of RISC is that it can floating-point arithmetic unit or DSP processor for high-
execute instructions quickly due to the simplicity of the accuracy scientific tasks using Verilog HDL and Altera Quartus
instructions [3]. A RISC microprocessor is characterized by its II. The module includes arithmetic operations such as addition,
limited number of instructions and ability to perform millions of subtraction, multiplication, and division [8].
instructions per second. This article discusses a CPLD which is

979-8-3503-1989-7/23/$31.00 ©2023 IEEE

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 II. METHODOLOGY TABLE. I. Complete List of The Implemented Instructions
The focus of this paper is on planned to follow a Bottom to
up approach while designing this ALU. Firstly, we implemented
simple logic blocks such as Comparator, Adder, Shifter, etc. in
Verilog. Then after verifying their performance in the ModelSim
simulator, with respect to generated signal patterns as inputs, we
implemented the whole design.
A. Design Block
The design comprises of 5 basic sections as shown in “Fig.
1”.
1. Opcode Decoder
2. Arithmetic Block
3. Logical Block
4. Comparator Block
5. Shifter Block
By combining these operations, it is possible to implement any
logic operation.

D. Arthimetic Block
This block is used to perform arithmetic operations such as
addition, subtraction and multiplication. The accumulator and
auxiliary register b provide input to this block, as shown in
“Fig. 2”.

Fig. 1. ALU Block Diagram

B. Opcode Decoder
The proposed design consists of a main opcode decoder Fig. 2. Pipelined RISC Architecture
that activates the corresponding function block based on the
instruction opcode executed by the processor and passed to the 1. Integer Addition/Subtraction
ALU block. The corresponding output lines will provide the
activation currents of the respective function blocks. The Fast addition is crucial in various digital systems, and
decoder is 6 to 43 bits, it takes a 6-bit opcode as input and it it's important to note that subtraction and addition are
turn activates the corresponding function block to perform the essentially the same operation. The only difference is that in
desired operation. subtraction, the second operand's sign is reversed. With this
understanding, it's easy to execute integer subtraction using any
C. Selected Instructions integer adder. To make the adder compatible with both
The ALU that was designed requires a clock signal, two 32- operations, slight modifications are necessary to perform
bit operands, and a 6-bit opcode as its inputs. The instructions addition and subtraction of integers, a logic must be set up. If
that have been implemented in the ALU can be found in subtraction is selected, the B operand needs to undergo a two's
TABLE I. complement conversion, while for addition, B should remain
the same. There are two ways to achieve this: using an inverter
“Table. I”. show the complete list of the implemented and a per-bit multiplexer or by using an XOR gate. In the XOR
instructions, and “Table. II”. show the Floating-Point: Special gate method, one bit is associated with control, and the other is
Cases. linked with the corresponding bit of B.
.

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 2. Integer Multiplication shifted by adding the shift symbol. In logical shifting, the empty
bit positions in the shift are filled with zeros like in “Fig.4” [9].
Multiplication is a commonly used operation that has
various applications, including scientific calculations and
signal processing. It is also essential for performing division.
Integer coefficients can be implemented through different
methods, with typical implementations being change and add.
When performing multiplication, both registers are utilized to
produce a 64-bit output. as in “Fig.3”

Fig. 3. Shift and Addition Multiplier Circuit

Fig. 4. 32 bit scaled shifter block
E. Comparator Block
This block includes a combinatorial HDL code that H. Floating Point Unit
performs bit matching and comparison. The corresponding
outputs can be used to derive instructions based on the Floating point units (FPUs) are specialized hardware
comparison. Likewise, numerical greater or less than indices components within the CPU that are responsible for
can be used on the respective operands. processing decimal operations. FPUs perform basic arithmetic
operations such as addition, subtraction, multiplication, and
division. However, unlike the Arithmetic Logic Unit (ALU)
F. Logical Block which handles integer values represented in binary numbers,
This block contains fundamental logic gates like AND, the FPU handles both integer and fractional parts of numbers.
OR, NOT, and XOR responsible for performing logic Since bit vectors cannot distinguish between integer and
operations on data operands. The outputs are stored in their fractional parts of numbers, the operands must be separated
respective latches. These logic gates perform standard logical into the sign, exponent, and mantissa parts of the number. This
operations on bit operands. If both Ai and Bi are 1, the AND allows for more accurate decimal calculation within the CPU.
operation produces 1 in the i output bit. If either Ai or Bi is 1
but not both, the OR operation produces 1 in the i output bit. I. IEEE 754 Standred
The NOR operation is the opposite of the OR operation, with a
0 inserted in the bit position if the conditions are not met. The The standard includes support for both 32-bit single-
ENV operation reverses the bits of A and B. precision and 64-bit double precision numbers. Double
precision has a wider range and higher precision than single
precision due to its 11 bits of exponent and 52 bits of fraction,
G. Shifter/ Rotat Block compared to 8 bits of exponent and 23 bits of fraction for single
This block contains simple shifters like the barrel shifter precision shown in “Fig 5”. Since this article only focuses on
and end cap turning mechanisms that can be used to shift data 32-bit inputs, we will only explore the single-precision format,
to the right. Two methods are used for this shift - arithmetic and which operates in the same way as double precision as shown
logical. In arithmetic shifting, the operation is expanded as it is in TABLE. II.

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Fig. 5. Single-Precision IEEE 754 Format

The standard accommodates 32-bit single-precision numbers

and 64-bit double precision numbers. It is noteworthy that the
double precision category offers a broader range, considering
that it has 11 bits of exponent as opposed to the 8 bits of single-
precision. Furthermore, double precision provides higher
precision, thanks to its 52 bits of fraction in comparison to the
23 bits available in single-precision as shown in “Fig 5”, and
TABLE. II.

Fig. 6. Block Diagram of Floating-Point Adder/Subtractor

TABLE. II. Floating-Point: Special Cases
Exponent
Number Sign Fraction (f) In order to align the smaller operand with the larger
(e)
0 X 00000000 00000000000000000000000
operand, one needs to shift the smaller operand to the right by
an amount determined by the difference between their
∞ 0 11111111 00000000000000000000000 exponents as shows in “Fig. 6”.
∞ 1 11111111 00000000000000000000000
2. Floating-Point Multiplication
NAN X 11111111 nonzero
Efficient multiplication design is crucial as floating-point
multiplication is widely used in various applications,
J. FPU Instruction comparable to floating-point addition/subtraction as shows in
“Fig. 7”.
The operations supported by the floating-point unit include
addition, subtraction, and multiplication as shows in TABLE.
VI.

TABLE. VI. FPU Operations

Operation OP Code

Addition 00

Subtraction 01

Multiplication 10

1. Floating-Point Adder/Subtractor

The most commonly employed floating-point operation

is FP addition/subtraction, analogous to the widespread use of Fig. 7. Generic FP Multiplier Block Diagram
integer addition/subtraction in the ALU.

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K. Hardware Test Environment
Our team has developed a comprehensive EDA (Electronic
Design Automation) printed circuit board system to enable
efficient and thorough testing and validation of the floating
point ALU in hardware. This system is intended to facilitate the
use of more advanced FPGA development tools as shows in
“Fig.8”.

Fig.11. FPU Multiplier

IV. CONCLUSION
The goal of this project is to create an architecture for an
arithmetic logic unit and floating-point unit that can handle all
arithmetic and logical operations for a RISC processor. The
design should be flexible enough to scale up to 32 bits. The
project uses Verilog language and utilizes software tools like
ModelSim 10.1 and Quartus II 12.1 for simulation and testing.
Fig.8. PCB with Cyclone FPGA The techniques utilized in this project provide a distinct
approach to design, test, and verify the system. The design
was done using electronic design automation tools.
III. SIMULATION AND RESULTS
REFERENCES
To confirm the proper functioning of each arithmetic block
and floating-point implementation, they were programmed
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[5] A. Athihrii, M. Stephen and S. Kumar, "Design and
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[7] R. Cherian, N. Thomas and Y. Shyju, "Implementation of Binary
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Fig.10 .FPU Subtractor

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