Scribd
Upload
0 views

verilog assignment-4

The document discusses Verilog code examples focusing on inferred latches and race conditions in combinational circuits. It explains how missing signals in sensitivity lists can lead to inferred latches and demonstrates the use of non-blocking assignments to avoid race conditions. Additionally, it covers event synchronization between processes in Verilog.

Uploaded by

nuthakkirewanth
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0 views

verilog assignment-4

The document discusses Verilog code examples focusing on inferred latches and race conditions in combinational circuits. It explains how missing signals in sensitivity lists can lead to inferred latches and demonstrates the use of non-blocking assignments to avoid race conditions. Additionally, it covers event synchronization between processes in Verilog.

Uploaded by

nuthakkirewanth
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

1.

a) VERILOG CODE USING DEFINE AND PARAMETER:

2.a)
3.a) Inferred latches happens in combina onal circuits.
Latches will create when there are undefined states , missing signals in sensi vity list .

CODE: WITH INFERRED LATCH , MISSING SIGNAL IN SENTIVITY LIST:

WITHOUT INFERRED LATCHES:


b) i) one flipflop.

ii) two flipflop,bcoz there are two non-blocking statements.

4.a)

5.a)
Using this code, there is race condi on between two always blocks.
So,we use non-blocking in this code to execute.

CODE:
always @(posedge clk or posedge reset)
begin
if (reset) begin
X1 <= 0; // reset
X2 <= 1; // set
end
else begin
X1 <= X2;
X2 <= X1;
end
end
#) X1 &X2 will swap there values.

6.a) In event ,one process waits for triggering of the other process, this synchronize the two processes.

CODE:
module event_syn( input data,clk,reset,
output data_out);
event received;
always @(posedge clk) begin
if(reset)
received<=0;
else
-> received;
end
always @(received) begin
data_out<=data;
end
endmodule

You might also like