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Experiment 3

The document provides a laboratory manual for designing Half Adder and Full Adder circuits using basic logic gates. It outlines the objectives, theory, circuit diagrams, truth tables, and required apparatus for each circuit. The Half Adder adds two input bits and produces a sum and carry, while the Full Adder adds three inputs, including a carry, and produces two outputs.

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9 views4 pages

Experiment 3

The document provides a laboratory manual for designing Half Adder and Full Adder circuits using basic logic gates. It outlines the objectives, theory, circuit diagrams, truth tables, and required apparatus for each circuit. The Half Adder adds two input bits and produces a sum and carry, while the Full Adder adds three inputs, including a carry, and produces two outputs.

Uploaded by

rishudos6
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Techno Main Salt Lake

EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

Laboratory Manual

Topic No. 5
Design of Half Adder circuit using Basic Logic Gates.
Objective:
Design of a Half Adder Circuit using basic logic gates
Theory:
Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and
carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and
the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily
constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit,
but it has a major disadvantage. The half adder can add only two input bits (A and B) and has nothing
to do with the carry if there is any in the input. So if the input to a half adder have a carry, then it will
be neglected it and adds only the A and B bits. That means the binary addition process is not complete
and that’s why it is called a half adder. The truth table, schematic representation and XOR//AND
realization of a half adder are shown in the figure below.
Circuit Diagram:

Fig 5.1 Circuit diagram of Half Adder.

Truth Table:
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

© Dept.of IT PCC-CS392_Lab Manual Page 23 of 40


Techno Main Salt Lake
EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

Laboratory Manual

Apparatus Required:

1. Power Supply 5v DC.


2. Breadboard.
3. Connecting wire.
4. IC 7408 & IC 7486
5. Logic Probe

Experimental Results:

INPUTS OUTPUTS**
A B SUM CARRY
0 0
0 1
1 0
1 1

**NOTE: To be filled by students.

© Dept.of IT PCC-CS392_Lab Manual Page 24 of 40


Techno Main Salt Lake
EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

Laboratory Manual

Topic No. 6
Design of Full Adder circuit using Basic Logic Gates.
Objective:
Design of a Full Adder Circuit using basic logic gates
Theory:
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B
and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output
is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create a byte-wide adder
and cascade the carry bit from one adder to another.

Logical Expression for SUM:

= A’ B’ C-IN + A’ B C-IN’ + A B’ CIN’ + A B C-IN


= CIN (A’ B’ + A B) + CIN’ (A’ B + A B’)
= CIN XOR (A XOR B)
= (1,2,4,7)

Logical Expression for C-OUT:

= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN


= A B + B C-IN + A C-IN
= (3,5,6,7)

Circuit Diagram:

Fig 6.1 Circuit diagram of Full Adder using Basic Logic Gates.

© Dept.of IT PCC-CS392_Lab Manual Page 25 of 40


Techno Main Salt Lake
EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

Laboratory Manual

Truth Table:
INPUT OUTPUTS
A B CIN SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Apparatus Required:

1. Power Supply 5v DC.


2. Breadboard.
3. Connecting wire.
4. IC 7408, IC 7486 & IC 7432
5. Logic Probe

Experimental Results:

INPUT OUTPUTS**
A B CIN SUM CARRY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

**NOTE: To be filled by students.

© Dept.of IT PCC-CS392_Lab Manual Page 26 of 40

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