İzmir University of Economics

EEE 332 Digital Electronics Lab

EXPERIMENT 2
NMOS Inverter with Resistor Loaded

A. Background
An NMOS inverter with resistive load is given in Fig. 2.1.
VDD=5V

RD

+
+
VO
VI
-
-

Fig. 2.1. NMOS Inverter with Resistor Load

A.1. Voltage transfer Characteristics

The voltage transfer characteristics (VTC) of the above inverter may be obtained by varying input
voltage VI from 0 to 5V. For the given value of the input voltage, VGS = VI and the output behaviour
of the NMOS changes with this VGS and a solution for VDS may be obtained. Then VO is determined
as VO = VDS. A typical VTC is given on Fig. 2.2.
V O, V CUT
OFF
VDD
VOH(min) slope = -1

SAT
Transition

NONSAT
slope = -1
VOL(max)
VOL(max)
Fig. 2.2. Voltage Transfer Characteristics of 0
an NMOS Inverter with a Resistor Load VTn VIL(max) VIt VIH(min) VDD VI, V

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The points, where the slope are -1, are important on the voltage transfer characteristics. These
points specify the limits of the voltage ranges used to specify Logic 0 and logic 1.
For the above characteristics the limits of the input low (logic 0) are approximately VIL(min) = 0 V
and VIL(max) = 1.55 V. Similarly the bounds for the input high level are VIH(min) = 3 V and VIH(max) =5 V.
On the other hand from the vertical axis the limits of the output low level are determined as
VOL(min) = 0.55 V and VOL(max) = 1.25 V, and the limits of the output high values are VOH(min) = 4.6 V
and VOH(max) = 5 V .
These values are represented on the voltage level diagram on Fig. 2.3.

VO VO

HIGH
5 VOH(max) VIH(max) 5
VOH(min)
4 NMH 4

3 VIH(min) 3

2 2
VIL(max)
1 VOL(max) NML
1
LOW LOW
VOL(min)
0 VIL(min) 0

Fig. 2.3. High and Low Noise Margins

For the above voltage transfer characteristics, the low and high noise margins are determined as:
NML = VIL(max) – VOL(max) = 1.55 – 1.25 = 0.3 V.
NMH = VOH(min) – VIH(min) = 4.6 – 3 = 1.6 V.

A.2. Average Power Dissipation

VDD=5V
The average power dissipated in the gate is
calculated assuming half of the period, input is high ID
(output is low) and during the other half input is RD
low (output is high).
When the output is high (VI = 0 V), the output
current is zero, ID(OH) = 0 V, since the transistor is
+
off. +
For VI = 5 V, the output is low (VOL = 0.55 V in the VO
above characteristics) and the current through is VI
-
-

Then the average power is Fig. 2.4. NMOS Inverter

and the average power dissipation is PD(avg) = VDD ID(avg) = (5V)(2.225mA) = 11.125 mW.

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B. Preliminary Work
B.1. Inverter Characteristics

Consider the NMOS inverter with resistor load given below in Fig. 2.5. The transistor parameters
are given on the right.
i. Determine and plot the voltage transfer characteristics (VTC) VO vs VI on Fig. 2.6.
ii. Graphically obtain the critical voltages input voltages VIL(min), VIL(max), VIH(min), VIH(max), and the
output voltages VOL(min), VOL(max), VOH(min) and VOH(max).
iii. Determine low noise margin (NML) and high noise margin (NMH) values.

VDD=5V Transistor Parameters

ID VTn = 1.4 V
RD Kn = 0.45 mA/V2
RD = 1.5 k

+
+
VO
VI
-
-

Fig. 2.5. NMOS Inverter

V O,
volts
5.0
Input voltages
4.5
VIL(min) = ……
4.0 VIL(max) = ……
VIH(min) = ……
3.5 VIH(max) = ……

3.0 Output voltages

VOL(min) = ……
2.5 VOL(max) = ……
VOH(min) = ……
2.0 VOH(max) = …….

1.5 Noise Margins

NML = ………
1.0 NMH = ………

0.5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI, volts
Fig. 2.6. Voltage Transfer Characteristics of the NMOS Inverter

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C. Experimental Work
C.1. Voltage Transfer Characteristics
1. Set up the following circuit (Fig. 2.7). The pin diagram of the NMOS transistor package is
given below in Fig. 2.8. (RD = 1.5 k and RG = 10 k
VDD=5V

RD

+
+
VO
VGG VI
-
-

Fig. 2.7. Voltage Transfer Characteristics Determination Circuit

Fig. 2.8. TC4007UBP Pin Diagram

(a) Obtain and plot VO vs VI on Fig. 2.9.

VI 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VO

(b) Now change RD and set RD = 390  and plot VO vs VI on Fig. 2.10.

VI 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VO

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 VO, volts

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI, volts

Fig. 2.9 VO vs VI for RD = 1.5 k.

V O,
volts
5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI, volts

Fig. 2.10 VO vs VI for RD = 390 .

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C.2. Power Dissipation
2. Set up the following circuit (Fig. 2.7) with RD = 1.5 k.

VDD=5V
ID
RD

+
+
VO
VGG VI
-
-

Fig. 2.11. Power Dissipation Measurements

Make the following measurements.
Table C.1

VGG ID (mA) Parameter

0V ID(OH)
5V ID(OL)

Component List:
Exp C.1 1.5 k 10 k TC4007UBP
resistor resistor
Exp C.2 1.5 k TC4007UBP
resistor

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D. Post Experiment Work
1. Using the VTC with RD = 1.5 K, graphically determine the points where the slope is -1. The
determine the following parameters:

VIL(min) =………………. VIL(max) =……………….

VIH(min) =………………. VIH(max) =……………….

and
VOL(min) =………………. VOL(max) =……………….

VOH(min) =………………. VOH(max) =……………….

Determine also low and high noise margin.

NML = ……………………………

NMH = ……………………………

2. Using the VTC with RD = 390 , graphically determine the points where the slope is -1. The
determine the following parameters:

VIL(min) =………………. VIL(max) =……………….

VIH(min) =………………. VIH(max) =……………….

and
VOL(min) =………………. VOL(max) =……………….

VOH(min) =………………. VOH(max) =……………….

Determine also low and high noise margin.

NML = ……………………………

NMH = ……………………………

3. Determine the average current and the average power dissipation.

ID(avg) = ……………………………..

PDD(avg) = ……………………………..

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