Sequential Circuits

Combinational circuits produce an output based on the values of current input variables
only. In sequential circuits, the present output depends on the present input as well as the
previous output (previous input variables). That is sequential circuits consist of memory
elements capable of storing binary information. The state of a sequential circuit at a time
is defined by this binary information stored.

Sequential Circuits

Examples of sequential circuits are flipflop, registers, counters, etc.

Types of Sequential Circuits
Based on the use of clock signal, Sequential circuits are classified into two.
Asynchronous Sequential Circuits
These circuits do not use a clock signal. Since there is no clock pulse these circuits are
faster. The state is changed immediately when the input signal is changed.

Asynchronous Sequential circuits

The output of these circuits are uncertain and they are difficult to design.
Synchronous Sequential Circuits
Circuits that use a clock pulse with their inputs is called a synchronous sequential circuit.
These circuits are slower, because they have to wait for the next clock pulse to perform
next operation.

Edge triggering and pulse triggering

Triggering is the process of making a circuit active. Triggering allows the circuit to take
input and generate output. The circuit will become active at certain states of clock pulse
depending upon the triggering methods we used.
What is a Clock?
A clock is a signal that oscillates between a high and a low state. It is used to coordinate
the actions of a digital circuit (like a metronome).

A clock signal

The transition of a signal from LOW to HIGH or from HIGH to LOW is called an edge. A LOW
to HIGH transition is a rising edge and a HIGH to LOW transition is a falling edge.
Types of Triggering
There are two types of triggering
Edge triggering
Level triggering
Level triggering
A level-triggered circuit will become active when the clock pulse is at a certain level.
Based on which level (HIGH / LOW ) the circuit is activated level triggering is again
classified as negative level triggering circuits and positive level triggering. In negative edge
triggering the circuit become active when the clock pulse is low. Similarly in positive edge
triggering the circuit become active when the clock pulse is high.
Edge triggering
An edge-triggered circuit will become active at a positive or negative edge of the clock
signal. When a clock signal goes from low to high, it is called a rising edge (positive edge).
A positive edge-triggered circuit will take input on the rising edge of the clock signal.
Similarly, when a clock signal goes from high to low, it is called a falling edge (negative
edge). A negative edge-triggered circuit will take input on the falling edge of the clock
signal.

SR latch
A latch is a temporary storage element that has two stable states (bistable). They operate
in signal levels rather than signal transitions. An active-HIGH input SR latch is formed with
two cross-coupled NOR gates and an active-LOW input latch is formed with two
cross-coupled NAND gate.
An SR Latch with two cross-coupled NOR gate is shown in the figure. It has two input S for
SET and R for RESET and two outputs and .
 SR latch using NOR gate.

Working of an SR Latch
When S=1 the output of G2 will be 0 (the output of a NOR gate is 0 when any of its input
are 1). Since this output is connected back to an input of G1, and the R input is also 0,
the output of G1 must be 1. This output 1 is coupled back to an input of G2, making its
output remain 1 even when the 1 on the S input is removed(Memory State). When the Q
output is HIGH, the latch is said to be in the SET state.
then &

SET operation of SR Latch

When R=1 and S=0, the output of G1 becomes 0. This 0 on the Q output is coupled back to
an input of G2, and since the S input is 0, the output of G2 becomes 1. This 1 on the
output is then coupled back to an input of G1, making the output Q remains 0 even when
the 1 on the R input is removed(Memory State). We can now say that the latch is in the
RESET state.
then &

RESET operation of SR Latch

When 1s are applied to both S and R at the same time, an invalid condition occurs in the
operation of an SR latch. As long as the 1s are held simultaneously on the inputs, both the
and outputs are forced to become 0. It will violate the basic complementary operation
of the outputs. Also, if the 1s are released simultaneously, both outputs will attempt to go
1. In this situation, you cannot reliably predict the next state of the latch.
This operation is summarized in the following truth table.
INPUTS OUTPUTS
COMMENTS

0 0 NC NC Memory State
0 1 0 1 RESET
1 0 1 0 SET
1 1 – – Not Used.

SR Latch using NAND gate

An SR latch can be also constructed by cross-coupling two NAND gates as shown in the
figure.

SR latch using NAND gate

The operation is described in the following truth table.

INPUTS OUTPUTS
COMMENTS

1 1 NC NC Memory State
0 1 1 0 SET
 INPUTS OUTPUTS
COMMENTS

1 0 0 1 RESET
0 0 – – Not Used

SR flip flop
Flip flops are synchronous bistable devices, also known as bistable multivibrators. The
term synchronous means that changes in the output occur in synchronization with control
input called a clock.
The basic form of an edge triggered flip-flop is the SR flipflop. The logic diagram of an SR
flip-flop is shown in the figure.

SR Flip flop block diagram

Circuit Diagram of SR Flip flop

The SR flip flop is designed by adding two NAND gates to a basic SR latch. The advantage
of this clocked circuit is that the inputs R and S are considered only when the clock pulse
is high. The circuit of the SR flip flop using the NAND gate is shown below.
 SR Flip flop circuit diagram

Working of SR Flip flop

When Clk = 0, irrespective of the value of S or R, the value of and will be whatever the
=
values stored in the previous state of the flip flop.
When Clk = 1, the output of the first two NAND gates, followed by inputs S and R, will be
and . When S 1, we get SET state and when R=1, we get the RESET state.
As before, the condition R = S = 1 is indeterminate and should be avoided when Clk is also
1.
This operation is described in the following truth table. Here indicated the present state
and indicates the next state. The characteristics table can be obtained from the truth
table is given below.
 -
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invalid
Truth table

0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X
Characteristics table

From these two tables, we know the transition from the present state to the next state. To
find the latch input conditions that will cause the specified transition, We need a table that
lists the required inputs for a given change of state. It is called an excitation table.
We can also obtain the expression for from the characteristics table using the K Map
technique as follows.
 0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Excitation Table

JK Flip flop
The JK Flip flop can be viewed as a modification of the SR Flip flop. The intermediate state
in a JK Flip flop is more refined and precise than that of an SR Flip flop.

Design of JK Flip flop

The design of a JK Flip flop is similar to that of an SR Flipflop. The output is connected
back to the input of NAND gate and output is connected back to the input of NAND
gate .

JK Flip flop circuit diagram

Working of JK Flip flop

When is 1 and is 0, the output goes 1 on the triggering edge of the clock pulse, and
the flip-flop is SET. When is 0 and is 1, the output goes 0 on the triggering edge of
the clock pulse, and the flip-flop is RESET.
When both and are 0, the output does not change from its prior state. When and
are both 1, the output of the JK flip-flop will toggle between 1 and 0. This is called the
race-around condition in a JK Flipflop. This is described in the following truth table.
 -
0 0 0 0
0 0 1 0
(
0 1 0 1
0 X X 0 1 1 1
1 0 0 1 0 0 1 0 0 0 X
1 0 1 0 1 0 1 0 0 1 1 X
1 1 0 1 1 1 0 1 1 0 X 1
1 1 1 Toggle) 1 1 1 0 1 1 X 0
Truth table Characteristic table Exctitation table

Expressions for , and can be obtained from the table using the K Map technique
as follows.

Master Slave JK Flip Flop

Race Around Condition in JK Flip flop
When both J and K input of a JK Flip flop is set to 1, the output of the JK flip-flop will
toggle between 1 and 0, which make the output of the flip-flop unstable. This is called the
race-around condition in a JK Flipflop. to avoid this problem, we use the concept of a
master-slave JK flip flop.
Design of Master Slave JK Flip flop
A Master-Slave JK Flip-Flop is designed by connecting two JK flip-flops in a series
configuration. In these one flip-flop act as the master and the other as a slave. The output
of the master flip-flop is connected to both the inputs of the slave flip-flop. Also, the
outputs of the slave flip-flop are fed back to inputs of the master flip-flop. Block diagram
of a master-slave JK flipflop is shown in the figure.

The circuit also includes an inverter and is connected. It passes the inverted clock pulse to
the slave flip-flop. If the clock pulse is set to 0 for the master, then the clock pulse will
become 1 for the slave and if Clk=1 for the master flipflop, it will become 0 for the slave
flipflop. The circuit diagram of a master-slave Jk Flip flop is given below.

Working of Master Slave JK Flip flop

The slave flip-flop is isolated until the Clk goes to 0. When the Clk goes to 0, values are
passed from the master flip-flop to the slave and output is obtained.
If and , output of the master becomes 1 which is then transferred to the K
input of the slave and the clock forces the slave to RESET, thus the slave flip-flop copies
the master flip-flop.
If and , output of the master becomes 1 and goes to the J input of the slave
and the clock sets the slave, copying the master.
If both and , the master toggles on the positive transition of the clock and the
slave toggles on the negative transition of the clock.
If J=0 and K=0, Q remains unchanged.
Timing Diagram of Master Slave JK Flip flop

D Flip Flop
The D(data) flip-flop stores the value that is given on the data line. It can be thought of as
a basic memory cell.
 D Flip flop Block Diagram

When both the inputs of an SR flip-flop are at the same logic level, then a no change or
invalid output condition occurs. If we avoid these conditions, there will be only two output
conditions: SET or RESET. There are many applications, where only SET and RESET
conditions of the latch are required. In these applications, we can use inputs (S and R)
which are always the complement of each other.
This can be designed by a single input (S) to the latch and the R input achieved by
inverting this S. This single input is called data input and it is labelled with D.

D Flip flop using SR Flip flop

Working of D Flip flop

The circuit diagram of a D flip-flop is given below:
 D Flipflop circuit diagram

When the clock is set to low, the output remains as it is whether the input signal is set high
or low.
When clock is high, if D = 1 then it is equivalent to S = 1 and R = 0 hence the latch is set(1).
On the other hand, when D = 0 then it acts like S = 0, and R = 1 hence the latch is reset(0).
The characteristics table and truth table of a D flip flop is given below.

0 0 0
0 1 1 0 X Qt
1 0 0 1 0 0
1 1 1 1 1 1
Characteristics table Truth table

The equation for and the excitation table derived from the characteristic table is
given below :

0 0 0
0 1 1
1 0 0
1 1 1 D Flipflop K-Map

T Flip Flop
A T flip-flop is a modified form of the JK flip flop. It is called a toggle flip flop because of
its toggling operation. T flip-flop is constructed by connecting the J and K inputs, creating
a single input called T as shown in the following figure.

T Flipflop from JK Flip flop

T Flip flop block diagram

Working of T Flip flop

The circuit diagram of a T flip-flop is given below:

T Flip flop circuit diagram

When the clock is set to low, the output remains as it is whether the input signal is set to
high or low.
When the clock is high, and the T signal is set to low(0), it will not affect the present state
of the output and the response will not change. When the T signal is set to high(1), then it
will invert the present output. That is, if the present output is high (1), it converts into low
(0); if the present output is low (0), it converts it into high (1). It means it will toggle the
output signal.
This operation is described in the following characteristics table and truth table.

0 0 0
0 1 1 0 X
1 0 1 1 0
1 1 0 1 1

The equation for can be derived from the excitation table using K-map as following.

0 0 0
0 1 1
1 0 1
1 1 0

Shift Registers
Registers
A register is a collection of flip-flops, each of which can store one bit of information. An n-
bit register is a group of n flip-flops that can store binary information of n bits. Register
memory is the smallest and most powerful type of memory in a computer. It stores
frequently used data, instructions, and memory addresses for use by the CPU.
in most digital systems, a master clock generator provides a continuous train of clock
pulses. The clock pulse is applied to all of the flip-flops and registers in the system.
Shift Registers
The information stored in registers can be transferred using shift registers. The registers
that shift the bits to the left are referred to as a shift left registers and the registers that
shift the bits to the right are referred to as shift right registers.
The shift register uses D flip flops. It is because the D flipflop can operate moving data
from the input to the output while a clock pulse is applied.
In shift registers, data can be entered and extracted sequentially or parallelly. Based on
this, Shift registers are classified as follows:
1. SISO – Serial In Serial Out
2. SIPO – Serial In Parallel Out
3. PISO – Parallel In Serial Out
4. PIPO – Parallel In Parallel Out
SISO (Serial In Serial Out) Shift Registers
The SISO is on the simplest of all the shift registers. The block diagram of a 4-bit shift
right SISO shift register is shown below. Each flipflop has one input(D),i one output and (Q)i
and a clock pulse input.

Serial In Serial Out Shift Register

In SISO shift registers, the input and output operation is performed serially. The data is
loaded into the input of the left-most flip-flop bit by bit. The data bit is shifted from one
flip-flop to the next for each clock pulse. The data inserted will be received bit by bit for
each clock pulse on the output side of the rightmost flipflop. An n-bit SISO shift register
requires 2n-1 clock pulses to shift n bit data.
Initially, the output of all the flip-flops is assumed to be logic 0.
Assume the data at the input terminal is 1.
The logic 1 at the input is shifted to the output of the first flip-flop during the first
clock pulse. Similarly, the data input to the remaining flip-flops is shifted by one position.
The logic 1 at the first and second flip-flop inputs is shifted by one position during the
second clock pulse. The logic 0 input at the input of the remaining flip-flops is also
shifted by one position.
This shifting process is repeated for each clock pulse. The loaded data bit ‘1′ will be
received at the output terminal at the end of the fourth clock pulse.
It takes 7 clock pulses to output all bits.
The truth table of shifting data 1111 is given below.

Initially 0 0 0 0
↓ 1 0 0 0
↓ 1 1 0 0
↓ 1 1 1 0
↓ 1 1 1 1
This operation can be also represented using a timing diagram as follows.
 Shift Right Registers Timing Diagram

SIPO (Serial In Parallel Out) Shift Registers

In a SIPO shift register, the data is loaded serially bit by bit. After shifting data inputs, the
output of each flip-flop can be taken out in parallel. The block diagram of a 4-bit shift right
SIPO shift register is shown below.

Serial In Parallel Out Shift Register

The data shifts from one stage to the next for each negative edge triggering of the clock
signal. We can access the outputs of all D flip-flops at the same time. So we get parallel
outputs from the shift register at the same time.
In SISO shift registers, the input and output operation is performed serially. The data is
loaded into the input of the left-most flip-flop bit by bit. The data bit is shifted from one
flip-flop to the next for each clock pulse. The data loaded will be received bit by bit for
each clock pulse on the output side of the rightmost flipflop.
An n-bit SIPO shift register requires n clock pulses to shift n bit data. That is, the above 4-
bit shift register only requires 4 clock pulses to shift the data given in the input.
PIPO (Parallel In Parallel Out) Shift Registers
In a PIPO shift register, the input data is loaded parallel into each flip-flop and the output is
received from each flip-flop parallelly.

Parallel In Serial Out Shift Register

It is used for temporary data storage or as a time delay device. Only a single clock pulse is
required to load and unload data in a PIPO shift register.
PISO (Parallel In Serial Out) Shift Registers
In a PISO shift register data is loaded into each flip flop in parallel, and the inserted data is
received at the output serially.

Parallel In Parallel Out Shift Register

The control signal decides the shifting and parallel loading actions.
Applying 0 to the control signal, will disable the AND gates 1, 3, 5 and enable the AND
gates 2, 4, 6. It will make the parallel data at the inputs(B0, B1, B2, B3) get stored in the
respective flip-flops. So parallel loading happens when the control signal is set to 0, that is
when is active. Only a single clock pulse is required for this loading operation.
When the control signal is 1, it will enable the AND gates 1, 3, 5 and disable the gates 2, 4,
6. On applying a clock pulse, the data at the input of each flip-flop is shifted to its output.
The data is shifted serially upon the application of each clock pulse. The serial output is
obtained from the output(Q0) of the last flip-flop.
An n-bit PiSO shift register requires n-1 clock pulses to shift n bit data.
Applications of Shift Registers
Shift registers are used to store temporary data.
Shift registers are also used as counters (Ring counter and Johnson Ring counter).
Shift registers can be used for data transfer and manipulation.
A PISO shift registers can be used to convert parallel data into serial data.
A SIPO shift registers can be used to convert serial data into parallel data.
A SISO and PISO registers can be used to add time delay to digital circuits.

Introduction to Counters
A counter is a sequential circuit that stores the number of times a particular event has
occurred in form of a clock pulse. Counters can be designed by connecting individual flip-
flops together.
Counters are used in digital electronics for the purpose of counting. When the clock pulses
are applied to a counter, it progresses from one state to the next, and the final output of
the counter’s flip-flop indicates the pulse count.
Counter Types
Basically, two types of counters are there.
1. Asynchronous Counters – Counters in which are flip flops are not clocked at the same
time.
2. Synchronous Counters – Counters in which all flip flops are clocked simultaneously.
The difference between synchronous counters and asynchronous counters are described
in the following table.
SYNCHRONOUS COUNTERS ASYNCHRONOUS COUNTERS
All flip flops are triggered with same clock Different flip flops are triggered with different clock,
simultaneously. not simultaneously.
Faster than asynchronous counter in operation. Slower than synchronous counters n operation.
Designing is complex due to increasing number of Designing as well as implementation is easy.
states.
Based on the type of counting, the following types of counters are also there:
1. Up Counter – Counts in increasing order.
2. Down Counter – Counts in decreasing order.
3. Up/ Down Counter – Count in both directions, increasing as well as decreasing.
Modulus of a Counter
The modulus of a counter indicates the maximum count a counter can reach or the total
number of states a counter has. The modulus of an n-bit counter is 2n. The maximum
decimal the counter can reach is given by 2n – 1.
That is the number of bits = n, modules = 2n, maximum count = 2n – 1.
For example, the modulus of a 3 bit counter is 23 = 8. The maximum count will be 7.
In the case of a Mod-16 counter,
2n=16. So n = 4, which means that it is a 4 bit counter, having 16 states, and the maximum
count it can reach is, 2n – 1 = 15.

Asynchronous Counters
Counters in which the flip-flops are supplied with different clock signals. The first flip-flop
is clocked by the external clock pulse and then each successive flip-flop is clocked by the
output of the preceding flip-flop.
2-bit Asynchronous Up Counter
The logic diagram of a 2-bit asynchronous up counter using JK flip-flop is shown in the
figure.

2-bit Asynchronous Up Counter Block Diagram

The J and K inputs of 2 flip flops are connected to logic 1. An external clock is applied to
flip-flop A and its output QA is applied to flip-flop B as the clock input. At the negative-
going edge of each clock pulse, flip-flop A changes its state. Flipflop B changes state only
when triggered by a negative-going transition of the QA output of flipflop A. The truth
table and timing diagram are given below.
CLOCK DECIMAL EQUIVALENT
Initially 0 0 0
🡫 0 1 1
🡫 1 0 2
🡫 1 1 3
 2-bit Asynchronous Up Counter Timing Diagram

From the timing diagram, it is clear that

Initially, the flip flops store zero.
When the negative edge of first clock pulse arrives, QA toggles from 0 to 1. Since a
positive edge of QA doesn’t toggle flip flop B, QB remains at 0.
Hence, we got a transition from 00 -> 01 (Q BQA).
Similarly, on the next clock pulse the counter goes to state 10, then 11, and after that it
goes back to sate 00.
As a result, it counted four states (from 0 to 3).
3-bit Asynchronous Up Counter
The logic diagram of a 3-bit asynchronous up counter using JK flip-flop is shown in the
figure.
 3-bit Asynchronous Up Counter Block Diagram

It works exactly the same way as a two-bit asynchronous binary counter mentioned
above, except it
has eight states due to the third flip-flop. The truth table and timing diagram are given
below.
CLOCK DECIMAL EQUIVALENT
Initially 0 0 0 0
🡫 0 0 1 1
🡫 0 1 0 2
🡫 0 1 1 3
🡫 1 0 0 4
🡫 1 0 1 5
🡫 1 1 0 6
🡫 1 1 1 7

3-bit Asynchronous Up Counter Timing Diagram

Initially, all the flip flops store zero.

When the negative edge of first clock pulse arrives, QA toggles from 0 to 1.
Since a positive edge of QA doesn’t toggle flip flop B, QB remains at 0.
 Also, since a positive edge of QB doesn’t toggle flip flop C, QC remains at 0.
Hence, we got a transition from 000 -> 001 (Q CQBQA).
Similarly, on the next clock pulse the counter goes to state 010, then 011, and so on.
The counter gets to a state 111 after which it goes back to sate 000.
Hence, it counted eight states (from 0 to 7).
4-bit Asynchronous Up Counter
The logic diagram of a 4-bit asynchronous up counter using JK flip-flop is shown in the
figure.

4-bit Asynchronous Up Counter Block Diagram

Here, we have 4 flip flops, and the number of states is 16, from 0000 – 1111 (0 to 15). The
truth table and timing diagram are given below.
CLOCK DECIMAL EQUIVALENT
Initially 0 0 0 0 0
🡫 0 0 0 1 1
🡫 0 0 1 0 2
🡫 0 0 1 1 3
🡫 0 1 0 0 4
🡫 0 1 0 1 5
🡫 0 1 1 0 6
🡫 0 1 1 1 7
🡫 1 0 0 0 8
🡫 1 0 0 1 9
 CLOCK DECIMAL EQUIVALENT
🡫 1 0 1 0 10
🡫 1 0 1 1 11
🡫 1 1 0 0 12
🡫 1 1 0 1 13
🡫 1 1 1 0 14
🡫 1 1 1 1 15

4-bit Asynchronous Up Counter Timing Diagram

3-bit Asynchronous Down Counter

An asynchronous down counter is designed the same way as an up counter with a few
corrections.
The inputs for JK flip flops are maintained at logic 1. Here the flip flops other than the first
one is
triggered by outputs of preceding flip flops. The counter output is taken as QC QB QA
itself.
 3-bit Asynchronous Down Counter Block Diagram

The counter designed thus counts in reverse order, from 7 to 0 as follows.

CLOCK DECIMAL EQUIVALENT
🡫 1 1 1 7
🡫 1 1 0 6
🡫 1 0 1 5
🡫 1 0 0 4
🡫 0 1 1 3
🡫 0 1 0 2
🡫 0 0 1 1
🡫 0 0 0 0

3-bit Asynchronous Down Counter Timing Diagram

Initially, all flip flops store zero, hence, the complemented output will be 1.
When the first clock pulse arrives, the negative edge triggers flip flop A and the output
goes from 0 to 1. The complimented output goes from 1 to 0 at the same time.
Since it triggers flip flop B, the negative edge toggles QB from 0 to 1.
Similarly, negative edge of complement output of B toggles QC from 0 to 1.
Now, we have 111, which equals 7.
On the next clock pulse, we have a state change 111 -> 110, then 110 -> 101 and so on.
When the state 000 is reached, the next clock pulse will toggle all outputs to 111. Hence it
counts from 7 to 0.
Asynchronous Up/ Down Counter
An up-down counter is a combination of an up-counter and a down-counter. It can count
in both directions, increasing as well as decreasing.
A mode control input(M) is used to select either up or down mode.
we have the M(mode control) input which decides whether or should be the clock
input to the next flip flop. We have to design a combinational circuit, that when applied M =
0 gives up counting and when M = 1 gives down counting.

The combination of inputs to the combinational circuit that we have to design and the
corresponding output it should produce is given below. The equation for Y can be found
out using K-Map.

0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Hence from the k-map, we got the equation in sum-of-product terms as .

A 4 bit up/ down counter can be designed as follows.

AND gates 1, 3 and 5 has one input connected with input and the other input from Q
output of flip flop preceding it. Similarly, gates 2, 4 and 6 have input from M and .
When M = 0, gates 1, 3 and 5 gives Q as output and gates 2, 4 and 6 gives 0.
When these outputs are given to OR gate, it produces Q as output, which is connected
to the clock input of next flip flop.
Hence, we have up counting.
When M = 1, gates 1, 3 and 5 gives 0 as output and gates 2, 4 and 6 gives Q as output.
When these outputs are given to OR gate, it produces Q as output, which is connected
to the clock input of next flip flop.
Hence, we have down counting.

Synchronous Counters
The clock inputs of all the individual flip-flops are clocked together at the same time by
the same clock signal, giving rise to the name “synchronous counter.” Because all of the
flip-flops are clocked together simultaneously (in parallel) at the same time, changes in
output occur in “synchronisation” with the clock signal.
As a result, all of the individual output bits change state at the same time, in response to
the common clock signal, with no ripple effect and thus no propagation delay, as in
asynchronous counters.
How to design a synchronous counter
The designing of synchronous counters follows the steps given below :
 Decide the number of flip flops required.
2. Decide the type of flip flop and draw excitation table of flip flop.
3. Draw the state diagram and circuit excitation table.
4. Obtain simplified equations for inputs using K-Map.
5. Draw the logic diagram based on the equations obtained.
Designing a 2-bit Synchronous up Counter
1
.
Step 1
Number of flipflops = 2, since it is a 2-bit counter.
Step 2
The flipflop we are going to use is JK flip flop. Excitation table of JK flip flop is:

0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Step 3
Since it is a 2-bit counter, it has 22 = 4 states. It can count from 0 to 3. Hence, the state
diagram can be drawn as shown below :

Using the excitation table of the flip-flop, we have to enter the flip-flop inputs, that are
capable of producing the next state of the counter from the present state in a table. For
this we create Circuit Excitation Table.
 0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
Step 4

Step 5
Based on the equations we found, we have to design the counter. The diagram hence
constructed is shown below. (Note that the clock input is given to all flip flops and here,
MSB is at Q1 and LSB is at Q2.)

Designing a 3-bit Synchronous up Counter

Step 1
The number of flip-flops needed is 3 since it’s a 3-bit counter.
Step 2
The flipflop we are going to use is T flip flop. The excitation table of JK flip flop is:

0 0 0
0 1 1
1 0 1
1 1 0

Step 3
Since it is a 3-bit counter, it has 23 = 8 states. It can count from 0 to 7. Hence, the state
diagram can be drawn as shown below :

Using the excitation table of the flip-flop, we have to enter the flip-flop inputs, that are
capable of producing the next state of the counter from the present state in a table. For
this, we create Circuit Excitation Table.

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
 1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Step 4

Step 5
Based on the equations we found, we have to design the counter. The diagram hence
constructed is shown below. Here MSB is at QC and LSB is at QA.

Decade Counter (BCD Counter)

A Binary Coded Decimal or a Decade counter is a counter that can count 10 states. A 4 bit
binary counter will act as a decade counter by skipping six outputs out of the 16 outputs.
The following truth table describes the counting operation of a decade counter.
CLOCK
0 0 0 0 0
↑ 0 0 0 1
↑ 0 0 1 0
↑ 0 0 1 1
↑ 0 1 0 0
↑ 0 1 0 1
↑ 0 1 1 0
↑ 0 1 1 1
↑ 1 0 0 0
↑ 1 0 0 1
↑ 1 0 1 0

State Diagram of Decade Counter

A counter is described by a state diagram, which shows the sequence of states through
which the counter goes through when it is clocked.

The count starts from 0000 (zero) to 1001 (9) and then on encountering 1010 (10) it resets
to 0000.
Decade Counter Circuit Diagram
The diagram given below shows an asynchronous decade counter constructed using JK
flip flops.

Decade Counter Circuit Diagram

J and K inputs of all flip flops are set to logic 1. Two asynchronous inputs PRESET(PRE) and
CLEAR(CLR) is given to all the flip flops. They have control over the outputs ( and )
regardless of clock input status. Both are active-low inputs.
When the PRESET input is activated, the flip-flop will be set regardless of any of the inputs
or the clock. When the clear input is activated, the flip-flop will be reset, regardless of any
of the inputs or the clock. PRESET is maintained at logic 1, hence it will not be activated.
When the clock pulse advances the counter to count 10 (1010), outputs of flip flops B and
C will be high. As we know that for high inputs, the NAND gate output will be low. The
NAND gate output is connected to clear input, so it resets all the flip flop stages in the
decade counter. This means the counter will restart after count 9.

RIng Counter and Johnsons Counter

Ring Counter
A ring counter is also known as SISO (serial in serial out) shift register counter. The
designing of the ring counter can be done by using four D-Flip Flops with a common clock
signal and an overriding input that can be connected to preset and clear.
All the flip-flops are arranged in series such that the output of the preceding flip-flop is fed
as an input to the immediate next flip-flop. The output of the last flip-flop is given as an
input to the first flip-flop.
The ring counter is a Synchronous Counter and also, number of states = number of flip
flops used. Therefore, a 4-bit Ring Counter can count 4 states.

Ring Counter Circuit Diagram

The overriding input(ORI) is connected to the PRE input of the first flip flop and the CLR
input of all other flip flops. They are active low, and hence, when ORI is low(0), the first flip
flop is SET(when PRE=0, Q 0 =0) and all other flip flops are RESET (when CLR=0,
output=0).
Initially, the ORI is low, therefore the state of counter is 1000.
After this, ORI is made high and hence the flip flops give outputs based on D input on
encountering the negative edge of incoming Clock pulses(Clk).
Ring counters have only one bit high at any instant of time.
The states of counter affected by each clock pulse are given below. The bit patterns
repeat after every 4 clock cycles.
ORI CLOCK
🡫 1 0 0 0
1 🡫 0 1 0 0
1 🡫 0 0 1 0
1 🡫 0 0 0 1
1 🡫 1 0 0 0
Johnson’s Counter
Also known as Inverse Feedback Counter or Twisted Ring Counter. Here, a D-flip flop is
used to construct a Johnson Counter. All flip-flops are arranged such that the output of
the preceding flip-flop is fed as an input to the immediate next flip-flop. It is to be noted
that the complement output of the last flip-flop is back-fed to the first flip-flop.
Johnson’s Counter is of Synchronous type and, Number of states = 2 x Number of flip
flops. Therefore, a 4-bit Johnson’s Counter can count 8 states.

Johnsons Counter Circuit Diagram

Here, the CLR signal is connected to the CLEAR input of all flip flops. Initially, CLR is
low(0) and hence the counter state is 0000.
After this, the CLR is maintained at high which will make the flip flops to produce
outputs on the negative edge of incoming clock pulses based on D inputs.
The states of counter affected by each clock pulse are given below. The bit patterns
repeat after every 8 clock cycles.
CLR CLOCK
0 X 0 0 0 0
1 🡫 1 0 0 0
1 🡫 1 1 0 0
1 🡫 1 1 1 0
1 🡫 1 1 1 1
1 🡫 0 1 1 1
1 🡫 0 0 1 1
CLR CLOCK
1 🡫 0 0 0 1
1 🡫 0 0 0 0
HAPPY
LEARNING

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