P.E.S.

COLLEGE OF ENGINEERING, MANDYA - 571401

(An Autonomous & Govt. Aided Institution, Affiliated to VTU, Belagavi)

SYNOPSIS ON
“DESIGN AND VERIFICATION OF UART USING
SYSTEM VERILOG”
Submitted in partial fulfilment for the award of the degree of
BACHELOR OF ENGINEERING
in
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

SAVITHA S 4PS22EC146
SHREEVARSHINI S 4PS22EC149
SNEHA JENIFER B 4PS22EC154
VIDYADHARE C 4PS22EC176

Under the guidance of

Mr. JANARDHANA S Y
Assistant Professor
Department of ECE, PESCE

DEPARTMENT OF ELECTRONICS AND COMMUCNICATION

ENGINEERING
2024 - 2025
 INDEX

Sl. No Contents Page No.

Introduction
1.  Problem statement
03-06
 Objective of the project

2. Literature Survey 07

3. Proposed Methodology
08-09

4. Project Design & Implementation 10-11

5. Expected Outcome 12

6. References 13
DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

ABSTRACT

The UART protocol is a widely used communication standard for serial data transmission in embedded
systems and System-on-Chip (SoC) designs. It facilitates asynchronous communication between
devices by converting parallel data from a processor into serial form and vice versa. The Design Under
Test (DUT) in this case ensures seamless communication between the transmitter (testbench) and
receiver (design), adhering to the UART protocol's specifications for data integrity and reliability.
UART operates without a clock signal, relying on pre-determined baud rates for synchronization
between the transmitter and receiver. It supports features such as configurable baud rates, parity checks
for error detection, and stop bits, making it highly suitable for low-cost and low-speed communication
applications. The verification process focuses on designing test cases to evaluate functionality under
various conditions, such as single-byte and multi-byte transmissions, with and without error scenarios,
including mismatched baud rates and parity errors. The design is implemented using Verilog HDL and
verified using a SystemVerilog-based testbench. The simulation tool (e.g.,QuestaSim) ensures
functional compliance with UART specifications. Test cases cover scenarios like data transmission,
reception, and error handling to validate protocol behavior. Simulation results demonstrate correctness,
performance, and efficiency, ensuring reliable communication for applications ranging from industrial
devices to microcontroller-based systems.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

INTRODUCTION

Universal Asynchronous Receiver/Transmitter (UART) is a simple yet widely used protocol for
asynchronous serial communication in embedded systems. It enables reliable data exchange by
converting parallel data into serial format for transmission and then back to parallel at the receiving
end. UART eliminates the need for a shared clock signal by relying on pre-configured parameters such
as baud rate, parity, and stop bits for synchronization. It also supports error detection through
mechanisms like parity checks, ensuring data integrity during communication. This makes UART
suitable for a variety of applications, including microcontroller communication, industrial automation,
and debugging systems. Despite its simplicity and cost-effectiveness, UART is best suited for low-
speed, short-distance communication due to its limited data rates and lack of advanced error correction.
However, its ease of implementation and flexibility have established it as a fundamental
communication standard in modern systems. By facilitating efficient point-to-point communication,
UART continues to play a significant role in both basic and advanced embedded applications.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

PROBLEM STATEMENT

The UART protocol is a basic standard for sending data between devices in embedded systems. While
it's simple and flexible, it comes with challenges like mismatched speeds (baud rates), detecting and
fixing errors during transmission, and limits in working well over long distances or high speeds. The
task is to create a reliable and reusable UART design using Verilog HDL (a hardware description
language) and to build a SystemVerilog-based testbench. This testbench will help check if the design
works correctly and performs well under different conditions, ensuring smooth communication for
modern uses.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

OBJECTIVE OF THE PROJECT

1. Develop a robust UART module in System Verilog, including core functionalities for serial
data transmission and reception.
2. Implement a parity check mechanism for error detection, ensuring support for both even and
odd parity.
3. Create a comprehensive testbench in System Verilog to verify the UART module’s
functionality and validate the parity check.
4. Incorporate features to detect and report parity errors during data transmission and
reception.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

LITERATURE SURVEY

1. Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter

(UART), Ashok Kumar Gupta; Ashish Raman; Naveen Kumar; Ravi Ranjan.
This paper presents the design of a UART system optimized for high-speed serial communication. It
focuses on reducing transmission delay, increasing baud rate support, and ensuring reliable data
transmission with optional parity checking. The implementation is verified on FPGA, demonstrating
efficient resource utilization and improved performance over conventional UART designs.

2. Design and Verification of UART using System Verilog; Yamini R, Ramya M V.

This paper focuses on the RTL design and functional verification of a UART module using System
Verilog. It highlights the use of object-oriented verification methodologies, particularly the Universal
Verification Methodology (UVM), to ensure robust and reusable testbenches. The work demonstrates
successful simulation and verification results, emphasizing the effectiveness of System Verilog for
verifying serial communication protocols like UART.

3. Analysis of UART Communication Protocol; Pranjal Sharma; Anup Kumar; Naresh Kumar.
This paper provides a detailed study of the UART protocol, its architecture, and its role in
asynchronous serial communication. The authors analyze key parameters like baud rate, data framing,
and error detection mechanisms. The paper aims to highlight UART’s simplicity, reliability, and
suitability for low-cost, low-speed data transfer applications, while also discussing limitations and
potential improvements in modern embedded systems.

4. Design of UART Communication System Based on Adaptive Baud Rate Technology;

Dong An; Zhouming Guo; Kehan Zhao.
This paper introduces a UART communication system that automatically adjusts its baud rate to match
that of the transmitting device. This adaptive capability enhances compatibility between devices
operating at different speeds, thereby improving communication efficiency. The authors detail the
system's design and implementation, highlighting its ability to dynamically synchronize baud rates
without manual configuration. This approach simplifies the communication setup process and reduces
potential errors associated with baud rate mismatches.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

PROPOSED METHODOLOGY

Fig - 3.1 UART Tx and Rx Block Diagram

The methodology for designing and verifying the UART communication model will include
the following key steps:
1. System Design and Specification:

Define the UART protocol specifications, including data format (start bit, data bits,
parity bit, stop bits), baud rate, and synchronization requirements.
Create a block-level architecture for the UART, including modules for the baud rate
generator, transmitter, receiver, and error-checking mechanisms.

2. Design Implementation:

Implement the transmitter and receiver modules using Verilog HDL.

Develop the baud rate generator for timing control, ensuring proper synchronization
between the transmitter and receiver.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

Fig 3.2 – System Verilog Testbench Architecture

3. Testbench Development:

Design a SystemVerilog-based testbench to verify the functionality of the UART

modules.
Create test cases to simulate various scenarios, such as single-byte and multi-byte data
transmission, mismatched baud rates, and parity errors.

4. Simulation and Verification:

Use simulation tools (e.g., QuestaSim or ModelSim) to verify the design under different
operating conditions.
Validate the UART protocol’s compliance with specifications by analysing simulation results
for data integrity, synchronization, and error handling.

5. Documentation and Analysis:

Document the design methodology, simulation results, and key performance metrics. Analyse
the system’s reliability, scalability, and suitability for modern embedded applications.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

PROJECT DESIGN AND IMPLEMENTATION PLAN

State Diagram:

Fig – 4.1 State Diagram

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

UART signals and functions of the signals:

Signal Name Direction Description

Tx (Transmit) Output Serial data output from the UART transmitter to the receiving device.

Rx (Receive) Input Serial data input received by the UART from the transmitting device.

Baud Rate Clock input used to set the baud rate for synchronization between
Input
Clock
transmitter and receiver.

The actual data bits being transmitted or received during the

Data Bits Bidirectional
communication process.

Indicates the start of a data frame and signals the receiver to prepare for
Start Bit Output
incoming data.

Signals the end of a data frame, allowing the receiver to reset for the
Stop Bit Output
next frame.

Used for error checking in the transmitted data frame (optional,

Parity Bit Output
depending on configuration).

Enable Input Activates the UART module to begin transmitting or receiving data.

Indicates errors such as framing errors, parity errors, or buffer

Error Flag Output
overflows during communication.

Signals that the UART is ready to transmit or that valid data is

Ready/Valid Output
available to be read.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

EXPECTED OUTCOMES

1. Successful Serial Data Transmission:

o Accurate conversion of parallel data into serial format by the transmitter.

o Reliable reception of serial data by the receiver and reconstruction into parallel format.

2. Synchronization:

o Proper alignment between transmitter and receiver based on pre-configured baud rate.

3. Error Handling:

o Effective detection and indication of errors such as parity errors, framing errors, or
mismatched baud rates.
4. Simulation Results:

o Validation of data integrity during single-byte and multi-byte transmissions.

o Correct handling of error scenarios with appropriate flags or notifications.

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DESIGN AND DEVELOPMENT OF UART USING SYSTEM VERILOG

REFERENCES

1. Design and Implementation of High-Speed Universal Asynchronous Receiver and

Transmitter (UART), Ashok Kumar Gupta; Ashish Raman; Naveen Kumar; Ravi Ranjan.

2. Design and Verification of UART using System Verilog; Yamini R, Ramya M V.

3. Analysis of UART Communication Protocol; Pranjal Sharma; Anup Kumar; Naresh Kumar.

4. Design of UART Communication System Based on Adaptive Baud Rate Technology;

DongAn; Zhouming Guo; Kehan Zhao

Signature of Guide
Janardhana S Y
Assistant Professor
Department of ECE
PESCE, Mandya

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