An Efficient Implementation of Edge

Detection Algorithm For Image Processing

Using FPGA
Kishor Kumar Dr Vijaya Lakshmi. D
(MTech in VLSI and Embedded System, BIT Bangalore) (Assistant Professor, Dept of ECE, BIT Bangalore)

true edges and false edges, true edges are those which are
Abstract: Edge detection is an important and growing area in correct and needed edges whereas false edges are unwanted
different fields such as image pattern recognition, machine or due to noise-formed edges and due to sensitiveness of a
learning and processing, and Computer vision. Edge detection detector. An edge detection algorithm generally has 3 steps
of an image of the object is the main goal for different Edge
detection algorithms. In Edge detection, the most important
they are: filter, enhancement, and finally detection. first step
step is to identify the edges of an image of the object and pixel Filtering is a process basically to eradicate the noise from
information of the Image In every edge detection algorithm. the input image. The second step is for magnifying the
There will be 2 types of masks one in the horizontal direction image pixel intensity values in enhancement so that we can
and the other in the vertical direction. The kernel or mask is a detect strong and meaningful edges. Nowadays as the
convolution vector of the nXn matrix which is multiplied by the technology is growing as well as the research on Artificial
sub-window of an image. The effective and efficient
performance of a digital system mainly depends on the delay,
Intelligence computer visioning and in the mobile industry
area, and power consumption. These parameters decide the for figure print, pattern recognition in these fields of edge
efficiency of any digital core system. This project converts the detection is becoming more important. Therefore, an
image pixel information to binary for processing with different effective edge detection algorithm is very important. There
edge detection algorithms like Canny, Sobel, Prewitt, and are different kinds of edge detection algorithms mainly
Roberts. The algorithms are then simulated and synthesized on Roberts, Prewitt, Sobel, and canny where it comes to
FPGA with the targeted device xc3s4000-4fg900. The input
image with resolution 256X256 is given as input to the performing speed, area and power consumption the Sobel
MATLAB version 2014a. The MATLAB code converts image edge detection algorithm has the upper hand as the
pixel intensity information to binary form as hardware input computation complexity is less and is widely used in the
can only be in binary not the pixel intensity information, so we more applications when its smooth and enhanced image
use MATLAB software to convert pixel intensity information canny has the upper hand but as its computational
to a hexadecimal value which is given as input to the model sim complexity is complex.
version 6.4a. The Different edge detection algorithm like Sobel,
Canny, Prewitt, and Robert is implemented using Verilog
HDL, the model sim is used for simulation, and synthesis is
performed using Xilinx software. The design parameters II. PROBLEM STATEMENT
results obtained for different edge detection algorithms are
compared, The Generated text file is sent to MATLAB The optimization of design parameters is the key
software for the extraction of edges. and synthesis is performed requirement that is considered in designing a digital system.
in the Xilinx platform to generate a synthesis report for RTL In the core image processing blocks, the major part is of the
schematic and Technology Schematic with a target device computational units basically multipliers, So the multiplier
xc3s4000-4fg900. The Proposed methodology gives better requirement leads to more area, power, and delay. As edge
performance with fewer lut’s of 119, slices 77, gates 1736, detection is based on basic matrix multiplication. Nowadays
overall delay 28.121ns, gate delay 15.304ns, and path delay as improvement in the technology is gradually growing
12.817ns along with 0 block ram and 0 distributed ram. where it needs to meet the performance requirement, in the
Keywords: FPGA, HDL, MATLAB, pixel, sub-window,
recognition, Xilinx.
applications like satellite monitoring, vehicle monitoring,
and medical fields speed is important where in these places
edge detection of an object is very important with faster
I. INTRODUCTION
response.
Edge detection has many edge detection algorithms which
can be used for image processing applications successfully.
In edge detection methodology we determine the maximum III. OBJECTIVE
or abrupt change in pixel intensity in an image, these
1. To design an efficient modified Sobel edge detection
changes in image pixel intensities are is indicated or algorithm using Verilog HDL for edge detection to
identified by different edge detection algorithms, depending reduce area, the computational complexity along with
upon the salient features of an object the edges of an object increased processing speed, and the reduced power
are detected and also edge detection algorithms will remove consumption
the redundant parts from an image. After the edge detection 2. To perform synthesis of the proposed Sobel edge
mechanism, the output of these edge detector edges is detection along with canny, Roberts, and Prewitt edge
classified into 2 types detection algorithm and analyze the delay, area, and
power consumption design parameters.
3. To implement the proposed Sobel edge detection v. Edge Detection By Sobel Operator
algorithm in an image processing application. Like
biomedical and satellite images, comparing the design For a Sobel Edge Detector, there are basically 2 types of
parameters of Sobel, Canny, Prewitt, and Roberts. masks or kernals, first is kernal which is shown in figure
4(a) gives us an edge in the horizontal direction when we
convolve with the 3X3 sub-window of an image which is
IV. PROPOSED METHODOLOGY
shown in figure 4(b). in the way, the second kernal in figure
A. Proposed Methodology Flow Diagram 4(a) gives the edges in the horizontal direction when we
The below diagram, as shown in figure 1 represents the convolved the second kernal with the 3X3 sub-window of
flow of the proposed methodology. The description of each an image.
block is discussed below

(a) (b)
Figure 1:Methodology Flow Diagram Figure 4:(a) Sobel Operator Masks(b) Example 3X3 Sub
window of Image
i. Load Image
The first step is to select the RGB image in JPG image Figure 5 shown below represents the convolution of the
format as an input image for the MATLAB code. The source image sub-window with the kernal then we obtain a
image(451x300) shown in figure 2(a) is selected as an input convolved image nothing but edge detected image.
image in this proposed methodology
ii. Resize Image
the MATLAB code will convert the image for an equal
resolution of 256X256 this is done by the resizing
mechanism in MATLAB. The converted image from the
resolution of 451x300 to 256x256 image is shown in figure
2(b).
iii. RGB To Gray Image
the resized image is then converted to the gray image as
shown in figure 2(c), the MATLAB process. This
conversion is done for reducing the memory size for
processing the data in the model sim.

Figure 5:Edge Detection Using Sobel Operator

The flow diagram for the proposed architecture is

represented in figure 6. The flow starts with aligning the
input image and then multiplying it with kernal using shift
operator and adders. This image is further compressed from
9 source pixels (obtained after convolving 3x3 matrices) to
1-pixel information. The obtained pixel information is
(a) (b) (c) compared with the threshold voltage. If greater than the
threshold value
Figure 2:(a) Input image, (b)Resized Image, and (c)Gray output is high else low.
Image
iv. Conversion To Binary Number
Then this gray pixel intensity information of an image is
converted to binary form and stored in the text file as shown
in figure 3. And this text file is given as input to the model
sim platform,

Figure 3: Hexadecimal
Texfile for an image
Figure 6:Flow diagram for the Proposed architecture
 V. TOOLS USED
The flow in figure 6, is explained in detail in figure 7. The
1. MATLAB
clock reset and start are the global signals which are applied
a. To convert the RGB input image to a
for all the blocks as we consider the 3X3 subblock of the
resizable image
image window as it consists of the 9 pixels with different
b. To convert resizable image to gray image
intensity values all these signals are input and these pixels’
c. This gray image consists of pixel intensity
information is given as input to the gy vertical gradient and
information this is converted to hexadecimal
gx horizontal gradient are calculated without any matrix
numbers and also vice versa.
multiplication instead we used the only adders and, shift
2. Xilinx
operators so it leads to very minimum area efficient.
a. To get a synthesis report which consists area
Then all these gy and gx is given as input for the gx_abs and
analysis report, power analysis report, and
gy_abs to get the absolute values
timing report
i.e depending upon the msb bit gy and gx respectively for
b. To view the RTL schematic and as well as the
the gx_abs and gy_abs is its msb bit is 1 then gives an
technological schematic
output of 2’s complement else gives output the as same
value.
3. Model Sim
Sum value is calculated on the summation of gx_abs and
a. To briefly the functionality
gy_abs then this output is transferred to the checkered part
b. To view the waveforms
of the value is about the threshold, then the value of output
dxy will be 1 i.e., respective central pixel else value of that
respective pixel will be zero. This way with less
computational complexity the working of the Sobel edge VI. RESULTS
detector takes place with a better performance compared to The simulations of the designed Sobel edge detector with
the conventional approach. the usage of appropriate adders and shift registers are
obtained as observed in the following waveforms. The
simulation outputs of the approximate Sobel edge detector
are as follows as seen in the following snapshots in figure 9.

Figure 7:Proposed architecture

vi. Image Conversion from Text

After getting the output from the proposed architecture
flow diagram we get the following file where 0 represents
low and 255 represents high. This output is obtained from Figure 9:Sobel Edge Detector Simulation Result
the model sim tool. These values are then fed to the
MATLAB tool which processes this file to produce an edge
detected as shown in figure 8. The above figure shows a second instance of the Sobel edge
detector with inputs c1, 24, a1, af, 15, ce, 5a, 05, and 53. On
the clock signal set high, along with reset low and start
signal high, the intermediate signals to calculate
approximate expressions are initially get computed, and then
finally, the approximate product is calculated. The
approximate output is observed to be 0 while the exact
output equals some number below the threshold.

The output summary of constraint values in the designed

Sobel, Canny, Prewitt, and Robert is as follows as shown in
table 1. The comparison of synthesis results of the design
Figure 8:Edge Detected image TextFile
constraint parameters such as delay, frequency, and slices in
the Generic to the proposed Sobel edge detector is tabulated
as seen in Tables 2 and 3. From the comparison and analysis
of values in Tables 1, 2, and,3, the proposed Sobel edge
detector with only an adder and shift register proves to be
better performing both with regard to its processing speed
and area consumption. The proposed Sobel edge detector
delay was almost reduced to 1.2 times the delay of the
Generic Sobel edge detector. The number of slices LUTs
and their occupation in the proposed multiplier has also
greatly decreased in the suggested approximate Sobel edge (b)
(a)
detector comparatively as observed in table 3.

Table 1:Comparision of Different Edge Detection

Algorithms

Parameters Sobel Robert Prewitt Canny

Delay 28.121ns 33.229 ns 30.745 ns 33.115

ns

Frequency 35.6MHz 30.09MHz 32.52MHz 30.1MHz

LUTs 119 266 306 634

Table 2:Comparison of Delay for Generic and (c) (d)

Proposed Sobel Edge Detectors
Figure 10:(a) Prewitt Edge Image (b) Canny Edge
Elements Total Delay Logical Delay Routing Delay Image(c)Sobel Edge Image and(d) Robert Edge Image
Generic 31ns 18.5ns 12.5ns
Sobel
Proposed 28ns 15ns 12 ns Figure 11(a)and11(b) is a RTL schematic and technological
Sobel schematic view of the Sobel edge detector design where is a
block view only signals can be viewed i.e. imp11, imp12,
Table 3:Comparison of Area for Generic and Proposed imp13, imp21, imp22, imp23, imp31, imp32, imp33 are the
Sobel Edge Detectors 8bit input for the block and clk, reset and start are one bit
global signals these are provided from the user during
Elements No of No of No of gates No of IOBs testing where only one 8 bit output dxy. in the inner circuitry
Luts slices
Generic 306 157 3761 182 view all these are i.e. RTL is the image of the design
Sobel independently of the FPGA circuit i.e. technology
Proposed 119 77 1736 75 independent is RTL.
Sobel

The figures in the proposed methodology-2(a), 2(b), and

2(c) shows 2(a) input image 2(b) resized images utilizing
2(c) gray image, and10(c) Sobel operator utilized only
adders and shift operators where PSNR=8.42 for Sobel
10(b) PSNR=8.00 for canny 10(d) PSNR=5.21 for Robert
10(a) PSNR=8.3 for Prewitt and for Sobel with proposed
approximate multiplier where PSNR=8.42. The input image
and output edge detected images after applying the Sobel
edge detection algorithm that utilizes the accurate and the
designed approximate Sobel operator in its operation are (a)
observed. With observation and analysis of the resultant
output images, despite the fact that the approximate result is
made use of, the designed Sobel edge detector, the
difference cannot be recognized in the quality changes of the
output image from the user level. There is the trivial quality
of a change measured in terms of PSNR value. between the
exact and all other edge detectors and the approximate Sobel
edge detector image processing application. Hence, because
of the restricted perceptiveness of the user in noticing
quality difference variation in images, usage of
approximation computations reducing computational (b)
complexity benefits speed and area.
Figure 11:Schematic (a) RTL (b) Technological
 VII. CONCLUSION [12] B. R. Gaines, “Stochastic computing systems,” in Advances in
Information Systems Science, J. T. Tou, Ed. New York, NY, USA: Springer,
This project mainly focuses on the simulation of the 1969, pp. 37–172.
design of the Sobel edge detection algorithm along with
other edge detection algorithms for a better more realistic [13] P. Li, D. J. Lilja, W. Qian, K. Bazargan, and M. D. Riedel,
comparison. The proposed Sobel edge detection algorithm “Computation on stoch astic bit streams digital image processing case
studies,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3,
uses two kernal which is of 3×3 convolution masks to pp. 449–462, Mar. 2014.
determine the edges along x and y direction and where in
this project results are shown with reduced area power and [14] Dr. R.Menaka Dr. R.Janarthanan Dr. K.Deeba, “FPGA
implementation of low power and high-speed image edge detection
latency for the Sobel edge detector and compared with all
algorithm,” Science Direct, 2020.
other edge detection Sobel proves to be more efficient and
effective in terms

VIII. FUTURE SCOPE

• The Sobel edge detection proposed can also be
extended to higher order image resolution where the
performance of the Sobel edge detector is better, including
the area and speed constraint parameters can show great
improvement in comparison with the conventional Sobel
edge detectors.
• The performance of the Sobel edge detector can
further be improved by applying pulse width modulation,
and time-encoded signals.
• The usage of a more efficient adder and multiplier
unit for obtaining better area utilization further can be
considered to better the overall proficiency of the system.

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