IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO.

5, MAY 2011 1059

A Fully-Integrated 16-Element Phased-Array

Receiver in SiGe BiCMOS for 60-GHz
Communications
Arun Natarajan, Member, IEEE, Scott K. Reynolds, Member, IEEE, Ming-Da Tsai, Sean T. Nicolson, Member, IEEE,
Jing-Hong Conan Zhan, Member, IEEE, Dong Gun Kam, Senior Member, IEEE, Duixian Liu, Fellow, IEEE,
Yen-Lin Oscar Huang, Alberto Valdes-Garcia, Member, IEEE, and Brian A. Floyd, Senior Member, IEEE

Abstract—A fully-integrated 16-element 60-GHz phased-array rates. The 60-GHz band has 9 GHz of available bandwidth and
receiver is implemented in IBM 0.12- m SiGe BiCMOS tech- can support short-range high data rate wireless links. Therefore,
nology. The receiver employs RF-path phase-shifting and is over the last five years there has been increasing research and
designed for multi-Gb/s non-line of sight links in the 60-GHz
ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end in- commercial development of integrated circuits for 60-GHz
cludes variable-gain LNAs and phase shifters with each front-end wireless links. At 60 GHz, the 5-mm wavelength implies a
capable of 360 variable phase shift (11.25 phase resolution) path-loss of 82 dB (assuming path-loss exponent of 2) for a
from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed 5 m wireless link and the signal is attenuated further by any
analysis of the noise trade-offs in the receiver array design is obstructions between the transmitter (TX) and receiver (RX).
presented to motivate architectural choices. The hybrid active
and passive signal-combining network in the receiver uses a
This attenuation is material dependent, e.g., the signal is attenu-
differential cross-coupled Gysel power combiner that reduces ated by more than 20 dB when a person stands between the TX
combiner loss and area. Each array front-end has 6.8-dB noise and RX and 10 dB when there is a 1-cm-thick wooden barrier
figure (at 22 C) and the array has 10 dB to 58 dB programmable between TX and RX. Fig. 1 outlines an example link budget
gain from single-input to output. Sixteen 60-GHz aperture-cou- for a 60-GHz system with obstructions, assuming typical in-
pled patch-antennas and the RX IC are packaged together in
tegrated RX performance [1]–[4]. The desired signal-to-noise
multi-layer organic and LTCC packages. The packaged RX IC is
capable of operating in all four IEEE 802.15.3c channels (58.32 ratio (SNR) is assumed to be 25 dB. With the line-of-sight
to 64.8 GHz). Beam-forming and beam-steering measurements (LOS) signal attenuated by 20 dB, the required transmitter
show good performance with 50-ns beam switching time. 5.3-Gb/s EIRP for a 5 m link is 53 dBm (assuming RX noise figure of
OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated 7 dB). Using high-gain antennas in the TX and RX can reduce
using the packaged RX ICs. Both line-of-sight links ( 7.8 m the required TX output power to achieve desired EIRP—for
spacing) and non-line-of-sight links using reflections ( 9 m total
path length) have been demonstrated with better than 18 dB example, 20 dB gain antennas in the TX and RX reduces the
EVM. The 16-element receiver consumes 1.8 W and occupies required PA output power to 13 dBm, which has been achieved
37.7 mm of die area. on-chip [5]–[7]. However, 20-dB antenna gain corresponds to
Index Terms—Beamforming, BiCMOS, millimeter-wave, noise, a beam width of 17 , which can be insufficient for applications
phased array, power combiners, power splitter, receiver, RF-path where the location of the transmitter or receiver is not fixed.
phase-shifting, SiGe, WiGig, 60 GHz, 802.11 ad, 802.15.3 c. Increasing the beam width implies lower antenna gain, and
therefore, higher TX output powers to achieve the same EIRP,
making it difficult to integrate the power amplifier on silicon.
I. INTRODUCTION Phased arrays are an excellent solution to this challenge

E MERGING mass-market applications such as wireless since they emulate a high-gain antenna by providing array
high-definition video links and wireless data transfer gain, while also allowing for the directional beam to be steered
between hard drives and computers require multi-Gb/s data using on-chip phase shifters. Using a phased-array RX and TX,
the wireless link can be established by using reflections from
features such as walls and ceilings. In this case, the reflective
Manuscript received September 02, 2010; revised February 11, 2011; ac- loss for the first reflection is assumed to be 10 dB based on
cepted February 11, 2011. Date of current version April 22, 2011. This paper measurements in a typical office environment [8]. Assuming
was approved by Guest Editor Yuhua Cheng. that a 16-element phased-array transmitter provides 24-dB
A. Natarajan, S. K. Reynolds, D. G. Kam, D. Liu and A. Valdes-Garcia are
with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA
improvement in EIRP (due to spatial power combining) and
(e-mail: [email protected]). that a 16-element phased array receiver has 12 dB higher SNR
M.-D. Tsai, J.-H. C. Zhan and Y.-L. O. Huang are with MediaTek Inc., at the output, the target 25-dB SNR can be achieved for the
Hsinchu 300, Taiwan.
S. T. Nicolson is with MediaTek Inc., San Jose, CA 95134 USA.
geometry in Fig. 1 when each TX element in the 16-element TX
B. A. Floyd was with the IBM T. J. Watson Research Center, Yorktown array generates 11 dBm. The required power can be generated
Heights, NY 10598 USA. He is now with the North Carolina State University, by on-chip PAs, making full silicon integration of transmitter
Raleigh, NC 27695 USA.
Color versions of one or more of the figures in this paper are available online
and receiver possible.
at http://ieeexplore.ieee.org. Phased-array beam-steering capability requires multiple-
Digital Object Identifier 10.1109/JSSC.2011.2118110 element RX and TX array with on-chip variable phase shifters,

0018-9200/$26.00 © 2011 IEEE

1060 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 1. An example link budget for single-element and phased-array 60-GHz wireless links.

variable gain stages, and combining and distribution circuits, architecture in [1]. The on-chip PLL, described in [14], gen-
leading to system and circuit complexity. Such mm-wave erates the LO signals for the channel frequencies specified
phased arrays have been demonstrated at 24 [9], 77 [5], 40 in IEEE 802.15.3c [12] (58.32 GHz, 60.48 GHz, 62.64 GHz,
[10], and 60 GHz [6], [7], [11]. Silicon integration allows the and 64.8 GHz) from a reference at 308.5714 MHz. The re-
complex system to be realized with high-yield and enables ceiver frequency plan is also compatible with other 60-GHz
high-volume applications such as wireless high-definition standards such as ECMA [15], WiGig, and WirelessHD, all
video links and multi-Gb/s data transfer. of which mandate the same channel frequencies. The on-chip
In the following sections, a 60-GHz phased-array receiver 16-to-18.6-GHz tuning-range VCO drives a frequency-tripler
targeted for multi-Gb/s wireless links is described. (A com- that provides the LO signal for the first downconversion (specif-
panion fully-integrated 16-element phased-array transmitter ically at 49.99 GHz, 51.84 GHz, 53.69 GHz, and 55.54 GHz).
was also designed and is described in [6]). The IC is designed in The sliding-IF frequencies are 8.33 GHz, 8.64 GHz, 8.95 GHz,
the 0.12- m IBM SiGe BiCMOS technology ( GHz; and 9.26 GHz, and a programmable resonant load in the IF
285 GHz) and supports non-line-of-sight (NLOS) amplifier (with fixed inductor and variable capacitors), keeps
wireless communication in all four channels in the 60-GHz its performance centered. A divide-by-two frequency divider
band, in accordance with the IEEE 802.15.3c standard [12]. generates in-phase and quadrature-phase LO signals which
Section II describes the architecture of the 60-GHz 16-element are applied to programmable phase rotators that drive the
phased-array RX, focusing on array output noise and SNR. downconversion mixers, allowing for quadrature phase error
Section III discusses the circuits in the array RX and includes correction. Finally, baseband channel-select filters were not
block-level measurements. Probe-based full-chip measure- included in this design, but were fabricated stand-alone for
ments are detailed in Section IV. The RX IC was packaged evaluation.
with 16 patch antennas on organic and LTCC substrates [13]
and beam-pattern and beam-steering measurements were per- B. RF-Path Phase-Shifting
formed in an antenna chamber. The packaged RX array IC
was also tested in conjunction with the packaged phased-array Integrated mm-wave phased-arrays have been demonstrated
transmitter IC to demonstrate line-of-sight and reflection-based using RF-path [6], [10], [16], LO-path [9] and IF/baseband
links using single-carrier (4.5 Gb/s) and OFDM (5.3 Gb/s) phase-shifting architectures [17]. Low power consumption and
modulation. The results of these phased array beam-pattern and area motivate the selection of RF-path phase shifting and RF
link measurements are presented in Section V. combining, since it requires the least number of parallel circuit
blocks per phased-array element; however, RF phase shifters do
II. ARCHITECTURE result in potential performance degradation due to phase-shifter
loss, noise, and linearity. Both active interpolator-based and
A. Double Down-Conversion Architecture passive reflection-type RF-path phase shifters were considered
The 60-GHz receiver architecture is shown in Fig. 2. The for this design, as detailed in [18]. Key considerations were
frequency plan is similar to the sliding-IF super-heterodyne noise figure, power consumption, and insertion loss versus
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1061

Fig. 2. Fully-integrated 60-GHz phased-array receiver architecture and frequency plan.

phase shift. It was found that with LNA gain of 22 dB and noise from different elements adds incoherently while the
noise figure of 6 dB, subsequent cascaded blocks with noise phase-shifted signals from all the elements add coherently [9].
figure (NF) of 15 dB degrade the front-end noise figure by less Correspondingly, if there is a correlation in the noise sources
than 0.25 dB. This means that either passive reflection-type in the elements, e.g. through antenna coupling [19], biasing
phase shifters (with insertion loss of 8 dB) or active vector circuits or through LO phase-noise (in the case of IF/Baseband
interpolators (with noise figure of 15 dB) can be used in the phase shifting), the improvement in SNR is degraded.
system. Though the noise trade-off between active and passive The noise factor of a receiver is defined as
phase shifters was not significant, the power consumption
is lower with the passive approach, ultimately leading to its (1)
selection for the phased array presented herein.
One challenge with the passive reflection-type phase shifter, In the case of an -element phased-array receiver, the ap-
though, is the dependency of phase-shifter loss on phase-shift plication of (1) is not straightforward, as it depends on whether
setting. This variation of loss with phase shift arises from the the input SNR is defined for a single-element or for the com-
use of a varactor in the passive phase shifter which has a rela- plete array. A single-element definition for is applied to
tively low and variable quality factor (3 to 8 @ 60 GHz). Ideally, the noise factor equation, as follows:
amplitude and phase shift would be independently adjustable in
the array, allowing for simple pattern synthesis. In this work, a (2)
variable-gain amplifier (VGA) was added following the passive
phase-shifter to compensate for the insertion-loss in the phase
shifter and to allow additional amplitude control for pattern syn- where the 1:N subscript refers to the fact that a single element
thesis. Furthermore, a discrete 180 phase shift can be easily input is taken with respect to an N-element output. Following
achieved in the VGA, which has the benefit of reducing the vari- the coherent-combining argument in the previous paragraph,
able phase-shift range required from the passive phase-shifter the output SNR can be times higher than the single-element
to 180 . The lower variable phase-shift range reduces phase- output SNR, potentially leading to (negative noise
shifter loss. Therefore, a hybrid passive-active RF-path phase figure in dB). For example, if the noise is dominated by
shifting approach was adopted as shown in Fig. 2. front-end noise

C. Array Noise and RF-Combining (3)

In the following, the SNR at the output of the array and array
output noise are used to analyze the RX array performance. The where is the front-end noise figure. In this case, ,
SNR at the output of an ideal -element phased-array with when . In (2), the numerator ignores the multiple re-
unit antenna gain , perfect isolation between elements, and ceive elements that form the array. In order to consider the in-
noiseless combining, is times higher than the SNR at the puts to all receiver elements, the concept of total array aperture
output of an equivalent single-element receiver with antenna is leveraged. In [20], a formulation for the SNR improvement
gain . Physically, this improvement occurs because the in an array is developed using the effective aperture area of the
1062 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 3. Simplified block diagram of a phased-array receiver with gain, noise and loss of receive chain blocks.

-element phased array. With elements in the array, the an- The RF-combining network in the array can be passive or
tenna aperture is times that of a single-element and the noise active—power dissipation and linearity constraints favor a full
factor of the array, is defined as passive-combining approach. Isolation between the inputs to the
combiner is preferable to accommodate array operation with a
(4) subset of elements turned on and to ensure that the phase-shift
settings of each element are independent of the state of other
The total noise at the output of the array will include (ideally) elements. Fig. 3 shows a simplified block diagram of the array
uncorrelated contributions from the front-ends in the array, with gain, noise figure and insertion loss of different blocks in
noise due to losses in the combination network, and correlated the array with the passive combiner loss lumped into the loss
noise arising after the combination and downconversion net- of the interconnect t-lines. In an ideal 3 dB combiner (e.g. an
work (e.g., in the mixer for an RF-combined array). If LNA gain ideal 3-dB Wilkinson-type combiner), when an input is applied
is high, the SNR at the output of the phased array is close to to only one of the input ports with the other input port terminated
but less than where is the SNR in a matched load, the output is 3 dB lower than the input. For a
at the output of each front-end. The effects of downstream loss 16-element array receiver, with passive combiners at each of the
and correlated noise can be encapsulated in an “array efficiency four stages of combining, the downconverter noise represents
term”, , as follows: more than 60% of the output noise when only one array ele-
ment is on, leading to poor noise performance (array efficiency
(5) of 0.27). Noise from the RF front-ends starts to dominate the
output noise as more elements are turned on; however the array
where . Combining (4) and (5) results in
efficiency for the cascade of blocks in Fig. 3 is 0.75 with eight
(6) elements on and 0.86 with all 16 elements on.
In this work, an active combiner was used in the third stage
of combining to improve array efficiency with a subset of ele-
In this formulation, as the gain of the RF front-end in each el-
ments on. With an active combiner gain of 2 dB and noise figure
ement increases, the array efficiency increases and hence
of 7 dB from each input to the output, the array efficiency im-
approaches the RF front-end noise figure (ignoring antenna-
proves to 0.51 with one element on, 0.90 with eight elements
coupling). In practice, power consumption trade-offs and device
on, and 0.95 with all 16 elements on. The differential cross-cou-
performance limit the RF front-end gain at 60 GHz, resulting in
pled Gysel passive-combiner network (described in Section III)
smaller as the array noise figure is sensitive to the loss and
adopted also reduces passive combining loss by reducing the
noise in the combining network and the downconversion chain.
length of the signal-routing t-lines, improving array efficiency
One benefit of the approach detailed above is that system-level
across different operation modes.
noise analysis is handled by considering the phased array as
being equivalent to a single receiver with noise factor , and
antenna gain of . It must be noted that the gain of the III. CIRCUITS AND BLOCK-LEVEL MEASUREMENTS
equivalent receiver is times the gain from each element to the
output. Compared to a single-element receiver with small unit A. RF Front-end
antenna gain, using multiple elements provides a technique to In the RF-path phase shifting architecture, each element must
achieve better sensitivity in the receiver while the beam steering be able to achieve 360 variable phase shift across the frequen-
capability allows for a wide field-of-view. cies of interest (57.2 to 65.9 GHz), while providing low noise
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1063

1) 60-GHz Low-Noise Amplifier: The single-ended 60-GHz

LNA (Fig. 4) has four stages and provides 2 bits of coarse gain
control. In the packaged system, the antennas are connected
to the LNAs through 50 traces on the package and con-
trolled-collapse chip connection (C4) flip-chip interconnect.
Therefore, the LNA input match is designed using models for
the C4 solder bump interconnect that were developed with EM
simulations. The simulations demonstrate 0.5 dB loss for the
single-ended ground-signal-ground C4 interconnect between
the IC and traces on the package. The LNA employs current
reuse in Stage 1 and Stage 2 similar to the design in [1]. Stage 3
and Stage 4 provide coarse gain step using an alternate signal
path [21]. When switch is high, Stage 3 of the LNA is in
high-gain mode. In this mode, the transistor is activated and
the path through transistor and is deactivated. In this
case, the transconductance of the combination of and ,
, is

(7)

where and are the transconductances of and

and is the base-emitter capacitance of . In low-
gain mode, switch is low which disables and enables
transistors and . The RF current from is divided be-
tween and . Furthermore, in the case of , there is a
voltage division between the capacitor at the base, , and the
base-emitter capacitance, . Ignoring parasitics, the admit-
tance looking into the cascode node in the low-gain mode, ,
is the sum of the parallel admittances looking into the emitters
of and

(8)

where and are the transconductances of Q2 and

Q3 respectively and and are the base-emitter
capacitances of and . The effective transconductance of
the combination of , , and in low-gain mode is given
by

(9)

When compared to (7), the RF current division between and

, along with the capacitive division at the base of re-
Fig. 4. Schematics of 60-GHz phased-array RF front-end circuits. (a) 60-GHz
sult in lower gain in (9). This switched-gain technique is im-
phased-array RF front-end. (b) 60-GHz LNA with switched-gain. (c) Reflection- plemented in Stage 3 as well as Stage 4 and provides nearly a
type phase shifter. (d) 60-GHz Lange-Lange balun. (e) Phase-inverting variable- dB-for-dB trade between gain and compression point for each
gain amplifier.
stage. The dummy transistor, , also reduces the difference
between in the high gain and low modes, which was nec-
essary in versions of the LNA that included a notch filter in the
figure and sufficient linearity. The RF front-end in each ele- cascade node for image rejection (used in single-element Rx).
ment consists of a 60-GHz variable-gain low-noise amplifier Measurements show that across the LNA gain settings the LNA
(LNA) followed by a reflection-type phase shifter (RTPS) that gain is 24, 16, 7, and 1 dB and the noise figure is 5.6, 6.8, 5.8
provides 180 of phase shift (Fig. 4). The phase-inverting vari- and 9.4 dB. When the LNA gain is reduced from 24 dB to 16 dB,
able-gain amplifier (PIVGA) following the RTPS provides a the measured improves from 28 dBm to 21 dBm. For
discrete 0/180 phase shift as well as variable gain in fine steps. the lowest LNA gain setting of 1 dB, the is 9 dBm.
Each RF front-end element occupies 1.7 mm by 0.65 mm. The LNA consumes 12 mA from 2.7 V.
1064 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 5. Measured 60-GHz reflection-type phase-shifter loss and phase shift

across control voltage [20].
Fig. 6. Measured PIVGA gain variation—PIVGA is capable of providing
6 dB of gain variation in 0 and 180 modes.

2) Reflection-Type Phase-Shifter (RTPS): The passive

RTPS at 60 GHz incorporates a Lange coupler with an opti-
mized reflective load (Fig. 4) [18], [22]. The phase shift from for RTPS gain variations) as well as a discrete phase shift of
input to output is varied by varying the varactors, and , 180 (Fig. 4). An earlier implementation of the PIVGA used a
jointly. As mentioned in Section II, the RTPS must provide tanh stage to generate the cascode transistor base voltages from
180 phase-shift variation across the band. Fig. 5 shows the the control voltage, thereby linearizing the gain response with
measured RTPS phase shift and loss across control voltage respect to control voltage [21]. This technique, however, dis-
settings [18]. The RTPS phase resolution is limited by the played temperature and process sensitivity in simulation. There-
resolution of the DAC providing the control voltage across fore, the PIVGA in this work uses a negative-feedback control
the varactors. In this receiver, a 6-bit voltage DAC was used scheme to linearize the gain response with respect to the control
to generate the control-voltage. The nonlinear relationship voltage. The scheme senses the dc current difference between
between control-voltage and phase-shift (Fig. 5) results in transistor and and forces it to be equal to using a
11.25 phase resolution in the RTPS with 4 max error (The negative feedback loop. is generated from a 3-bit current
PIVGA following the RTPS provides 1 bit phase control (0 or DAC with one extra bit that ensures maximum gain by making
180 phase shift), resulting in overall 5-bit phase resolution in all the RF current flow through or . The measured variable
the array). The quality factor of the varactors in RTPS varies gain control in the PIVGA at 60.18 GHz in 0 and 180 mode
from 3 to 8 at 60 GHz. The resulting loss variation across is shown in Fig. 6. The negative-feedback scheme reduces the
phase shift settings in the RTPS (Fig. 5) is undesirable as it impact of mismatch between and , thereby reducing the
results in amplitude mismatch between elements (each element sensitivity of the gain control to temperature and process varia-
of the array will have a different phase shift setting to steer tions. Note that all circuits in the receiver following the PIVGA,
the beam in a particular direction). The loss also implies that i.e. the combiners, RF mixer, IF mixer, and baseband circuits are
cascading two RTPS to achieve 360 phase variation leads differential.
to phase-shifter loss varying from 8 dB to 15 dB depending
B. RF Combining
on phase-shift setting. Therefore, a phase-inverting VGA was
designed to achieve both 180 phase shift and fine variable The signals from 16 elements are combined in a binary
gain to compensate for RTPS loss. Measurements on the RTPS scheme in four stages: two stages of passive combining using a
across a wafer show rms phase shift variation of 2.7 , while cross-coupled Gysel combiner, followed by an active combiner,
the maximum relative phase-shift variation from 10 C to 85 C with a final passive combiner driving the differential RF mixer.
is 9 . These measurements indicate repeatable RTPS perfor- 1) Differential Cross-Coupled Gysel Combiner: The signals
mance, allowing for the relative phase shift in an element to be from all 16 elements in the receiver must be combined before the
set without any need for chip or element calibration. RF mixer. In addition to small area and insertion loss, the com-
3) Phase-Inverting Variable Gain Amplifier (PIVGA): The biner must also provide isolation between different elements
LNA and the RTPS are single-ended, hence a broadband pas- to ensure that the output of an element is independent of any
sive Lange-Lange balun is used to generate a differential signal other element state and to allow the array to operate with only a
(Fig. 4). It consists of two Lange couplers in series with an subset of elements on. Passive transmission-line (t-line) based
open at the through and coupled ports of the second coupler. power combiners such as Wilkinson (single-ended and differ-
The Lange-Lange balun is larger than a transformer (it occupies ential) [23] have been used at mm-wave frequencies. While the
m m) but was chosen because of its large band- Wilkinson combiner satisfies loss, isolation and bandwidth cri-
width and to reduce the sensitivity of the design to EM modeling teria, in a practical Wilkinson combiner layout, the two inputs
errors. Following the balun, the PIVGA uses cascode current have to be close to each other to allow the isolation resistor to
steering to achieve variable gain (at least 4 dB to compensate be connected between them. This leads to long signal routing
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1065

“twist” connection—a resistor of value provides matching

for differential inputs but is effectively open for common-mode
inputs. Therefore, a more complex network is used to present a
load impedance for common-mode inputs as well.
Fig. 7(b) and (c) show an analysis of the structure
for differential and common-mode inputs, demonstrating
matching in odd-mode and even-mode. Here, differential and
common-mode are used to describe the local phase relationship
between the positive and negative signals on the differential
transmission line, whereas even and odd-mode are used to
describe the global phase relationship between the two inputs
to the combiner. There are therefore four cases to consider,
as follows: even-mode inputs with differential signaling (the
“normal” operational mode in the phased-array receiver),
even-mode inputs with common-mode signaling, odd-mode
inputs with differential signaling, and odd-mode inputs with
common-mode signaling.
For differential signaling, the structure is matched for both
odd and even mode inputs as shown in Fig. 7(b). For common-
mode signaling and odd-mode inputs, as shown in Fig. 7(c),
there is effectively an open-circuit input impedance. Since the
output of the PIVGA is differential, the common mode sig-
nals are small and mismatches between PIVGA common-mode
output impedance and the combiner common-mode impedance
have minimal impact on performance.
Fig. 8 shows the simulated and measured performance of the
cross-coupled Gysel combiner. Port 1 and Port 2 are the differ-
ential input ports while Port 3 is the differential output port. The
measurements in Fig. 8 were performed on a breakout and in-
clude the loss of the pads and t-lines feeding the combiner.
2) Active Combiner: As shown in the analysis in Section II,
the array noise performance is adversely affected if only passive
combiners are used in the array. Therefore, an active combiner
is used in the third stage of combining. The combiner consists of
two differential cascode transconductance stages (Fig. 9). The
output currents from the two transconductance stage are added
after the cascode transistors to achieve signal combining. The
Fig. 7. Differential cross-coupled power combiner. (a) Differential cross-cou-
pled-Gysel power combiner. (b) Analysis for differential input. (c) Analysis for output of the combiner is matched to 100 differential load. The
common-mode input. bias of each of the transconductance stages can be varied (not
shown in Fig. 9). In addition, each of the branches can be inde-
pendently turned off by making S1 or S2 low, dividing the array
in a corporate tree-combining structure, resulting in larger area into blocks of four elements. The combiner consumes 17 mA
and higher loss. from a 2.7-V supply. Fig. 10 shows the measurement S-param-
In this design, we use a differential cross-coupled Gysel eters for the active combiner. The combiner 1-dB compression
power-combiner [Fig. 7(a)]. This combiner is based on the point with respect to each input was simulated to be 10 dBm.
Gysel power combiner that allows the two inputs to be located
far from each other [24] which allows the signal routing t-lines C. RF-to-IF Mixer
to be folded into the combiner structure, significantly reducing The combined output power from 16 front-ends is theoreti-
loss and the area required for the combining network area. cally 12 dB higher than in the case of a single-element Rx, as-
In a traditional Gysel combiner, isolation is provided be- suming ideal passive combining. In the present RX, considering
tween the two inputs by connecting a t-line which is one both the passive combiner losses and the gain of the single ac-
wavelength long at the frequency of operation together with tive combining level, the input power to the RX core can be
two absorbing loads in value located at the and higher than 10 dBm. At the same time, the RF-to-IF mixer
positions along the isolation arm. When differential signals can contribute to the overall RX NF, particularly if not all ele-
and transmission lines are used, the length of this isolation arm ments are in use. Thus, the RF-to-IF mixer and the RX core are
can be reduced to only by introducing a cross-connection designed to have wide dynamic range. A simplified schematic
(or “twist”) in the t-line between the inputs, achieving a 180 of the RF-to-IF mixer is shown in Fig. 11; it is a double-bal-
phase shift. The load-absorbing resistor is placed across the anced Gilbert cell with a differential, common-base input stage.
1066 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 8. Simulated and measured differential modified-Gysel S-parameters from one input to output.

tap on a resistive voltage divider. The inset in Fig. 11 shows

the IF switch, which is implemented as a switched emitter-fol-
lower. The RF-to-IF mixer achieves a measured SSB NF of
10.4–11.5 dB over the four IEEE channels, and an input-referred
1-dB compression point of 4 dBm. The LO power requirement
is 4 dBm for optimum performance.

D. IF and Baseband
The IF-signal from the RF-to-IF mixer passes through a
second set of quadrature mixers and is converted to a baseband
signal. A phase rotator between the LO divide-by-two and the
quadrature mixers allows adjustment of the quadrature LO
phases to achieve quadrature accuracy of . The baseband
Fig. 9. Schematic of 60-GHz active combiner used in the third stage of signal passes through a series of coarse (6 dB) and fine (1 dB)
combining. step attenuators and 16-dB fixed gain amplifiers to provide the
required gain range. The attenuation sequence (using the base-
band and IF attenuators, and the RF gain control) is selected
to avoid compressing any internal stages, such that the input
compression point of the overall Rx rises monotonically as the
gain is reduced. The phased-array receiver includes a frequency
discriminator for demodulating up to 2-Gb/s FSK/MSK signals
and an AM detector for demodulating up to 2-Gb/s ASK
modulated signals. The circuits are described in detail in [25].

IV. ON-WAFER PHASED-ARRAY RECEIVER IC

MEASUREMENT RESULTS
The fully-integrated 60-GHz phased-array receiver occupies
6.08 mm by 6.2 mm and the chip includes 1900 NPN and
330K CMOS transistors (Fig. 12). Each of the 16 Rx front-
ends occupies 1.7 mm by 0.65 mm. The chip has extensive dig-
Fig. 10. Measured active combiner differential S-parameters from one input to
ital programmability and the on-chip digital interface can be
output (including t-line and pad losses). read and written in serial and parallel modes. The RF front-
ends include a 32-word register array that can store gain and
phase settings for all elements corresponding to 32 beam direc-
The bias current through each of the legs is nominally 7 mA and tions, enabling fast beam switching. The RX IC also includes
is made adjustable by switch-selecting various values of emitter three temperature sensors located at the eastern edge, western
resistors in the common-base stage. The IF-output RLC load is edge and center of the chip. Two variants of the chip were de-
tuned to the IF in the 8.3–9.3-GHz range, and the center fre- signed: one with pads compatible with probe-based testing and
quency is made adjustable with selectable capacitors. The nom- another with pads that have solder-bumps for flip-chip pack-
inal voltage conversion gain is 15 dB, and the IF output can aging. The circuits in the array were also characterized using
be attenuated in 6-dB steps by switch-selecting the appropriate breakouts containing particular blocks (the individual block-
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1067

Fig. 11. Simplified schematic of the high-linearity RF-to-IF mixer, with an inset showing implementation of the multiplexer used in the output attenuator.

Fig. 12. Fully-integrated 60-GHz 16-element phased-array receiver implemented in IBM BiCMOS 8HP.

level measurements were described in Section III). In this sec- to 65.9 GHz. The cascaded 9-GHz IF amplifier and baseband
tion, on-wafer Rx IC measurements are presented. amplifiers result in a net channel bandwidth of 1 GHz.
Fig. 13 shows the Rx gain across frequency for the four IEEE The input and output compression points of the receiver
channels. The gain is measured by providing an input to a single across different gain settings are shown in Fig. 14. The data
element and taking the output using the differential I signal. were obtained by performing compression measurements
These four curves are swept-IF measurements, obtained for a at each of the gain attenuation settings. The input power levels
constant LO frequency and varying RF frequency. Superim- refer to a single input, but the compression is plotted based on
posed on this plot is the measured RF front-end frequency re- calculations that assume that all 16 inputs are driven at the same
sponse, measured by varying RF and LO together to keep the power level; total input power from all 16 inputs is therefore
IF signal frequency constant. The front-end gain is sufficiently 12 dB higher than shown. The measurements were carried out
broadband to cover all four channels of interest from 57.2 GHz in IEEE channel 2 at 60.48 GHz, where the RX has the highest
1068 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 13. Rx conversion gain in the four IEEE channels and performance of RF
front-end.
Fig. 15. Adjacent channel IIP3, measured by applying tones in channels 2 and
3, and looking for intermodulation products in channels 1 and 4.

Fig. 14. Receiver input and output compression for different Rx gain settings.

gain and poorest compression performance. The RX has an

input-referred compression point of 59 dBm @ 47 dB gain
and 37 dBm @ 20 dB gain.
The RX IIP3 has been measured for both in-channel and ad-
jacent-channel intermodulation. The in-channel IIP3 measure-
ments are consistent with the RX compression characteristics
presented in Fig. 14. Adjacent-channel measurements were per-
formed by applying tones in channels 2 and 3 at 60.58 GHz
and 62.74 GHz, and looking for intermodulation products ap-
pearing in channels 1 and 4. Such a measurement quantifies
the receiver’s ability to reject adjacent-channel interference in a
multi-channel WPAN environment. The present receiver’s adja- Fig. 16. (a) Noise figure of the 60-GHz RF front-end. (b) Receiver noise figure
cent-channel IIP3 is limited by the absence of explicit channel- across gain settings.
select filters in the baseband. However, the limited bandwidth of
the baseband amplifiers and IF-filters does provide 10–15 dB of
adjacent-channel rejection. Fig. 15 shows an adjacent-channel different gain settings. The noise figure is 7.4 dB at the highest
IIP3 of 26.5 dBm with the Rx gain (single-input-to-output) set gain setting, and 11.6 dB when the receiver gain is set to 15 dB.
to 35 dB. Thus, both the range of gain and the location of the gain pro-
Fig. 16(a) shows the noise figure of the RF front-end across grammability allow the Rx array to operate under different gain,
frequency and temperature. In the case of array noise measure- linearity and noise figure requirements. The dynamic range of
ments, the noise at the output of the array is estimated from noise the Rx array, under different gain conditions, can be determined
figure measurements of front-end and downconversion chain from Fig. 14 and Fig. 16(b). Assuming 2 GHz noise bandwidth,
breakouts, along with the noise figure measured when only one the sensitivity at 30 dB Rx gain setting is 86 dBm (assuming
element is active. This noise figure is plotted in Fig. 16(b) for a 12 dB improvement in SNR) while the input-referred is
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1069

TABLE I
RX POWER CONSUMPTION BY BLOCK (AT 2.7 V)

TABLE II
60-GHz PHASED-ARRAY RECEIVER PERFORMANCE SUMMARY

Fig. 17. Two-element array measurements at 60 GHz.

Fig. 18. Rx phase noise, taken in Channel 2 (60.48 GHz) with 60.38 GHz input
signal at 57 dBm, resulting in 100 MHz output tone. Phase noise at 1 MHz compensation as well. Fig. 19 shows the measured IQ phase and
offset is 90.6 dBc/Hz. gain mismatch for four different RX samples before and after
compensation. The mismatch was measured at 10 MHz offset
from carrier in each of the channel frequencies. The phase ro-
44 dBm. Similarly, for Rx 10 dB gain setting, the sensitivity tator and baseband amplifier gain settings that achieved lowest
is 68 dBm and the input-referred is 24 dBm. IQ mismatch varied from sample to sample.
Fig. 17 demonstrates the phase-shift and gain equalization Table I shows the total 1.8 W power consumption of the Rx
performance of the array. In order to measure the phase-shift broken down by block. Each of the 16 RF front-ends consumes
performance of the array, the elements are activated in pairs. about 57 mW, and the two active power combiners 50 mW
The phase and gain setting of one element are kept constant each, for a total of 1.0 W in the RF front-end and power com-
while the phase of the other element is varied. Fig. 17 shows a bining network. The frequency synthesizer consumes 150 mW,
measured 6 dB increase in output power when the signals from and the frequency tripler and associated LO buffer 120 mW.
the elements add in phase. The signals are attenuated by more The Rx core (exclusive of the synthesizer and tripler) consumes
than 20 dB when the signals are combined out-of-phase. 250 mW. Finally, the 50 matched output buffers for the differ-
The phase noise of the receiver was measured by providing a ential I and Q baseband outputs consume a total of 280 mW. The
CW tone (at 60.38 GHz) to the receiver and measuring the phase phased-array receiver performance is summarized in Table II.
noise of the baseband output (at 100 MHz). Fig. 18 shows the
measured phase noise of 90 dBc/Hz at 1 MHz offset. Detailed
V. BOARD-LEVEL MEASUREMENTS OF PACKAGED RX IC
measurements of the synthesizer are described in [14]. Measure-
ments at phase shifter setting 31 (where the slope of the phase 1) 60-GHz Antenna Testbed Measurements for Beam-
shift with respect to control voltage is high) and phase shifter steering: The 60-GHz RX array IC is packaged using both
setting 0 (where the slope of the phase shift with respect to con- multilayer-organic (MLO) and LTCC packages that included 16
trol voltage is low) confirmed that array phase shift settings have antennas [13]. Aperture-coupled patch antennas that included
no impact on the total phase noise. an air-cavity between the antenna and ground plane were used
The chip includes programmable phase rotators in the I and to achieve the desired 9 GHz of bandwidth and high efficiency.
Q LO-path for the second downconversion that allow for com- The measured input return loss of all 16 antennas is better
pensation for IQ phase mismatch (Fig. 2). Independent gain con- than 10 dB in the band of interest. A detailed description of
trol in the I and Q baseband amplifiers enable IQ gain mismatch the 60-GHz patch antennas can be found in [26]. The MLO
1070 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 19. Measured IQ phase and amplitude mismatch before and after on-chip compensation.

Fig. 20. Packaged phased-array receiver and transceiver on evaluation board.

This board was used for pattern and link measurements.

and LTCC packages include 60-GHz microstrip t-lines con-

necting the ICs to the patch antennas. The TX and RX ICs are
attached to the packages using flip-chip technology. Each of
the 28 mm x 28 mm 288-pin BGA packages is then attached to
transceiver evaluation boards (Fig. 20). On-chip temperature
sensors indicate that the IC temperature is 20 C higher than Fig. 21. 60-GHz antenna test chamber—the Rx array evaluation board can be
that of the environment. The packaged RX IC was tested rotated in and for pattern measurements.
in a 60-GHz antenna chamber that is capable of performing
two-dimensional antenna pattern measurements (Fig. 21). The
test-fixture loss was determined using S-parameter measure- output across phase shift settings with two elements on, as
ments and a path-loss exponent of 2 is assumed to determine shown in Fig. 17.
the path loss between the board and the horn antenna (or Fig. 22 shows the improvement in output SNR as a func-
circular-polarized antenna in the case of 2D pattern measure- tion of number of active elements. In this measurement, the
ments). While on-wafer tests show insignificant gain and phase phased-array beam is pointed towards the horn antenna which
offsets between elements, the flip-chip interconnect and the is normal to the array. The phase settings of each element com-
60-GHz traces on the package can introduce systematic phase pensate for the offset measured in the calibration step, while the
offsets between elements. Furthermore, coupling between gain settings compensate for gain variation due to antenna cou-
antennas leads to both antenna pattern and gain mismatch pling and phase shift setting. As expected, the output SNR in-
between elements (in the case of the RX LTCC antennas there creases as more elements are activated. Based on equation 5 in
is 2.5 dB variation in the antenna gain perpendicular to the Section II-C, the SNR improvement is a function of the number
array between the 16 antennas [13]). Gain and phase calibration of elements as well as the array efficiency factor, which in-
of the packaged IC is done by orienting the array perpendicular creases with number of elements. Therefore, the expected SNR
to the antenna in the test-bed. In this position, gain offsets are improvement with all 16 elements active (array efficiency: 0.95)
calculated by measuring the elements one at a time and phase relative to the case when only 1 element is active (array effi-
offsets are calculated by determining the null in the baseband ciency: 0.5), is 14.8 dB. Fig. 22 shows a 14.2 dB improvement
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1071

Fig. 24. Measured phase-shifter transient response.

Fig. 22. Measured SNR as a function of number of active elements.

Fig. 25. Setup for 60-GHz link measurements using phased-array receiver and
companion phased-array transmitter.

between the measurements and theoretical predictions, similar

to the correlation shown in Fig. 23.
As discussed in the companion TX paper [6], the digital core
can be read and written in serial and parallel I/O mode. To deter-
mine the response time of the chip to changes in phase and gain
settings, a 60-GHz input is provided to two of the front-ends
in the Rx IC. Fig. 24 shows the baseband output as the phase
shifter in one of the elements is varied such that the signals
first combine constructively and then destructively. The on-chip
phase-shifter settings change at the rising edge of the Parallel
I/O clock and it can be seen that the baseband output changes
from high (constructive addition) to low (destructive addition)
in 50 ns.
2) 60-GHz Wireless Link Measurements: Fig. 25(a) shows
Fig. 23. Contour plots of theoretical and measured phased-array patterns show the 60-GHz wireless link measurement setup using the pack-
good correlation. aged phased-array RX and companion phased-array TX. In
this setup, the digital baseband is implemented in software
(MATLAB) and includes modulator, demodulator, forward
in SNR, showing 12 dB improvement as expected. The mea- error correction and carrier recovery. The link testing was done
sured SNR improvement is limited by the mismatches between by creating data frames using the software, that were provided
the antennas and the accuracy of gain calibration and phase to the high-speed Arbitrary Waveform Generator (Tektronix
offset compensation. AWG7000) which drives the I and Q inputs to the transmitter.
For beam pattern measurements, the element weights (gain The output of the receiver was sampled using a high-speed
and phase) necessary to achieve desired array patterns are cal- oscilloscope (Tektronix DSA72004) which emulates A/D
culated (taking gain and phase offsets into account) and applied converter. The captured frame was provided to the software
to the packaged IC in the testbed. Fig. 23 shows the expected and demodulator which includes algorithms to correct for frequency
measured 2D pattern measurements for different sets of element offset between TX and RX. The link was evaluated using both
weights. The theta and phi coordinates in Fig. 23 are polar co- 16-QAM OFDM (5.3 Gb/s) and Single-Carrier (4.5 Gb/s)
ordinates corresponding to the Cartesian coordinates in Fig. 21. modulation formats. Initial measurements on the link were
Multiple antenna patterns corresponding to narrow as well as performed with TX and RX 4 m apart (limited by laboratory
broad beams were measured and very good correlation was seen space). Fig. 26 shows the constellations for 5.3 Gb/s OFDM
1072 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 26. Constellation in each of the IEEE channels for array Tx-array Rx wire-
less link. (OFDM modulation, 5.3 Gb/s, at 4 m Tx-Rx separation).

Fig. 28. Measured constellations for 60-GHz multi-Gb/s wireless links using
phased-array TX and RX. (a) SC (4.54 Gb/s) and OFDM (5.29 Gb/s) line-of-
sight links. (b) SC (4.54 Gb/s) and OFDM (5.29 Gb/s) NLOS link using reflec-
tion from whiteboard.

VI. CONCLUSION

A 16-element 60-GHz phased-array receiver was success-

fully implemented in a 0.12 m SiGe BiCMOS process tech-
nology. RF-path phase shifting was adopted in the array, leading
to reductions in area and power consumption. Each front-end
uses a combination of active and passive phase-shifting to
minimize phase shifter loss and ensure 360 of phase variation
Fig. 27. 60-GHz wireless link in conference room—7.5 m to 8 m separation from 57 to 65 GHz with 11.25 phase step. The LNA and
between TX and RX. Whiteboard is 2.2 m from the line-of-sight. discrete phase shifter in the front-end also provide coarse and
fine gain variation. The low variation in phase shift across
process and temperature implies that each element can be
link in each of the four IEEE channels with 4 m TX-RX sepa- set to desired phase-shift without any calibration for on-chip
ration with only 6 TX elements and 12 RX elements activated variations. The relative noise contributions of different array
[4]. The link shows lower than 18 dB EVM in channels 1, 2, blocks was analyzed, and the RF signal combining network was
and 3. designed using both passive and active combiners to improve
Fig. 27 shows the photograph of an experimental setup in output SNR. A differential cross-coupled Gysel combiner was
a conference room with a whiteboard along one of the walls. implemented to reduce passive combiner loss and area. Each
During the line-of-sight tests, the TX and RX phased array RF front-end has a NF of 6.8 dB at 22 C and 7.5 dB at 65 C.
beams are pointed at each other and for non-line-of-sight links, The array has 58 dB gain from single-element input to output
the beams are steered towards the whiteboard which acts as at 60 GHz. There is extensive digital programmability on the
the reflector. The TX and RX were 7.5 m to 8 m apart and chip and the gain can be varied from 58 dB to 10 dB. The
the distance to the reflector was 2.2 m. Fig. 28(a) shows the phased-array receiver IC was packaged in LTCC and MLO
constellation for line-of-sight link with 5.3 Gb/s OFDM and packages that included 16 60-GHz antennas. Beam pattern and
4.5 Gb/s SC modulations with all 16 elements active in the TX steering tests on the packaged receiver IC show good match
and RX. Fig. 28(b) shows the OFDM and SC constellations between theory and measurements and the array is capable
when the phased-array TX and RX beams are steered towards of switching beam directions in 50 ns. The packaged receiver
the whiteboard. In this case, the total path length is 9 m. The was used in conjunction with the companion phased-array
EVM in all cases was lower than 18 dB. The beam-steered transmitter IC to demonstrate line-of-sight and reflection-based
links demonstrate the ability of the phased-array TX and RX to links capable of multi-Gb/s data transfer (5.3 Gb/s OFDM and
establish a 60-GHz link when the LOS is blocked. 4.5 Gb/s SC).
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1073

ACKNOWLEDGMENT [20] J. Lee, “G/T and noise figure of active array antennas,” IEEE Trans.
Antennas Propag., vol. 41, no. 2, pp. 241–244, Feb. 1993.
[21] A. Natarajan, M. Tsai, and B. Floyd, “60 GHz RF-path phase-shifting
The authors thank Sammi Chan, Rodel Anonuevo, Lay-Poh two-element phased-array front-end in silicon,” in IEEE Symp. VLSI
Loh, Doris Lee, Young Kim, Hsin-Hung Chen, John Zhang, and Circuits Dig., 2009, pp. 250–251.
Lawrence Loh from Mediatek, and Benjamin Parker, Donald [22] M. Chirala and B. Floyd, “Millimeter-wave lange and ring-hybrid cou-
plers in a silicon technology for E-band applications,” in IEEE MTT-S
Beisser, Sudhir Gowda, and Mehmet Soyuer from IBM for their Int. Microwave Symp. Dig., 2006, pp. 1547–1550.
valuable contributions to this work. [23] E. Wilkinson, “An N-way hybrid power divider,” IRE Trans. Microw.
Theory Tech., vol. MTT-8, no. 1, pp. 116–118, 1960.
[24] U. Gysel, “A new N-way power divider/combine suitable for high-
power applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 1975,
REFERENCES pp. 116–118.
[25] A. Valdes-Garcia, S. Reynolds, and T. Beukema, “Multi-mode mod-
[1] S. Reynolds et al., “A silicon 60-GHz receiver and transmitter chipset ulator and frequency demodulator circuits for Gb/s data rate 60 GHz
for broadband communications,” IEEE J. Solid-State Circuits, vol. 41, wireless transceivers,” in Proc. IEEE Custom Integrated Circuits Conf.
no. 12, pp. 2820–2831, Dec. 2006. (CICC), 2007, pp. 639–642.
[2] M. Varonen et al., “A 60-GHz CMOS receiver with an on-chip ADC,” [26] D. Liu, J. Akkermans, and B. Floyd, “A superstrate patch antenna for
in IEEE Radio Frequency Integrated Circuits Symp. (RFIC) Dig., 2009, 60-GHz applications,” in Proc. European Conf. Antennas and Propa-
pp. 445–448. gation (EUCAP), 2009, pp. 2592–2594.
[3] E. Cohen, C. Jakobson, S. Ravid, and D. Ritter, “A thirty two element
phased-array transceiver at 60 GHz with RF-IF conversion block in
90 nm flip chip CMOS process,” in IEEE Radio Frequency Integrated
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[4] S. Reynolds et al., “A 16-element phased-array receiver IC for 60-GHz
communications in SiGe BiCMOS,” in IEEE Radio Frequency Inte-
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[5] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri,
“A 77-GHz phased-array transceiver with on-chip antennas in silicon: Arun Natarajan (S’03–M’07) received the B.Tech.
Transmitter and local LO-path phase shifting,” IEEE J. Solid-State Cir- degree in electrical engineering from the Indian
cuits, vol. 41, no. 12, pp. 2807–2819, Dec. 2006. Institute of Technology, Madras, India, in 2001, and
[6] A. Valdes-Garcia et al., “A fully integrated 16-element phased-array the M.S. and Ph.D. degrees in electrical engineering
transmitter in SiGe BiCMOS for 60-GHz communications,” IEEE J. from the California Institute of Technology (Cal-
Solid-State Circuits, vol. 45, no. 12, pp. 2757–2773, Dec. 2010. tech), Pasadena, in 2003 and 2007, respectively.
[7] W. Chan, J. Long, M. Spirito, and J. Pekarik, “A 60 GHz-band 2 x He joined IBM in 2007 and is presently a Research
2 phased-array transmitter in 65 nm CMOS,” in IEEE Int. Solid-State Staff Member at the IBM T. J. Watson Research
Circuits Conf. (ISSCC) Dig., 2010, pp. 42–43. Center, Yorktown Heights, NY. His research focuses
[8] A. Maltsev, R. Maslennikov, A. Sevastyanov, A. Khoryaev, and A. Lo- on the design of high-frequency integrated circuits.
mayev, “Experimental investigations of 60 GHz WLAN systems in of- His current research interests include RF and analog
fice environment,” IEEE J. Sel. Areas Commun., vol. 27, no. 8, pp. circuit design, wireless transceivers, and multiple-antenna system design.
1488–1499, Aug. 2009. Dr. Natarajan received the Caltech Atwood Fellowship in 2001, the Analog
[9] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz Devices Outstanding Student IC Designer Award in 2004, and the IBM Research
eight-element phased-array receiver in silicon,” IEEE J. Solid-State Fellowship in 2005.
Circuits, vol. 39, no. 12, pp. 2311–2320, Dec. 2004.
[10] K.-J. Koh, J. May, and G. Rebeiz, “A millimeter-wave (40–45 GHz)
16-element phased-array transmitter in 0.18- m SiGe BiCMOS tech-
nology,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1498–1509,
May 2009. Scott K. Reynolds (M’06) received the Ph.D. de-
[11] J. Gilbert, C. Doan, S. Emami, and C. Shung, “A 4-Gbps uncompressed gree in electrical engineering from Stanford Univer-
wireless HD A/V transceiver chipset,” IEEE Micro, vol. 28, no. 2, pp. sity, Stanford, CA, in 1987.
56–64, Mar. 2008. He joined IBM in 1988 and has worked on a
[12] Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer wide variety of IBM products, including ICs for
(PHY) Specifications for High Rate Wireless Personal Area Networks disk drive channels, electrical and optical I/O, and
(WPANs) Amendment 2: Millimeter-Wave-Based Alternative Physical RF communication. He has recently been engaged
Layer Extension, IEEE Standard 802.15.3c-2009, Sep. 11, 2009. in development of silicon millimeter-wave ICs and
[13] D. G. Kam, D. Liu, A. Natarajan, S. Reynolds, and B. Floyd, “Low- packaging for high-data-rate wireless links and other
cost antenna-in-package solutions for 60-GHz phased-array systems,” applications. He has more than 25 U.S. patents and
IEEE Electrical Performance of Electronic Packaging and Systems many technical publications, including two papers
(EPEPS), pp. 93–96, Oct. 2010. on 60-GHz wireless transceiver circuits which won the best paper awards at
[14] B. Floyd, “A 16-18.8-GHz sub-integer-N frequency synthesizer for ISSCC in 2004 and 2006. He is currently a research staff member and manages
60-GHz transceivers,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. the RF Circuits & Systems group at the IBM T. J. Watson Research Center,
1076–1086, May 2008. Yorktown Heights, NY.
[15] ECMA-387 High Rate 60 GHz PHY, MAC and HDMI PAL, ECMA,
Dec. 2008.
[16] A. Natarajan, B. Floyd, and A. Hajimiri, “A bidirectional RF-com-
bining 60 GHz phased-array front-end,” in IEEE Int. Solid-State Cir- Ming-Da Tsai received the Ph.D. degree from the
cuits Conf. (ISSCC) Dig., 2007, pp. 202–597. Graduate Institute of Communication Engineering,
[17] S. Kishimoto, N. Orihashi, Y. Hamada, M. Ito, and K. Maruhashi, “A National Taiwan University, Taipei, in 2005.
60-GHz band CMOS phased array transmitter utilizing compact base- Upon graduation, he joined MediaTek Inc.,
band phase shifters,” in IEEE Radio Frequency Integrated Circuits Hsinchu, Taiwan, where he has been involved with
Symp. (RFIC) Dig., 2009, pp. 215–218. RF integrated circuits for cellular applications. From
[18] M.-D. Tsai and A. Natarajan, “60 GHz passive and active RF-path 2007 to 2009, he was with the 60-GHz IBM-MTK
phase shifters in silicon,” in IEEE Radio Frequency Integrated Cir- Joint-Development Project at IBM T. J. Watson Re-
cuits Symp. (RFIC) Dig., 2009, pp. 223–226. search Center, Yorktown Heights, NY. His research
[19] J. Weem and Z. Popovic, “A method for determining noise coupling in interests are in the areas of RF and millimeter-wave
a phased array antenna,” in IEEE MTT-S Int. Microwave Symp. Dig., integrated circuits.
2001, vol. 1, pp. 271–274. Dr. Tsai was the recipient of the 2004 MediaTek Fellowship.
1074 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Sean T. Nicolson (S’96–M’03) received the B.A.Sc. From 1990 to 1996, he was with Valor Enterprises Inc. Piqua, Ohio, ini-
degree in electronics engineering from Simon Fraser tially as an Electrical Engineer and then as the Chief Engineer, during which
University, Vancouver, BC, Canada, in 2001, and the time he designed an antenna product line ranging from 3 MHz to 2.4 GHz
Ph.D. degree in electrical and computer engineering for the company, a very important factor for the prestigious Presidential “E”
from the University of Toronto, Toronto, ON, Award for Excellence in Exporting in 1994. Since April 1996, he has been with
Canada, in 2008. the IBM T. J. Watson Research Center, Yorktown Heights, NY, as a Research
In 2002, he developed low-power integrated Staff Member. He has received three IBM’s Outstanding Technical Achieve-
circuits for implantable medical devices at Neu- ment Awards and one Corporate Award, the IBM’s highest technical award. He
roStream Technologies. During his Ph.D. research was named Master Inventor in 2007. He has edited a book titled Advanced Mil-
work, he held research internships at the IBM T. limeter-wave Technologies—Antennas, Packaging and Circuits (Wiley, 2009).
J. Watson Research Center in New York, USA, He has authored or coauthored approximately 80 journal and conference pa-
and S.T. Microelectronics in Grenoble, France, where he designed silicon pers. He has 37 patents issued and 19 patents pending. His research interests are
integrated circuits for applications over 100 GHz. Currently, he is at MediaTek antenna design, EM modeling, chip packaging, digital signal processing, and
working on 60 GHz phased array radio. His research interests include W-band communications technologies.
radar, multi-antenna systems, SiGe HBT devices, and high-speed current mode Dr. Liu is an associate editor for the IEEE TRANSACTIONS ON ANTENNAS
logic. AND PROPAGATION and was a Guest Editor for the IEEE TRANSACTIONS ON
Dr. Nicolson has twice been a recipient of the scholarships from the National ANTENNAS AND PROPAGATION special issue on Antennas and Propagation As-
Science and Engineering Research Council (NSERC), and was the recipient of pects of 60–90 GHz Wireless Communications (October 2009). He has been
the Best Student Paper Award at BCTM 2006. an organizer or chair for numerous international conference sessions or special
sessions and served as a technical program committee member for many inter-
national conferences. He was the general chair of the 2006 IEEE International
Workshop on Antenna Technology: Small Antennas and Novel Metamaterials,
White Plains, New York. He has served as an external Ph.D. examiner for sev-
Jing-Hong Conan Zhan (S’97–M’04) was born in
eral universities and external examiner for some government organizations on
Hsinchu, Taiwan, in 1974. He received the Ph.D.
research grants.
degree in electrical engineering and computer sci-
ence from Cornell University, Ithaca, NY, in 2004,
specializing in VCO and high-speed clock and data
recovery circuit design using BiCMOS and CMOS
technologies. Yen-Lin Oscar Huang received the M.S. degree in
From 1999 to 2001, he was with MediaTek, electrical engineering from National Taiwan Univer-
Hsinchu, Taiwan, where he developed read channel sity, Taipei, Taiwan, in 2008, focusing on millimeter-
data path and spindle motor control circuitry for wave transceiver circuits design.
optical storage systems as a logic design engineer. He joined the Millimeter Wave division of Me-
In June 2004, he joined Intel Communication Circuit Lab, Hillsboro, Oregon, diatek, Hsinchu, Taiwan, in 2008, where he was
where he focused on receiver front-end circuitry for broadband multi-standard involved in millimeter-wave communication system
applications using digital CMOS process for microprocessors production. In design and system integration testing environment
September 2006, he joined MediaTek RF division, where he led a DVB-H development. In 2009, he participated the joint
tuner design team, designed various front-end building blocks, and supervised development project of 60 GHz phased-array system
the chipset design activities. He also designed DCOs for digital intensive PLLs with IBM T. J. Watson Research Center, Yorktown
targeting for mobile phone applications. From October 2007 to October 2009, Heights, NY. He is currently a RF system architecture design engineer of
he participated the joint development of a 60 GHz phased-array system with Mediatek, developing Bluetooth transceiver system for multi-radio single chip
IBM T. J. Watson Research Center design team. He co-designed the synthe- products.
sizer, oversaw chipset, antenna, packaging design and fabrication activities.
Since October 2009, Dr. Zhan has supervised a centralized RF synthesizer
design team, and led MediaTek’s millimeter-wave chipset development.
Alberto Valdes-Garcia (S’00–M’05) received
the B.S. degree in electronic systems engineering
degree from the Monterrey Institute of Technology
(ITESM), Campus Toluca, Mexico, in 1999 (highest
Dong Gun Kam (S’01–M’06–SM’10) received
honors as best score from all majors) and the Ph.D.
the B.S. degree in physics with a double major in
degree in electrical engineering from Texas A&M
electrical engineering, the M.S. and Ph.D. degrees
University, College Station, TX, in 2006.
in electrical engineering, all from KAIST, Daejeon,
In 2000 he was a Design Engineer with Motorola,
Korea, in 2000, 2002, and 2006, respectively.
Broadband Communications Sector. During his grad-
From 2006 to 2007, he worked for Silicon Image,
uate studies, he held internships with Agere Systems
Sunnyvale, CA, as a Member of Technical Staff
(former Lucent Technologies, now LSI) and IBM Re-
in the areas of signal integrity. In 2007, he joined
search in 2002 and 2004, respectively. Since January 2006 he has been a Re-
the IBM T. J. Watson Research Center, Yorktown
search Staff Member with the Communication and Computation Subsystems
Heights, NY, where he is currently a Research
Department, IBM T. J. Watson Research Center, Yorktown Heights, NY. His
Staff Member concentrating in the areas of antenna
present research work is on silicon-integrated millimeter-wave communication
and package development for millimeter-wave communication systems, and
systems and carbon electronics.
subsystem design and analysis of high-speed electrical, optical, and wireless
From 2006 to 2009 he served as voting member and technical contributor
links.
to the IEEE 802.15.3 c 60 GHz standardization committee, and he served in
Dr. Kam is an Associate Editor of the IEEE TRANSACTIONS ON COMPONENTS,
the millimeter-wave working group of the 2009 International Roadmap for
PACKAGING, AND MANUFACTURING TECHNOLOGY and is currently serving as a
Semiconductors (ITRS). He currently serves as Chair of the Semiconductor
Guest Editor for the Special Issue on Through Silicon Vias. He has authored or
Research Corporation (SRC) Integrated Circuits and Systems Sciences Co-
coauthored over 50 technical papers and has four issued patents. He has served
ordinating Committee and in the Technical Program Committee of the IEEE
on the technical program committees for the ISQED and DesignCon. He re-
Custom Integrated Circuits Conference (CICC). He has authored or coauthored
ceived the Best Paper Award at DesignCon 2008.
more than 45 peer-referred technical publications and has two issued U.S.
patents. He is a co-editor of the book 60 GHz Technology for Gbps WLAN and
WPAN: From Theory to Practice (Wiley, 20011).
From 2000 to 2005, Dr. Valdes-Garcia was the recipient of a scholarship from
Duixian Liu (S’85–M’90–SM’98–F’09) received the B.S. degree in electrical the Mexican National Council for Science and Technology (CONACYT). He is
engineering from XiDian University, Xi’an, China, in 1982, and the M.S. the winner of the 2005 Best Doctoral Thesis Award presented by the IEEE Test
and Ph.D. degrees in electrical engineering from The Ohio State University, Technology Technical Council (TTTC). He is the recipient of the 2007 National
Columbus, in 1986 and 1990, respectively. Youth Award for Outstanding Academic Achievements, presented by the Presi-
NATARAJAN et al.: A FULLY-INTEGRATED 16-ELEMENT PHASED-ARRAY RECEIVER IN SiGe BiCMOS FOR 60-GHz COMMUNICATIONS 1075

dent of Mexico. In 2008 he was a co-recipient of an IBM Corporate Outstanding of 3G WCDMA receivers in SiGe BiCMOS and CMOS technologies and
Innovation Award for the demonstration of wireless high definition video links then the development and demonstration of some of the first silicon-based
with 60 GHz SiGe radios. He is a co-recipient of the 2009 Pat Goldberg Memo- millimeter-wave receivers, transmitters, and frequency synthesizers for appli-
rial Award to the best paper in computer science, electrical engineering, and cations at 60 GHz and above. In 2007, he became the manager of the wireless
mathematics within IBM Research for the work Operation of Graphene Tran- circuits and systems group at IBM Research, working on the development
sistors at GHz Frequencies. of 60-GHz phased-array transceiver, antenna, and package solutions under
the IBM and MediaTek joint development program. In 2010, he joined the
Department of Electrical and Computer Engineering at North Carolina State
University, Raleigh, as an Associate Professor. His research interests include
Brian A. Floyd (S’98–M’01–SM’10) received the millimeter-wave circuits and systems for high-speed communications and
B.S. degree with highest honors, and the M. Eng. and imaging applications.
Ph.D. degrees in electrical and computer engineering Dr. Floyd has authored or coauthored over 60 technical papers and has 13
from the University of Florida, Gainesville, in 1996, issued patents. He serves on the technical program committee for the Interna-
1998, and 2001, respectively. While at the Univer- tional Solid-State Circuits Conference and both the steering and technical pro-
sity of Florida, he held the Intersil/Semiconductor gram committees for the RFIC Symposium. From 2006 to 2009, he served on the
Research Corporation Graduate Fellowship and technical advisory board to the Semiconductor Research Corporation integrated
the Pittman Fellowship, working on CMOS RFIC circuits and systems science area. He was a winner of the 2000 SRC Copper De-
design for on-chip wireless clock distribution. sign Challenge; a recipient of the 2006 Pat Goldberg Memorial Award for the
During the summers of 1994–1996, he worked best paper in computer science, electrical engineering, and mathematics within
with the Motorola Paging Products Group, Boynton IBM Research, and a two-time recipient of the IEEE Lewis Winner Award for
Beach, FL, in the areas of RF product development and IC design. In 2001, the best paper at the International Solid-State Circuits Conference in 2004 and
he became a research staff member at the IBM Thomas J. Watson Research 2006.
Center, Yorktown Heights, NY. His work at IBM included the development