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Genus Physical Flow

The Genus Physical Guide, version 22.1, provides comprehensive information on physical design flows and methodologies for Cadence's Genus synthesis tool. It includes sections on physical information, layout estimation, floorplanning, and various flows such as Simple PLE and iSpatial Flow. The document also outlines customer support options, reporting issues, and legal disclaimers regarding the use of the publication.

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0% found this document useful (0 votes)

737 views99 pages

Genus Physical Flow

Uploaded by

Yun Shao

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Available Formats

Download as PDF, TXT or read online on Scribd

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Genus Physical Guide

Product Version 22.1

February 2023
© 2023 Cadence Design Systems, Inc. All rights reserved.
Used by permission. Printed in the United States of America.
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registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are
used with permission.
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are attributed to Cadence with the appropriate symbol. For queries regarding Cadence trademarks, contact
the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are
the property of their respective holders.
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Disclaimer: Information in this publication is subject to change without notice and does not represent a
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Genus Physical Guide

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reporting Problems or Errors in Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Cadence Online Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Other Support Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supported User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Command-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Getting the Syntax for a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Getting Attribute Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Searching For Commands When You Are Unsure of the Name . . . . . . . . . . . . . . . . 16
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Physical Information in Genus Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Physical Flows in Genus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Files Needed for Physical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Physical Information in the Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2
Simple PLE Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Layout Estimation (PLE) Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Attributes Affecting the PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Tasks Associated with PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reading the LEF Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

February 2023 3 Product Version 22.1

Troubleshooting Tips While Reading LEF libraries . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Loading Parasitic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Consistency between LEF and Parasitic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Checking Physical Layout Estimation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Setting Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reading the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Components of DEF File Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Analyzing the Results of PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Sample Script for Simple PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3
RTL Floorplanning Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RTL Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Settings Required for predict_floorplan Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Incomplete DEF in RTL Floorplanning Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Recommended Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4
iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Genus iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Attributes Affecting the iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pre-requisites for iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Tasks Associated with iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Analyzing the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Handing off to Innovus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Basic Script for iSpatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5
Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Attributes Affecting the Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

February 2023 4 Product Version 22.1

Tasks Associated with Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Setting up the Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Handling Incomplete DEF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Loading Generated PLE Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Synthesizing, Estimating, and Optimizing for Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 70
Analyzing the Results of Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Sample Script for Genus-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6
Structured Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SDP Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SDF File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SDP File Skeleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
datapath Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
column Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
inst Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
row Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SDP File Syntax Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SDP Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SDP Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Datapath-SDP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
FF Column SDP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

A
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

February 2023 5 Product Version 22.1

February 2023 6 Product Version 22.1

Preface

■ About This Manual on page 8

■ Additional References on page 8
■ Reporting Problems or Errors in Manuals on page 9
■ Customer Support on page 10
■ Supported User Interfaces on page 12
■ Messages on page 13
■ Man Pages on page 14
■ Command-Line Help on page 15
■ Documentation Conventions on page 17

February 2023 7 Product Version 22.1

About This Manual

This manual describes how to use physical information in Genus.

Additional References
The following sources are helpful references, but are not included with the product
documentation:
■ TclTutor, a computer aided instruction package for learning the Tcl language:
http://www.msen.com/~clif/TclTutor.html.
■ TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley
Publishing Company
■ Practical Programming in Tcl and Tk, Brent Welch and Ken Jones
■ IEEE Standard Hardware Description Language Based on the Verilog Hardware
Description Language (IEEE Std.1364-1995)
■ IEEE Standard Hardware Description Language Based on the Verilog Hardware
Description Language (IEEE Std. 1364-2005)
■ IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and
Verification Language (IEEE STD 1800-2009)
■ IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1987)
■ IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1993)
■ IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-2008)
Note: For information on purchasing IEEE specifications go to http://shop.ieee.org/store/ and
click on Publications & Standards.

February 2023 8 Product Version 22.1

Reporting Problems or Errors in Manuals

The Cadence® Help online documentation, lets you view, search, and print Cadence product
documentation. You can access Cadence Help by typing cdnshelp from your Cadence tools
hierarchy.

Contact Cadence Customer Support to file a CCR if you find:

■ An error in the manual
■ An omission of information in a manual
■ A problem using the Cadence Help documentation system

February 2023 9 Product Version 22.1

Customer Support
Cadence offers live and online support, as well as customer education and training programs.

Cadence Online Support

The Cadence® online support website offers answers to your most common technical
questions. It lets you search more than 40,000 FAQs, notifications, software updates, and
technical solutions documents that give you step-by-step instructions on how to solve known
problems. It also gives you product-specific e-mail notifications, software updates, case
tracking, up-to-date release information, full site search capabilities, software update
ordering, and much more. For more information on Cadence online support go to http://
support.cadence.com

Other Support Offerings

■ Support centers—Provide live customer support from Cadence experts who can
answer many questions related to products and platforms.
■ Software downloads—Provide you with the latest versions of Cadence products.
■ University software program support—Provides you with the latest information to
answer your technical questions.
■ Training Offerings—Cadence offers the following training courses for Genus users:
❑ Basic Static Timing Analysis
❑ Advanced Synthesis with Genus Stylus Common UI
❑ Fundamentals of IEEE 1801 Low-Power Specification Format
❑ Genus Low-Power Synthesis Flow with IEEE 1801
❑ Genus Synthesis Solution with Stylus Common UI
❑ Joules Power Calculator
❑ Low-Power Synthesis Flow with Genus Stylus Common UI
❑ Test Synthesis with Genus Stylus Common UI
The courses listed above are available in North America. For further information on the
training courses available in your region, visit Cadence Training or write to
[email protected].
Note: The links in this section open in a new browser.

February 2023 10 Product Version 22.1

■ Video Library
Several videos are available on the support website: Genus: Video Library

For more information on the support offerings go to http://www.cadence.com/support

February 2023 11 Product Version 22.1

Supported User Interfaces

Genus supports the following user interfaces:
■ Unified User Interface. Genus, Innovus and Tempus offer a fully unified Tcl scripting
language and GUI environment. This unified user interface (also referred to as common
UI) streamlines flow development and improves productivity of multi-tool users.
When you start Genus, you will by default start with the common UI. You will see the
following prompt:
genus:root: 1>

■ Legacy User Interface. Genus can also operate in legacy mode which supports RTL
Compiler commands/attributes and scripting.
To start Genus with legacy UI, you can
❑ Start the tool with legacy UI as follows:
%genus -legacy_ui -files script
....
legacy_genus:/>

❑ Switch to legacy UI if you started the tool with the default common UI.
%genus
genus:root: 13> set_db common_ui false
legacy_genus:/>

Important
This document provides information specific to the common user interface.

February 2023 12 Product Version 22.1

Messages
■ You can get detailed information for each message issued in your current Genus run
using the report_messages command.
genus:root:> report_messages

The report also includes a summary of how many times each message was issued.
■ You can also get specific information about a message.
For example, to get more information about the TUI-613 message, you can type the
following command:
genus:root:> vls -a TUI-613
message:TUI/TUI-613 (message)
Attributes:
base_name = TUI-613
count = 0
escaped_name = TUI/TUI-613
help = The user_speed_grade is only applicable to datapath subdesigns.
id = 613
name = TUI/TUI-613
obj_type = message
print_count = 0
priority = 1
screen_print_count = 0
severity = Warning
type = The attribute is not applicable to the object.

You can also use the help command:

genus:root:> help TUI-613
Message:
name: TUI/TUI-613
severity: Warning
type: The attribute is not applicable to the object.
help: The user_speed_grade is only applicable to datapath
subdesigns.

If you do not get the details that you need or do not understand a message, either contact
Cadence Customer Support to file a CCR or email the message ID you would like improved
to [email protected]

February 2023 13 Product Version 22.1

Man Pages
In addition to the Command and Attribute References, you can also access information about
the commands and attributes using the man pages in Genus.

To use man pages from UNIX shell:

1. Set your environment to view the correct directory:
setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man_common

2. Access the manpage by either of the following ways:

❑ Enter the name of the command or attribute that you want. For example:
❍ man check_dft_rules
❍ man max_output_voltage
❑ Specify a section number with man command to look for the command or attribute
information in the specific section of the on-line manual.
Commands are in section 1, attributes are in section 2, and messages are in section
3 of the on-line manual. In the absence of section number, man will search through
sections 1, 2, 3 (in this sequence) and display the first matching manual page.
This is useful in cases where both commands and attributes exist with the same
name. For example:
❍ man 1 retime
will display manhelp for retime command
❍ man 2 retime
will display manhelp for retime attribute
Note: Refer to man for more information on the man command.

February 2023 14 Product Version 22.1

Command-Line Help
You can get quick syntax help for commands and attributes at the Genus command-line
prompt. There are also enhanced search capabilities so you can more easily search for the
command or attribute that you need.
Note: The command syntax representation in this document does not necessarily match the
information that you get when you type help command_name. In many cases, the order of
the arguments is different. Furthermore, the syntax in this document includes all of the
dependencies, where the help information does this only to a certain degree.

If you have any suggestions for improving the command-line help, please e-mail them to
[email protected]

Getting the Syntax for a Command

Type the help command followed by the command name.

For example:
genus:root:> help path_group

This returns the syntax for the path_group command.

Getting Attribute Help

Type the following:
genus:root:> help attribute_name

For example:
genus:root:> help max_transition

This returns the help for the max_transition attribute and shows on which object types the
attribute can be specified.

February 2023 15 Product Version 22.1

Searching For Commands When You Are Unsure of the Name

You can use help to find a command or a Tcl process if you only know part of its name, even
as little as one letter. You can type a single letter or sequence of letters and press Tab to get
a list of all commands and any user-defined Tcl processes that start with that letter(s). For
example:
genus:root:> ad<Tab>

This returns the following commands:

add_assign_buffer_options add_clock_gates_obs
add_clock_gates_test_connection add_opcg_hold_mux
...

February 2023 16 Product Version 22.1

Documentation Conventions
To aid the readers understanding, a consistent formatting style has been used throughout this
manual.
■ UNIX commands are shown following the unix> string.
■ Genus commands are shown following the genus:root: xx> string.

Text Command Syntax

The list below defines the syntax conventions used for the Genus text interface commands.

literal Non-italic words indicate keywords you enter literally. These

keywords represent command or option names.
arguments and Words in italics indicate user-defined arguments or information
options for which you must substitute a name or a value.
| Vertical bars (OR-bars) separate possible choices for a single
argument.
[] Brackets indicate optional arguments. When used with OR-
bars, they enclose a list of choices from which you can choose
one.
{} Braces indicate that a choice is required from the list of
arguments separated by OR-bars. Choose one from the list.
{ argument1 | argument2 | argument3 }
{ } Braces, used in Tcl commands, indicate that the braces must
be typed in.
... Three dots (...) indicate that you can repeat the previous
argument. If the three dots are used with brackets (that is,
[argument]...), you can specify zero or more arguments. If
the three dots are used without brackets (argument...), you
must specify at least one argument.
# The pound sign precedes comments in command files.

February 2023 17 Product Version 22.1

February 2023 18 Product Version 22.1

1
Introduction

■ Physical Information in Genus Synthesis

❑ Physical Flows in Genus
❑ Objective of Each Flow
■ Files Needed for Physical Flows
■ Physical Information in the Design Hierarchy

February 2023 19 Product Version 22.1

Physical Information in Genus Synthesis

Traditional synthesis tools use vendor-supplied wire-load models based on fanouts, which do
not provide accurate wire delay information especially for designs where a significant portion
of the delays are contributed by the wires. Consequently, you can see relative big differences
in performance, area, and power between the logic and physical designs.

Custom wire-load models are considered to be the starting point for synthesis, as they are
more accurate than the vendor-supplied wire-load models. But the disadvantage is that you
need to place the design to create custom wire-load models. In addition, placement depends
on an initial pass of gate generation done with ad hoc methods. Furthermore, custom wire-
load models represent a static view of the design and depend on the netlist used to generate
the placement. As the RTL and constraints change over the design cycle, the custom wire-
load models become increasingly inaccurate. In many cases, the custom wire-load models
generated at the start of the design can be worse than the vendor-supplied wire-load models
at the end of the project.

Physical layout estimation (PLE) uses physical information to model the effects of placement
based on the current state of the RTL and the constraints, and provides you with a level of
analysis and optimization that would not be available with a traditional synthesis methodology.
Furthermore, using physical information gives a level of down-stream predictability that is
superior to using vendor supplied wire-load models. Predictability will enable you to better
gauge how the design will perform after place and route and help to reduce frontend to
backend hand-off iterations. Ultimately, using physical information in synthesis gives you the
opportunity to develop a smaller, faster design in less time than with traditional synthesis.

The following table summarizes the differences between performing synthesis using physical
layout estimation or wire-load models.

Table 1-1 PLE versus WLM

Physical Layout Estimation (PLE) Wire-load Models (WLM)

Uses actual design and physical library Wire-load models are statistical.
information.
Dynamically calculates wire delays for Wire-load models are calculated based on
different logic structures in the design. the nearest calibrated area.
Selection of appropriate wire-load models for
a design is tedious.
Correlates better with place and route. Correlation is difficult even with custom wire-
load models.

February 2023 20 Product Version 22.1

Physical Flows in Genus

Genus offers three physical-related flows. They provide increasing accuracy in predicting the
wire lengths.

Simple PLE Flow Genus-iSpatial flow Genus-Physical flow

Uses technology Uses a rapid placement to Uses complete placement and
information and cell areas better estimate long wires in considers congestion and legal
from the LEF libraries your design. This helps deliver placement as a cost function
instead of from the more accuracy to the core during the RTL-to-gates phase,
synthesis technology synthesis optimization engine to create a better netlist.
libraries. during RTL-to-gate synthesis.
The PLE flow uses
parasitic resistance and
capacitance values from
the LEF libraries or the
capacitance tables (if
available) when
estimating the wire
lengths.
This flow works in all base This flow works in all base This flow requires an Genus
Genus products. Genus products with Genus Physical Option (GEN40)
Physical Option license - license in addition to a base
Genus_Physical_Opt. Genus product license and
requires access to the Innovus
System.

You do not need a deep, technical knowledge of physical design to use physical information
in Genus. The usage model is kept simple on purpose and the physical data is as abstract as
possible. Reading through this document should be sufficient to becoming effective in using
physical information in synthesis.

Objective of Each Flow

Each flow has a particular purpose. Choosing the best flow depends on design
characteristics and goal objectives.

February 2023 21 Product Version 22.1

Simple PLE Flow Genus-iSpatial flow Genus-Physical flow

PPA is low but the PPA and prediction** of PPA and prediction of design is
turnaround time (TAT*) is design is medium post Genus very good post Genus
very fast. Synthesis, but it comes at a Synthesis, but it comes at a
cost of runtime which is cost of runtime.
between PLE and Physical.
PLE flow can be used Spatial flow can be used when Physical flow can used there is
when the design is not there is need of correlation demand for high PPA and
complex and need to be between Synthesis and Place prediction.
analyzed quickly. and Route (PnR) flow.

Summarizing this information from a different perspective. The following table summarizes
each flow and its purpose:

Objective PLE iSpatial Physical

PPA Low Medium High
(Power Performance Area)
TAT Fast Medium Slow
(TurnAround Time)
Prediction Low Medium High

* Turnaround time (TAT) is the time which the tool takes to execute the flow or the runtime of
the flow.

** Prediction is early insight into real timing and placement related issues in the physical
implementation of the design.

February 2023 22 Product Version 22.1

Files Needed for Physical Flows

The following figure shows the data flow for the physical flows.

Figure 1-1 Physical Information Files

DEF Synthesis RTL Constraint

Floorplan Libraries Files File
File

Genus
LEF Capacitance
Libraries Table File

SDC Gate-Level Innovus

DEF
Constraints Netlist Database
File
Files

Files added
for physical
Optional file

Mandatory or
File type Description
Optional
LEF Mandatory LEF libraries are the physical libraries that
contain information such as layer, via,
placement site type, routing design rules,
process information, and standard cell and
macro cell definitions.

February 2023 23 Product Version 22.1

Mandatory or
File type Description
Optional
Capacitance Table Recommended Capacitance tables contain the same type of
parasitic information as the LEF files but the
resistance and capacitance information in
the capacitance table is more detailed and
therefore more accurate than in the LEF file.
The values in a capacitance table comes
from the same process definition files that
drive sign off extraction as well as the
various other extractors used in Cadence
tools.
DEF Recommended DEF files are ASCII files that contain
in the Genus- information that represent the design at any
PLE and Genus- point during the layout process. In Genus,
iSpatial flow, and the DEF is primarily used for floorplan
is required for the information.
Genus-Physical
flow

February 2023 24 Product Version 22.1

Physical Information in the Design Hierarchy

Genus stores the original design data along with additional information in the physical files in
the design information hierarchy in the form of attributes. The following shows the design
information hierarchy.

Figure 1-2 Design Information Hierarchy

(genus:root:>)
root

designs messages obj_types libraries hdl_libraries

design_name INVS library_set

constants PHYS
default_library_set base_cells
PLC
dft
library1
insts
blockages library2
hinsts bumps
def_pins lib_cells
hnets fills
gcells
nets
groups

physical styles physical_cells

fills
power route_rules operating_conditions
pcells
wireload_models
port_busses pdomains
pnets wireload_selections
ports
regions lib_cells
pg_hnets rows
tracks
pg_nets slots
specialnets
modules

timing
layers
tech sites
vias

February 2023 25 Product Version 22.1

The root directory contains the root attributes which apply to all designs that you read in. The
root directory has six main directories.

Directory Description
designs Have several subdirectories each representing a design in memory.
hdl_libraries Contain information about the ChipWare and third party libraries,
and about the Verilog modules and/or VHDL architectures and
entities that were read using the read_hdl command.
libraries Have several subdirectories each representing a technology library
in memory. The physical_cells contain information about the
physical cells that are present in the LEF files (have a LEF MACRO
definition), but not in synthesis libraries.
messages Contain all information for all messages that can be displayed
during an Genus session. Physical-related messages are stored in
the INVS, PHYS, and PLC subdirectories.
obj_types List all attributes for all database objects (designs, modules, pins,
and so on) in the design hierarchy.

Each design also has a physical directory with the following subdirectories:

Subdirectory Description
blockages Information about the BLOCKAGES defined in the DEF file.
bumps Information about the solder bumps on the chip. A BUMP is
instantiated in the DEF COMPONENTS section but is not
instantiated in the netlist.
def_pins Information about external pins in the design. The information
is based on the PIN statement in the DEF file.
fills Information about every metal FILL defined in the DEF file.
gcells information about the global routing cells (gcell). Gcells are
derived from the GCELLGRID statements in the DEF file.
groups Information about the GROUPS defined in the DEF file.
layers Information about the metal layers defined in the LEF or
capacitance table file.

February 2023 26 Product Version 22.1

Subdirectory Description
pcells Information about the physical cells (pcell) instantiated in the
COMPONENTS section of the DEF file. Pcells are not instantiated
in the netlist.
pdomains Physical information about the power domains defined in the
DEF file.
pnets Information based on the NETS section in the DEF file.
regions Information about every REGION defined in the DEF file.
rows Information about every ROW defined in the DEF file.
route_rules Information based on the NONDEFAULTRULES statement in
the DEF file.
sites Information based on the SITE statement in the LEF file.
slots Information about the slotting of the wires in the design. The
information is based on the SLOTS statement in the DEF file.
specialnets Information based on the SPECIALNETS statement in the DEF
file.
styles Information based on the STYLES statement in the DEF file.
tracks Track (or routing grid) information for each layer. The
information is based on the TRACKS statements in the DEF
file.
vias Information about fixed vias and generated vias. The via names
correspond to the via names specified in the VIAS statement.

February 2023 27 Product Version 22.1

February 2023 28 Product Version 22.1

2
Simple PLE Flow

■ Physical Layout Estimation (PLE) Flow

■ Attributes Affecting the PLE Flow
■ Tasks Associated with PLE Flow
❑ Reading the LEF Libraries
❑ Loading Parasitic Information
❑ Consistency between LEF and Parasitic Files
❑ Checking Physical Layout Estimation Information
❑ Setting Appropriate Synthesis Mode
❑ Reading the Floorplan
❑ Analyzing the Results of PLE Flow
❑ Exporting Files for Place and Route
■ Sample Script for Simple PLE Flow

February 2023 29 Product Version 22.1

Physical Layout Estimation (PLE) Flow

The simple PLE flow does not differ much from the generic flow except that you will be using
LEF files and capacitance tables to drive synthesis. Any steps that overlap with the generic
flow will not be covered in this chapter.

Figure 2-1 Simple PLE Flow

Start

Target
Read timing libraries
libraries

LEF
Read LEF libraries
libraries

Capacitance
file Load parasitic information
QRC tech
file

Review consistency between

LEF and parasitic files

Read HDL files and elaborate Modify source

HDL
files design

Check physical layout

estimation information

Set synthesis mode

Change physical constraints
DEF
Read floorplan
file
Change SDC constraints
SDC Apply constraints
constraints

Synthesize No

Task added for Meet

Physical Analyze constraints?

Export design
Optional task Yes

February 2023 30 Product Version 22.1

Attributes Affecting the PLE Flow

Attribute Name Object Type Default

aspect_ratio design double 1.000
avoid_no_row_libcell design boolean false
cap_table_file root string
interconnect_mode root string wireload
lef_library root string
lef_stop_on_error root boolean false
number_of_routing_layers design integer
phys_ignore_nets design boolean false
phys_ignore_special_nets design boolean false
qrc_tech_file root string
shrink_factor root float
use_area_from_lef root enumerated type false
utilization layer float

February 2023 31 Product Version 22.1

Tasks Associated with PLE Flow

The tasks below list only the steps that are different from the generic flow or illustrate a new
step needed for physical design synthesis:
1. Reading the LEF Libraries
2. Loading Parasitic Information
3. Consistency between LEF and Parasitic Files
4. Checking Physical Layout Estimation Information
5. Setting Appropriate Synthesis Mode
6. Reading the Floorplan
7. Analyzing the Results of PLE Flow
8. Exporting Files for Place and Route

Reading the LEF Libraries

LEF files are ASCII files that contain physical library information such as layer, via, placement
site type, routing design rules, process information, and standard cell and macro cell
definitions. The technology information and the cell definitions are usually available in
separate LEF files for easier management.

The timing library area will be used if

❑ The physical libraries do not contain any cell definitions.
❑ You only read in the technology LEF file (containing only the metal routing layer
information without the standard cell/macro definitions).
Note: For best results, always use all available LEF files (standard cell, macro and
technology LEF).

Read the libraries using the following steps:

1. Use the lef_library attribute to import LEF files. Specify all LEF files, the technology
library and the cell libraries. It is a good practice to specify the technology LEF file first.
The following example imports a technology and cell library LEF files.
genus:root:> set_db lef_library {tech.lef cell.lef}

2. Use the get_db command to confirm the list of imported LEF files:

February 2023 32 Product Version 22.1

genus:root:> get_db lef_library

tech.lef
cell.lef

In simple-PLE flow, the cell area defined in the LEF libraries is used instead of the cell area
defined in the timing library (.lib).

Genus will check whether the following definitions are in the LEF file:
■ CAPACITANCE CPERSQ
■ EDGECAPACITANCE
■ RESISTANCE RPERSQ
■ SITE
■ WIDTH

If any of these definitions are missing, Genus will issue a warning message.

Genus supports LEF 5.8 and above. Refer to the LEF/DEF Language Reference for more
information on LEF files.

Troubleshooting Tips While Reading LEF libraries

MACRO definitions

If there is at least one MACRO definition in the LEF file, Genus checks if all the cells in the
timing library have a corresponding definition in the LEF library. Any cells that are defined in
the timing library but not in the LEF will be marked as avoid (they will not be used during
synthesis) and a warning message will be issued. The resistance and capacitance
information can be found in the capacitance table file.
Note: Genus supports LEF 5.8 and above. Refer to the LEF/DEF Language Reference for
more information on LEF files.

Only one LEF file seems to be imported

Check if the lef_library attribute was set more than once or was part of a loop.

February 2023 33 Product Version 22.1

In the following example, the existing LEF file is replaced because it specifies the files
separately with two set_db commands as opposed to a Tcl list with one set_db command.
genus:root:> set_db lef_library tech.lef
genus:root:> set_db lef_library cell.lef

Loading Parasitic Information

Capacitance tables’ files or QRC technology files contain the same type of parasitic
information as the LEF files but the resistance and capacitance information in these files have
a finer granularity. For technologies below 28nm, the Innovus System requires a QRC
technology file instead of a capacitance table file.

The capacitance in a LEF comes from a foundry and is generated by whatever process it sees
as appropriate. The capacitance information in a capacitance table or QRC technology file
comes from the same process definition files that drive sign off extraction as well as the
various other extractors used in Cadence tools. The process definition files define layer
thicknesses, compositions, and spacing.

Scaling factors are used to align a design with a particular process. A capacitance table is
process specific where as a scaling factor is design specific. The scaling factors are provided
to be consistent with Innovus. Only use a scaling factor if it will also be used in the back-end.
1. Use the cap_table_file attribute to load the capacitance table file:
genus:root:> set_db cap_table_file my.cap

2. Use the qrc_tech_file attribute to load the QRC technology file:

genus:root:> set_db qrc_tech_file techfile.qrc

Note: If you specify both a capacitance table file and a QRC technology file, the QRC
technology file takes precedence.

It is recommended to specify both LEF and parasitic files.

Genus will check if the following information is available in the parasitic file:
■ PROCESS_VARIATION
■ BASIC_CAP_TABLE
■ width
■ Cc
■ Carea
■ Cfrg

February 2023 34 Product Version 22.1

If any of these definitions are missing, Genus will issue a warning message. It will purposely
disregard the EXTENDED_CAP_TABLE section because the PLE is intended to synchronize
with a view of the design where fast extractors are typically used.

Tip
For best results, the corner for the parasitic file used should match the corner for the
timing library. That is typically max or worst.

Related Topics
■ cap_table_file
■ qrc_tech_file

Consistency between LEF and Parasitic Files

You can skip this step if you are using generated PLE data.

After you load both your LEF and parasitic files, Genus will perform consistency checks
between the two files. This happens automatically, much like the check between the LEF and
timing library files.
■ Number of Layers — Genus will check to determine if the number of layers defined in
the LEF and the parasitic files are equal.
If the LEF has more layers than the parasitic file, then an error message will be issued
and you will need to manually check both of the files to resolve the inconsistency.
If the parasitic file has more layers than the LEF, a warning message will be issued and
the number of routing layers will be set to the number specified in the parasitic file.
■ Width of Layers — Genus will check to determine if the width of the layers defined in
the LEF and the parasitic files are equal. A warning will only be issued if the width
difference defined in the two files is greater than 10%.

Genus reports the inconsistencies in the log file. Review the log file for the same. For
example, check for messages PHYS-15 through 27.

February 2023 35 Product Version 22.1

Checking Physical Layout Estimation Information

After loading the LEF libraries, the capacitance information, and the design information, you
can check the physical layout estimation information for the design once all physical data has
been read in.
➡ Use the report_ple command to report the physical layout estimation information for
the design.This command reports information like aspect ratio, shrink factor, site size,
layer names, direction of layers, capacitance, resistance, and area. It also shows the
source that it used to extract the physical information.

Figure 2-2 Example of PLE Report

genus:root:> report_ple
===============================================================
Generated by: Genus(TM) Synthesis Solution version
Generated on: date
Module: DTMF_CHIP
Technology libraries: library1
library2
...
physical_cells
abstract_models
Operating conditions: slow
Interconnect mode: global
Area mode: physical library
==============================================================

Aspect ratio : 1.00

Shrink factor : 1.00
Scale of res/length : 1.00
Scale of cap/length : 1.00
Net derating factor : 1.00
Thermal factor : 1.00
Via Resistance : 6.40 ohm (from lef library)
Site size : 5.70 um (from lef [tech+cell])

Capacitance
Layer / Length Data source:
Name Direction Utilization (pF/micron) cap_table_file
------------------------------------------------
M1 H 0.00 0.000274
M2 V 1.00 0.000242
M3 H 1.00 0.000242
M4 V 1.00 0.000242
M5 H 1.00 0.000242
M6 V 1.00 0.000304

Resistance
Layer / Length Data source:
Name Direction Utilization (ohm/micron) lef_library
-------------------------------------------------
Metal1 H 0.00 0.439130
Metal2 V 1.00 0.360714
Metal3 H 1.00 0.360714
Metal4 V 1.00 0.360714

February 2023 36 Product Version 22.1

Metal5 H 1.00 0.360714

Metal6 V 1.00 0.102273

Area
Layer / Length Data source:
Name Direction Utilization (micron) lef_library
-------------------------------------------------
Metal1 H 0.00 0.230000
Metal2 V 1.00 0.280000
Metal3 H 1.00 0.280000
Metal4 V 1.00 0.280000
Metal5 H 1.00 0.280000
Metal6 V 1.00 0.440000

Note: The Interconnect mode in the report header is set to global, which indicates that
you are running in PLE mode.

Setting Appropriate Synthesis Mode

Genus has two synthesis modes: wireload and ple:
■ In wireload mode (default), you use wire-load models to drive synthesis.
■ In ple mode, you use Physical Layout Estimation (PLE) to drive synthesis. PLE is the
process of using physical information, such as LEF libraries, to provide better closure
with back-end tools.

These modes are set using the interconnect_mode attribute. To test and set this mode,
follow these steps:
1. The interconnect_mode attribute is automatically set to ple when you read in LEF
libraries.
2. To switch to the wireload mode, manually set the interconnect_mode attribute to
wireload after loading the LEF libraries.
Note: Do not change this setting for PLE or Genus-P flows.

February 2023 37 Product Version 22.1

Reading the Floorplan

Similar to providing timing and design constraints for the logic design, you should provide
physical constraints in the form of a floorplan when you use PLE flow.

In Genus, you provide floorplan information through a DEF file. DEF files can contain both
logical information and physical information.
■ Logical information includes grouping information and physical constraints
■ Physical information includes
❑ The die or block bounding box
The die determines the placement area and therefore influences the net length.
❑ Pin and macro locations
These influence the standard cell placement and thus the net length.

To read the floorplan, follow these steps:

1. Use the read_def command to import a DEF file:
genus:root:> read_def def_file

The DEF file must define the die size. For better synthesis results, you should also have
the pin, macro locations, and standard cell placement specified in the DEF.
2. Use the def_file attribute to check which DEF is loaded in the tool:
genus:root:> get_db design:design_name .def_file

Genus will perform a consistency check between the DEF and the Verilog netlist and issue
relevant messages if necessary. For example:
Parsing DEF file...
Warning : DEF parser message. [PHYS-155]
: WARNING (DEFPARS-7019): The PATTERNNAME statement is obsolete in version
5.6 and later.
Warning : Component not present in netlist. [PHYS-171]
: The component ’IOPADS_INST/Pcornerll’ does not exist.
: This message has a default max print count of ’25’, which can be
changed by setting the ’max_print’ attribute.
Warning : Component not present in netlist. [PHYS-171]
: The component ’IOPADS_INST/Pcornerlr’ does not exist.
...
Done parsing DEF file (time 0s).

An example of DEF statistics printed after the DEF file has been processed:

Figure 2-3 Example of DEF Statistics

February 2023 38 Product Version 22.1

Summary report for DEF file ’/xxx/floorplan/fplan_mp.def’

Components
----------
Cover: 0
Fixed: 71
Physical: 0
Bump: 0
Placed: 0
Unplaced: 1
TOTAL: 72 (1 is class macro)

There are 4 components that do not exist in the netlist.

Pins
----
Cover: 0
Fixed: 0
Physical: 5
Placed: 0
Unplaced: 57
TOTAL: 62

Nets
----
Read: 0
Skipped: 0
TOTAL: 0

SpecialNets
-----------
Read: 2
Skipped: 0
TOTAL: 2

Fences: 0
Guides: 1
Regions: 1
Done processing DEF file.

========================
Physical Message Summary
========================

5 / 5 I PHYS-154 Creating physical pin.

4 / 4 W PHYS-171 Component not present in netlist.
71 / 0 I PHYS-181 Full preserve set on instance.

Done reading and processing DEF file '/xxx/fplan_mp.def' (time: 1s).

Note: Genus supports DEF 5.8 and above. Refer to the LEF/DEF Language Reference
for more information on DEF files.

Related Topics
■ def_file
■ read_def

February 2023 39 Product Version 22.1

Components of DEF File Report

The following tables explain some of the components of the read_def command output
report.

Table 2-1 Component Types in DEF File Report

Type Explanation Tip

Cover A component that has a location and is a part of A large number of cover cells can indicate that
a cover macro. A COVER component cannot be the DEF file is not a floorplan but instead
moved. could be the DEF for a fully placed design.
Fixed A component that has a location and that cannot All components in a floorplan DEF should be
be moved by automatic tools. set as fixed to avoid unwanted movement
during placement
Physical A component that is instantiated in the DEF but A large number of physical components can
not in the netlist. indicate that the DEF is not a floorplan DEF.
Placed A component that has a location and that can be These components are not expected in a
moved by automatic tools. floorplan.
Unplaced A component that has no location. These components are not expected in a
floorplan.
class A large component. For example, a memory. The number of class macros should be less
macro than or equal to the number of fixed
components.

Table 2-2 Pin Types in DEF File Report

Type Explanation Tip

Cover A pin that has a location, orientation, and that is

part of the cover macro. A COVER pin cannot
be moved
Fixed A pin that has a location, orientation and that It is recommended to have all pins fixed.
cannot be moved by automatic tools.
Placed A pin that has a location, orientation and that
can be moved by automatic tools.
Unplaced A pin that has no location.

For more information on these terms, refer to the Glossary.

February 2023 40 Product Version 22.1

Related Topics
■ Glossary
■ read_def

Analyzing the Results of PLE Flow

You can use various reports to analyze results. report_area and report_qor are the
commonly used reports for analyzing the results.
1. Use the report_area command to print an area report:
genus:root:> report_area
===============================================================
Generated by: Genus(TM) Synthesis Solution version
Generated on: date
Module: DTMF_CHIP
Technology libraries: library1
library2
...
physical_cells
Operating conditions: slow
Interconnect mode: global
Area mode: physical library
=================================================================

Instance Module Cells Count Cell Area Net Area Total Area
-----------------------------------------------------------------------------
DTMF_CHIP 4969 1218398 74621 1293018
IOPADS_INST iopads 67 721450 0 721450
DTMF_INST dtmf_recvr_core 4902 496948 71032 567980
TDSP_CORE_INST tdsp_core 2831 74538 41884 116422
MPY_32_INST mult_32 775 21339 10900 32238
M16X16_INST m16X16 592 18422 7083 25505
EXECUTE_INST execute_i 631 21472 7071 28543
ALU_32_INST alu_32 583 8898 7730 16628
TDSP_CORE_GLUE_INST tdsp_core_glue 458 8073 5268 13341
DECODE_INST decode_i 157 5279 1394 6673
PROG_BUS_MACH_INST prog_bus_match 57 2628 474 3102
PORT_BUS_MACH_INST port_bus_match 57 2635 466 3100
DATA_BUS_MACH_INST data_bus_match 55 2644 437 3081
TDSP_CORE_MACH_INST tdsp_core_match 36 1221 383 1604
ACCUM_STAT_INST accum_stat 17 316 119 435
RAM_256x16_TEST_INST ram_256X16_test 17 113630 132 113762
RAM_128x16_TEST_INST ram_128X16_test 17 100778 132 100910
RESULTS_CONV_INST result_conv 1779 46573 23785 70358
ARB_INST arb 22 69455 233 69688
SPI_INST spi 45 2415 509 2924
DMA_INST dma 45 1943 454 2396
ULAW_LIN_CONV_INST ulaw_lin_conv 58 1207 592 1800
DATA_SAMPLE_MUX_INST data_sample_mux 28 659 85 744
DIGIT_REG_INST digit_reg 10 725 0 725
TDSP_DS_CS_INST tdsp_ds_cs 22 446 123 568
TDSP_MUX tdsp_data_mux 17 439 12 451

February 2023 41 Product Version 22.1

TEST_CONTROL_INST test_control 8 126 49 175

The Interconnect mode in the report header is still set to global because in the
simple PLE flow the design is synthesized without placement information.
The report shows the total count of cells mapped against the hierarchical blocks, the
combined cell area in each of the blocks and the top level design. The Cell Area
numbers are based on the information in the LEF libraries. The Net Area refers to the
estimated post-route net area and is based on the minimum wire widths defined in the
LEF and capacitance table files and the area of the design blocks.
2. Use the report_qor command to get an overall report containing slack information,
instance count, area information, cell power, runtime, and host name information.
genus:root:> report_qor
==============================================================
Generated by: Genus(TM) Synthesis Solution version
...
...
Interconnect mode: global
Area mode: physical library
==============================================================

Timing
--------

Clock Period
--------------
vclk1 5000.0
vclk01 5000.0
vclk2 5000.0
vclk02 6000.0

Cost Critical Violating

Group Path Slack TNS Paths
--------------------------------------
default No paths 0
vclk1 -423.7 -409 1
vclk01 No paths 0
vclk2 2021.0 0 0
vclk02 No paths 0
--------------------------------------
Total -409 1

Instance Count
--------------
Leaf Instance Count 4969
Physical Instance Count 0
Sequential Instance Count 546
Combinational Instance Count 4423
Hierarchical Instance Count 26

Area
------------
Cell Area 1216937.389

February 2023 42 Product Version 22.1

Physical Cell Area 0.000

Total Cell Area (Cell+Physical) 1216937.389
Net Area 69625.622
Total Net Area (Cell+Physical+Net) 1286563.011

Floorplan Utilization 36.04%

Max Fanout 540 (scan_enI)
Min Fanout 0 (DTMF_INST/DATA_SAMPLE_MUX_INST/
d_datain[13])
Average Fanout 2.5
Terms to net ratio 3.5
Terms to instance ratio 3.9
Runtime 115.987 seconds
Elapsed Runtime 3167 seconds
Genus peak memory usage: 415.35
Innovus peak memory usage: no_value
Hostname host

Since you performed physical synthesis and started with a floorplan, the report also
contains the floorplan utilization in %.

Related Topics
■ report_area
■ report_qor

Exporting Files for Place and Route

The final part of the physical flow involves exporting the data for place and route processing.
➡ Use the write_design -innovus command to export the data.

The write_design -innovus command generates the following files:

■ Netlist (.v)
■ SDC constraints (.sdc)
■ Tcl script (.invs_setup.tcl)
■ Genus init script (.genus_init.tcl)
■ Mode file (.mode)
■ DEF file (.def)
■ Metrics file (.metrics.json)
■ NDR and minimum layer data files (.ndr.tcl)

February 2023 43 Product Version 22.1

■ Timing derate file (.derate.tcl) — generated when Genus changed the default timing
derate values

February 2023 44 Product Version 22.1

Sample Script for Simple PLE Flow

set_db source_verbose true
set_db information_level 9"
set_db invs_temp_dir genus_invs
set_db init_lib_search_path path
set_db library "library_list"
set_db lef_library "lef_list"
# read parasitic information from capacitance table or QRC tech file
# set_db cap_table_file file
# set_db qrc_tech_file techfile.qrc
read_hdl DESIGN/dtmf_chip.v
elaborate DTMF_CHIP
report_ple
read_sdc dtmf.sdc
read_def DESIGN/floorplan/dtmf.def
syn_generic -physical
syn_map -physical
syn_opt
report_area
report_qor
write_design -innovus

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3
RTL Floorplanning Flow

■ RTL Floorplanning on page 48

❑ Settings Required for predict_floorplan Flow on page 49
❑ Incomplete DEF in RTL Floorplanning Flow on page 50
■ Recommended Flow on page 51

February 2023 47 Product Version 22.1

RTL Floorplanning
The early-physical and iSpatial flow in Genus involves placement of synthesized logic and,
hence, provides better correlation and prediction of back-end QOR. But, this flow requires a
floorplan. If, however, a floorplan DEF is not available, Genus can create one based on target
utilization.

Hence, if either no DEF file has been read (during early design stages), or, an incomplete
DEF has been read, you can use the RTL Floorplanning Flow. This flow calls Innovus for
creating a floorplan. This floorplan will be of sufficient quality to perform Genus functions but
will not include power routing, end-caps, and other such information.

Start

Set timing libraries

HDL Load HDL files or Netlist

files

Perform elaboration

Apply constraints

Apply optimization settings

Predict Floorplan

Synthesize

Handoff to Innovus

Note: This floorplan is just a rough starting point. You should carefully create a floorplan
based on the needs of the design. Things like the floorplan size, port locations, macro
placement, obstructions, and regions can have a very significant impact on the timing,
congestion, and overall QOR. The Genus-created floorplan is a very preliminary estimate of
the design QOR while running the iSpatial Flow.

February 2023 48 Product Version 22.1

Attributes Affecting the Flow

Attribute Name Object Type Default

aspect_ratio design double 1.000
invs_temp_dir root string
innovus_executable root
physical_force_predict_floorplan root boolean auto
predict_floorplan_allow_core_reshape root boolean true
predict_floorplan_allow_illegal_macro root boolean false
predict_floorplan_enable_during_generic root boolean false
predict_floorplan_keep_fences root boolean false
predict_floorplan_use_innovus root boolean false

Settings Required for predict_floorplan Flow

Some attributes need to be set before executing this flow.

1. When no DEF is present, and you want to invoke Innovus to predict the floorplan during
syn_generic -physical stage, set attribute
predict_floorplan_enable_during_generic to TRUE.
In this case, during syn_opt -spatial (iSpatial flow), Innovus would be invoked
automatically to create floorplan.
2. Set attribute physical_force_predict_floorplan to TRUE to invoke Innovus even
when you have complete DEF file.
Note: Ensure to reset physical_force_predict_floorplan attribute after
syn_generic -physical, otherwise, predict_floorplan flow will be again called
during iSpatial synthesis.
3. You can also call predict_floorplan as a standalone command to invoke Innovus to
create the floorplan.

February 2023 49 Product Version 22.1

Related Topics
■ predict_floorplan_enable_during_generic
■ physical_force_predict_floorplan
■ predict_floorplan

Incomplete DEF in RTL Floorplanning Flow

If DEF is read in Genus, but it is incomplete in terms of macro placement, that is, there are
macros in the netlist which are NOT marked FIXED or COVER, Innovus will be invoked to
create the floorplan.

In this case, Genus will give PHYS-61messages

:Design has macros not marked as FIXED/COVER. Floorplan estimation will be
invoked.

The predict_floorplan_use_innovus attribute should be set to call Innovus to do the

MACRO placement. This will call the GigaPlace GXL placer in Innovus.
Note: Macros will be placed regardless of whether you use this attribute or not. But they will
be placed better with this attribute set to true

In case a viable DEF is not loaded, Genus will error out during iSpatial flow (syn_opt -
spatial). To overcome this, set the physical_force_predict_floorplan attribute to
true. This will indicate Genus to invoke Innovus to create the floorplan first and then initiate
the iSpatial flow.
genus:root: > set_db physical_force_predict_floorplan true

Note: If you have to place the macros using this flow, it will check out the
Innovus_GigaPlace_GXL_Opt License.

In case Innovus is not invoked, it is safe to presume that Genus considers that floorplan DEF
provided with the netlist is complete.

Related Topics
■ physical_force_predict_floorplan

February 2023 50 Product Version 22.1

Recommended Flow
set_db invs_temp_dir invs_temp_dir
set_db innovus_executable path_to_innovus_build
...
set_db predict_floorplan_enable_during_generic true
set_db physical_force_predict_floorplan true; # if an incomplete input floorplan
is read before syn_generic
syn_generic -physical
syn_map -physical
set_db physical_force_predict_floorplan false; # to disable executing
predict_floorplan again
syn_opt -spatial
...

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4
iSpatial Flow

■ Genus iSpatial Flow

■ Attributes Affecting the iSpatial Flow
■ Pre-requisites for iSpatial Flow
■ Tasks Associated with iSpatial Flow
■ Basic Script for iSpatial Flow

February 2023 53 Product Version 22.1

Genus iSpatial Flow

The Genus Integrated Spatial (iSpatial) flow is targeted to deliver best-in-class PPA as part
of a full RTL2GDS implementation flow, as well as excellent prediction of preCTS QoR for the
RTL designers and synthesis engineers.

The iSpatial flow in Genus uses internal engines of Innovus for physical synthesis. This helps
realize a unified placement, routing, and optimization engine from front-end to back-end. This
helps to improve predictability of front-end synthesis to back-end placement and routing,
reducing optimization efforts that waste runtime, area, and power; and hence, shorter
turnaround time. The resulting layout can be directly taken into Innovus for further incremental
preCTS optimization. The flow can also be used to deliver quick feedback on floorplan quality.

The iSpatial flow also introduces physical restructuring. After placement and physical
optimization, the netlist can be restructured to improve the design efficiency and optimize
timing—when the true critical paths are visible.

This flow also supports Cadence or third-party DFT IP, which minimizes the impact of test on
PPA. It uses the scan reordering engine from the Innovus system, estimating congestion and
QoR in an earlier stage of the whole process, improving the consistency of the front-end and
back-end.

The whole flow runtime of the iSpatial flow has also been greatly reduced from bringing a
higher quality design into the Innovus system. Without having to optimize the placement, the
Innovus system only does incremental optimization, therefore converging timing quickly.

February 2023 54 Product Version 22.1

Figure 4-1 iSpatial Flow

Start

Design setup

iSpatial setup

DEF file Read floorplan

Synthesize

Analyze

Export files to Innovus

Handoff to Innovus

February 2023 55 Product Version 22.1

Attributes Affecting the iSpatial Flow

As the iSpatial flow utilizes the Innovus engines in form of a customized
place_opt_design call, most of the controls for this part of the flow are also available in
the Genus iSpatial context.

For the most common features, dedicated Genus attributes have been created to pass down
the flow configuration into the Innovus iSpatial call. Any other feature not available in Genus
via attribute can be injected into the flow via the postload script.

Attribute Name Object Default

design_power_effort root none
opt_drv_margin design 0.0
opt_spatial_effort root standard
opt_spatial_useful_skew root true
opt_spatial_early_clock root false
opt_spatial_merge_flops root false
opt_leakage_to_dynamic_ratio root 1.0
design_process_node root
invs_temp_dir root
invs_save_db root false
invs_preload_script root
invs_postload_script root
number_of_routing_layers root

Note: Use of a postload file is under limited access and needs a special key. Contact
Cadence support in case you need to use a postload file. You then need to set the keys via
the limited_access_feature attribute, as shown in the following example:
set_db limited_access_feature [list
{syn_opt_ispatial_restricted_features NNN} \
]

February 2023 56 Product Version 22.1

Pre-requisites for iSpatial Flow

The following files are needed for iSpatial flow execution:
■ Tech lef and standard cell (.lef) files
■ Liberty (.lib) files — standard cell files
■ Floorplan (.def) file
■ MMMC configuration file
Note: iSpatial flow requires an Innovus executable which is set using the
innovus_executable attribute or the environment variables – PATH or CDN_SYNTH_ROOT.

Note: Genus_Physical license is required to run the iSpatial Flow.

February 2023 57 Product Version 22.1

Tasks Associated with iSpatial Flow

The tasks below list only those that are different from the generic flow or illustrate a new step.
1. Reading the LEF Libraries
2. Loading Parasitic Information
3. Consistency between LEF and Parasitic Files
4. Setting Appropriate Synthesis Mode
5. Reading the Floorplan
6. Synthesizing the Design
7. Analyzing the Results
8. Exporting Files for Place and Route
9. Handing off to Innovus

Synthesizing the Design

After you have set the logical and physical constraints for your design, perform physical aware
synthesis. This helps in performing optimization taking physical domain into consideration.
1. Configure iSpatial flow using opt_spatial_effort attribute before synthesis.
With the default value (standard), it gives a decent PPA, but with
opt_spatial_effort set to extreme, it gives the best PPA with additional runtime.
For example,
set_db opt_spatial_effort extreme

2. Synthesize the design using the syn_* commands:

Note: To run DFT insertions, run them after syn_map and before iSpatial.
For example,
syn_gen -physical
syn_map -physical
<DFT insertions here> //optional
syn_opt -spatial

Analyzing the Results

You can analyze the results by generating the most important reports.

February 2023 58 Product Version 22.1

1. Use the write_snapshot command to generate important reports.

genus:root:> write_snapshot -directory report_directory -tag final

2. To get an overall report containing slack information, instance count, area information,
cell power, runtime, and host name information, use the report_qor command.
3. To print an area report, use the report_area command.

The timing information after iSpatial is based on accurate extraction data from Innovus and,
thus, correlates very well with timing seen after importing the design into Innovus.

Related Topics
■ report_qor
■ report_area

Exporting Files for Place and Route

The final part of the physical flow involves exporting the data for place and route processing.
➡ Use write_design -innovus -db to write out the DB file. The DB already contains
the placement and optimization data which allows Innovus place_opt_design to run
faster and converge better with a faster TAT automatically.

The write_design -innovus -db command generates the following files:

■ Netlist (.v)
■ Innovus configuration file (.invs_init.tcl),
■ SDC constraints (.sdc)
■ Tcl script (.invs_setup.tcl)
■ Mode file (.mode)
■ DEF file (.def) —of the floorplan
■ Timing derate file (.derate.tcl) — generated when Genus changed the default timing
derate values
■ An encrypted file containing placement information (.spl.etf). To reload this file, use
the decrypt command.

February 2023 59 Product Version 22.1

Handing off to Innovus

The output needs to be handed over to Innovus for the next steps.
➡ For standard flow, write_design -innovus -db will do database handoff.
DB handoff:
#load db from Genus
read_db outdir/final_db/design.stylus.enc
time_design -report_only
#execute prects optimization
place_opt_design

➡ For netlist handoff, use write_design -innovus command.

Netlist handoff:
#load only specific files from Genus
read_mmmc mmmc_config.tcl
read_physical -lef LEF_files
read_netlist outdir/final_netlist/design.v
init_design
time_design -report_only
#execute prects optimization
place_opt_design

Only the DB handoff passes the placement information to Innovus. DB contains information
that tells Innovus that a full place_opt_design is not required. Only the database handoff
ensures that a lot of the design setup like MMMC configuration, design-specific attributes like
dont_touch, dont_use are passed in a consistent manner between the tools. Hence, it is
recommended to not use the -incremental switch when running Innovus
place_opt_design in either handoff modes.
Note: When attribute opt_spatial_effort is set to extreme, write_db -innovus -
db would do DB handoff with placement and route information and pre-CTS would run in
incremental mode automatically. Also, if opt_spatial_effort is extreme, you can force
netlist handoff by using write_design -innovus -db -handoff false

February 2023 60 Product Version 22.1

Basic Script for iSpatial Flow

set_db invs_temp_dir genus_invs
set_db opt_spatial_effort exterme

# physical flow attributes

set_db design_process_node 7
set_db number_of_routing_layers 9

#For power optimization

set_db design_power_effort low
set_db opt_leakage_to_dynamic_ratio 1.0

read_def DESIGN/floorplan/xxx.def
#early physical flow
syn_generic -physical
syn_map -physical

#iSpatial call
syn_opt -spatial

#reports
report_qor
write_snapshot -directory output_directory -tag final

#write handoff DB for INVS prects

write_design -innovus -db -base_name ./final_db/design

# OR write netlist handoff files for INVS prects

# -gzip_files saves disk space and is optional
write_design -innovus -gzip_files -base_name ./final_db/design

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February 2023 62 Product Version 22.1

5
Genus-Physical Flow

■ Physical Flow
■ Attributes Affecting the Genus-Physical Flow
■ Tasks Associated with Genus-Physical Flow
■ Sample Script for Genus-Physical Flow

February 2023 63 Product Version 22.1

Physical Flow
In addition to using technology information and cell areas from the LEF libraries, and parasitic
resistance and capacitance values from the LEF libraries or capacitance tables, the Genus-P
flow uses a complete placement and considers congestion and legal placement as a cost
function during the RTL-to-gates phase, to create a better netlist. This flow ensures both the
best accuracy and the most predictable closure with back-end tools.

Specifically, the physical flow will:

■ Use physical process information along with areas and fanout to dynamically derive wire
length
■ Calculate load and delay using average resistance (in OHMs per micron) and
capacitance (in pF per micron) per unit length. The resistance and capacitance are
derived from the process technology information.
Alternatively, extracted resistance and capacitance parasitic information is used when
available.
■ Calculate wire area in microns using the average net width from the process technology
information
■ Perform physically-aware synthesis

This flow is useful for blocks or chips with complex floorplans.

February 2023 64 Product Version 22.1

Figure 5-1 Genus-Physical Flow

Start

Target
libraries
Read timing libraries

LEF libraries Read LEF libraries

Capacitance
file Load parasitic information
QRC tech
file
Review consistency between
LEF and parasitic files

Read HDL files and elaborate Modify source

HDL files
design

Set synthesis mode

Check physical layout

estimation information

Change physical constraints

DEF file Read floorplan

SDC Change SDC constraints

Apply constraints
constraints

Load generated PLE data Using

generated
Check physical layout PLE data
estimation information

No
Synthesize, estimate, and optimize for
silicon with syn_gen, syn_map, Meet
syn_opt -physical constraints?
Task added for
Physical
Analyze Yes

Optional task Perform incremental optimization with

syn_opt -physical -incremental

Export design

February 2023 65 Product Version 22.1

Attributes Affecting the Genus-Physical Flow

Attribute Name Object Type Default

aspect_ratio design double 1.000
auto_super_thread root boolean true
cap_table_file root string
congestion_avoid lib_cell boolean false
congestion_effort root enumerated type off
def_output_escape_multibit root boolean true
def_output_version root string 5.8
invs_assign_buffer root string none
invs_assign_removal root boolean false
invs_gzip_interface_files root boolean true
invs_launch_servers root string
invs_module_plan root boolean true
invs_postload_script root string
invs_pre_place_opt root boolean true
invs_preexport_script root string
invs_preload_script root string
invs_scan_def_file root string
invs_temp_dir root string
invs_timing_driven_place root boolean true
invs_user_contsraint_file root string
invs_user_mode_file root string
innovus_executable root
interconnect_mode root string wireload
lef_library root string
lef_stop_on_error root boolean false

February 2023 66 Product Version 22.1

Attribute Name Object Type Default

number_of_routing_layers design integer
phys_annotate_ndr_nets root boolean true
phys_checkout_innovus_lice root boolean false
nse
phys_fix_multi_height_cell root boolean false
s
phys_flow_effort root enumerated type medium
phys_ignore_nets design boolean false
phys_ignore_special_nets design boolean false
phys_mp_constraints root string no_value
phys_pre_place_iopt root string auto
phys_premorph_density root double 0.96
pqos_ignore_msv root boolean false
pqos_ignore_scan_chains root boolean false
pqos_placement_effort root enumerated type no_value
qos_report_power root string auto
qrc_tech_file root string
scale_of_cap_per_unit_leng root double 1.0
th
scale_of_res_per_unit_leng root double 1.0
th
shrink_factor root float
use_area_from_lef root enumerated type false
utilization layer float

February 2023 67 Product Version 22.1

Tasks Associated with Genus-Physical Flow

The tasks below list only those that are different from the generic synthesis flow or illustrate
a new step.
1. Setting up the Genus-Physical Flow
2. Reading the LEF Libraries
3. Loading Parasitic Information
4. Setting Appropriate Synthesis Mode
5. Checking Physical Layout Estimation Information
6. Loading Generated PLE Data
7. Synthesizing, Estimating, and Optimizing for Silicon
8. Analyzing the Results of Genus-Physical Flow
9. Exporting Files for Place and Route

Setting up the Genus-Physical Flow

For the Genus-Physical flow, you need to specify the Innovus version to be used.
1. Specify the Innovus executable that you want to use for the Genus-P flow by setting the
following root attribute:
set_db innovus_executable path_to_executable

2. If this attribute is not set, the following (default) search order is used:
❑ Innovus environment variable
❑ PATH environment variable
❑ CDN_SYNTH_ROOT environment variable

Handling Incomplete DEF File

In the absence of DEF file or an incomplete DEF file:
➡ Use the predict_floorplan command to create a DEF file for your design. This
command can be called at any stage after elaboration, that is, before syn_gen,
syn_map or syn_opt.

February 2023 68 Product Version 22.1

predict_floorplan
[-constraints file] [-script string] [design]

To use this command, you need to have the Innovus License and set the
innovus_executable attribute:
Alternatively, you can use the predict_floorplan_script attribute in place of the
-script option and set the predict_floorplan_constraints attribute for the
-constraints option for this command.
set_db innovus_executable <path_to_innovus>

Related Topics
■ predict_floorplan
■ innovus_executable

Loading Generated PLE Data

To load the PLE data you need to generate it. Refer to Generating PLE Correlation Data
for more information on how to create this file.
➡ To load the encrypted customized PLE information for the design, use the following command:
decrypt PLE_file

A successful restoration will issue the following message:

PLE correlation data restored.

Tip
When using physical-aware mapping in the Genus-Physical flow, you do not need to
use the create_ple_model flow. The PLE data is automatically generated based
on internally generated placement and using the native parasitic extraction engine.

If the PLE model is stale, the tool will issue warnings indicating a possible number of reasons
why the model might not be valid. Check the header of the encrypted file for clues.

When you compare the PLE report with the PLE report when no generated PLE data are
used, you see that the Data source for the capacitance and resistance values is no longer the
cap_table_file, but user override, because the values are based on trialRoute
extraction.

Figure 5-2 Report PLE with generated PLE data

genus:root:> report_ple
============================================================

February 2023 69 Product Version 22.1

.......
Interconnect mode: global
Area mode: physical library
============================================================
Aspect ratio : 0.98
Shrink factor : 1.00
Scale of res/length : 1.00
Scale of cap/length : 1.00
Net derating factor : 1.00
Thermal Factor : 1.00
Via Resistance : 6.40 ohm (from lef_library)
Site size : 5.70 um (from lef [tech+cell])
Capacitance
Layer / Length Data source:
Name Direction Utilization (pF/micron) user override
------------------------------------------------------------------
<extracted> U n/a 0.000126
<extracted> V n/a 0.000128
<extracted> H n/a 0.000125
Resistance
Layer / Length Data source:
Name Direction Utilization (ohm/micron) user override
------------------------------------------------------------------
<extracted> U n/a 0.353355
<extracted> V n/a 0.353355
<extracted> H n/a 0.353355
Area
Layer / Length Data source:
Name Direction Utilization (micron) lef_library
------------------------------------------------------------------
Metal1 H 1.00 0.230000
Metal2 V 1.00 0.280000
...
Metal6 V 1.00 0.440000

Related Topics
■ Generating PLE Correlation Data

Synthesizing, Estimating, and Optimizing for Silicon

After you have set the logical and physical constraints for your design, you can proceed with
synthesizing your design.
1. Synthesize the design
❑ To run the design without physical-aware mapping and physical-aware structuring,
use the following commands:
syn_gen
syn_map
syn_opt -physical

February 2023 70 Product Version 22.1

❑ To run physical-aware synthesis, use the following commands:

syn_gen -physical
syn_map -physical
syn_opt -physical

The syn_opt -physical command calls the Innovus place and route tool to create a
good quality initial placement.

Important
You will need the Genus Physical Option (GEN40) to execute the command and to
access an Innovus executable. It is highly recommended to use the same version of
Innovus as Genus, or at most one version older.
The syn_opt -physical command will not work with encrypted netlists.Therefore,
decrypt your netlist before using this command.
2. The tool generates several Innovus interface files during the syn_opt -physical
command. Files with the genus2invs prefix can be used to transfer data from Genus to
the Innovus place and route tool. Files with the invs2genus prefix can be used to
transfer data from the place and route tool to Genus. Before you use the syn_opt
-physical command, set the following root attribute to specify the directory where
these files should be stored.
genus:root:> set_db invs_temp_dir directory

Tip
Setting this attribute prevents deletion of the directory. In case you encounter a
program failure, you can use these files to restore the session.

In the Genus Physical flow, the assign statements inserted by Innovus on constants will not
be removed by default, because inserting extra buffers to remove assigns on constants could
lead to higher congestion. To remove assigns on constants after the Physical flow, use the
following command:
remove_assigns_without_optimization -dont_skip_unconstrained_paths \
-design design
Note: The command will not remove assignment statements when this could lead to an NEQ.

February 2023 71 Product Version 22.1

Analyzing the Results of Genus-Physical Flow

You can use the area report to analyze the physical design.
1. To print an area report, use the report_area command.
genus:root:> report_area
Computing net loads.
==============================================================
Generated by: Genus(TM) Synthesis Solution version
Generated on: date
Module: DTMF_CHIP
Technology libraries: library1
library2
...
physical_cells
Operating conditions: slow
Interconnect mode: placement
Area mode: physical library
==============================================================
Instance Module Cell Count Cell Area Net Area Total Area
---------------------------------------------------------------------------------
DTMF_CHIP 5304 1219518.676 98646.489 1318165.64
DTMF_INST_TEST_CONTROL_INST test_control 13 129.730 345.962 475.692

The Interconnect mode in the report header is now set to placement because the
design is synthesized using detailed placement information.
The report shows the total count of cells mapped against the hierarchical blocks, the
combined cell area in each of the blocks and the top level design. The Cell Area
numbers are based on the information in the LEF libraries. The Net Area refers to the
estimated post-route net area and is based on the minimum wire widths defined in the
LEF and capacitance table files and the area of the design blocks.
2. To get an overall report containing slack information, instance count, area information,
cell power, runtime, and host name information, use the report_qor command.
genus:root:> report_qor
===============================================================
Generated by: Genus(TM) Synthesis Solution version
...
Interconnect mode: placement
Area mode: physical library
===============================================================
Timing
--------

Clock Period
--------------
vclk01 5000.0
vclk02 5000.0
vclk1 5000.0
vclk2 6000.0

Cost Critical Violating

February 2023 72 Product Version 22.1

Group Path Slack TNS Paths

--------------------------------------
default No paths 0
vclk01 No paths 0
vclk02 No paths 0
vclk1 -156.5 156.5 1
vclk2 2603.7 0 0
---------------------------------------
Total -156.5 1

Instance Count
--------------
Leaf Instance Count 5304
Physical Instance Count 0
Sequential Instance Count 546
Combinational Instance Count 4758
Hierarchical Instance Count 1

Area
------------
Cell Area 1225632.599
Physical Cell Area 0.000
Total Cell Area (Cell+Physical) 1219518.676
Net Area 98646.488
Total Area (Cell+Physical+Net) 1318165.164

Floorplan Utilization 41.76%

Max Fanout 540 (FE_OFN7_scan_enI)
Min Fanout 0 (UNCONNECTED)
Average Fanout 2.5
Terms to net ratio 3.5220
Terms to instance ratio 3.8646
Runtime 508.12278 seconds
Elapsed Runtime 1326 seconds
Genus peak memory usage 1047.90
Innovus peak memory usage 1040.21
Hostname host

Physical Data
-------------
Total Net Length 352308.89 um
Average Net Length 60.62 um
Routing Congestion H: 0.08% V: 0.03%

Because you executed the syn_opt -physical command, the QoR report also
contains a Physical Data section that lists the total and average net length in micron,
and the routing congestion in %. Routing congestion is a measure of track overflow.

Related Topics
■ report_area
■ report_qor

February 2023 73 Product Version 22.1

Exporting Files for Place and Route

The final part of the physical flow involves exporting the data for place and route processing.
This is done through the write_design -innovus command.

The write_design -innovus command generates the following files:

■ Netlist (.v)
■ Innovus configuration file (.invs_init.tcl),
■ SDC constraints (.sdc)
■ Tcl script (.invs_setup.tcl)
■ Mode file (.mode)
■ DEF file (.def)
■ Timing derate file (.derate.tcl) — generated when Genus changed the default timing
derate values
■ Congestion map (.cmap.gz)
Note: The full DEF file that is generated is the exact same DEF file that was loaded or
generated by syn_opt -physical. However, Genus generates the information for the
Scan DEF file (.scan.def). Although the scan chains will be re-ordered in the back-end
once the placement is determined, any scan reordering done in synthesis is based on the
current placement. This placement may not be carried forward. For example, the placement
will change if more optimization is done in Genus. There will always be slight adjustments to
the scan order, which are best accomplished in the back-end. The scan DEF file is generated
for continual convergence: getting closer to the final result with each reordering.

Use the -base_name option to specify both an output directory and a custom basename:
genus:root:> write_design -innovus -base_name output/final

February 2023 74 Product Version 22.1

Sample Script for Genus-Physical Flow

set_db source_verbose true
set_db information_level 9
suppress_message "xxx "
set_db innovus_executable path_to_executable
set_db invs_temp_dir directory
set_db init_lib_search_path path
set_db library "library_list"
set_db lef_library "lef_list"
# read parasitic information from capacitance table or QRC tech file
# set_db cap_table_file cap_file
# set_db qrc_tech_file tech_file
read_hdl DESIGN/dtmf_chip.v
elaborate DTMF_CHIP
report_ple
read_def DESIGN/floorplan/dtmf.def
read_sdc dtmf.sdc
#if using generated PLE data, add following two commands
# decrypt PLE_file
# report_ple
syn_generic -physical
syn_map -physical
syn_opt –physical
syn_opt -physical -incremental
report_area
report_qor
write_design -innovus -base_name genp_output

February 2023 75 Product Version 22.1

February 2023 76 Product Version 22.1

6
Structured Data Path

■ SDP Capability
■ SDF File Syntax
❑ SDP File Skeleton
❑ column Statement Syntax
❑ inst Statement Syntax
❑ row Statement Syntax
❑ SDP File Syntax Summary
■ SDP Information in the Design Information Hierarchy
❑ Row with several instances
■ SDP Flows

February 2023 77 Product Version 22.1

SDP Capability
Genus with the Genus Physical Option allows you to specify Structured Data Path (SDP)
information to get better performance, power, and area.

You can specify the SDP information by importing an SDP relative placement file. Correct
SDP placement ensures uniform routing.

Use the SDP capability when:

■ The design is data path intensive, that is, the design contains standard cell columns and
rows that require alignment
■ Performance increase is required
■ Time to market does not allow for full custom flow

Important
SDP is a semi-custom methodology that requires manual intervention so you need
to have detailed design knowledge in order to get better speed, power, and area.
The tool makes it easy for you to try different SDP experiments and evaluate their
impact on congestion, timing, and power. However, the tool still relies on the relative
placement information you specify for placing and handling SDP elements.

Benefits of Using SDP

SDP provides a uniform environment for data path and control logic for placement, routing,
and timing analysis.

SDP controls data path cell placement so that SDP cells are fixed before normal placement
for other standard cells.

The main advantage of this SDP placement is that it ensures uniform routing.

February 2023 78 Product Version 22.1

SDF File Syntax

The list below describes the syntax conventions used in the SDP file statements.

literal or boldface Non-italic words indicate keywords that you must type literally.
They can only be used in the places indicated by the syntax.
Keywords are case insensitive.
italic Words in italics indicate user-defined arguments for which you
must substitute a name or a value.
| Vertical bars (OR-bars) separate possible choices for a single
argument.
[ ] Brackets denote options. When used with OR-bars, they
enclose a list of choices from which you can choose one.
{ } Braces denote arguments and are used to indicate that a
choice is required from the list of arguments separated by OR-
bars. You must choose one from the list
{ argument1 | argument2 | argument3 }
Braces, used in Tcl command examples, indicate that the
braces must be typed in.
... Three dots (...) indicate that you can repeat the previous
argument. If the three dots are used with brackets (that is,
[argument]...), you can specify zero or more arguments. If
the three dots are used without brackets (argument...), you
must specify at least one argument, but can specify more.
{ } Braces in bold-face type must be entered literally.

February 2023 79 Product Version 22.1

SDP File Skeleton

The SDP file describes the relative placement of structured datapath elements in the design.
The following table describes the various statements used in an SDP file.
[alias new_keyword predefined_keyword]...
datapath name {
[hierPath name]
[origin x y]
{row row {...} | column {...} }...
}...

Statement Syntax Description

alias alias new_keyword Redefines a predefined keyword. You can
predefined_keyword redefine any predefined keyword. .
datapath datapath name { Describes the relative placement of a data
[hierPath name] path structure. The file can have many
[origin x y]
datapath statements, each describing the
{row row {...} | column
{...} }..... placement of one data path component. The
}... placement is described in terms of rows and
columns that can be nested.
column column column { Describes one column in the relative
[ orient placement of a data path structure. A
{R0|R90|R180|R270|MX|MY|
column statement can be specified many
MY90|MX90}]
[ justifyBy times in a datapath statement. It can
{NW|SW|SE|NE|W|E|N|S|MID appear almost immediately after the
}] datapath statement or it can appear within
[ flip {X| Y| XY}] a row statement.
[ skipSpace Val A column can contain the following
| inst name [orient elements: empty spaces, instances or rows.
{...}] [justifyBy {...}] These elements will be placed in the column
[flip {...}]
in the order they are specified in the column
| row row {...}]...
} statement.

inst inst name Describes an instance. An instance

[orient statement can be specified many times in a
{R0|R90|R180|R270|MX|MY|
column or row statement.
MY90|MX90}]
[justifyBy
{NW|SW|SE|NE|W|E|N|S|MID
}]
[flip {X| Y| XY}]

February 2023 80 Product Version 22.1

row row row { Describes one row in the relative placement

[ orient of a data path structure. A row statement
{R0|R90|R180|R270|MX|MY|
can be specified many times in a datapath
MY90|MX90}]
[ justifyBy statement. It can appear almost immediately
{NW|SW|SE|NE|W|E|N|S|MID after the datapath statement or it can
}] appear within a column statement.
[ flip {X| Y| XY}]
A row can contain the following elements:
[ skipSpace Val empty spaces, instances or columns. These
| inst name [orient elements will be placed in the row in the
{...}] [justifyBy {...}] order they are specified in the row
[flip {...}]
statement.
| column column
{...}]...
}

Related Topics
■ SDP File Syntax Summary
■ row Statement Syntax
■ column Statement Syntax
■ inst Statement Syntax

datapath Statement Syntax

The following table explains the syntax of the datapath statement in SDP.

column {...} Describes one column in the relative placement.

hierPath name Specifies the hierarchical path name of the data path structure
in the design.
name Specifies the name of one data path structure.
origin x y Specifies the location of the database structure.
row {...} Describes one row in the relative placement.

February 2023 81 Product Version 22.1

column Statement Syntax

The following table explains the syntax of the column statement in SDP.

column Specifies the name of the column.

flip {X | Y | XY} Specifies to flip the column (and its elements) around the X or Y
axis, or both.
Default: Y
justifyBy {SW|SE|NW|NE|N|W|S|E|MID}
Specifies the anchor point that will be used to align the column.
Default: SW
inst name Describes one instance in the column.
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Specifies the orientation to be set for the column.
Default: R0
row {...} Describes one row in the column.
skipSpace Val Skips the specified number of spaces in the column.

inst Statement Syntax

The following table explains the syntax of the inst statement in SDP.

flip {X | Y | XY} Specifies to flip the instance around the X or Y axis, or both.
Default: Y
justifyBy {SW|SE|NW|NE|N|W|S|E|MID}
Specifies the anchor point that will be used to align the
instance.
Default: SW
name Specifies the name of the instance.
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Specifies the orientation to be set for the instance.

February 2023 82 Product Version 22.1

Default: R0

row Statement Syntax

The following table explains the syntax of the column statement in SDP.

column Describes one column in the row.

flip {X | Y | XY} Specifies to flip the row (and its elements) around the X or Y
axis, or both.
Default: Y
justifyBy {SW|SE|NW|NE|N|W|S|E|MID}
Specifies the anchor point that will be used to align the row.
Default: SW
inst name Describes one instance in the row.
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Specifies the orientation to be set for the row.
Default: R0
row Specifies the name of the row.
skipSpace Val Skips the specified number of spaces in the row.

February 2023 83 Product Version 22.1

SDP File Syntax Summary

[alias new_keyword predefined_keyword]...
datapath name {
[hierPath name]
[origin x y]
row row {
[ orient {R0|R90|R180|R270|MX|MY|MY90|MX90}]
[ justifyBy {NW|SW|SE|NE|W|E|N|S|MID}]
[ flip {X| Y| XY}]

[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| column column {
[ orient {...}]
[ justifyBy {...}]
[ flip {...}]

[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| row row {
[ orient {R0|R90|..}]
[ justifyBy {NW|SW|SE|NE|W|E|N|S|MID}]
[ flip {X| Y| XY}]
[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| colomn column {... }]...
}
}...
}...
}...
datapath name {
[hierPath name]
[origin x y]
column column {
[ orient {R0|R90|..}]
[ justifyBy {NW|SW|SE|NE|W|E|N|S|MID}]
[ flip {X| Y| XY}]

[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| row row {
[ orient {...}]
[ justifyBy {...}]
[ flip {...}]

[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| column column {
[ orient {R0|R90|..}]
[ justifyBy {NW|SW|SE|NE|W|E|N|S|MID}]
[ flip {X| Y| XY}]
[ skipSpace Val
| inst name [orient {...}] [justifyBy {...}] [flip {...}]
| row row {... }]...
}
}...
}...
}...

February 2023 84 Product Version 22.1

SDP Information in the Design Information Hierarchy

Genus stores the original design data along with additional information in the SDP file in the
design information hierarchy in the form of attributes. The following figure highlights where the
information is stored in the design information hierarchy.

Figure 6-1 Design Information Hierarchy

(genus:root:>)
root

designs dex hdl_libraries libraries messages obj_types

design
SDP
constants

cpf

dex_settings

dft

hinsts

insts

instances_seq

modes

nets

hnets

port_busses_out

ports_in

ports_out sdp_instances

power sdp_columns sdp_column sdp_rows • ••

sdp_groups sdp_group

subdesigns sdp_rows sdp_row sdp_columns •••

timing sdp_instances

February 2023 85 Product Version 22.1

The design hierarchy has a directory for datapath components, columns, rows, and instances.
To represent spaces between rows, columns, and instances, the concept of dummy rows,
columns, and instances was introduced. For each row, column, or instance defined in the
SDP file a corresponding dummy is added:
■ skip_column_x
■ skip_row_x
■ skip_instance_x

Each dummy item has the same attributes as the corresponding actual items, but only two
attributes are relevant: index and skip_value. These attributes give an indication of the
position of the empty spaces and how many empty spaces there are. See the examples below
for more information.

Example 6-1 Row with several instances

SDP file
datapath my_row {
row adder {
justifyBy SW
inst inMux
inst inFF
inst leftShifter
inst rightShifter
inst outFF
inst outMux
}
}

Visual Representation

February 2023 86 Product Version 22.1

Representation in the hierarchy

/designs/test/sdp_groups/my_row/
/designs/test/sdp_groups/my_row/sdp_columns ;empty
/designs/test/sdp_groups/my_row/sdp_rows/
/designs/test/sdp_groups/my_row/sdp_rows/adder
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_columns ;empty
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_0
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_1
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_2
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_3
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_4
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/skip_instance_5
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/inFF
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/inMux
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/leftShifter
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/outFF
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/outMux
/designs/test/sdp_groups/my_row/sdp_rows/adder/sdp_instances/rightShifter
/designs/test/sdp_groups/my_row/sdp_rows/skip_row_0/
/designs/test/sdp_groups/my_row/sdp_rows/skip_row_0/sdp_columns ;empty
/designs/test/sdp_groups/my_row/sdp_rows/skip_row_0/sdp_instances ;empty

In this example, one actual row was created with 6 instances (shown in blue). The tool created
dummy entries for each of these actual SDP items (shown in red). Since the SDP file has no
skipSpace statements, the skip_value will be 0 for all the dummy entries.

February 2023 87 Product Version 22.1

Example 6-2 Columns nested in row

SDP file
datapath mydp {
row adder {
justifyBy SW
column inMux {
inst M0
inst M1
inst M2
}
column inFF {...}
skipSpace 2
column outFF {...}
column outMux {...}
}
}

Visual Representation

February 2023 88 Product Version 22.1

Representation in the hierarchy

/designs/test/sdp_groups/mydp
/designs/test/sdp_groups/mydp/sdp_columns ;empty
/designs/test/sdp_groups/mydp/sdp_rows
/designs/test/sdp_groups/mydp/sdp_rows/adder
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inFF
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inFF/sdp_instances/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inFF/sdp_rows/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/M0
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/M1
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/M2
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/skip_instance_0
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/skip_instance_1
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_instances/skip_instance_2
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/inMux/sdp_rows ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outFF
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outFF/sdp_instances/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outFF/sdp_rows/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outMux
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outMux/sdp_instances/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/outMux/sdp_rows/...
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_0
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_0/sdp_instances ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_0/sdp_rows ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_1
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_1/sdp_instances ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_1/sdp_rows ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_2
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_2/sdp_instances ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_2/sdp_rows ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_3
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_3/sdp_instances ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_columns/skip_column_3/sdp_rows ;empty
/designs/test/sdp_groups/mydp/sdp_rows/adder/sdp_instances ;empty
/designs/test/sdp_groups/mydp/sdp_rows/skip_row_0
/designs/test/sdp_groups/mydp/sdp_rows/skip_row_0/sdp_colums ;empty
/designs/test/sdp_groups/mydp/sdp_rows/skip_row_0/sdp_instances ;empty

This example has one actual row with 4 columns (shown in blue). The first column has 3
instances. The dummy entries for each of these actual SDP items are shown in red. The SDP
file has one skipSpace statement, the skip_value will be 2 for skip_column_1.

February 2023 89 Product Version 22.1

SDP Flows
There are two flows using Genus Physical and Innovus
■ Datapath-SDP Flow or Combinational Flow
■ FF Column SDP Flow

These flows can also be used in combination.

The type of flow can be set through the attribute sdp_type. The default value is no_value.

These flows read in an SDP file which describes the relative placement of structured datapath
elements in the design. To read in a SDP relative placement file, use the read_sdp_file.

Related Topics
■ sdp_type
■ read_sdp_file
■ FF Column SDP Flow

February 2023 90 Product Version 22.1

Datapath-SDP Flow
Also known as the Combinational Flow, this flow is used for large SDP blocks in the design
as shown in the figure.

Figure 6-2 Datapath SDP Flow or Combinational Flow

February 2023 91 Product Version 22.1

FF Column SDP Flow

This flow is used for small and medium-sized SDP blocks as shown in the following figure:

Figure 6-3 One pass FF Column SDP Flow

February 2023 92 Product Version 22.1

A
Terminology

■ Abbreviations
■ Glossary

February 2023 93 Product Version 22.1

Abbreviations

DEF Design Exchange Format

LEF Library Exchange Format
PLE Physical layout Estimation
R/C Resistance/Capacitance (parasitics)
Genus-P Genus with Physical
SDC Synopsys Design Constraints
SPEF Standard Parasitic Exchange Format
SVP Silicon Virtual Prototype
WLM Wire Load Model

February 2023 94 Product Version 22.1

Glossary

Term Origin Definition

BLOCKAGES DEF Prevent either placement or routing in the
specified area. Types are:
LAYER—prevent signal net routing
PLACEMENT—prevent placement. See also
SOFT, PARTIAL, and PUSHDOWN.
BUMP DEF Defines a solder bump on the chip.
Bumps are instantiated in the DEF
COMPONENTS section but not instantiated in
the netlist. Bump cells are usually placed with
+ COVER placement status.
CLASS DEF Defines the macro type. Examples are:
BLOCK—hierarchical block
CORE—standard cell, including memory cells
COVER—contains fixed floorplan data, such as
power routing
PAD—I/O cell
congestion tool Measures the routability of the design by
comparing the number of required tracks and
the number of available tracks.
density screen See PARTIAL
FENCE DEF Type of REGION that only allows instances
associated with the region to be placed in it.
FILL DEF Rectangular shape that defines a metal fill in
the design.
gcell One unit of the GCELLGRID.
GCELLGRID DEF Global routing grid whose cells enclose a
specified number of tracks
GROUPS DEF Defines a group of components (logical
elements) that are typically placed close
together.

February 2023 95 Product Version 22.1

Term Origin Definition

You can associate a REGION with a group. If
you do not associate a region with the group,
the group can be placed anywhere but the
instances in the group will be placed closely
together.
GUIDE DEF Type of REGION in which instances associated
with the region should be placed by preference.
Other instances can also be placed in this
region, and the instances associated with the
region can migrate outside the boundary of the
region.
HALO DEF Placement blockage around a component. This
type of blockage is associated with the
component. As a result a halo moves with the
component.
LAYER LEF Layer information.
MACRO LEF Physical description of a library cell.
morphing Genus Congestion optimization technique that moves
cells from high utilization regions to low
utilization regions.
NETS DEF Defines the netlist connectivity for nets.
NONDEFAULTRULES DEF Nondefault rules used in this design that are not
specified in the LEF file.
OBS LEF Routing layer obstruction associated with a
MACRO.
PARTIAL (placement DEF Type of PLACEMENT blockage that allows a
blockage) percentage of the blockage area to be used for
standard cells during initial placement.
pcell Cell with a physical description that does not
appear in the RTL/netlist. Examples are filler
cells, antenna cells, feedthrough cells.
pdomain tool Physical information for a CPF power domain.
PIN DEF Defines the direction, layer, location, and size of
a signal or power connection point on a
MACRO.

February 2023 96 Product Version 22.1

Term Origin Definition

PITCH LEF Defines the distance between routing tracks in
the preferred direction for a given routing layer.
porosity tool Measure of unused space during initial
placement which allows for cell resizing and
new cell insertion during optimization.
process shrink Technique to create a new process by optically
shrinking the geometries from an existing
process.
PUSHDOWN DEF Type of PLACEMENT blockage created a
higher level in the hierarchy and pushed down
into the block.
REGION DEF Defines a location (physical area) for a GROUP.
By default, all instances in the group are placed
inside the predefined location, but other
instances can also be placed in this location.
You can further constrain a region by assigning
a type: choose between FENCE and GUIDE.
Rho capacitance resistivity table based on the width and spacing
table of the layer
ROW DEF Core rows in the core area of the design define
the legal placement locations for the standard
cells.
ShrinkFactor capacitance Factor used to model the process shrink
table technique.
SITE LEF Defines a placement site in the design
SOFT (placement DEF Type of PLACEMENT blockage that prevents
blockage) instances from being placed in the specified
area during initial placement.
SLOTS DEF Defines the rectangular shapes that are cut into
wide metal wires to prevent dishing.
SPACING LEF Specifies the minimum spacing allowed
between wires on the same layer, or between
two via cuts on the same net or on different
nets.

February 2023 97 Product Version 22.1

Term Origin Definition

SPECIALNETS DEF Describes the wiring of prerouted nets, such as
power and ground nets. These nets are not
touched by the automatic router.
steiner tree An algorithm to find the shortest interconnect for
a given set of objects. Given a set V of points
(vertices), "steiner tree" interconnects them by a
network (graph) of the shortest length, where
the length is the sum of the lengths of all edges.
STYLES DEF A style polygon defines a wire's outer boundary.
TRACKS DEF Predefined routing resources that define the
routing grid.
utilization tool Percentage of available placement area filled
with placed instances. High utilization can lead
to congestion. Low utilization can lead to long
wires and need for buffering.
VIAS DEF Describes fixed vias and generated vias.
■ A fixed via is defined using rectangles or
polygons, and does not use a VIARULE.
■ A generated via is defined using VIARULE
parameters that are derived from a
VIARULE GENERATE statement in the LEF
file.
All vias consist of shapes on three layers: a cut
layer and two routing layers that connect
through the cut layer.

February 2023 98 Product Version 22.1

Index
A simple PLE flow 45
SDF file
attributes syntax 79
cap_table_file 34, 35 SDP file
def_file 38 reading in 90
innovus_executable 68, 69
interconnect_mode 37
lef_library 33
predict_floorplan_constraints 69
predict_floorplan_script 69
qrc_tech_file 34, 35

C
cells
reporting cell count 42, 72
commands
predict_floorplan 68
read_def 38
read_sdp_file 90
report_area 41, 59, 72
report_ple 36, 37
report_qor 42, 43, 59, 72, 73
syn_opt -physical 70, 71
write_design -innovus 43, 59, 74

D
design information hierarchy
physical information 25
SDP information 85

P
physical information
in design hierarchy 25

S
scripts
Genus-Physical flow 75
ispatial flow 61

February 2023 99 Product Version 22.1

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