Holistic Optimization Framework for FPGA Accelerators

STÉPHANE POUGET, University of California, Los Angeles

MICHAEL LO, University of California, Los Angeles
LOUIS-NOËL POUCHET, Colorado State University
JASON CONG, University of California, Los Angeles
Customized accelerators have revolutionized modern computing by delivering substantial gains in energy efficiency and performance
arXiv:2501.09242v4 [cs.AR] 6 Apr 2025

through hardware specialization. Field-Programmable Gate Arrays (FPGAs) play a crucial role in this paradigm, offering unparalleled
flexibility and high-performance potential. High-Level Synthesis (HLS) and source-to-source compilers have simplified FPGA devel-
opment by translating high-level programming languages into hardware descriptions enriched with directives. However, achieving
high Quality of Results (QoR) remains a significant challenge, requiring intricate code transformations, strategic directive placement,
and optimized data communication.
This paper presents Prometheus, a holistic optimization framework that integrates key optimizations—including task fusion,
tiling, loop permutation, computation-communication overlap, and concurrent task execution—into a unified design space. By leveraging
Non-Linear Programming (NLP) methodologies, Prometheus explores the optimization space under strict resource constraints, enabling
automatic bitstream generation. Unlike existing frameworks, Prometheus considers interdependent transformations and dynamically
balances computation and memory access.
We evaluate Prometheus across multiple benchmarks, demonstrating its ability to maximize parallelism, minimize execution stalls,
and optimize data movement. The results showcase its superior performance compared to state-of-the-art FPGA optimization frame-
works, highlighting its effectiveness in delivering high QoR while reducing manual tuning efforts.

CCS Concepts: • Hardware → High-level and register-transfer level synthesis; • Software and its engineering → Compilers.

Additional Key Words and Phrases: High-Level Synthesis, NonLinear Programming, Compiler

1 Introduction
The rise of customized accelerators has revolutionized modern computing, driving significant improvements in energy
efficiency and performance through hardware specialization. Among these accelerators, Field-Programmable Gate Ar-
rays (FPGAs) have gained widespread adoption due to their flexibility, high performance, and adaptability across di-
verse domains, including machine learning, scientific computing, financial modeling, and embedded systems. Unlike
fixed-function hardware such as Application-Specific Integrated Circuits (ASICs), FPGAs offer reconfigurability, en-
abling hardware adaptation to workload-specific requirements. However, achieving a good Quality of Result (QoR) on
FPGAs remains a complex and resource-intensive process, requiring careful tuning of computation, memory access,
and parallelism strategies.
To address this complexity, High-Level Synthesis (HLS) tools and source-to-source compilers [8, 19, 29, 30, 36, 39, 46,
58, 60, 75, 76, 78, 79, 81] have emerged as critical enablers of FPGA adoption, allowing developers to write hardware-
accelerated programs in high-level languages such as C++ and Python. These tools generate synthesizable hardware
descriptions, leveraging pragmas (hardware directives) and code transformations to optimize execution. Despite their
advantages, HLS-generated designs still require substantial manual tuning to achieve high QoR, as the compiler’s
ability to optimize performance remains highly dependent on the structure and directives applied to the input code.
Authors’ Contact Information: Stéphane Pouget, [email protected] of California, Los Angeles; Michael Lo, [email protected] of
California, Los Angeles; Louis-Noël Pouchet, [email protected] State University; Jason Cong, [email protected] of California,
Los Angeles.
1
2 Pouget et al.

1.1 Challenges in FPGA Optimization

Despite significant advancements in HLS automation and FPGA design methodologies, achieving high-performance
and resource-efficient FPGA implementations remains a challenging problem. This complexity arises from the intricate
interactions between computation, memory access, and parallel execution strategies. Several key challenges must be
addressed to unlock the full potential of FPGA acceleration.
Code Transformation and Design Space Exploration: FPGA performance is highly dependent on how compu-
tations are structured and scheduled. Optimizations such as loop tiling, loop permutation, and loop unrolling play a
crucial role in exposing parallelism and improving memory access efficiency.
Task Concurrency and Resource Management: Maximizing throughput in FPGA designs requires efficient task
concurrency, where multiple computation kernels execute in parallel. However, coordinating parallel tasks introduces
challenges in managing resource contention, memory bandwidth, and routing complexity. Overlapping computations
effectively demands intelligent scheduling strategies that minimize stall cycles while avoiding bottlenecks caused by
limited on-chip storage and off-chip memory latency.
Computation-Communication Overlap: FPGA acceleration is often hindered by inefficient data movement be-
tween off-chip memory (DDR/HBM) and on-chip compute units. Many workloads experience severe performance
degradation due to memory access bottlenecks rather than computational limitations. Dataflow architectures aim to
address this by implementing FIFO-based streaming to pipeline data transfers, but they often fail to exploit intra-task
parallelism efficiently. In contrast, shared buffer models [58, 78] improve data reuse, but their rigid memory manage-
ment strategies make it difficult to overlap computation and communication dynamically. A more adaptive approach
is needed to orchestrate data movement in parallel with execution, reducing overall memory stalls.
Scalability and Multi-SLR Utilization: FPGA architectures, especially those using Stacked Silicon Interconnect
(SSI) technology, feature multiple Super Logic Regions (SLRs) to enhance scalability. However, most frameworks, in-
cluding Merlin-based tools (e.g., AutoDSE, HARP, NLP-DSE) and Sisyphus, restrict designs to a single SLR, leading to
underutilization of FPGA resources. While designing across multiple SLRs is possible, it significantly increases routing
congestion, timing closure failures, and bitstream generation complexity. Without an SLR-aware optimization strategy,
large-scale tasks face a high probability of bitstream generation failures or degraded performance due to excessive
inter-SLR communication overhead.
Comprehensive Design Space Exploration: Current design space exploration (DSE) methodologies are often
narrow in scope, considering only a limited subset of optimizations at a time. Each transformation—whether it in-
volves loop reordering, tiling, pipelining, or data partitioning—has a profound impact on the overall performance and
resource usage. Frameworks that optimize only one aspect of the design fail to account for the interdependencies be-
tween different optimizations, leading to suboptimal results. To achieve maximum efficiency, FPGA designs require a
global optimization approach that integrates all possible transformations while considering the constraints imposed
by memory hierarchy, computation parallelism, and hardware utilization.
Addressing these challenges requires a unified optimization strategy that seamlessly integrates code transformation,
task concurrency management, computation-communication overlap, and hardware-aware scheduling into a single
framework. The proposed work aims to develop such an approach, ensuring high-performance FPGA implementations
while maintaining synthesis feasibility.
Holistic Optimization Framework for FPGA Accelerators 3

1.2 Contributions and Prometheus Method

This work introduces Prometheus, a unified framework that automates FPGA design space exploration by integrating
multiple optimizations into a single methodology. Unlike existing tools that optimize isolated aspects of FPGA acceler-
ation, Prometheus holistically addresses code transformation, memory management, task concurrency, and hardware-
aware scheduling. It leverages a hybrid execution model that balances shared memory reuse and dataflow streaming
to maximize parallelism while minimizing memory overhead.
To explore the vast design space efficiently, Prometheus formulates the optimization process as a Non-Linear Pro-
gramming (NLP) problem, enabling automatic selection of loop transformations, tiling strategies, pragma configura-
tions, and memory partitioning policies. Unlike heuristic-based approaches, this formulation captures complex opti-
mization interdependencies and ensures globally efficient designs. Additionally, Prometheus incorporates SLR-aware
task scheduling, which partitions tasks across multiple Super Logic Regions (SLRs). This addresses a major limitation in
prior works that restrict execution to a single SLR, leading to underutilization of FPGA resources. By integrating SLR-
aware optimizations, Prometheus reduces routing congestion, improves scalability, and ensures successful bitstream
generation.
The methodology follows a structured process: First, Prometheus performs affine code analysis to identify paral-
lelism opportunities and dependencies. It then generates a dataflow graph and fuses tasks that share the same outputs
to minimize unnecessary communication overhead. Next, Prometheus constructs a comprehensive design space that
includes all key optimizations outlined in Section 2, such as task concurrency via dataflow, computation-communication
overlap, and adaptive parallelism, while ensuring resource constraints are met for each SLR. The NLP-based design space
exploration model, as described in Section 4, is then employed to identify the theoretically optimal set of transforma-
tions. Once the best configuration is identified, Prometheus automatically generates the optimized design. Finally, the
system produces an OpenCL host code and compiles the FPGA bitstream with the HLS compiler.
The key contributions of this work are:

• Unified FPGA optimization framework that jointly optimizes loop transformations, pragma insertion, task con-
curency and computation-communication overlap while considering interdependencies between computation
and data movement.
• Hybrid execution model that dynamically selects between shared buffering and dataflow streaming to maxi-
mize parallelism and efficient memory access.
• NLP-based design space exploration that automates the selection of loop tiling, scheduling, and memory strate-
gies for globally theoretical optimal performance.
• SLR-aware scheduling and multi-SLR partitioning to balance routing complexity and FPGA resource utilization,
overcoming single-SLR limitations in prior works.
• End-to-end compilation and automation that generates optimized HLS-C++ code, OpenCL host code, and FPGA
bitstreams with minimal manual intervention.
• Comprehensive performance evaluation, demonstrating superior QoR compared to AutoDSE [65], Sisyphus [58],
ScaleHLS [78], Stream-HLS [8] and Allo [14].
4 Pouget et al.

2 Background and Motivation

Optimizing latency and performance in FPGA designs relies on a combination of code transformations and strategic
insertion of directives within High-Level Synthesis (HLS) [18]. This section explores various HLS optimization tech-
niques, their role in enhancing parallelism and resource utilization, as well as their limitations and challenges.
Table 1 presents a comparative analysis of various frameworks built on top of AMD Vitis HLS. These frameworks are
categorized based on their underlying methodologies, including Model-Free, AI-Based, Cost Model Communication,
Cost Model Computation, and NLP-Based approaches. The table evaluates their capabilities across key optimization
techniques and objectives.

2.1 HLS Optimization

2.1.1 Pragma Insertion. HLS optimizations rely extensively on a range of directives that control loop execution, data
access patterns, and computation scheduling to maximize performance. Among these, three fundamental pragmas—unroll,
pipeline, and array partitioning—are particularly critical for improving parallelism and reducing execution latency.
The unroll directive enables the expansion of loop iterations in the hardware design, allowing multiple iterations
to execute in parallel. By eliminating loop control overhead and enabling greater resource utilization, unrolling can
significantly boost throughput. However, its effectiveness is limited by FPGA resource constraints, such as available
DSP slices, BRAM, and routing congestion.
The pipeline pragma restructures loop execution to allow overlapping operations, thereby reducing the initiation in-
terval (II)—the number of cycles required to launch consecutive iterations. This directive is essential for achieving high
throughput in applications with iterative computations, such as matrix multiplications and stencil operations. Careful
tuning of pipeline depth and initiation interval is necessary to balance resource usage while avoiding performance
bottlenecks due to memory access contention.
Array partitioning is another crucial optimization that enhances memory access parallelism. By splitting large arrays
into smaller banks stored in separate on-chip BRAM blocks or distributed memory structures, this pragma allows
simultaneous data accesses, facilitating more effective unrolling and pipelining. Without partitioning, memory conflicts
and bandwidth limitations can restrict performance, especially with multiple concurrent memory accesses.
Beyond these fundamental pragmas, additional directives such as loop flattening, and dependency pragmas can fur-
ther optimize execution. Loop flattening combines nested loops into a single loop to improve hardware efficiency.
Dependency pragmas help manage data dependencies to ensure efficient scheduling without unnecessary synchro-
nization delays.
Pragma insertion has been extensively studied using various methodologies to optimize performance and resource
utilization in HLS designs. These approaches include bottleneck analysis, as employed by AutoDSE [65], performance
estimation through Graph Neural Networks (GNN) in frameworks like Harp [64], and cost model optimization lever-
aging Non-Linear Programming (NLP) in NLP-DSE [56, 57].
Each method presents distinct advantages and limitations. AutoDSE achieves full accuracy by running the HLS com-
piler for each configuration, ensuring precise performance measurements. However, this approach is computationally
expensive and time-consuming, making it impractical for rapid design exploration. HARP, on the other hand, can esti-
mate performance across configurations without direct compilation, significantly reducing evaluation time. However,
it requires extensive training datasets and fine-tuning for each new kernel to accurately model compiler behavior.
While this approach enables learning-based adaptation to different designs, its effectiveness depends heavily on data
Holistic Optimization Framework for FPGA Accelerators 5

Model AI Model Cost Cost NLP-Based

Free Model Model
Commu- Compu-
nication tation
AutoDSE HARP PolyOpt- ScaleHLS HeteroCL StreamHLS NLP- Sisyphus Prometheus
[65] [64] HLS [54] [78] / [36] / [8] DSE [57] [58]
POM [80] Allo [14]
Pragma Insertion ✓ ✓ Limit. ✓ ✓ ✓ ✓ ✓ ✓
Code Transfor- ✗ ✗ ✓ Limit ✓ Limit ✗ ✓ ✓
mation (Tiling)
Code Transfor- ✗ ✗ Limit Limit ✓ ✓ ✗ ✓ ✓
mation (Loop
Permutation)
Code transforma- ✗ ✗ ✓ ✗ ✗ ✗ ✗ ✓ ✓
tion + pragma in-
sertion (unified)
Task Concur- ✗ ✗ ✓ Limit. ✗ ✓ ✗ ✗ ✓
rency
Dataflow ✗ ✗ ✓ ✗ ✓ ✓ ✗ ✗ ✓
Computation- ✗ ✗ ✓ Limit. ✗ ✗ ✗ ✗ ✓
Communication
Overlap
Data Packing ✓ ✓ ✓ ✗ ✓ ✗ ✓ ✓ ✓
Padding (Com- ✗ ✗ ✓ ✗ ✗ ✗ ✗ ✗ ✓
munication)
Padding (Compu- ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✓
tation)
Hardware Aware ✗ ✗ ✗ ✗ ✗ ✗ ✗ Limit. ✓
Hardware- Limit. Limit. ✗ ✗ ✗ ✗ Limit. Limit. ✓
feasible
Management of ✓ ✓ ✓ ✗ ✓ ✗ ✓ ✓ ✓
Off-Chip and On-
Chip Memory
Transfers
Objective Comm + Comm + Comm Comp - Comp Comm + Comm + Comm +
Comp Comp Comp Comp Comp
Enumeration (AI, ✓ ✓ ✗ ✓ Manual ✗ ✗ ✗ ✗
heuristics, . . . )
Table 1. Comparison of HLS-Based FPGA Optimization Frameworks. This table summarizes key features supported by various frame-
works, including pragma insertion, code transformations, task concurrency, dataflow modeling, and hardware-awareness, catego-
rized by their underlying optimization strategies.
6 Pouget et al.

quality and model calibration. Conversely, NLP-DSE explores the entire design space efficiently by formulating the
optimization as a Non-Linear Programming problem. This method allows for rapid exploration and selection of theo-
retical optimal configurations. However, it relies on a theoretical cost model, which may introduce inaccuracies if the
compiler behaves unpredictably or if certain optimizations are not accurately captured by the model. Consequently,
while NLP-DSE provides a fast and scalable solution, its reliability depends on the fidelity of the cost model to actual
HLS compilation behavior.
While pragma insertion is a powerful optimization technique, its effectiveness is inherently dependent on the in-
teraction between memory hierarchy, computational resources, and FPGA-specific constraints. Moreover, its impact is
tightly coupled with the program’s execution schedule, meaning that without appropriate code transformations, the
benefits of pragma insertion remain limited. Effective optimization requires a synergy between pragma directives and
structural modifications to the code to fully exploit FPGA parallelism and resource utilization.

2.1.2 Code Transformation. Code transformations are fundamental for optimizing execution on FPGAs. While pragma
insertion plays a crucial role in enhancing performance, it must be complemented by effective code transformations to
fully exploit FPGA resources. Techniques such as loop reordering (permutation), task fusion, and data tiling enhance
data locality and increase parallelism, thereby improving both computational efficiency and memory access patterns.
Various code transformation strategies have been developed specifically for FPGAs [17, 40, 42–44, 55, 82, 83]. While
transformations originally designed for CPUs and GPUs achieve substantial performance gains by optimizing for their
respective architectures, they do not inherently align with FPGA requirements, which prioritize fine-grained paral-
lelism and efficient resource utilization. Several studies have utilized Pluto [13], a leading compiler framework origi-
nally designed for CPU optimizations, to transform FPGA kernels [82, 83]. While Pluto excels at tiling and minimizing
dependencies to enhance memory reuse, its direct application to FPGA optimization is constrained due to the funda-
mental differences in optimization strategies required for CPUs and FPGAs. Unlike CPUs, where memory hierarchy and
cache locality are primary concerns, FPGA optimization focuses on maximizing parallelism, minimizing resource con-
tention, and efficiently utilizing on-chip memory, making Pluto’s conventional transformation techniques less effective
in this context. Conversely, studies such as [17, 40, 42–44, 55] focus on code transformations tailored to specific FPGA
performance goals. The work in [55] aims to reduce communication overhead between off-chip and on-chip memory,
achieving superior Quality of Results (QoR) for memory-bound kernels. Meanwhile, research efforts in [17, 40, 42–
44] concentrate on optimizing pipelining strategies to maximize instruction-level parallelism and resource utilization.
Sisyphus [58] introduces a unified approach by integrating code transformation and pragma insertion into a single
optimization problem. By formulating this as a Non-Linear Programming (NLP) problem, Sisyphus efficiently explores
the design space to identify theoretical optimal configurations, streamlining FPGA acceleration while maintaining a
balance between computation and memory access efficiency.

2.1.3 Task Concurrency. HLS tools like Vitis HLS support the dataflow pragma, which structures computations into
actors that communicate through FIFO queues. This approach allows overlapping execution of multiple tasks, signifi-
cantly reducing overall latency . By enforcing a producer-consumer model, dataflow scheduling enables each task to
process data as soon as it becomes available, rather than waiting for an entire stage to complete, which is particularly
beneficial.
For computational kernels such as 3mm (Listing 3), the dataflow paradigm allows the first two matrix multiplications
to execute in parallel while the third begins as soon as its required inputs are produced. This overlapping of execution
helps maximize throughput and minimize idle time for computing units. Additionally, dataflow optimizations facilitate
Holistic Optimization Framework for FPGA Accelerators 7

task-level parallelism, allowing independent tasks to run concurrently across multiple compute resources, such as DSP
blocks and BRAM, ensuring efficient utilization of available FPGA resources.
However, despite its advantages, pure dataflow parallelism presents several challenges. One major limitation is intra-
task parallelism, which is constrained by the reliance on FIFO-based communication. Since each FIFO can only transfer
up to 512 bits per cycle (as this is the maximum off-chip memory bitwidth supported), this inherently restricts the
amount of data that can be processed concurrently within a task. To further enhance intra-task parallelism, alternative
approaches must be explored.
Stream-HLS [8] attempts to address this limitation by increasing the number of FIFOs connecting two tasks, as-
suming that all data resides on-chip. While this approach simplifies certain aspects of the design space, it is neither
scalable nor generalizable for transferring data from off-chip to on-chip memory. By using 𝑛 FIFOs to transfer 𝑛 data
elements in parallel between two tasks, the method significantly increases resource consumption without proportion-
ally improving efficiency. The additional FIFOs complicate the design, potentially leading to routing congestion and
excessive hardware overhead.
Moreover, modern FPGAs feature up to 32 off-chip memory banks, making the multi-FIFO approach impractical
for handling off-chip data transfers. A more effective and scalable strategy must be developed to optimize intra-task
parallelism while ensuring efficient communication between off-chip and on-chip memory, without introducing un-
necessary complexity or resource constraints.

2.1.4 Shared Buffering. Shared buffering is a critical technique in FPGA memory optimization, enabling efficient data
access and reuse across multiple computational units. It can be employed at a global level, as seen in frameworks like
AutoDSE [65], Sisyphus [58], and ScaleHLS [78], or within individual dataflow tasks to enhance execution efficiency.
This approach involves preloading data buffers into on-chip memory, allowing multiple computations to access
shared data without redundant transfers. By reducing memory access latency and improving bandwidth utilization,
shared buffering facilitates high parallelism and optimizes overall performance. It is particularly beneficial in applica-
tions which are computation bound.
However, shared buffering presents challenges in maintaining concurrency. While it enables efficient data reuse, it
can introduce synchronization overhead, especially when multiple tasks attempt to access the same memory region
simultaneously. Managing concurrent access requires arbitration mechanisms, which can lead to increased latency and
potential bottlenecks. Additionally, routing congestion can occur due to high interconnect demands, limiting scalability
in complex FPGA designs.
One limitation of shared buffering is its impact on initiation interval (II) in pipelined architectures. Unlike dataflow-
based designs that rely on FIFO queues for seamless data streaming, shared buffering requires explicit read and write
coordination, which may introduce stalls if not carefully managed. Moreover, FPGA resource constraints, such as
limited BRAM and URAM availability, impose restrictions on buffer size and allocation strategies.
To address these challenges, advanced techniques such as double-buffering, memory partitioning, and adaptive
scheduling have been explored. Double-buffering enables overlapping computation with data transfer, reducing idle
cycles. Memory partitioning distributes data across multiple banks to alleviate contention, while adaptive scheduling
dynamically assigns buffer access based on task priority and workload demands.
By effectively integrating shared buffering with intelligent memory management strategies, FPGA designs can
achieve a balance between computational parallelism and efficient memory access. Future advancements should focus
8 Pouget et al.

on automated buffer allocation techniques and dynamic access pattern optimization to further enhance performance
in high-level synthesis (HLS) workflows.

2.1.5 Computation-Communication Overlap. Overlapping computation and communication is crucial for high-performance
FPGA designs. Techniques such as double buffering (ping-pong buffering) and advanced data tiling help mask com-
munication latency while keeping computational units busy. Managing data transfers efficiently between on-chip and
off-chip memory ensures that processing units remain active without waiting for data.

2.1.6 Data Packing and Padding. Modern FPGA architectures support high-bandwidth data transfers (up to 512-bit
wide on AMD/Xilinx FPGAs). Data packing and padding optimize memory alignment, reducing the number of required
memory cycles. For instance, transferring 216 floating-point values using a 256-bit width (8 floats per transfer) requires
27 cycles, making efficient packing crucial for minimizing overhead.
To fully exploit data packing, padding must be considered to enable even faster data transfers. Additionally, padding
is valuable for achieving finer control over parallelism and resource utilization by expanding the available design space
for loop unrolling, thereby enhancing computational throughput and efficiency.

Padding for Communication. Padding must be considered to increase the flexibility of data packing. The original size
of the data may impose restrictions on packing efficiency, but by introducing padding, we create a larger space that
may allow for a more efficient transfer. However, padding is not a free optimization, as increasing it also increases the
amount of data that needs to be transferred.
For example, in the code presented in Listings 1 and 2, where 𝐽 = 190, transferring all elements along the second
dimension (iterated by loop 𝑗) of array 𝐵 onto the chip is constrained by the available memory bandwidth. Without
padding, the maximum transfer rate is 64 bits per cycle, as 190 × 32 is divisible by 64 but not by 128. However, by
introducing padding with 𝑃 = 2 and adjusting 𝐽 to 192 (190 + 2), the data alignment enables a significantly higher
transfer rate of 512 bits per cycle, as 192 × 32 is now perfectly divisible by 512. This optimization maximizes memory
bandwidth utilization, reducing transfer latency and improving overall data throughput.

Padding for Computation. Padding can also be used for computation, if we take a similar method than Sisyphus [58]
which tiled and unroll the intra-tile loops which correspond to the transformation from Listing 1 to Listing 2. We will
have an unroll factor which correspond to 𝐼 1 × 𝐽 1 × 𝐾1 but we want to have 𝐼 1 divide 𝐼 , 𝐽 1 divide 𝐽 and 𝐾1 divide K
because we do not want to use extra ressource to only compute a partial tile which would correspond to the execution
of the last tile which is not complete. For example if we have a trip count of 190 and we use an unroll factor of 8 then
we will execute 184 × 8 a full tile and then 6 iterations for the partial tile.
But we restrict the unroll factor to be divisible of the trip count we restrict considerably the space of possibilities. So
the solution is to pad which allow to considerably increase the space of possibilities. Hence with a trip count of 190 the
possible unroll factor are include in 𝑈 𝐹 ∈ {1, 2, 5, 10, 19, 38, 95, 190} but with padding of 2 (a trip count of 192) the space
become 𝑈 𝐹 ∈ {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 192}. And of course all pading can be considered. Padding enables
finer control over unrolling and resource utilization, allowing for more flexible and efficient hardware implementation
while optimizing computational parallelism.
 Holistic Optimization Framework for FPGA Accelerators 9

1 for ( i = 0; i < I ; i ++)

2 for ( j = 0; j < J; j ++)
3 for ( k = 0; k < K ; k ++)
4 C [ i ][ j ] += A [i ][ k ] * B [ k ][ j ];

Listing 1. Baseline Implementation of Matrix Multiplication in C. This code depicts a naive triple-nested loop structure used for matrix-
matrix multiplication, serving as the unoptimized reference for further transformations.

1 for ( i0 = 0; i0 < I0 ; i0 ++)

2 for ( j0 = 0; j0 < J0 ; j0 ++)
3 for ( k0 = 0; k0 < K0 ; k0 ++)
4 for ( i1 = 0; i1 < I1 ; i1 ++)
5 # pragma HLS unroll
6 for ( j1 = 0; j1 < J1 ; j1 ++)
7 # pragma HLS unroll
8 for ( k1 = 0; k1 < K1 ; k1 ++)
9 # pragma HLS unroll
10 C [ i0 * I1 + i1 ][ j0 * J1 + j1 ] += A[ i0 * I1 + i1 ][ k0 * K1 + k1 ] * B [ k0 * K1 + k1 ][ j0 * J1 + j1 ];

Listing 2. Matrix Multiplication with Loop Tiling and Fully Unrolled Intra-Tile Computation. This implementation showcases a
performance-optimized matrix multiplication using loop tiling to enhance data locality and fully unrolled intra-tile loops to expose
fine-grained parallelism.

2.2 Performance and Hardware Considerations

2.2.1 Performance Evaluation. Performance evaluation in HLS is a multi-stage process that assesses different aspects
of a design’s efficiency and feasibility. It is typically conducted at three levels: estimation (e.g., Vitis HLS reports), RTL
simulation, and FPGA-based evaluation. Each of these stages provides critical insights, but they vary in accuracy, speed,
and resource requirements.
(1) Estimation (HLS Reports): The first level of evaluation relies on estimation tools provided by HLS compilers
such as Vitis HLS. These reports generate quick approximations of key performance metrics, including latency,
resource utilization (DSPs, LUTs, BRAMs), and throughput. While these estimations are useful for early-stage
design exploration, they do not account for low-level placement and routing effects, which can significantly
impact real-world performance. The optimistic assumptions of HLS reports often fail to capture routing con-
gestion, memory access delays, and other architectural bottlenecks.
(2) RTL Simulation: To achieve more accurate performance insights, RTL simulation is performed after HLS compi-
lation. This stage involves generating synthesizable RTL code, which is then simulated using hardware descrip-
tion language (HDL) tools. RTL simulation provides cycle-accurate performance metrics, allowing designers
to analyze pipeline behavior, data dependencies, and execution timing. However, while RTL simulation models
hardware more precisely than HLS reports, it does not incorporate real-world FPGA constraints such as clock
tree synthesis, interconnect delays, and power distribution, which can affect the final implementation.
(3) FPGA-Based Evaluation: The most accurate method of performance evaluation involves deploying the design
onto an actual FPGA. This process includes place-and-route, bitstream generation, and execution on hardware.
FPGA-based evaluation provides real execution metrics such as operating frequency, power consumption, and
10 Pouget et al.

effective memory bandwidth. It also reveals practical challenges, including timing closure issues, placement
inefficiencies, and resource contention that cannot be detected in earlier stages. This level of evaluation is
essential for validating Quality of Results (QoR) and ensuring the design meets real-world constraints.

The transition from RTL simulation to FPGA implementation often introduces additional challenges, such as in-
creased routing complexity, unexpected timing violations, and suboptimal resource utilization. These discrepancies
arise due to the abstraction gap between HLS-generated code and final FPGA hardware constraints. To mitigate these
issues, it is essential to develop robust tools that enable rapid design regeneration by modifying specific configurations
within a well-defined portion of the design space. Such tools would enable engineers to efficiently iterate on design
parameters without requiring a complete code regeneration, which can be time-consuming and may result in a signif-
icantly different design that still fails to generate a valid bitstream. Having the ability to selectively modify only the
congested parts of the design while preserving the rest of the configuration would be highly valuable, ensuring faster
convergence toward an optimized and feasible FPGA implementation.

2.2.2 Hardware Awareness and Resource Constraints. Many existing studies conclude their evaluations at the Vitis
HLS report or RTL simulation stage, overlooking the critical impact of placement and routing constraints. However,
as the design progresses toward bitstream generation, the available design space becomes increasingly constrained.
Addressing hardware limitations early in the HLS process is essential to avoid costly design iterations and ensure
convergence toward a feasible and deployable FPGA implementation.
Additionally, Super Logic Region (SLR)-aware optimizations are crucial for multi-SLR FPGA architectures. A Super
Logic Region (SLR) is a physically distinct section of an FPGA die in Stacked Silicon Interconnect (SSI) technology.
Each SLR contains a subset of the device’s computational resources, including DSP, LUT and FF, similar to those in
monolithic FPGA devices.
Effectively mapping tasks across SLRs is critical for balancing resource utilization and minimizing routing conges-
tion, as inter-SLR communication introduces additional latency and can become a performance bottleneck. By inte-
grating SLR-aware task partitioning, optimized scheduling, and efficient data movement strategies, FPGA designs can
achieve higher scalability, improved parallelism, and enhanced synthesis feasibility. Ensuring that computation and
memory access patterns align with the physical structure of multi-SLR FPGAs is essential for achieving high QoR while
maintaining timing closure and efficient resource allocation.
Some recent frameworks, such as RapidStream-TAPA [25, 26] and PASTA [33], aim to improve the design scalability
and performance of HLS programs on modern multi-die FPGAs through hardware-aware co-optimization of HLS and
physical design. While RapidStream-TAPA focuses on latency-insensitive, FIFO-based communication and exploits
coarse-grained floorplanning and pipelining for timing closure and parallel compilation, PASTA extends this model to
include buffer-based inter-task communication using a generalized channel abstraction. Despite their advances, both
frameworks still require a manually optimized task-parallel input code, which demands substantial expertise in HLS
and hardware design, limiting their accessibility for non-expert users.

2.3 Challenges
While existing HLS optimizations provide substantial performance improvements, several challenges remain. One of
the primary limitations is that many prior works restrict their optimization space to specific techniques or separate
Holistic Optimization Framework for FPGA Accelerators 11

their optimization processes into multiple independent steps. This fragmented approach can lead to incoherent de-
sign decisions, where optimizations applied at one stage may not align with or may even counteract those applied at
subsequent stages. Refer to Table 1 for a detailed comparison of these approaches.
A common oversimplification in many frameworks is the assumption that all data resides on-chip. While this simpli-
fies memory access patterns in design space exploration, it often results in low Quality of Results (QoR) when deployed
on real hardware. This assumption prevents frameworks from incorporating crucial tiling strategies, which are essen-
tial for optimizing data locality, reducing memory access overhead, and ensuring efficient off-chip communication.
When off-chip memory management is treated as a separate optimization step, decisions made in earlier phases may
restrict the effectiveness of later memory optimizations, leading to suboptimal performance and resource utilization.
The limitations of current HLS optimization frameworks that rely on shared buffering are exemplified through the
3mm kernel. It consists of two independent matrix multiplications, whose outputs serve as inputs for a final matrix
multiplication.
As illustrated in Listing 3, each matrix multiplication consists of deeply nested loops that are well-suited to paral-
lelization techniques such as loop unrolling, pipelining, and computation-communication overlap. However, conven-
tional shared buffering strategies often fall short in effectively leveraging concurrency, primarily due to their limited
exploitation of dataflow principles and insufficient overlap between computation and communication.
Another major challenge is balancing parallelism and routing complexity. Excessive parallelization can lead to rout-
ing congestion, increased place-and-route time, and ultimately, failure to generate a valid bitstream. Current method-
ologies lack adaptive mechanisms to dynamically adjust parallelism levels based on available routing resources and
FPGA architecture constraints. Without such mechanisms, achieving high-performance designs often requires manual
intervention and iterative fine-tuning.
While pragma-based optimizations such as unroll and pipeline significantly improve performance, their effectiveness
is inherently tied to the underlying code structure. Without proper transformations to expose parallelism and optimize
memory access patterns, pragma insertion alone cannot fully unlock the potential of FPGA acceleration.
Addressing these challenges requires a holistic approach that integrates memory-aware optimizations, automated
design space exploration, and adaptive scheduling techniques. Future research should focus on frameworks that jointly
optimize data placement, computational parallelism, and resource utilization while considering real hardware con-
straints. By developing more cohesive and intelligent HLS optimization strategies, FPGA-based acceleration can achieve
greater efficiency, scalability, and deployment feasibility.
Model-free approaches, such as AutoDSE [65] and AI-based frameworks like HARP [64, 71, 72], rely on either HLS
compilers or AI models to predict performance and resource utilization. However, these methods are currently limited
to pragma insertion and space enumeration. Even though AI-based models provide fast estimations (on the order
of milliseconds), exhaustively exploring large design spaces remains infeasible. Our previous work, NLP-DSE [57],
addresses this limitation by leveraging NLP techniques to efficiently explore pragma configurations. However, like the
other approaches, it remains restricted to pragma insertion.
PolyOptHLS [54] focuses on optimizing designs by minimizing memory transfers. While reducing communication
latency can significantly improve performance, it does not always lead to optimal results. In many cases, the primary
bottleneck may shift from communication to computation, limiting overall efficiency and potentially degrading the
quality of results (QoR). This approach, therefore, lacks a balanced optimization strategy that considers both compu-
tation and communication trade-offs.
 12 Pouget et al.

ScaleHLS [78] and POM [80] extend optimization beyond pragma insertion by incorporating code transformations.
However, their exploration space is constrained by the assumption that data is already on-chip. Additionally, their trans-
formations are based on heuristics, such as permuting the reduction loop to the outermost level. While they employ a
cost model to minimize computation latency, they still rely on exhaustive enumeration of possible configurations.
Allo [14] aims to reduce development time and enhance design quality. However, it still requires significant manual
intervention from an expert, limiting its usability for non-specialists.
Our previous work, Sisyphus [58], enables both code transformations and pragma insertion but is restricted to
optimizing a single task. It lacks support for optimizations that dataflow techniques can provide, which would be
necessary for broader efficiency improvements.
Stream-HLS [8] effectively leverages dataflow pragmas by selecting a good loop ordering strategy to maximize
streaming efficiency. However, it imposes constraints on the design space by assuming that data is on-chip. Moreover,
its approach to increasing parallelism relies on multiple FIFOs, which is not generalizable when off-chip memory access
is required.
A significant limitation of all these frameworks is that none of them account for hardware constraints in their explo-
ration space. While this simplifies the exploration process, it reduces real-world applicability. Additionally, frameworks
such as Merlin-based tools (AutoDSE, HARP, NLP-DSE) and Sisyphus can generate all necessary components, includ-
ing off-chip memory, for bitstream generation. However, they are constrained to a single Super Logic Region (SLR),
leading to under-utilization of the FPGA board. Although generating a design that spans multiple SLRs is theoreti-
cally possible, it significantly increases the risk of bitstream generation failures. Even if the bitstream is successfully
generated, timing violations often degrade performance.

1 for ( i = 0; i < 180; i ++) // MM 1

2 for ( j = 0; j < 190; j ++) {
3 E [ i ][ j ] = 0.0; // S0
4 for ( k = 0; k < 200; ++ k )
5 E [ i ][ j ] += A [i ][ k ] * B [ k ][ j ];} // S1
6 for ( i = 0; i < 190; i ++) // MM 2
7 for ( j = 0; j < 210; j ++) {
8 F [ i ][ j ] = 0.0; // S2
9 for ( k = 0; k < 220; ++ k )
10 F [ i ][ j ] += C [i ][ k ] * D [ k ][ j ];} // S3
11 for ( i = 0; i < 180; i ++) // MM 3
12 for ( j = 0; j < 210; j ++) {
13 G [ i ][ j ] = 0.0; // S4
14 for ( k = 0; k < 190; ++ k )
15 G [ i ][ j ] += E [i ][ k ] * F [ k ][ j ];} // S5
Listing 3. Reference Implementation of the 3mm Kernel from PolyBench. This listing shows the baseline version of the 3mm benchmark,
comprising three matrix multiplication operations. The first two multiplications are independent and produce intermediate results
that serve as inputs to the final matrix multiplication.

2.4 Overview of Prometheus

We introduce Prometheus, a unified optimization framework designed to efficiently navigate complex design spaces
using a Non-Linear Programming (NLP) cost model. Prometheus streamlines FPGA design development by provid-
ing an intuitive, engineer-friendly interface with tunable parameters, including tile size, array partitioning, and loop
unrolling factors.
Holistic Optimization Framework for FPGA Accelerators 13

The framework integrates all the optimization techniques discussed in previous sections, ensuring a comprehen-
sive and cohesive approach to performance enhancement. Additionally, Prometheus is SLR-aware, enabling intelligent
task distribution across Super Logic Regions (SLRs). This capability not only simplifies bitstream generation but also
optimizes the trade-off between computational performance and resource utilization.

Prometheus
Extract Task-flow Graph
Intermediate
with PoCC Generate 1 2
C++ Code Representation
(dependencies, trip counts)
3 4

Formulate a Non-Linear
Problem
encoding the full
optimization design space
Solve NLP
Bitstream
Files for HLS Compiler Generate All Parameters of the Space
with HLS
HLS-C++, OpenCL, Config e.g. data-tile of array 𝐴 is 32 × 64
Compiler

Fig. 1. Overview of the Prometheus Framework Workflow. This diagram illustrates the end-to-end pipeline of the Prometheus opti-
mization framework, starting from C++ source code and proceeding through intermediate representation extraction, task-flow graph
generation, Non-Linear Programming (NLP)-based design space exploration, and final compilation into FPGA bitstreams using HLS
compilers.

Figure 1 illustrates the workflow of Prometheus. The process begins with an input C++ code, from which we extract
an intermediate representation containing dependencies, trip counts, schedules, and other relevant information. This
extraction is performed using PoCC [51], which provides all necessary details for analysis. Next, we construct the
task-flow graph based on this extracted information and formulate the corresponding Non-Linear Programming (NLP)
problem. Solving this NLP problem determines the theoretical optimal parameters for the design space. Once the NLP
solver provides these parameters, we have all the required information to proceed. At this stage, we automatically
generate the HLS-C++ code along with all the necessary files to produce the FPGA bitstream, ensuring an efficient and
fully automated compilation process.
To support efficient exploration of the design space, Prometheus defines a set of tunable parameters and architectural
constraints that capture the key aspects of FPGA acceleration. Table 2 provides a detailed overview of these parame-
ters, including memory-related configurations (e.g., bitwidth, tiling, and reuse levels), parallelism controls (e.g., loop
unrolling and array partitioning), and structural transformations (e.g., loop permutations and SLR assignments). In ad-
dition, the table outlines hardware constraints such as DSP budgets, on-chip memory limits, and maximum legal array
partitioning. These variables and constraints jointly define the feasible design space that the NLP-based optimization
engine systematically explores to generate high-performance, hardware-aware FPGA implementations.
The pseudo-code in Listing 4 demonstrates how Prometheus processes the 3mm kernel (Listing 3). Load and store
operations manage data transfers to and from off-chip memory, while send and receive operations handle inter-task
communication using FIFO.
14 Pouget et al.

Group Parameter Description

Design Variables
Bit Width (𝐵𝑊𝑎 ) Width of memory transfer in bits;
Data-tile Size (modeled via Size of the data tile of array 𝑎 transferred either from off-chip to
Memory Transfer Level 𝑡𝑎,𝑙 in Section 4) on-chip memory or between tasks. The transfer level determines
this size.
Data-tile Reuse Size (modeled Size of the data tile of array 𝑎 reused within a task. The reuse
via Reuse Level 𝑑𝑎,𝑙 in Sec- level dictates this tile size.
tion 4)
Buffering (𝑁𝑎 ) Number of buffers (2 for double buffering, 3 if read & write), en-
abling overlap of load/compute/store.
Communication Padding Additional data added to enable wider burst transfers and better
bandwidth utilization.
Unroll Factors (𝑇𝐶 𝑙intra ) Unroll factor for each task, determined through tiling, where
Parallelism the intra-tile loop is fully unrolled to expose fine-grained par-
allelism.
Array Partitioning (𝐴𝑃𝑎,𝑑 ) Number of partitions for array 𝑎 along dimension 𝑑 to support
parallel accesses.
Compute Padding Padding applied to loop trip counts to increase legal unroll fac-
tors.
Loop Permutations Legal reordering of loops to optimize data locality and paral-
Code Structure lelism; synchronized across fused statements.
Tiling Splitting loops into inter- and intra-tile levels for optimization
and pipelining.
SLR Assignment (𝑠𝑙𝑟 𝑡 ) Mapping of each task 𝑡 to a Super Logic Region (SLR) to enable
spatial task distribution.
Design Constraints
Max Array Partitioning Total partitions across all arrays must not exceed architectural
Resource Limits limits.
DSP Budget Maximum DSP slices per SLR; used to limit total DSP usage by
pipelined/unrolled tasks.
On-Chip Memory Total memory usage by buffered tiles (considering reuse and
buffering) must be within BRAM capacity.
Table 2. Design Variables and Architectural Constraints in the Prometheus Optimization Space. This table outlines the key configurable
parameters used in Prometheus—including loop tiling, unrolling, array partitioning, and buffer management—along with hardware
constraints such as resource limits and memory capacity. The cost model also accounts for concurrent task execution enabled by
the dataflow pragma, as well as computation-communication overlap achieved through automatic double or triple buffering. These
elements jointly define the valid and efficient design space explored by Prometheus.

Each taski in the pseudo-code corresponds to the fully unrolled computation of an intra-tile for statement Si in
Listing 3. An example of such a task is illustrated in Listing 5.
 Holistic Optimization Framework for FPGA Accelerators 15

Arrays 𝐸, 𝐹 , and 𝐺 are initialized to zero within their respective tasks (e.g., S0, S2, and S4) and are not preloaded,
reducing unnecessary memory overhead.
Prometheus enhances computation efficiency by fusing statements that produce the same outputs (e.g., in Listing
3), and it automatically formulates an NLP problem to determine the theoretically optimal parameters, such as loop
schedules, array bit widths (e.g., 512 bits), tile sizes, reuse buffer sizes, transfer locations, and padding. The framework
dynamically adjusts bit widths for arrays like 𝐹 , 𝐷, and 𝐺 to achieve a better balance between parallelism and resource
usage.

1 /* ************** Fused Task 0 ************ ** * */

2 float B [204][192]; load_B ( B) ;
3 for ( i0 = 0; i0 < 18; i0 ++) // inter - tile loop
4 float A [10][204]; load_A (A ) ;
5 for ( j0 = 0; j0 < 6; j0 ++) { // inter - tile loop
6 float E [10][32];
7 task0 ( E) ; // S0 + intra - tile loops
8 for ( k0 = 0; k0 < 51; ++ k0 ) // inter - tile loop
9 # pragma HLS pipeline II =3
10 task1 (E , A , B) ; // S1 + intra - tile loops
11 store_E ( E ) ; sent_E ( E ) ;
12 /* ************** Fused Task 1 ************ ** * */
13 float C [190][222]; load_C ( C) ;
14 for ( j0 = 0; j0 < 7; j0 ++) // inter - tile loop
15 float D [222][32]; load_D (D ) ;
16 for ( i0 = 0; i0 < 10; i0 ++) { // inter - tile loop
17 float F [19][32];
18 task2 ( F) ; // S2 + intra - tile loops
19 for ( k0 = 0; k0 < 74; ++ k0 ) // inter - tile loop
20 # pragma HLS pipeline II =3
21 task3 (F , C , D) ; // S3 + intra - tile loops
22 store_F ( F ) ; sent_F ( F ) ;
23 /* ************** Fused Task 2 ************ ** * */
24 float E [180][192];
25 for ( j0 = 0; j0 < 7; j0 ++) // inter - tile loop
26 float F [192][32];
27 receive_F ( F ) ;
28 for ( i0 = 0; i0 < 18; i0 ++) { // inter - tile loop
29 float G [10][32];
30 receive_E ( E ) ;
31 task4 ( G) ; // S4 + intra - tile loops
32 for ( k0 = 0; k0 < 32; ++ k0 ) // inter - tile loop
33 # pragma HLS pipeline II =3
34 task5 (G , E , F) ; // S5 + intra - tile loops
35 store_G ( G ) ;
Listing 4. Transformed and Fused 3mm Kernel Pseudocode Generated by Prometheus. This code highlights the result of Prometheus
optimizations, including fused task generation, tiled loops, memory buffer management, and pipelined execution with dataflow
pragmas.

Efficient computation-communication overlap is achieved through ping-pong buffering, while concurrent task exe-
cution and FIFO-triggered dependent tasks maximize overall performance. Fused Tasks 0 and 1 execute concurrently,
while Fused Task 2 begins as soon as the data tiles for 𝐹 and 𝐸 become available.
To assess the effectiveness of our proposed framework, we evaluate the performance of the 3mm kernel using sev-
eral state-of-the-art HLS-based FPGA optimization tools. As shown in Table 3, Prometheus significantly outperforms
existing frameworks in terms of throughput, achieving 368.36 GF/s. This represents a substantial improvement over
16 Pouget et al.

Sisyphus (178.97 GF/s) and Stream-HLS (174.00 GF/s), and far exceeds the results of Allo, ScaleHLS, and AutoDSE.
The superior performance of Prometheus stems from its holistic design space exploration strategy, which integrates
loop transformations, memory tiling, concurrent task execution, and SLR-aware scheduling to deliver optimized and
hardware-feasible designs.

Metric Prometheus Sisyphus Stream-HLS Allo ScaleHLS AutoDSE

Throughput (GF/s) 368.36 178.97 174.00 60.40 43.04 1.74
Table 3. Measured Throughput of the 3mm Kernel Using Various FPGA Frameworks. This table presents the runtime throughput (in
GF/s) obtained from RTL simulation of the 3mm kernel across multiple frameworks. Prometheus is shown to outperform other
methods, including Sisyphus, Stream-HLS, and AutoDSE.

3 Code Transformation
In our dataflow model, we adopt a synchronous dataflow where the sizes of the arrays are known during compile time.
This compile-time awareness enables us to construct a precise model that facilitates rigorous optimizations. To leverage
FPGA parallelism, we implement an acyclic dataflow graph, ensuring parent nodes do not receive data from their
children. While this constraint limits graph configurations and may increase resource usage, it reduces overall latency.
To support this structure, we inline [15] each function in the input code to generate the required acyclic graph. Our
primary objective is to minimize latency within resource constraints by overlapping communication and computation
within tasks and executing independent tasks concurrently. To achieve this, we apply various transformations and
optimizations, explored in this section, and navigate the design space using an NLP-based approach, detailed in Section
4.

3.1 Dependency Graph Creation

Our process starts with affine C/C++ code as input, which undergoes maximal distribution to ensure each loop body
contains only one statement, provided no dependencies exist within the loop. ISCC [67] verifies the legality of these
transformations, ensuring dependencies are preserved. After achieving full distribution, we construct a dependency
graph using PoCC [50]. PoCC provides the necessary information about the schedule and dependencies, enabling
us to build the graph. In this graph, the nodes represent tasks, while the edges capture data communication arising
from inter-task dependencies. Tasks with identical outputs are then merged (when legal), creating fused tasks with
output-stationary properties. This ensures that each tile’s output is handled (loaded, computed, and either stored or
transmitted) only once. If a dependency prevents distribution, the framework will still function but with a more limited
optimization space, making it more effective when distribution is possible.
Prometheus’s solution space includes:

3.2 Data-tiling and Padding

In the fused dependency graph, edges represent data communication between tasks as well as between tasks and off-
chip memory, involving the transfer of data tiles with specified sizes. Data tiling divides loop iterations into smaller
𝑙
tiles, splitting array accesses into subsets. Each loop 𝑙 iterating over an array 𝑎 is divided into an outer loop (𝑇𝐶𝑖𝑛𝑡𝑒𝑟 )
𝑙
and an inner loop (𝑇𝐶𝑖𝑛𝑡𝑟𝑎 ), with feasible permutations applied. For each array and dimension iterated by the loop 𝑙,
the tile factor is a common choice that influences all arrays iterated by this loop.
Holistic Optimization Framework for FPGA Accelerators 17

To optimize memory transfers, padding is applied to arrays in two ways. Simple padding increases the bit width
(𝐵𝑊𝑎 ) for efficient transfers while maintaining the original loop trip count. Composite padding adjusts both 𝐵𝑊𝑎 and
the loop trip count (𝑇𝐶 𝑙 ) to support unroll factors that do not evenly divide the original trip count, allowing irregular
tile sizes and expanding the design space. Tile sizes are consistent within a fused task but vary between tasks. In Listing
4, the tile size of array F is 19 × 32 in Fused Task 1 and 192 × 32 in Fused Task 2.

3.3 Fine-grained Parallelism

Data-tile selection involves splitting each loop and permuting them to create two levels of the original loops. Using
ISCC [67], we verify the legality of these permutations, resulting in two loop levels: inter-tile (outer) and intra-tile
(inner). If permutation is not feasible, the inter-tile loop retains its legal position. For tasks belonging to the same fused
task, we merge their inter-tile loops, which are non-reduction. For instance, in Listing 4, the inter-tile loops on lines
3 and 5 iterate over task0 and task1. The intra-tile loops are fully unrolled, ensuring that all data accesses within the
intra-tile remain on-chip. Array partitioning, determined by the unroll factor, ensures data resides in separate BRAM
banks for simultaneous access. Reduction loops across inter-tiles are pipelined with an initiation interval (𝐼 𝐼 = 𝑛 > 1),
where n matches the reduction latency. For instance, in Listing 4, additions take 3 cycles, resulting in 𝐼 𝐼 = 3.

3.4 Loop Order

Due to the full unrolling of the intra-task, there is no need to select the loop order within the intra-tile. We place the
inter-tile reduction loops directly above the task and are pipelined. If multiple reduction loops exist, we rank them by
the size of their trip counts, placing the loop with the highest trip count innermost to ensure an efficient pipeline. This
setup provides the flexibility to choose the order of the inter-tile loops that are not reduction loops. This order will
subsequently be determined by the NLP (cf. Section 4). As shown in Listing 4, the loop order of Fused Tasks 1 and 2 is
permuted compared to the original program in Listing 3.

3.5 Automatic Overlapping of Communication and Computation

To overlap communication and computation, we use on-chip buffers. The buffer size and data transfer location are
determined by various options explored via NLP (cf. Section 4). Since data must stay on-chip for intra-task computation,
transfers occur either below an inter-tile loop or before any loops start. The transfer position determines the data tile
size, covering all data accessed below it. To improve data reuse, buffer size can match or exceed the transferred data
tile. Similar to transfer location, buffer size is determined by its position relative to inter-tile loops or before any loops.
Two boolean variables, 𝑑𝑎,𝑙 and 𝑡𝑎,𝑙 , define and transfer array 𝑎 under loop 𝑙 when set to true. If defined or transferred
before loops, 𝑙 = 0. Double-buffering is used for read-only or write-only arrays, and triple-buffering for arrays that are
both read and written. Following [18], we perform an initial load, then overlap loading the next tile with computing
the current one.

3.6 Coarse-Grained Parallelism: Automatic Execution of Concurrent Tasks

Due to the use of the dataflow pragma, tasks can begin computation as soon as they have sufficient data, allowing for
concurrent execution. This concurrency significantly increases overall performance.
 18 Pouget et al.

1 for ( int j1 = 0; j1 < 32; j1 ++) {

2 # pragma HLS unroll
3 for ( int i1 = 0; i1 < 19; i1 ++) {
4 # pragma HLS unroll
5 for ( int k1 = 0; k1 < 3; k1 ++) {
6 # pragma HLS unroll
7 j = j0 *32+ j1 ; i= i0 *19+ i1 ; k = k0 *3+ k1 ;
8 F [ i1 ][ j1 ] += C [ i ][ k ] * D [ k ][ j1 ];}
Listing 5. Implementation of Task 3 in the 3mm Kernel (from Listing 4). This listing illustrates the structure of Task 3, where the intra-
tile computation is fully unrolled to expose fine-grained parallelism. The unrolling enables concurrent execution of loop iterations.

3.7 Memory Transfer

Communication latency is reduced by transferring more data per cycle using increased bit width with padding. Read-
only arrays are duplicated in off-chip memory for tasks with multiple reads, eliminating feed-through logic. For non-
read-only arrays, data passes between tasks via FIFOs, using the same bit width as for off-chip memory transfer.

4 NLP Formulation
To determine the tile size, loop order, bit width, and memory transfers, we formulate a cost model as a NLP problem
aimed at minimizing overall latency. This approach builds upon the methodology proposed in our previous work [56–
58], which we have further adapted to meet the specific requirements and constraints of our current framework. In our
work, we incorporate dataflow considerations along with all the optimizations detailed in Section 3. We employ PoCC
[50] to extract compile-time information such as schedules, loop trip counts, dependencies, and operation counts per
statement. ISCC [67] then generates all legal permutations for each loop body.
Table 4 delineates the sets, variables, and constants utilized in our NLP formulation.

4.1 Constraints
We now describe the constraints by using the code of Listings 3, 4 and 5.

4.1.1 Data-tiling and Unroll Factor. The intra-tile transformation, as explained in Section 3, can divide either the
original loop trip count or the original trip count with padding, thereby increasing the range of possibilities. Equation
1 ensures that the trip count of the intra-tile is a divisor of one of these two possibilities. The user has the option to
constrain the padding using Equation 2, which simplifies the solution space for the NLP solver. For instance, in Listing
5, for the array 𝐹 , the loop 𝑗 (line 7 in Listing 3) has been split into 𝑗0 (line 14 in Listing 4) and 𝑗1 (intra-tile). The trip
𝑗1 𝑗
count of the intra-tile loop 𝑗1, denoted as 𝑇𝐶 intra = 32, does not evenly divide the original trip count 𝑇𝐶 ori = 210, but
it does divide the trip count of the padded loop 𝑇𝐶 𝑗 = 224.

𝑙
∀𝑙 ∈ L, 𝑇𝐶𝑖𝑛𝑡𝑟𝑎 𝑙 == 0||𝑇𝐶 𝑙
%𝑇𝐶𝑜𝑟𝑖 𝑙
𝑖𝑛𝑡𝑟𝑎%𝑇𝐶 == 0 (1)
𝑙 𝑙
(𝑜𝑝𝑡)∀𝑙 ∈ L, ∃𝑛 ∈ N ≤ 𝑁 ∈ N, s.t. 𝑇𝐶 = 𝑇𝐶𝑜𝑟𝑖 +𝑛 (2)

4.1.2 Bit Width. B denotes the number of elements that can be transferred simultaneously, determined by the bit
width and the data type. Hence, if we have a bit width under 512 bits for float the set is {1, 2, 4, 8, 16}. Equation 3
computes the bit width for each array based on the last dimension of the data-tile transferred on-chip. For example,
Holistic Optimization Framework for FPGA Accelerators 19

Constants Description
𝐼 𝐼𝑙 II of the loop 𝑙
𝐼 𝐿𝑝𝑎𝑟 , Iteration Latency of the operations without (𝑝𝑎𝑟 ) and with (𝑟𝑒𝑑) dependencies of the statement 𝑠
𝐼 𝐿𝑟𝑒𝑑
𝑇𝐶𝑜𝑟𝑖𝑙 Original Trip Count of the loop 𝑙
𝑓𝑎,𝑙 Footprint of the array 𝑎 if transferred to on-chip after the loop 𝑙
𝑁 𝐹𝑇 Number of fused task
𝐷𝑆𝑃𝑠𝑜𝑝 Number of DSP used by the statement 𝑠 for the operation 𝑜𝑝
𝐷𝑆𝑃 Number of DSP available for the FPGA used
𝑚𝑎𝑥𝑝𝑎𝑟𝑡 Maximum array partitioning
𝑆𝐿𝑅 Number of SLR available for the FPGA used
Variables Description
𝑙
𝑇𝐶𝑖𝑛𝑡𝑟𝑎 , TC of the loop 𝑙 for the intra and inter tile
𝑙
𝑇𝐶𝑖𝑛𝑡𝑒𝑟
𝑇𝐶 𝑙 Trip Count of the loop 𝑙 after padding
𝑆𝑎𝑙𝑎𝑠𝑡 Size of the last dimension of the array 𝑎 transferred on-chip
𝐵𝑊𝑎 Bit width of the array 𝑎
𝑡𝑎,𝑙 , 𝑑𝑎,𝑙 Boolean to know if the array 𝑎 is transferred and defined (respectively) on-chip after the loop 𝑙 in
the inter-tile
𝑝𝑖𝑙 Position of the loop 𝑙 under the 𝑖-th permutation
𝑠𝑙𝑟 𝑡 ID of the SLR use by the task 𝑡
Sets Description
L, A, S The set of loops, arrays and statements
L𝑠 The set of loops which iterate the statement 𝑠
L𝑠𝑟𝑒𝑑 The set of reduction loops which iterate the statement 𝑠
L𝑎𝑙𝑎𝑠𝑡 The set of loop which iterate the last dimension of the array 𝑎
L𝑖𝑛𝑡𝑒𝑟 , The set of loops which belong to the inter-tile and intra-tile respectively
L𝑖𝑛𝑡𝑟𝑎
B Set of possible burst size for the data type
C𝑎𝑑 The set of loops which iterates the array 𝑎 at the dimension 𝑑
𝐴𝑃𝑎,𝑑 Array Partition for the array 𝑎 in dimension 𝑑
P𝑠 All permutation of the loops which iterate the statement 𝑠
F𝑖 The set of statements which belong to the fused task 𝑖
T The set of tasks in the dataflow

Table 4. Mathematical Notation for Constants, Variables, and Sets in the NLP-Based Optimization Model. This table defines the for-
mal notation used in Prometheus’ Non-Linear Programming (NLP) model for design space exploration, including loop trip counts,
bitwidths, SLR mappings, resource limits, and legal transformations.

𝑙𝑎𝑠𝑡 = 32, which is divisible by 16.

the array D in Fused task 1 is transferred in line 15 with a size of 222 × 32, so 𝑆𝐷
Therefore, it has a bit width of 16.

∀𝑎 ∈ A, ∀𝑙 ∈ L𝑎𝑙𝑎𝑠𝑡 , max 𝐵𝑊𝑎 = 𝑏 s.t. 𝑆𝑎𝑙𝑎𝑠𝑡 %𝑏 = 0 (3)

𝑏∈B
20 Pouget et al.

4.1.3 Permutation. Equation 4 requires the NLP to choose identical permutations for loops that are shared by state-
ments fused within the same task. For example, in Fused task 1, the loops iterating statement S2 can be permuted as
(𝑖0, 𝑗0) or (𝑗0, 𝑖0), and similarly, loops iterating statement S3 can be permuted as (𝑖0, 𝑗0) or (𝑗0, 𝑖0). However, since the
loops 𝑖0 and 𝑗0 iterate both S2 and S3, they must use the same permutation; either (𝑖0, 𝑗0) for both or (𝑗0, 𝑖0) for both.

∀𝑖 ∈ È0, 𝑁 𝐹𝑇 È, ∀(𝑓 𝑡 0 , 𝑓 𝑡 1 ) ∈ F𝑖2 ,

𝑙 = 𝑝𝑙
∀(𝑖 0, 𝑖 1 ) ∈ P𝑓 𝑡0 × P𝑓 𝑡1 , ∀𝑙 ∈ L, 𝑝𝑖0 (4)
𝑖1

4.1.4 Transfer and Reuse. Equation 5 permits the selection of a single level where each array can be defined (and
reused) and transferred. Equation 6 constrains that the definition of the array must occur lexicographically before or
at the same time as the transfer.
The array 𝐸, defined on line 24 in Listing 4, is defined before any loops, so 𝑑 𝐸,0 = 1 (0 indicating it is defined before
any loops). However, it is transferred under the loop 𝑖0, so 𝑡𝐸,𝑖0 = 1. Equation 6 simply means that the definition of
array E should occur before or at the same level as the transfer. We cannot transfer E under loop 𝑖0 if E is defined under
𝑘0. Similarly, in Listing 4, the array 𝐴 is defined and transferred in line 4, with 𝑑𝐴,𝑖0 = 1 and 𝑡𝐴,𝑖0 = 1.

Õ Õ
∀𝑎 ∈ A, 𝑙 ∈ L𝑖𝑛𝑡𝑒𝑟 , 𝑡𝑎,𝑙 = 1, 𝑙 ∈ L𝑖𝑛𝑡𝑒𝑟 , 𝑑𝑎,𝑙 = 1 (5)
Õ
2
∀𝑎 ∈ A, (𝑙 0, 𝑙 1 ) ∈ L𝑖𝑛𝑡𝑒𝑟 |𝑑𝑎,𝑙 0 , 𝑡𝑎,𝑙 1 = 1, then 𝑙 0 4 𝑙 1 (6)

4.1.5 On-chip Memory. Equation 7 constrains the footprint of the array to be within the available resources, based on
where the array is defined, the number of double buffers used and the footprint of the array transferred at this level.

Õ Õ
𝑑𝑎,𝑙 × 𝑓𝑎,𝑙 × 𝑁𝑎 ≤ 𝑀𝑒𝑚, (7)
𝑎∈ A 𝑙 ∈ L

with 𝑁𝑎 being the number of double buffer for the array 𝑎.

4.1.6 Array Partitioning. Equation 8 limits the maximum partitioning of each array. This partitioning is crucial as it
impacts the maximum unroll factor, necessitating the distribution of data across different BRAM banks under fully
unrolled loops, thereby influencing the utilization of BRAMs. Equation 9 computes the array partitioning needed for
each array based on the trip count of the fully unrolled intra-tile loops.
Array D in Listing 5 is traversed by two unrolled loops: 𝑘1, which iterates 3 times (𝐴𝑃𝐷,0 = 3), and 𝑗1, which iterates
32 times (𝐴𝑃𝐷,1 = 32). Therefore, the total number of partitions needed is 3 × 32 = 96. Consequently, these 96 values
of F are stored in different banks, allowing all of them to be accessed in parallel. However, this value must be less than
or equal to 𝑚𝑎𝑥𝑝𝑎𝑟𝑡 .

Ö
∀𝑎 ∈ A, 𝐴𝑃𝑎,𝑑 ≤ 𝑚𝑎𝑥𝑝𝑎𝑟𝑡 (8)
𝑑 ∈N
𝑙
∀𝑎 ∈ A, ∀𝑑 ∈ N, ∀𝑙 ∈ 𝐶𝑎𝑑 , 𝐴𝑃𝑎,𝑑 = 𝑇𝐶𝑖𝑛𝑡𝑟𝑎 == 0 (9)
Holistic Optimization Framework for FPGA Accelerators 21

4.1.7 DSP Utilization. Equation 10 constrains the number of DSPs used based on the available DSP resources. In
contrast to [56–58], we utilize pessimistic DSP utilization. This approach is necessary because concurrent execution
and resource reuse between tasks are not feasible when two tasks can run simultaneously. Given 𝐷𝑆𝑃+ = 2, 𝐷𝑆𝑃∗ = 3,
and 𝐼 𝐼𝑆3 = 3, the DSP usage for Task 3 is calculated as (2 + 3) × 1824, accounting for the unroll factor. However, since
the loop is pipelined with 𝐼 𝐼 = 3, the HLS compiler optimizes resource usage, effectively reducing the DSP count by
approximately dividing by 𝐼 𝐼 .

Õ Õ Ö
𝑙
(𝐷𝑆𝑃𝑠𝑜𝑝 /𝐼 𝐼𝑠 ) × 𝑇𝐶𝑖𝑛𝑡𝑟𝑎 ≤ 𝐷𝑆𝑃 (10)
𝑜𝑝 ∈ {+,−,∗,/} 𝑠 ∈ S 𝑙 ∈ L∫

4.1.8 SLR Selection. For each task, the NLP determines the SLR on which the task will be implemented (Equation 11).
Additionally, Equations 7 and 10 are applied to each SLR to manage resource allocation per SLR effectively.

∀𝑡 ∈ T , 𝑠𝑙𝑟 𝑡 ∈ È0, 𝑆𝐿𝑅È (11)

4.2 Objective Function

The objective function models the dependency graph of the fused task. Independent tasks execute simultaneously, with
latency set by the longest task. Dependent tasks overlap partially, with the second task starting once it receives enough
data from the first. The latency is the maximum of both tasks’ durations plus the “shift”, the interval before the second
task starts. For our 3mm example, the graph is shown in Figure 2, and the corresponding latency is:




 𝐿𝑎𝑡 (𝑇0, 𝑇1 ) = max(𝐿𝑎𝑡 (𝑇0 ), 𝐿𝑎𝑡 (𝑇1 ) + 𝑠ℎ𝑖 𝑓 𝑡𝑇0 ,𝑇1 )





 𝐿𝑎𝑡 (𝑇2, 𝑇3 ) = max(𝐿𝑎𝑡 (𝑇2 ), 𝐿𝑎𝑡 (𝑇3 ) + 𝑠ℎ𝑖 𝑓 𝑡𝑇2 ,𝑇3 )



𝐿𝑎𝑡 (𝑇0, .., 𝑇4 ) = max(𝐿𝑎𝑡 (𝑇0,𝑇1 ), 𝐿𝑎𝑡 (𝑇2,𝑇3 ), 𝐿𝑎𝑡 (𝑇4 ))






 𝐿𝑎𝑡 = max(𝐿𝑎𝑡 (𝑇0, .., 𝑇4 ), 𝐿𝑎𝑡 (𝑇5 )



 + max(𝑠ℎ𝑖 𝑓 𝑡𝑇1 ,𝑇5 , 𝑠ℎ𝑖 𝑓 𝑡𝑇3 ,𝑇5 , 𝑠ℎ𝑖 𝑓 𝑡𝑇4 ,𝑇5 ))


T0 T1
T5 T4
T2 T3

Fig. 2. Maximally distributed dataflow graph of the 3mm kernel, where each node represents a task and each edge indicates a data
dependency between tasks.

The latency of the intra-task for a statement 𝑠 is determine similarly to [56–58] with Equation 12. And if the intra-
task is iterated by the reduction loops in the inter-tile the latency is represented by Equation 13.

Ö
𝐿𝑎𝑡𝑖𝑛𝑡𝑟𝑎 = 𝐼 𝐿𝑝𝑎𝑟 + 𝐼 𝐿𝑠𝑒𝑞 × log2 ( 𝑙
𝑇𝐶𝑖𝑛𝑡𝑟𝑎 ) (12)
𝑙 ∈ L𝑠𝑟𝑒𝑑
Ö
𝑙
𝐿𝑎𝑡 = 𝐿𝑎𝑡𝑖𝑛𝑡𝑟𝑎 + 𝐼 𝐼 × ( 𝑇𝐶𝑖𝑛𝑡𝑒𝑟 − 1) (13)
𝑙 ∈ L𝑠𝑟𝑒𝑑
22 Pouget et al.

For each level 𝑛 ≥ 0 (with the outermost level being 0) of the inter-tile, we consider the shifting of load, compute,
and store operations to enable overlapping of computation and communication. The overlap factor 𝛼 is set to 1 for
read-only operations and 2 for read and store operations:

𝑓𝑎,𝑙 𝑓𝑎,𝑙
𝐿𝑎𝑡𝑛 = max(𝐿𝑎𝑡𝑛+1, ) + 𝐿𝑎𝑡𝑛+1 + ×𝛼 (14)
𝐵𝑆𝑎 𝐵𝑆𝑎
And then, the final objective function is computed using the dataflow graph, where the latency of the task is estab-
lished by the latency of the outermost level, denoted as 𝐿𝑎𝑡 0 .

5 Code Generation
Prometheus takes as input affine C/C++ code and automatically produces an HLS-C++ file, OpenCL host files, and all
necessary files for code verification, RTL simulation, and bitstream generation. The NLP described in Section 4 gives
the parameters of the space such as loop order, tiling factor, etc. However, in order to be efficient, the code generation
needs some specific rules.

5.1 Communication with Off-Chip Memory

To enable overlapping communication and computation, a load function transfers data on-chip using FIFOs, ensuring
effective overlap management by the compiler. Furthermore, to guarantee that the load operation transfers data with
the correct bit width, we automatically restructure the data in off-chip memory to enable sequential loading. Once data
accumulates in the FIFO, a read function moves it to the shared data-tile buffer, whose size is determined by the NLP.
For outputs, a write function transfers data from the buffer to a FIFO, and a store function writes it back to off-chip
memory.

5.2 Communication between the Fused Task

The communication within the same fused task is not required as they use shared buffers. Similarly, for communication
with off-chip memory, we choose to use FIFOs to facilitate communication between fused tasks, thereby simplifying
the overlap.

5.3 Intra-Task
Each intra-task, corresponding to an intra-tile selected by the NLP, is implemented as a fully unrolled, independent
function without communication with off-chip memory. Data for these tasks resides entirely on-chip.
If the task involves reduction loops, inter-tile reduction loops are integrated into the function and pipelined. While
the pipeline initiation interval (II) is greater than 1 due to reduction dependencies, other operations in the statement
are pipelined efficiently.
Padding is handled at the intra-tile level. Non-reduction loops remain unchanged, allowing computation of padding
values without excessive resource usage. For reduction loops, full tiles are computed first, and the intra-tile loop is
adjusted to handle padding for partial tiles accurately.

5.4 Inter-Tile Loop

For each fused task and each inter-tile loop, we generate independent functions to facilitate efficient double or triple
buffering. Using information from the NLP, we determine which arrays are defined and which are transferred at each
Holistic Optimization Framework for FPGA Accelerators 23

level of granularity. Once we identify the data being transferred, we implement double buffering if only reads or writes
are involved, or triple buffering if both reads and writes are required. This strategy allows us to overlap the operations
of reading, storing, and computing at the innermost level, optimizing both communication and computation overlap.

5.5 Concurrent Execution

Using the dataflow pragma, independent tasks execute concurrently without requiring manual rewrites. Computation
in a receiving task begins as soon as its shared buffer contains sufficient data.

5.6 SLR Management

The NLP determines the SLR ID for each task, specifying where it will be executed. Prometheus generates a separate
C++ file for each SLR, and data transfers between SLRs are managed via ap_axiu streams, ensuring efficient communi-
cation and minimizing transfer overhead.

5.7 Design Regeneration

In cases where bitstream generation fails for a given design, we support automatic regeneration of the design. Several
strategies can be applied, such as tightening resource constraints or reducing the maximum unrolling factor. By reduc-
ing the available resources, the design becomes smaller, which can help alleviate congestion. Thanks to the flexibility
of our NLP-based approach, we can retain parts of the previous solution—such as the SLR assignment—and selectively
restrict resources only for the specific task or group of tasks responsible for the congestion. This is the method we
employ to regenerate designs when bitstream generation fails.

6 Evaluation
6.1 Setup
We evaluated our method using kernels from Polybench/C 4.2.1 [53] with medium-sized datasets and single-precision
floating-point computations. The selected kernels represent both memory-intensive and computation-intensive scenar-
ios. Medium problem sizes were chosen to balance demonstration of efficacy and the feasibility of time-consuming RTL
evaluations. Due to Allo’s lack of automatic code generation, we limited our experiments to the subset of PolyBench
kernels provided in its artifact evaluation package [1], as results for other kernels were not available. NLP problems
were solved using the AMPL description language and the Gurobi solver (version 11.0.0) with the qp:nonconvex=2
option for non-convex quadratic objectives and constraints. Evaluations included RTL simulation and on-board exe-
cution using the Alveo U55C FPGA, with a targeted frequency of 220 MHz. RTL simulation provided accurate latency
estimates, contrasting with the overly optimistic Vitis HLS reports that assume perfect task overlapping with dataflow
pragma. The generated code from the frameworks are compiled using AMD/Xilinx Vitis HLS 2023.2 using the Vitis flow
[3]. This flow assumes that data initially resides off-chip and has a default latency of 64 cycles to bring onto on-chip
memory. All frameworks utilize "unsafe math" optimizations, enabling commutative/associative reduction operations
at the expense of precision.
24 Pouget et al.

6.2 Experimental Evaluation

The objective of this evaluation is to demonstrate the capability of our framework to generate code with high QoR,
whether for memory-bound or computation-bound kernels. To achieve this, we compare our work with Allo, ScaleHLS,
Sisyphus, AutoDSE and Stream-HLS.
For ScaleHLS [78], Allo [14], and Stream-HLS [8], their kernels assume that data is already present in on-chip
memory. To ensure a fair comparison, we modified their code to incorporate off-chip to on-chip data transfers. However,
Allo’s 2mm and 3mm kernels already include this transfer mechanism, requiring no modifications. We left Sisyphus
and AutoDSE unchanged, as they already optimize bit width according to the problem size. We use AutoDSE with the
bottleneck method, setting a DSE timeout of 1,000 minutes and an HLS synthesis timeout of 180 minutes per task. For
Allo-generated designs, we utilize kernels from their artifact repository since Allo does not employ a DSE [1]. Sisyphus
generated designs are generated using parameters consistent with the paper [58]. We observe some differences in
Sisyphus results, as our evaluation is conducted on a different board. The design variations between boards may lead
to differences in performance.
For RTL simulation, we assume that the frameworks can utilize all the resources on the U55C FPGA with a constraint
of partitioning any array of 1,024 due to AMD/Xilinx limitations. For on-board FPGA evaluations, we consider two
scenarios. The first scenario utilizes 60% of one Super Logic Region (SLR), equivalent to 20% of total board resources,
for all frameworks. The second scenario is unique to our framework, leveraging all three SLRs, with 60% utilization per
SLR. Most frameworks are not place-and-route aware, leading to congestion issues that prevent bitstream generation.
Limiting frameworks to one SLR increases the likelihood of meeting timing requirements. AutoDSE, for instance, lacks
dataflow support and applies pragmas within a single function, making multi-SLR bitstream generation impossible
without manual intervention to split the function across SLRs. If congestion persists within an SLR, we adjust the NLP
constraints to address the issue and regenerate the HLS-C++ file in just a few minutes.
It is worth noting that there is a difference in results between RTL simulation and on-board evaluation. This dif-
ference is expected, as RTL simulation involves fewer constraints, allowing for more aggressive unrolling and full
utilization of available resources. In contrast, on-board evaluation is more complex, and excessive unrolling can easily
lead to congestion. Therefore, we compare RTL simulation results with those of other frameworks to demonstrate
our performance improvements. More importantly, we show that our approach generates code that can actually be
implemented on board.

6.3 Comparison
Table 5 presents the RTL simulation results for Prometheus, Sisyphus [58], AutoDSE [65], ScaleHLS [78], and Allo [14].
The last lines show the average and geometric mean performance improvement (PI) of Prometheus across evaluated
kernels.
Results marked with ∗ are from the Vitis HLS report, showing minimum latency as an optimistic estimate. The RTL
simulation for 3mm with Allo was incomplete after two days. The N/A values in the table for Scale-HLS correspond
to kernels that have at least one loop with a non-constant trip count. Stream-HLS does not handle these cases, so we
cannot make a comparison.
Prometheus consistently achieves superior QoR across all evaluated kernels compared to other frameworks. While
Sisyphus [58], designed primarily for computation-bound kernels, demonstrates competitive results for these kernels,
it shows a weakness for 2mm and 3mm. This disparity is due to Sisyphus lacking concurrent execution capabilities
Holistic Optimization Framework for FPGA Accelerators 25

Kernel Ours Sisyphus ScaleHLS Allo AutoDSE Stream-HLS

2mm 308.38 195.09 37.13 46.58 0.41* 150.27
3mm 368.36 178.97 43.04 60.40* 1.74* 174.75
Atax 3.56 2.32 1.58 1.96 1.97* 1.71
Bicg 15.41 2.32 1.70 14.17 0.99* 1.73
Gemm 419.14 227.09 40.53 37.50 110.81* 203.48
Gesummv 10.21 2.28 1.78 8.85 1.98* 1.72
Mvt 14.65 5.54 7.39 8.77 7.80* 13.31
Symm 212.20 200.30 0.06 16.72 14.68* N/A
Syr2k 267.31 149.89 0.08 41.15 12.35* N/A
Syrk 158.25 105.59 0.27 20.57 23.16* N/A
Trmm 193.47 166.72 0.07 5.10 0.02* N/A
PI (Avg) 2.39x 927.20x 8.58x 973.14 3.46x
PI (gmean) 2.03x 48.03x 4.92x 25.82 2.71x

Table 5. Throughput Comparison (in GF/s) of PolyBench Kernels Across Frameworks Using RTL Simulation

for independent matrix multiplications. The performance advantage of Prometheus stems from both concurrent task
execution and efficient overlapping of computation and communication.
Although for bicg, Allo and Prometheus do not use the same code transformation, the results are similar. Allo retains
the original code structure by permuting the reduction loop outermost. The non-reduction loop is fully unrolled, and
the reduction loop is pipelined. Prometheus partially unrolls both loops and pipelines the reduction loop.
On Board Evaluation Table 6 presents the results for the on-board evaluation. The column 𝑇 (𝑚𝑠) indicates the
kernel execution time in milliseconds, GF/s represents the throughput in Giga Floating Operations per second, and the
resource usage is detailed in the thousands for both LUTs (L) and FFs. URAM utilization is excluded as no kernels use
it. Column F (MHz) shows the frequency achieved by each design, with a target frequency of 220 MHz for all designs.
For Bicg and Atax, targeting 60% of resources on one SLR caused congestion, requiring regeneration with a 55%
constraint. The 3mm bitstream from AutoDSE succeeded only with a 15% constraint.
Prometheus achieves a remarkable 77.16x performance improvement over AutoDSE. This gain is accompanied by
an average increase in resource utilization: 2.38x more DSPs, 1.08x more BRAM, 1.36x more LUTs, and 1.42x more FFs,
reflecting the trade-offs made to achieve such high efficiency. When compared to Sisyphus, Prometheus demonstrates
a notable 2.59x performance boost, leveraging an average of 3.88x more DSPs, 1.04x more BRAM, 1.31x more LUTs,
and 1.33x more FFs, illustrating its ability to deliver substantial improvements while effectively utilizing additional
resources.
Table 7 shows the parameters found by the NLP. We use the same name of the iterator as Polybench 4.2.1 [53]
code. 𝑆𝑖 represent the statement in position 𝑖 in the code. The second column gives the statement fused inside the same
tasks, the third column sets the fused task order and loop order found by the NLP for the fused task and the last column
supplies the data-tile size found by the NLP, if the array is present in a different fused task the fused-task (defined in
the second column) is precise.
Permutations are evident in the implementations of 3mm, Atax, and Bicg. For 2mm and 3mm, the NLP opted to
fully transfer array B instead of overlapping computation and load, as the load operation had higher latency than
computation. In 2mm, the NLP retains the original loop order. Array tmp is transferred from the first task to the
26 Pouget et al.

Kernel T (ms) GF/s DSP BRAM L(K) FF(K) F (MHz)

2mm 1.20 30.57 556 510 213 276 220

Sisyphus
3mm 1.52 29.89 984 611 230 300 220

1 SLR
Atax 0.62 1.03 173 450 240 250 220
Bicg 0.63 1.02 173 451 238 265 217
2mm 92.25 0.40 963 353.5 287 292 205

AutoDSE
3mm 110.34 0.41 1117 470 278 306 220

1 SLR
Atax 2.88 0.22 452 630.5 170 212 220
Bicg 1.13 0.56 196 867.5 168 217 214
2mm 0.56 65.13 1941 635.5 371 454 216
3mm 0.87 51.95 1551 635.5 342 423 220
1 SLR
Ours

Atax 0.24 2.62 1081 533.5 234 287 184

Bicg 0.15 4.04 732 311.5 250 302 220
2mm 0.29 125.54 2752 546 428 549 220
3mm 0.34 134.07 4379 600 684 840 207
3 SLR
Ours

Atax 0.20 3.10 1823 634.5 405 539 137

Bicg 0.14 4.34 1226 241 291 380 177
Table 6. On-Board Evaluation of Performance and Resource Utilization Across Frameworks and SLR Configurations

second, with both tasks iterating over the first dimension using loop 𝑖. This enables a 4 × 32 data tile to be sent to the
second task, which starts computation once a 4 × 192 tile of tmp(FT1) is filled.

Fused Statement Loop Order Data Tile Size

2mm FT0: S0, S1, FT1: S2, FT0: i,j,k, FT1: tmp(FT0): 4×32, B: 212×192, A: 4×212, D: 4×32, C:192×32,
S3 i,j,k tmp(FT1): 4 × 192
3mm FT0: S0, S1, FT1: S2, FT0: i,j,k, FT1: E(FT0): 9 × 16, A: 9 × 200,
S3, FT2: S4, S5 j,i,k FT2: j,i,k B: 200 × 192, F(FT1): 10 × 10,
C: 10 × 224, D: 224 × 10, G: 9 × 10, E(FT2): 9 × 192, F(FT2):
192 × 10,
Atax FT0: S1, S2, FT1: S0, FT0: i,j, FT1: j,i tmp(FT0): 56, y: 16, A(FT0): 392 × 416, A(FT1): 392 × 16,
S3 tmp(FT1): 392
Bicg FT0: S1, S2, FT1: S0, FT0: j,i FT1: i,j s: 16, A (FT0): 416 × 16, r: 416, q: 10, A (FT1): 10 × 400, p: 400,
S3

Table 7. Fusion, loop order and data-tile size found by the NLP for the kernel evaluated on Table 6 for 1 SLR

As other frameworks cannot generate bitstreams for 3 SLRs without human intervention, we compare results for 1
and 3 SLRs using our framework. For 2mm and 3mm, performance improves due to increased resource utilization. How-
ever, for atax and bicg, where the bottleneck is memory transfer between off-chip and on-chip rather than parallelism,
the improvement is negligible.

6.4 Scalability
Our NLP solver includes the option to set a timeout, returning the best design found so far without guaranteeing
optimality. This feature enables efficient exploration of the solution space while ensuring adherence to time constraints
when necessary.
Holistic Optimization Framework for FPGA Accelerators 27

When analyzing the time required to solve the Non-Linear Programming (NLP) problem in Sisyphus, we observe
that our framework, Prometheus, achieves similar solution times for most benchmarks. However, there is a notable
exception: the 3mm benchmark, which times out after 4 hours in Sisyphus, while Prometheus successfully finds a
solution.
This efficiency stems from Prometheus’ ability to explore a larger optimization space while still maintaining fast
solution times. The key reason is that all optimization techniques are seamlessly integrated within the design space.
This structured integration ensures that when a decision is made for one optimization parameter, it naturally constrains
the possible choices for others, thereby reducing the search complexity. As a result, even with a broader search space,
Prometheus efficiently converges to a solution in 21.37 seconds.
A detailed comparison of solution times can be found in Table 8, which highlights the impact of our approach in
managing the design space effectively.

Benchmark Sisyphus Prometheus

2mm 22.37 15.98
3mm 14400.08 21.37
Atax 3.18 7.03
Bicg 3.17 5.09
Gemm 2.19 4.31
Gesummv 1.57 8.07
Mvt 1.71 1.26
Symm 7.13 11.46
Syr2k 5.29 6.07
Syrk 2.56 3.94
Trmm 4.34 5.96
Average 1313.96 8.23
Geo Mean 7.95 6.50
Table 8. Time Required (in seconds) for the NLP Solver to Find an Optimal Solution: Sisyphus vs. Prometheus Across Benchmarks
(Timeout Set at 14,400s)

7 Related Work
Dataflow Dataflow principles have been extensively studied in models such as Kahn Process Networks [32], Den-
nis Dataflow [22], synchronous dataflow languages [11, 38], and for FPGA applications [2, 4, 10, 12, 14, 24, 49, 74].
DaCe [10] introduces Stateful DataFlow multiGraphs to separate program definition from optimization, enabling
transformations like tiling and double-buffering, though requiring user intervention. Stream-HLS [8] automatically
generates dataflow; however, it assumes that data are already on-chip, thereby overlooking communication with off-
chip memory. Additionally, it offers very limited opportunities for parallelism. Flower [4] automates FPGA dataflow
development but limits parallelism. Frameworks like [14, 74], built on HeteroCL [36], optimize data placement and
compute scheduling for heterogeneous systems, maximizing data reuse and bandwidth utilization. Systolic arrays
28 Pouget et al.

[9, 20, 31, 37, 69] offer efficient computation for specific patterns but lack generalization. Application-specific frame-
works [5, 16, 21, 23, 27, 34, 47, 61] demonstrate dataflow advantages but do not generalize across domains. RapidStream-
TAPA [25, 26] enhances the performance of dataflow designs and automates SLR placement. However, it requires an
optimized kernel with a dataflow structure as input.
Shared Buffer Shared buffer utilization through HLS has been extensively explored using methods such as NLP-based
pragma insertion [56–58], bottleneck DSE [65], and GNN-based latency and resource estimation [7, 62–64, 66, 71, 73].
However, these approaches lack effective integration of dataflow optimization techniques.
Code Transformation Code transformation has been explored for CPUs [6, 13, 35, 52], GPUs [68], and FPGAs [17, 40,
42–44, 55, 82, 83]. Pluto [13] minimizes communication and improves locality but can limit parallelism. FPGA-specific
adaptations [55] leverage FIFOs for overlapping communication and computation but are restricted in parallelism.
Recent works [82, 83] selectively use Pluto for latency minimization while avoiding non-HLS-friendly code. While
[17, 40, 42–44] focus on optimizing pipelining techniques, they do not address parallelism or the coordination of
computation and communication overlap, which are crucial for our objectives. The [14, 29, 36, 77, 78] compilers perform
code transformations and pragma insertion, their modifications are primarily heuristic and based on loop properties.
The paper [58] described in Section 2 generates design with high QoR, but the absence of dataflow utilization hinders
concurrent task execution. Additionally, their approach avoids padding, limiting the unroll factor to divisors of the
loop’s trip count and constraining tiling space.
Tiling and Padding Tiling is essential for balancing computation and communication. While prior works [41, 45]
use cost models to minimize communication, our approach extends this to reduce overall latency. Techniques like
NLP-based tiling [41] focus on CPUs, while Wedler [59] optimizes DNNs on GPUs by fusing operators, enhancing data
reuse, and employing padding to prevent bank conflicts. Padding is well-studied for reducing cache misses [28, 48] and
improving memory transfers [70], but its use for varying unroll factors on FPGAs remains underexplored.

8 Conclusion
In this work, we introduced Prometheus, a holistic optimization framework that unifies loop transformations, task
concurrency, computation-communication overlap, and hardware-aware scheduling for FPGA accelerators. By formu-
lating the optimization process as a Non-Linear Programming (NLP) problem, Prometheus enables a structured explo-
ration of the vast design space while considering hardware constraints, memory bandwidth, and task parallelism.
Our framework addresses key limitations in existing methodologies, which often optimize only isolated aspects of
FPGA acceleration. Prometheus surpasses these approaches by integrating SLR-aware scheduling, dynamic memory
management, and hybrid execution models that effectively balance dataflow streaming and shared buffering. This
enables more efficient utilization of FPGA resources, leading to significant improvements in latency, throughput, and
scalability.
Through extensive performance evaluations on computation-bound kernels, we demonstrated that Prometheus out-
performs state-of-the-art frameworks.
Furthermore, Prometheus’ automatic design space exploration significantly reduces the manual effort required in
FPGA development. By automatically generating HLS-C++ code, OpenCL host code, and FPGA bitstreams, the frame-
work streamlines the deployment process, making FPGA acceleration more accessible to a broader range of applica-
tions.
In summary, Prometheus provides an innovative and effective approach to FPGA optimization, delivering high-performance
solutions while minimizing the complexity of hardware design.
Holistic Optimization Framework for FPGA Accelerators 29

Acknowledgments
This work was supported by the NSF award #CCF-2211557. It is also supported by CDSC industrial partners and the
AMD/HACC Program.

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Received 20 February 2007; revised 12 March 2009; accepted 5 June 2009