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CSE460 Assignment 3

The document outlines an assignment for a CSE460 course, consisting of multiple questions related to chip design, digital systems, and algorithms. It includes tasks such as calculating width scaling factors for a NOR gate, analyzing power dissipation in a CMOS inverter, and applying the Kernighan-Lin algorithm for graph partitioning. The assignment requires students to perform various calculations and provide graphical representations based on given scenarios.

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81 views3 pages

CSE460 Assignment 3

The document outlines an assignment for a CSE460 course, consisting of multiple questions related to chip design, digital systems, and algorithms. It includes tasks such as calculating width scaling factors for a NOR gate, analyzing power dissipation in a CMOS inverter, and applying the Kernighan-Lin algorithm for graph partitioning. The assignment requires students to perform various calculations and provide graphical representations based on given scenarios.

Uploaded by

zahannusrat10
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 3

CSE460, Fall’24
Q1. Brook is a chip designer who works specifically on the λ = 1.5 μm process. However, he has messed
up the layout design of a 3-input NOR gate (Figure 1(a)) because of which, the NOR gate has an
equivalent rise resistance that is four times its equivalent fall resistance. Also, the NOR gate’s equivalent
rise resistance is twice the rise resistance of a unit inverter for that design process. But at least he made
sure to keep the source-drain terminals shared where possible to reduce capacitance. The gate
capacitance and parasitic (diffusion) capacitance of are 0.5 fF/μm. This NOR gate is loaded with a Unit
inverter and the output node Y has a voltage waveform as shown in Fig. 1(c).

Figure 1(a) Figure 1(b) Figure 1(c)

(a) Find the value of width scaling factors - kp and kn of the NOR gate designed by Brook. Thereafter,
calculate the actual width of the pMOS and nMOS.

(b) Draw the RC equivalent model of the above 3-input NOR gate. Lump the capacitances together
where possible.

(c) Find the capacitance of the Y node (in fF units), when it is loaded with a unit inverter, as shown in Fig.
2(b).

(d) Find the best-case falling edge contamination delay (tcdf) of Y-node in terms of R and C of unit MOS.

(e) Find the switching power of the Y-node, if the system has a supply voltage of 5 V.

Q2. A digital system is driven by a clock frequency of 1 MHz and a supply voltage of 10 V. A small part of
the system can be modeled by a CMOS inverter driving a capacitive load (CL), the figure of which is given
below. When the input node Vin is low, the output node Vout is high, and to make the output node high
once, 10 nJ of energy is supplied by the voltage source, VDD. [A joule (J) is the SI unit of energy.

(a) Assuming that Vin stays low, how much of the energy supplied by the voltage source (VDD) is stored
in the load capacitor CL?
(b) What is the capacitance of the load capacitor CL?

(c) If the activity factor of the output node is 0.2, calculate the average switching

power dissipation of the CMOS inverter.

Q3. In the following figure, you can see the grids for Lee’s Maze Algorithm.

(a) Using the algorithm, find the shortest path from S to T1 and T2 allowing minimum bends.

(b) Show the graph representation of the connected gates ignoring the grids. (Convert gates to nodes).

(c) Compare the initial cut cost with that of after the first iteration of the KL algorithm for partitioning.
Assume initial Cut Sets: A (g1,g2) and B (g3,g4).

Q4. The graph below (nodes a-f) can be optimally partitioned using the Kernighan-Lin

algorithm. The dotted line represents the initial partitioning. Assume all the edges have

the same weight.


(a) What is the initial cut cost?

(b) Perform the first pass of the algorithm. For the “i”th iteration of the first pass, until all the nodes are
swapped and fixed, do the following:

i. Compute the node costs of all unfixed nodes

ii. Find the maximum gain of swapping a pair of nodes (Δgi)

iii. Swap the pair and draw the updated graph

(c) Finish the first pass by computing the maximum positive gain, Gm. Suggest how many swaps should
be actually executed in the first pass.

(d) Should you perform subsequent passes of the algorithm? Why or why not?

Q5. Suppose the technology you are using to design a VLSI system has λ = 80 nm, a clock frequency of 5
MHz, and a supply is 5 V. The chip you are designing has 5 million transistors, of which 1 million remain
active at any given time. The activity factor is defined by the fraction of total components which remain
active. The gate and diffusion capacitances are 12 fF/μm and 5 fF/μm, respectively for all the 5 million
transistors. The gate width is 20λ. You also obtain the following power consumption data:

• Short circuit power = 0.5 W

• Leakage power = 0.01 W

• Subthreshold power = 0.02 W

The acceptable TOTAL power consumption of a chip is 3 W.

(a) Find the activity factor and load capacitance of the system described above.

(b) Calculate the switching power consumption of the chip.

(c) Calculate the dynamic and static power of the chip. Thereafter calculate the TOTAL power
consumption.

(d) Is the TOTAL power consumption within the acceptable range? If not, find the maximum clock
frequency to keep the TOTAL power within the acceptable range?

(e) For a 10-input NAND gate, what should be the ratio of width scaling factors – kp/kn - for the NMOS
and PMOS to keep the rise and fall resistances equal?

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