Low Power Embedded EEPROM Design for MCU in Battery-less Tire

Pressure Monitoring System

Chao-Jun Chi, Li-Ji Wu*, Xiang-Min Zhang, Li-Yang Pan

Tsinghua National Laboratory for Information Science and Technology
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
*Email: [email protected]

Abstract circuit and process data in the pressure monitoring

module. The program which ran by the MCU is stored in
A 16 Kbits EEPROM is designed and taped out in a the EEPROM.
0.35μm 40V BCD Embedded EEPROM automotive EEPROM is widely used for MCU, smartcard and RFID
electronic process. Low power is achieved by optimizing etc [2]. In this design, the critical problem is to design
sense amplifier (SA) and other readout circuit. A low low power consumption, large capacity, high stability
power 64 Kbits 3V only EEPROM is designed and will and reusability circuit to meet the automotive
be taped out soon. It uses an improved on chip electronics’ harsh environment and battery-less use.
high-voltage generator. By using dynamic charge
transfer switches, a high performance 3-V-to-14-V 2. EEPROM Architecture
charge pump is designed. At read action, the power
consumption of the 16 Kbits EEPROM is 0.8mA while The architecture of the 64 Kbits EEPROM is shown in
the 64 Kbits 3V only EEPROM is 1.3mA. A variety of Figure 2. The memory array is composed of bit cells
operating modes are designed to reduce operating time which are the storage devices, and its basic operating
and improve testability. The EEPROM can operate in a unit is one byte. Decoder is used to select the exact unit
broad range of temperature and voltage, it is applicable according to an address. The voltage switch and the data
for automobile. latch are used for programming or erasing operation. The
SA is used for reading the stored information out. The
1. Introduction control logic is providing the controlling signals which
are needed by other parts. The high voltage generator is
Tire pressure monitoring system (TPMS) real-time used to generate the internal high voltages which are
monitors the tire pressure and other tire related used for programming and erasing operations.
parameters required. It can improve driving safety and
decrease fuel consumption. It is widely used in Address Latch Address
automobiles [1].
Data line
Decoder Data
Display screen Central
13.56MHz Transmitter High Voltage
Controlling
MCU module Generator Data Latch
Receiver
BL Switch

Word
433MHz Transmitter WL
Power recovery circuit Line
Switch
Memory Array
Decoder
MCU

EEPROM
Sensors
Sense Amplifier
pressure monitoring module Control Logic
Data
Figure 1. Battery-less TPMS
Figure 2. Architecture of the EEPROM memory
The block diagram of the battery-less TPMS is shown in
figure 1. In battery-less TPMS, battery is replaced by The memory array’s structure is parallel NOR, and it
power recovery circuit. The TPMS is composed of organized into 64*128*8 bits.
power transmitter, the pressure monitoring module and
the central controlling module. MCU is used to control 3. Circuit Design

978-1-4673-2475-5/12/$31.00 ©2012 IEEE

 In order to achieve low power consumption and high
3.1 Operation mode reliability, the current of the reference branch is set to a
The basic Operational unit is one byte. certain value which is half of the bit line’s current value
There is only one reading mode, byte reading. when reading the stored message “1”. Theoretically, the
Parallel programming which can significantly shorten bit line’s current value is zero when reading the stored
the programming time is used in the EEPROM. There message “0”.
are four programming modes, byte programming, page The high voltage generator described below is shut down
programming, block programming and chip when high voltage isn’t needed, and its efficiency is
programming. One page defines as one row while one improved by using an improved structure and optimizing
block defines as one column. Page programming is to the circuit.
program one page or part of one page at once. Block
programming is to program the whole column at once. 3.3 High voltage generator
Chip programming is program the whole chip at once. A A 3-V-to-14-V high voltage generator is designed which
row of data latches are used to reduce programming is used to generate the high voltage needed when
time. programming or erasing. The block diagram of the high
There are four erasing modes too, byte erasing, page voltage generator is shown in figure 4. The high voltage
erasing, block erasing and chip erasing. generator is composed of a charge pump and auxiliary
Several testing modes are designed to test the circuit. circuits. The auxiliary circuits are used to set the voltage
Bit cell has four ports, word line (WL), bit line (BL), of VPP at a certain value. In this design, VPP is set to
control gate (CG), source line (SL). At each action, exact 14V.
value of voltage of each port must be provided. In this
process, the value of each port’s voltage value needed VPP
Charge Pump
when operate is shown in table 1.

Table 1. Operating voltage value of bit cell’s ports Clock

State BL WL CG SL Clock
Controller Voltage
Read 1V VDD 1V 0V Divider
Reference
Program VPPL VPPH 0V Float
Comparator Votage
Erase Float VPPH VPPL 0V
Figure 4. High voltage generator
3.2 Design for Low power consumption
At read action, SA is critical to power consumption [3].
At program or erase action, the high voltage generator
Current mode differential SA is used to read out the
consumes most of the power in the chip. In order to
stored information [4], the SA is shown in figure 3. The
optimize the power consumption, an improved Dickson
SA stops working when Bias is 0V in order to lower the
charge pump in CMOS technology is used [5]. The basic
power consumption. SA is charging the bit line when
idea of this modified charge pump is to use MOS
Bias raise to a certain value and Charge is low. M2, M4
switches directing charge flow during pumping, the
and M6 clamp bit line’s voltage to a certain value. SA
MOS switches controlled by the high voltage which is
began to read the information out when Charge becomes
already established by the charge pump. As an example,
high after pre-charging.
a four stage of this improved charge pump is shown in
figure 5.
VDD

Charge M1 VDD Vout

M2 M3

Out
Bias M4 M5
C1 C2 C3 C4 C5 C6
M6 Reference CLK1
branch CLK2 HV_CLK

M7 M8 Reference
Figure 5. Charge pump
Discharge
voltage
Bitline In this charge pump, Dynamic charge transfer switches
GND
(CTS) is used to improve the voltage pumping gain.
Figure 3. Sense amplifier Voltage pumping gain defined as the voltage difference
between two adjacent nodes [5]. For Dickson charge
pump, the voltage pumping gain is VPPL is 13.32uA.
According to simulation, the 64 Kbits 3V only EEPROM
C I out is still working when the voltage range is 2.7V to 3.3V
GV   V   Vth (1) and temperature range is -40℃ to 125℃.
C  Cs (C  Cs )  f osc The area of one bit cell is 15.81μm2 and the chip size is
about 2.64mm2. The layout of the 16 Kbits EEPROM
For this improved charge pump, the forward voltage without high voltage generator is shown in figure 8. The
drop at each node is eliminated, the voltage pumping chip has been taped out earlier.
gain is

C I out
GV   V  (2)
C  Cs (C  Cs )  f osc

4. Verification and layout

According to simulation, at read action, the power

consumption of the 16 Kbits EEPROM is 0.8mA, and
the power consumption of the 64 Kbits EEPROM is
1.3mA. Power supply voltage is 3V. Figure 8. Layout of the the 16 Kbits EEPROM
The speed of access highly depends on the speed of
pre-charging and discharging of the bit line. When 5. Conclusion
capacity is large the driving ability of bit cell’s each port
need to strengthen. By optimizing the circuit and device, In this paper, the key technologies needed in EEPROM
the 64 Kbits EEPROM’s access time is reduced to 100ns. designing are described. A 16 Kbits EEPROM has been
At typical situation, the simulated voltage value of bit designed and is under fabricating. A 64 Kbits 3V only
cell’s ports is shown in left part of figure 6. EEPROM is designed with a CMOS compatible process
and will be taped out soon, at read action, its power
consumption is 1.3mA, its access time is reduced to
WL, 3V 100ns. A variety of operational modes have been
designed to reduce programming time and erasing time,
VPPL, 12V
VPPH, 14V the testability of the EEPROM is improved at the same
CG, 1V time. The read-out circuit especially the SA has been
optimized to reduce power consumption. The high
BL, 1V
voltage generator has been optimized to improve
SL, 0V efficiency. In addition, two columns of redundant bit
cells have been added in the memory array to increase
Figure 6. The simulated voltage values of bit cell (left) yield.
and high voltage generator (right) According to simulation, the EEPROM meets the
battery-less TPMS’s demand which is low power and
At typical situation, byte programming time is 1030us, large capacity etc.
page programming time and chip programming time is
1282us, block erasing time is 1030us, page erasing and References
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