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DWC Mobile Storage

The Synopsys SD/eMMC Host Controller IP is designed for mobile, consumer, IoT, and automotive applications, compliant with SD 6.0, SDIO 4.10, and eMMC 5.1 specifications. It features advanced capabilities such as a Command Queuing Engine, low-power options, and a high-performance AXI interface, while also supporting various DMA modes for efficient data transfer. The IP is rigorously verified using UVM methodologies and is in volume production, making it suitable for a wide range of applications.

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74 views3 pages

DWC Mobile Storage

The Synopsys SD/eMMC Host Controller IP is designed for mobile, consumer, IoT, and automotive applications, compliant with SD 6.0, SDIO 4.10, and eMMC 5.1 specifications. It features advanced capabilities such as a Command Queuing Engine, low-power options, and a high-performance AXI interface, while also supporting various DMA modes for efficient data transfer. The IP is rigorously verified using UVM methodologies and is in volume production, making it suitable for a wide range of applications.

Uploaded by

yaivanov913
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SYNOPSYS IP DATASHEET

SD/eMMC Host Controller IP

Highlights Overview
• Compliant with the SD 6.0, SDIO 4.10 The Synopsys SD/eMMC Host Controller IP addresses the growing storage
and eMMC 5.1 specifications and needs of mobile, consumer, IoT and automotive applications. The IP provides
earlier versions advanced features such as ADMA3 for the SD 6.0, SDIO 4.10 specifications and
• Supports advanced eMMC features Command Queuing Engine (CQE) for the SD 6.0 and eMMC 5.1 specifications.
including HS400 mode and built-in The IP also provides advanced high-performance 32- and 64-bit AXI interface to
CQE with priority sensitive scheduling the system-on-chip (SoC).
algorithm for high performance
The IP architecture leverages power management techniques, making it ideal for
• Low power features with power gating low-power applications. The highly configurable and scalable IP is packaged with
and multi-power rails Synopsys coreConsultant tool and is optimized to reduce gate count and power
• Supports host controller interface (HCI) consumption while ensuring compatibility with previous and future generation SD
specification for SD ensuring the usability and eMMC specifications.
of standard software drivers with support
A rigorous UVM-based verification methodology is applied to the DesignWare SD/
for SDMA, ADMA2 and ADMA3 modes
eMMC Host Controller IP, consisting of directed tests and constrained random
• Includes high-performance 32- and 64-bit verification. The simulation-based verification is further augmented with FPGA
AXI bus interface hardware verification based on Synopsys’ HAPS®-DX FPGA-based prototyping
• Supports multiple options for system. The FPGA development board is tested with all major SD cards, SDIO
software-based, software-assisted commands, and eMMC devices. The IP is in volume production and has been
and hardware-driven tuning successfully implemented in a wide range of applications.

Target Applications
• Mobile
• Consumer
• Internet-of-Things (IoT)
• Automotive

Figure 1: Synopsys SD/eMMC Host Controller IP block diagram

synopsys.com/ip
Key Features
• Compliant with SD HCI specification
• CQE capable of reordering task execution based on priority
• Data prefetching for back to back tasks—further improves random IOPS
• Low-power features with power gating and multi-power rails
• Independent clock domains help in shutting down intelligently to save power
• Support for in-line encryption
• UVM-based verification approach with single Test Environment for SD 6.0, eMMC 5.x, SDIO 4.10 specifications
• Includes high-performance 32- and 64-bit AXI bus interface
• Support for advanced DMA modes to improve data transfer between system memory and SD card
• Data buffering with configurable FIFO depth and automatic packing/unpacking of data to fit FIFO width
• Combined and separate interrupt outputs with support for interrupt enabling and masking
• Scatter—gather DMA
• Configurable block size (1 to 65,535 Bytes)

Command Queue
The new Command Queue feature in the eMMC 5.1 and SD 6.0 specifications is a mechanism that improves user experience.
Multiple commands are collected and executed in order of priority or in the order that makes sense for the current purpose, instead
of executing each command as they arrive. Performance is improved with command queuing, particularly in multitasking scenarios
where the storage device needs to perform many small read and write operations.

Verification IP
Synopsys Verification IP for eMMC, SD, and AMBA® specifications are based on next-generation architecture and implemented in
native SystemVerilog and UVM. It offers native performance, native debug within the Verdi® Protocol Analyzer environment, enhanced
ease of use, complete configurability and comprehensive coverage.

Verification IP Features
• SystemVerilog testbench
• Native UVM support
• Runs natively on all major simulators and Verification Compiler™
• Built-in verification plan and coverage
• Verdi integrated protocol-aware debug
• Built-in protocol checks
• HTML based documentation
• Ease of integration and use with Interface IP
• Common platform used for internal verification and customer deliverable

2
Deliverables
• Databook
• Application notes
• CoreTools packaged customer configurable Verilog RTL source code
• Synthesis scripts for Synopsys Design Compiler
• Verification testbench, test cases and test configurations

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP
portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired interface IP, wireless interface IP,
security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP
into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits, IP Virtualizer Development Kit and IP subsystems.
Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology
enables designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit synopsys.com/designware .

©2023 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at http://www.synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
05/02/23.CS12208_Synopsys_SD_eMMC_Host_DS.

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