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LIBRARY Ieee

The document describes a testbench for a VHDL entity named 'cv_counter'. It includes the definition of signals, a clock process, and a stimulus process to simulate the behavior of the counter. The clock period is set to 10 ns, and the testbench is structured to instantiate the counter and apply test stimuli.

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Walid Ibn Zinnah Ayon
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24 views5 pages

LIBRARY Ieee

The document describes a testbench for a VHDL entity named 'cv_counter'. It includes the definition of signals, a clock process, and a stimulus process to simulate the behavior of the counter. The clock period is set to 10 ns, and the testbench is structured to instantiate the counter and apply test stimuli.

Uploaded by

Walid Ibn Zinnah Ayon
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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-----LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY cv_counter_tb IS
END cv_counter_tb;

ARCHITECTURE behavior OF cv_counter_tb IS

COMPONENT cv_counter
PORT(
cnt : INOUT std_logic_vector(2 downto 0);
clk : IN std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
--BiDirs
signal cnt : std_logic_vector(2 downto 0);

-- Clock period definitions


constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: cv_counter PORT MAP (
cnt => cnt,
clk => clk
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

wait;
end process;

END;

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