DIGITAL CIRCUITS QUESTIONS

QUESTION 4:
Expression of a function f(a,b,c,d) is given in 2nd canonical form that includes 6 maxterms.
f(a,b,c,d)= (a+b+c+d′)(a+b′+c+d′)(a′+b′+c+d)(a′+b′+c+d′)(a′+b′+c′+d)(a′+b+c+d′)

a. Draw the Karnaugh map of the function f(a,b,c,d) and find all prime implicants.
b. Find all prime implicants of the complement (𝑓̅(a,b,c,d)) of the function using the Quine-
McCluskey method.
QUESTION 5:
a. Find the sufficient base with the lowest cost (minimal covering sum) for the following chart.
Calculate the cost. Show your work.

0 2 4 5 7 8 10 11 13 14 Cost
A X X 6
B X X X X X 8
C X X X X 8
D X X X 8
E X X X X X X 10
F X X X X 10

QUESTION 6:
A BC D
An incomplete logic function Z=f(A,B,C,D) is
implemented by using a 4:16 decoder and a NOR s3 s2 s1 s0
gate. Don’t care input values (A,B,C,D) is:1100 O0
O1 1
a. Draw the Karnaugh map of the function and find O2
4:16 O3
all prime implicants. O4
Decode r O5
as 𝑎̅.
To show complements put a dash over literals, such
O6 6
O7
O8
b. Construct the prime implicant chart. O9 9 Z
The cost criteria: 2 units for each variable and 1 unit O101
for each complement sign. O12
O13
O14
13
c. Simplify the prime implicant chart and find the 5
cheapest expression of the function. O1

QUESTION 7:
‘0’ ‘1’
The given combinational circuit has four inputs (a,b,c,d) and one d
output (z).
I0
a. Construct the truth table of this circuit and write the expression of
the logical function z=f(a,b,c,d) in 1st canonical form. I1
b. Minimize the expression using axioms and theorems of the I
Boolean algebra. 2 8:1
MUX O z
c. Design and draw the same circuit using a 4:16 decoder and other I
necessary logic gates. 3
I
4
I5 s2 s1 s0

a b
c
QUESTION 8:
a) The combinational circuit (Operator) shown on right performs
operations on three 4-bit unsigned integers A=A3 A2 A1 A0 , B=B3 B2 A B C
B1 B0 and C=C3 C2 C1 C0 . The type of the operation is determined by
the inputs x and y as follows: 4 4 4

x y Operation x
0 0 Z=A Operato
y
0 1 Z=B r
1 0 Z=A+B
1 1 Z=A+C 4

Design and draw this combinational circuit (Operator) using one parallel Z
adder, multiplexers and other necessary logic gates.

QUESTION 9: O0
The block diagram of a 3:8 decoder is shown on the right. O
Design and draw a 3:8 decoder using only two 2:4 decoders with “enable - EN” inputs and 1
one NOT gate. 3: OO3
Fully label all inputs and outputs (including those on the decoders). 8
Dec
O4
O
5
O
6

QUESTION 10:
Analyze the given circuit by applying different input values and show that this circuit can be used
as a memory unit.
Derive the next state equation for Q as Q(t+1)=f(A,B,Q(t)).

A
B Q

QUESTION 11:
a. Analyze the given clocked synchronous
A ‘0’ ‘1’ ‘1’
circuit with two inputs (A,B) and one J Q1 ‘0’
output Q
B K
CLK I3 I2 I1 I0
(Z) and construct the State/Output table. s
Note: Q1is the most significant state Z
1
s0 4:1 Z
variable and Q0 is the least significant one.
MUX
Show steps shortly, how you created the Q0
table. ‘1 T
’ CLKQ
Draw the state diagram of the circuit.
Cloc
b. Design and draw the circuit with the k
same behavior (as in a.) by using D flip-
flops and only 2-input NAND gates.
QUESTION 12:
A clocked synchronous circuit with one input (X) and one output (Z) will be designed using the
Moore model. Whenever the total number of “1”s received at input X during the positive edges
of the clock signal is odd and greater than 2 (3, 5, 7, …), the output Z will be “1”, otherwise “0”.
The “1”s at the input X don’t need to be successive.
Example of input and output sequences:
X=11100101010
Z=00111001100

a. Draw the state diagram and construct the State/Output table of the circuit.
b. Implement and draw the circuit using positive edge triggered JK flip-flops and other necessary
logic gates.

QUESTION 13:
The internal structure of a CMOS logic gate is given
on the right.
Examine the given circuit.
Make a table showing the state s (on/off) of the
transistors (Qx).
Write the expression for the function Z=f(A).

Q2
Q4

A Z
Q3
Q1