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UNIT-III

MEMORY INTERFACING WITH 8086 & PERIPHERAL DEVICES:

The 8086 Memory Interface

Memory Devices
 Simple or complex, every microprocessor-based system has a memory system.
 Almost all systems contain four common types of memory:
 Read only memory (ROM)
 Flash memory (EEPROM)
 Static Random access memory (SARAM)
 Dynamic Random access memory (DRAM).
 Before attempting to interface memory to the microprocessor, it is essential to
understand the operation of memory components.

Memory Pin Connections

Figure (1) shows a general form diagram of ROM and RAM pins. Pin connections common to
all memory devices are:
 Address connections
 Data connections
 Selection connections
 Control connections

Address connections: All memory devices have address inputs that select a memory location
within the memory device. Address inputs are labeled from A0 to An

Data connections: All memory devices have a set of data outputs or input/outputs. Today many
of them have bi-directional common I/O pins.

Selection connections: Each memory device has an input that selects or enables the memory
device. This kind of input is most often called a chip select ( CS ), chip enable ( CE ) or simply
select ( S ) input.
 RAM memory generally has at least one CS or S input and ROM at least one CE .
 If the CE , CS , S input is active the memory device perform the read or write.
 If it is inactive the memory device cannot perform read or write operation.
 If more than one CS connection is present, all most be active to perform read or write
data.

Control connections:
 A ROM usually has only one control input, while a RAM often has one or two control inputs.
 The control input most often found on the ROM is the output enable ( OE ) or gate ( G ),
this allows data to flow out of the output data pins of the ROM.

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 A RAM memory device has either one or two control inputs. If there is one control input it
is often called R .
W
 This pin selects a read operation or a write operation only if the device is selected by the
selection input ( CS )

Fig. 1: Memory Component

Read-only memory (ROM)

 Read-only memory (ROM) permanently stores programs/data resident to the system, and
must not change when power disconnected
 Often called nonvolatile memory, because its contents do not change even if power is
disconnected.
 A device we call a ROM is purchased in mass quantities from a manufacturer.
programmed during fabrication at the factory
 The EPROM (erasable programmable read-only memory) is programmed in the field on a
device called an EPROM programmer.
 Also erasable if exposed to high-intensity ultraviolet light, depending on the type of
EPROM.
 The PROM (programmable read-only memory) is also programmed in the field by burning
open tiny NIchrome or silicon oxide fuses. Once it is programmed, it cannot be erased.
 A newer type of read-mostly memory (RMM) is called the flash memory.
 Flash memory is also often called an EEPROM (electrically erasable programmable ROM)
or EAROM (electrically alterable ROM) or a NOVRAM (nonvolatile RAM)
 Electrically erasable in the system, but they require more time to erase than normal RAM.
 The flash memory device is used to store setup information for systems such as the video
card in the computer.

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Static Random Access Memory (SRAM)

 A Static RAM is a volatile memory device which means that the contents of the memory
array will be lost if power is removed.
 Unlike a dynamic memory device, the static memory does not require a periodical refresh
cycle and generally runs much faster than a dynamic memory device.
 Static RAM is used when the size of the read/write memory is relatively small, today, a
small memory is less than 1M byte.
 The main difference between ROM and RAM is that RAM is written under normal
operation, whereas ROM is programmed outside the computer and normally is only read.

Dynamic Random Access Memory (DRAM)

 Available up to 256M X 8 (2G bits).
 DRAM is essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an
integrated capacitor.
 After 2 or 4 ms, the contents of the DRAM must be completely rewritten (refreshed),
because the capacitors, which store a logic 1 or logic 0, lose their charges.

8086 Memory Interface

 The memory address space of the 8086-based microcomputers has different logical and
physical organizations (see Fig. 2).

(a) (b)
Fig. 2: (a) Logical memory organization, and (b) Physical memory organization
(high and low memory banks) of the 8086 microprocessor.

 Logically, memory is implemented as a single 1M × 8 memory chunk. The byte-wide

storage locations are assigned consecutive addresses over the range from 00000H
through FFFFFH
 Physically, memory is implemented as two independent 512 Kbyte banks: the low (even)
bank and the high (odd) bank. Data bytes associated with an even address (00000H,

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00002H, etc.) reside in the low bank, and those with odd addresses (00001H, 00003H,
etc.) reside in the high bank.
 Address bits A1 through A19 select the storage location that is to be accessed. They are
applied to both banks in parallel. A0 and bank high enable ( BHE ) are used as bank-select
signals.
 The memory locations 00000-FFFFF are designed as odd and even bytes. To distinguish
between odd and even bytes, the CPU provides a signal called BHE (bus high enable).
BHE and A0 are used to select the odd and even byte, as shown in the table below.

BHE A0 Function
0 0 Choose both odd and even memory bank
0 1 Choose only odd memory bank
1 0 Choose only even memory bank
1 1 None is chosen

Minimum mode Memory Interface

 Figure (3) show block diagram of minimum mode 8086 memory interface.

ALE

AD0-AD15

Memory
RD Subsystem
8086 and bus
MPU WR
interface
M/IO Circuit
DT/R

Vcc DEN

BHE
MN/MX

Fig. 3: Minimum mode memory interface

 The control signals provided to support the interface to the memory subsystem are
ALE , M I , DT R , RD , WR , DEN and BHE
 When Address
O latch enable (ALE) is logic 1 it signals that a valid address is on the bus.
This address can be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
 M I (memory/IO) and DT R tells external circuitry whether a memory or I/O transfer
is taking
O place over the bus, and whether the 8086 will transmit or receive data over the
bus.

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 The bank high enable ( BHE ) signal is used as a memory enable signal for the most
significant byte half of the data bus, D8 through D15.
 The signals WR (write) and RD (read) identify that a write or read bus cycleis in
progress.
 DEN (data enable), is also supplied. It enables external devices to supply data to the
microprocessor.

Maximum mode Memory Interface

 Figure (4) show block diagram of maximum mode memory interface.
 In maximum mode the 8086 not directly provides all control signal to support the
memory interface.
 Instead, an external Bus Controller (8288) provides memory commands and control
signals as shown in table (5) in lecture (8).

8086

Fig. 4: Maximum mode memory interface

Memory expansion
In many applications, the microcomputer system requirement for memory is greater than
what is available in a single device. There are two basic reasons for expanding memory capacity:
1. The byte-wide length is not large enough
2. The total storage capacity is not enough bytes.

Both of these expansion needs can be satisfied by interconnecting a number of ICs.

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Example 1: show how to implement 32K× 16 EPROM using two 32K×8 EPROM?
Solution:

Example 2: Design 8086’s memory system consisting of 512K bytes of RAM memory and 128K
bytes of ROM use the devices in figure below. RAM memory is to reside over the address range
00000H through 7FFFFH and the address range of the ROM is to be A0000H through BFFFFH

Example 3: Design 8086’s memory system consisting of 64K bytes of ROM memory, make use of
the devices in figure below. The memory is to reside over the address range 60000H through
6FFFFH

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Example 4: Design a 8086 memory system consisting of 1Mbytes, Using 64K× 8 memory.

Solution:

Example5: show how to implement 64K× 8 EPROM using two 32K×8 EPROM?

Example5: show how to implement 32K× 32 EPROM using four 32K×8 EPROM?

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8251A- PROGRAMMABLE COMMUNICATION INREFACE

The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

• The address lines A5, A6 and A7 are decoded to generate eight chip select signals
(IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.

• The address line A0 and the control signal M/IO(low) are used as enable for
decoder.

• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal

addresses.

• The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data

transfer.

• The RESET and clock signals are supplied by 8284 clock generator. Here the
processor clock is directly connected to 8251A. This clock controls the parallel data transf
er between the processor and 825lA.

• 8251A in I/O mapped in the system is shown in the figure.

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  The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers
like programmable timer 8254 and then used as clock for serial transmission and reception.

 In 8251A the transmission and reception baud rates can be different or same.

 The TTL logic levels of the serial data lines and the control signals necessary for serial transmission
and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard
9-pin D-.type connector.

 The device, which requires serial communication with processor, can be connected to this 9-pin D-
type connector using 9-core cable.

8257 DMA Controller

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows
the device to transfer the data directly to/from memory without any interference of the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the device
is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

 Initially, when any device has to send data between the device and the memory, the device has to
send DMA request (DRQ) to DMA controller.

 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the
HLDA.

 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.

 Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses
between the CPU, memory, and I/O devices.

Features of 8257

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Here is a list of some of the prominent features of 8257 −

 It has four channels which can be used over four I/O devices.

 Each channel has 16-bit address and 14-bit counter.

 Each channel can transfer data up to 64kb.

 Each channel can be programmed independently.

 Each channel can perform read transfer, write transfer and verify transfer operations.

 It generates MARK signal to the peripheral device that 128 bytes have been transferred.

 It requires a single phase clock.

 Its frequency ranges from 250Hz to 3MHz.

 It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

The following image shows the architecture of 8257 −

8257 Pin Description

The following image shows the pin diagram of a 8257 DMA controller −

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 DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices for using
DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the lowest
priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of
their request by the CPU. These lines can also act as strobe lines for the requesting devices.

Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus of
DMA controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the master
mode, these lines are used to send higher byte of the generated address to the latch. This address is further latched
using ADSTB signal.

IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of 8257
in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory write cycle.

IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit mode
register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is used
to load the data to the peripheral devices during DMA memory read cycle.

CLK
It is a clock frequency signal which is required for the internal operation of 8257.

RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects one of
the registers to be read or written. In the master mode, they are the four least significant memory address output lines
generated by 8257.

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 CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the
master mode, it disables the read/write operations to/from 8257.

A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.

HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it is connected
with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.

HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted to the
requesting peripheral by the CPU when it is set to 1.

MEMR
It is the low memory read signal, which is used to read the data from the addressed memory locations during
DMA read cycles.

MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location during
DMA write operation.

ADST
This signal is used to convert the higher byte of the memory address generated by the DMA controller into the
latches.

AEN
This signal is used to disable the address bus/data bus.

TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.

MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates the
current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.

Vcc
It is the power signal which is required for the operation of the circuit.

8255A - Programmable Peripheral Interface

The 8255A is a general purpose programmable I/O device designed to transfer the data from I/O to interrupt
I/O under certain conditions as required. It can be used with almost any microprocessor.
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It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

 Port B is similar to PORT A.

 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by
the control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C.
Group B includes PORT B and lower PORT C. These two groups can be programmed in three different
modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is
named as Mode 2.

Operating Modes
8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each
port can be programmed in either input mode or output mode where outputs are latched and inputs
are not latched. Ports do not have interrupt capability.

 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either
input or output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs
are latched.

 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in Mode
0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The
remaining three signals from Port C can be used either as simple I/O or as handshake for port B.

Features of 8255A

The prominent features of 8255A are as follows −

 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.

8255 Architecture

The following figure shows the architecture of 8255A −

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8255A - Pin Description
Let us first take a look at the pin diagram of Intel 8255A −

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is
transmitted or received by the buffer as per the instructions by the CPU. Control words and status

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information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts
the input from the CPU address and control buses, and in turn issues command to both the control groups.

CS

It stands for Chip Select. A LOW on this input selects the chip and enables the communication between the
8255A and the CPU. It is connected to the decoded address, and A0 & A1 are connected to the
microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X No Selection

WR

It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.

RESET

This is an active high signal. It clears the control register and sets all ports in the input mode.

RD

It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1

These input signals work with RD, WR, and one of the control signal. Following is the table showing their
various signals with their result.

A1 A0 RD WR CS Result
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 0 0 0 1 0 Input Operation

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus
0 0 1 0 0 Output Operation

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D

8253 - Programmable Interval Timer

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform
timing and counting functions using three 16-bit registers. Each counter has 2 input pins, i.e. Clock & Gate,
and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded in its register. On command, it
begins to decrement the count until it reaches 0, then it generates a pulse that can be used to interrupt the
CPU.

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254
Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not available Read-Back command is available
Reads and writes of the same counter cannot be Reads and writes of the same counter can be
interleaved. interleaved.

Features of 8253 / 54
The most prominent features of 8253/54 are as follows −

 It has three independent 16-bit down counters.

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  It can handle inputs from DC to 10 MHz.

 These three counters can be programmed for either binary or BCD count.

 It is compatible with almost all microprocessors.

 8254 has a powerful command called READ BACK command, which allows the user to check the
count value, the programmed mode, the current mode, and the current status of the counter.

8254 Architecture
The architecture of 8254 looks as follows −

8254 Pin Description

Here is the pin diagram of 8254 −

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In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a control
register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT.

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus. It
has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode, the RD and
WR signals are connected to IOR and IOW, respectively. In the memorymapped I/O mode, these are
connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied to a
decoded address. The control word register and counters are selected according to the signals on lines A0 &
A1.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection

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Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word, which
specifies the counter to be used, its mode, and either a read or write operation. Following table shows the
result for various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation

Counters

Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or BCD. Its
input and output is configured by the selection of modes stored in the control word register. The programmer
can read the contents of any of the three counters without disturbing the actual count in process.

8253/54 - Operational Modes

8253/54 can be operated in 6 different modes. In this chapter, we will discuss these operational modes.

Mode 0 ─ Interrupt on Terminal Count

 It is used to generate an interrupt to the microprocessor after a certain interval.

 Initially the output is low after the mode is set. The output remains LOW after the count value is
loaded into the counter.

 The process of decrementing the counter continues till the terminal count is reached, i.e., the count
become zero and the output goes HIGH and will remain high until it reloads a new count.

 The GATE signal is high for normal counting. When GATE goes low, counting is terminated and the
current count is latched till the GATE goes high again.

Mode 1 – Programmable One Shot

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  It can be used as a mono stable multi-vibrator.

 The gate input is used as a trigger input in this mode.

 The output remains high until the count is loaded and a trigger is applied.

Mode 2 – Rate Generator

 The output is normally high after initialization.

 Whenever the count becomes zero, another low pulse is generated at the output and the counter will
be reloaded.

Mode 3 – Square Wave Generator

 This mode is similar to Mode 2 except the output remains low for half of the timer period and high
for the other half of the period.

Mode 4 − Software Triggered Mode

 In this mode, the output will remain high until the timer has counted to zero, at which point the
output will pulse low and then go high again.

 The count is latched when the GATE signal goes LOW.

 On the terminal count, the output goes low for one clock cycle then goes HIGH. This low pulse can
be used as a strobe.

Mode 5 – Hardware Triggered Mode

 This mode generates a strobe in response to an externally generated signal.

 This mode is similar to mode 4 except that the counting is initiated by a signal at the gate input,
which means it is hardware triggered instead of software triggered.

 After it is initialized, the output goes high.

 When the terminal count is reached, the output goes low for one clock cycle.

8259A Programmable Interrupt Controller

 8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor. There
are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by connecting
8259 with CPU, we can increase the interrupt handling capability. 8259 combines the multi interrupt
input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from
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 IR0-IR7.

For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor
from 5 to 8 interrupt levels.

Features of 8259 PIC microprocessor –

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can masked individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PIC.
5. Clock cycle is not required.

Pin Diagram of 8259 –

We can see through above diagram that there are total 28 pins in 8259 PIC microprocessor where Vcc :5V
Power supply and Gnd: ground. Other pins use are explained below.

Block Diagram of 8259 PIC microprocessor

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The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer
Comparator, Control Logic, Priority Resolver and 3 registers-ISR, IRR, IMR.

1. Data bus buffer –

This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer. It
takes the control word from the 8085 (let say) microprocessor and transfer it to the control logic of 8259
microprocessor. Also, after selection of Interrupt by 8259 microprocessor, it transfer the opcode of the
selected Interrupt and address of the Interrupt service sub routine to the other connected microprocessor. The
data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of
8 bits data can be transferred at a time.

2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins are active low pins
used for read and write operations.

3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block.It has pin INTR which is
connected with other microprocessor for taking interrupt request and pin INT for giving the output. If 8259
is enabled, and the other microprocessor Interrupt flag is high then this causes the value of the output INT
pin high and in this way 8259 responds to the request made by other microprocessor.

4. Interrupt request register (IRR) –

It stores all the interrupt level which are requesting for Interrupt services.

5. Interrupt service register (ISR) –

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 It stores the interrupt level which are currently being executed.

6. Interrupt mask register (IMR) –

It stores the interrupt level which have to be masked by storing the masking bits of the interrupt level.

7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the priority of the
interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt level which is
already been serviced in IRR.

8. Cascade buffer –

To increase the Interrupt handling capability, we can further cascade more number of pins by using
cascade buffer. So, during increment of interrupt capability, CSA lines are used to control multiple interrupt
structure. SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave and in
Buffered mode, SP/EN pin is used as an output to enable data bus

Programmable Communication Interface 8251 USART

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between microprocessor
and peripheral to transmit serial data into parallel form and vice versa.

1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).

Block Diagram of 8251 USART –

It contains the following blocks:

1. Data bus buffer –
This block helps in interfacing the internal data bus of 8251 to the system data bus. The data transmission is

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 possible between 8251 and CPU by the data bus buffer block.

2. Read/Write control logic –

It is a control block for overall device. It controls the overall working by selecting the operation to be done.
The operation selection depends upon input signals as:

In this way, this unit selects one of the three registers- data buffer register, control register, status register
.
3. Modem control (modulator/demodulator) –
A device converts analog signals to digital signals and vice-versa and helps the computers to communicate
over telephone lines or cable wires. The following are active-low pins of Modem.

 DSR: Data Set Ready signal is an input signal.

 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit.
 RTS: It is an output signal which is used to set the status RTS.

4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for conversion into serial
signal and further transmission onto the common channel.

 TXD: It is an output signal, if its value is one, means transmitter will transmit the data.

5. Transmit control – This block is used to control the data transmission with the help of following pins:

o TXRDY: It means transmitter is ready to transmit data character.

o TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all the data
characters and transmitter is empty now.

 TXC: An active-low input pin which controls the data transmission rate of transmitted data.

6. Receive buffer – This block acts as a buffer for the received data.

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  RXD: An input signal which receives the data.

7. Receive control – This block controls the receiving data.

 RXRDY: An input signal indicates that it is ready to receive the data.

 RXC: An active-low input signal which controls the data transmission rate of received data.

 SYNDET/BD: An input or output terminal. External synchronous mode-input terminal and

asynchronous mode-output terminal.

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