Standard Combinational Modules & Modular Networks

Introduction
It is known that any combinational circuit can be implemented by a 2-level AND-OR (or OR-
AND) network.
Similarly, any combinational circuit can be implemented by a 2-leven NAND-NAND or NOR-
NOR network.
The systematic approach consists in
- Truth table
- K_Map(s)
However, for large (complex) combinational systems, this approach may become impractical.

For example, consider the design of an 8-bit digital comparator.

If we use the systematic approach, then the truth table would require 216 rows or combinations
(an 8-bit comparator has 2 inputs of 8-bit each; therefore, we should have a truth table of 216
combinations). It is impractical. Moreover, we need the use of 8-variable K_Maps!!!

For these reasons and others, we should use an alternate approach: a modular technique. In
others words, we should design such systems at block or module level instead of gate level.
• This unit discusses a number of commonly used standard combinational modules or
blocks, namely
1. Decoders
2. Multiplexers
3. Demultiplexers
4. Encoders
5. Code Converters
• Several examples and applications will illustrates this approach
• VHDL descriptions will also be given

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1. DECODERS
1.1 Single-Gate Decoders
The simplest decoder is a single-gate. It is used to detect the presence of one particular binary
value (or code).
Consider the 2 gates of Figure 1.

X3 X3
X2 X2
X1 11 X1 13
X0 X0

(a) (b)

Figure 1 (a) Active HIGH indicator, (b) Active LOW indicator

(a) The output of the AND gate is a logic ‘1’ only when its input is (1011)2 = (11)10
(b) The output of the NAND gate is a logic ‘0’ only when its input is (1101)2 = (13)10

1.2 Definition of a Decoder

A decoder, DEC for short, is a multi-output combinational logic module. It has
- n inputs (X = Xn-1, Xn-2, …, Xi, …, X1, X0)
- 2n outputs (Y = Y2n-1, Y2n-2, …, Yi, …, Y1, Y0)
Figure 2 depicts the block diagram of an (n : 2n) binary DEC

2n
n Y2n-1
Xn-1
Y2n-2
Xn-2

X n : 2n Y
Xi DEC Yi

X0 Y1
En Y0

Figure 2 Block diagram of an n : 2n DEC with active H outputs provided with an Enable

Principle of operation
When enabled (En = 1), each combination on the inputs drives exactly ONE of the 2n output
lines HIGH and all the others LOW. The index of that output corresponds to the binary value
(code) applied on the inputs.

For example, if we apply code all zeros X = (00…0…0)2 on the inputs, only output Y0 will be
HIGH and all the others will be LOW.
Similarly, if we apply code all ones X = (11…1…1)2 on the inputs, only output Y2n-1 will be
HIGH and all the others will be LOW.

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The n:2n DEC generates all 2n minterms of the inputs. This is why; a DEC is sometimes called a
minterm generator.

To facilitate networking, an additional input, the module Enable (En) is provided (some DECs
have more than one Enable input).

When the enable is asserted (En = 1), the module is enabled. When di-asserted (En = 0), the
module is disabled, all output are LOW.

Assuming an active HIGH outputs and active HIGH module enable (Figure 2), the n:2n DEC
can be described as
1 when X= i and En = 1
Yi =
0 otherwise

As a Boolean expression, Yi can be expressed as

Yi = En mi(X)

where mi(X) is the i-th minterm of the n-variable input vector X

The simplest multi-output DEC is the 1:2 DEC

X Y0 Y1 Y1
0 1 0 X 1:2
DEC Y0
1 0 1

Y0 = m0(X) = X
Y1 = m1(X) = X
The internal circuit of a 1:2 DEC is

Y0 = X

X ● Y1 = X

1.3 The internal structure of a 2:4 DEC

The internal circuit of a 2:4 DEC with an active HIGH Enable
i- Truth table ii- Block diagram

En X1 X0 Y0 Y1 Y2 Y3 Y3
0 - - 0 0 0 0 X1 2:4
DEC Y2
1 0 0 1 0 0 0 X0 Y1
1 0 1 0 1 0 0
En Y0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Boolean equations

Y0 = En m0(X) = En X1 X 0

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 Y1 = En m1(X) = En X1 X 0
Y3
Y2 = En m2(X) = En X1 X 0
Y3 = En m3(X) = En X1 X 0
X1 Y2

X0 Y1

Y0
En

1.4 Applications of DECODERS

DECs are widely used in digital systems. Below is a list of some of its applications
1. Detect a particular code or value
2. To implement Boolean functions
3. For address decoding in microprocessor base systems
4. To select a function from an op-code

Example
Using a DEC of appropriate size and a minimum number of gates, implement the following 3-
input 3-output combinational system described by its Boolean functions

f1(a, b, c) = Σ m(1, 2, 7)
f2(a, b, c) = Σ m(4, 5)
f3(a, b, c) = Σ m(0, 2, 3, 6)
The advantage of using a DEC is that it is not necessary to minimize the Boolean function using
K_Maps
Solution
This system requires a 3:8 DEC which provides the 8 possible minterms. To logically sum the
minterms of the functions, we need a 3-input OR for f1, a 2-input OR for f2 and a 4-input OR for
f3.

7
2 1 f1
6 7

a X2 5
4 f2
X1 3:8 4 5
b
DEC 3
c X0
2 0
2 f3
1 3
1 6
En 0

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2. VHDL descriptions of binary decoders

Example 1
Y3
X1 2:4
Write a behavioural VHDL code for the 2:4 Decoder DEC Y2
shown next X0 Y1
En Y0

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 Example 2
Write the behavioral VHDL code to synthesize a 3:8 DEC provided with an active HIGH Enable
(En) and active LOW outputs.
Solution

6
3. Exercises

Exercise 1
Consider the following block diagram.
It consists of a Mod-8 up counter and a 3:8 DEC driving 8 LEDs.

7
6

3 :8
DEC

Clk 0
Mod-8

RST

1. Write the behavioral VHDL code to synthesize this digital system

2. Write a structural VHDL to synthesize this digital system

Exercise 2
It is desired to control the lightning of a lamp. The lamp should be turned ON when a Mod-16
UP counter is counting between 3 and 12 else, the lamp is OFF.
1. Write a VHDL code to synthesize this controller
2. Design this controller using the minimum set of sequential and combinational modules
we have considered so far.

Exercise 3
Using a 4:16 DEC with active LOW outputs and gates (any), implement the following set of
Boolean functions

f1(a, b, c, d) = Σ m(1, 12, 15)

f2(a, b, c, d) = Σ m(6, 8, 11)
f3(a, b, c, d) = Σ m(0, 9, 13, 14)