SEQUENTIAL CIRCUITS

Introduction:
Logic circuits are divided into two types.
1. Combinational Logic Circuits
2. Sequential Logic Circuits
1. Combinational Logic Circuit:
The circuit in which outputs depends on only present value of inputs. So it is possible to describe
each output as function of inputs by using Boolean expression. No memory element involved. No
clock input. Circuit is implemented by using logic gates. The propagation delay depends on, delay of
logic gates. Examples of combinational logic circuits are: full adder, subtractor, decoder, code-
converter, multiplexers etc.

2. Sequential Circuits:
Sequential Circuit is the logic circuit in which output depends on present value of inputs at that instant
and past history of circuit i.e. previous output. The past output is stored by using memory device. The
internal data stored in circuit is called as state. The clock is required for synchronization. The delay
depends on propagation delay of circuit and clock frequency. The examples are flip-flops, registers,
counters etc.
Basic Bistable element.
One Bit memory cell is also called Basic Bistable element. It has two cross-coupled inverters,
2 outputs Q and 𝑄 . It is called “Bistable” as the basic bistable element circuit has two stable states
logic 0 and logic 1.

Let us assume that when power is switched on to the circuit, input ‘x’ is at 1. Therefore, 𝑥 =0 and
thus Q=0. This implies y=0 and 𝑦=1 or 𝑄 =1. So, Q=0, 𝑄 =1 and the circuit continues in this state until
power to the circuit is switched off. This is one of the two stable states of the circuit. On the other
hand, let x=0 when power is switched on. This implies 𝑥 =1 and Q=1. Therefore, y=1 and 𝑦=0 and
𝑄 =0. Now Q=1 ad 𝑄 =0 and this is the other stable state of the circuit in which it indefinitely remains
until power to the circuit is switched off.

The 1 or 0 stored in the basic bistable element is called the state of the element. It is said to be in
the 1 -state when it stores a 1 (Q=1) ad it is said to be in the 0 -state when it stores a 0 (Q=0).

Besides the two stable states, the bistable element can also be in a metastable state which happens
when both the outputs are midway between 0 and 1 in terms of voltages. However, a slight change in
the circuit conditions, caused by a small noise will revert the circuit to one of its two stable states.
Since the circuit can stay in its metastable state for a long time; this period of time is however
unpredictable. There are ways of preventing the circuit to reside in its metastate.

There is no mechanism in the figure shown above by which the basic bistable element can be
forced into a desired state. We need to add input lines which can be used to change the state of the
bistable element. A flip-flop is a bistable circuit with input lines. The flip-flop remains in one of its
two stable states until power is switched off or until an input signal triggers a change in state. A flip-
flop is said to be set or preset when an input signal causes it to store a 1 and it is said to be reset or
cleared when an input signal causes the flip-flop to store a 0.

The inputs to the flip-flop could be synchronous or asynchronous. The flip-flop changes state
immediately in response to appropriate changes in its asynchronous inputs. On the other hand, a
synchronous input can only effect a change of state at certain times with reference to a clock, such as
on the rising edge of a clock. Any changes in inputs between two rising edges goes unrecognized.
Synchronous flip-flops will have enable or clock inputs in addition to the inputs used to cause a
change in state.
LATCHES:

In order for a logical circuit to "remember" and retain its logical state even after the controlling
input signal(s) have been removed, it is necessary for the circuit to include some form of feedback.
We might start with a pair of inverters, each having its input connected to the other's output. The two
outputs will always have opposite logic levels.

A latch is a class of flip-flop whose output responds immediately to appropriate changes in the
input inspite of the presence of an enable or clock input. There are several types of latches based on
types of inputs and enable lines.

S-R Latch: Set-reset Flip-Flop:

Latch is a storage device by using Flip-Flop.
Latch can be controlled by direct inputs.
Latch outputs can be controlled by clock or enable input.
Q and Q are present state for output.
Q+ and Q+ are next states for output.
The function table / Truth table gives relation between inputs and outputs.
The S=R=1 condition is not allowed in SR FF as output is unpredictable.

The circuit shown below is a basic NAND latch. The inputs are generally designated "S" and "R"
for "Set" and "Reset" respectively. Because the NAND inputs must normally be logic 1 to avoid
affecting the latching action, the inputs are considered to be inverted in this circuit. The outputs of any
single-bit latch or memory are traditionally designated Q and 𝑄 . In a commercial latch circuit, either or both
of these may be available for use by other circuits.
Truth Table

S R Q 𝑄
0 0 1 1 *Forbidden State
0 1 1 0
1 0 0 1
1 1 Q 𝑄 Previous State

* Unpredictable Behavior

For the NAND latch circuit, both inputs should normally be at a logic 1 level. Changing an input
to a logic 0 level will force that output to a logic 1. The same logic 1 will also be applied to the second
input of the other NAND gate, allowing that output to fall to a logic 0 level. This in turn feeds back
to the second input of the original gate, forcing its output to remain at logic 1.
Applying another logic 0 input to the same gate will have no further effect on this circuit.
However, applying a logic 0 to the other gate will cause the same reaction in the other direction, thus
changing the state of the latch circuit the other way.

Note that it is forbidden to have both inputs at a logic 0 level at the same time. That state will
force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever
input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting
state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the
final state of the latch cannot be determined ahead of time.
The same functions can also be performed using NOR gates. A few adjustments must be made
to allow for the difference in the logic function, but the logic involved is quite similar.

The circuit shown below is a basic NOR latch. The inputs are generally designated "S" and "R"
for "Set" and "Reset" respectively. Because the NOR inputs must normally be logic 0 to avoid
overriding the latching action, the inputs are not inverted in this circuit. The NOR-based latch circuit
is:

Truth Table

R S Q 𝑄
0 0 Q 𝑄 Previous State
0 1 1 0
1 0 0 1
1 1 0 0 Forbidden State

For the NOR latch circuit, both inputs should normally be at a logic 0 level. Changing an input
to a logic 1 level will force that output to a logic 0. The same logic 0 will also be applied to the second
input of the other NOR gate, allowing that output to rise to a logic 1 level. This in turn feeds back to
the second input of the original gate, forcing its output to remain at logic 0 even after the external
input is removed.

Applying another logic 1 input to the same gate will have no further effect on this circuit.
However, applying a logic 1 to the other gate will cause the same reaction in the other direction, thus
changing the state of the latch circuit the other way.

Note that it is forbidden to have both inputs at a logic 1 level at the same time. That state will
force both outputs to a logic 0, overriding the feedback latching action. In this condition, whichever
input goes to logic 0 first will lose control, while the other input (still at logic 1) controls the resulting
state of the latch. If both inputs go to logic 0 simultaneously, the result is a "race" condition, and the
final state of the latch cannot be determined ahead of time.

One problem with the basic RS NOR latch is that the input signals actively drive their respective
outputs to a logic 0, rather than to a logic 1. Thus, the S input signal is applied to the gate that produces
the Q' output, while the R input signal is applied to the gate that produces the Q output. The circuit
works fine, but this reversal of inputs can be confusing when you first try to deal with NOR-based
circuits.
Application of SR Latch: Switch debouncer

Flip-flops:
Latches are asynchronous, which means that the output changes very soon after the input
changes. Most computers today, on the other hand, are synchronous, which means that the outputs of
all the sequential circuits change simultaneously to the rhythm of a global clock signal.

A flip-flop is a synchronous version of the latch.

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops
are shown in the two Figures shown below. Each flip-flop has two outputs, Q and
𝑄 , and two inputs, set ‘S’ and reset. ‘R’. This type of flip-flop is referred to as an SR flip-flop or SR
latch. The flip-flop in second Figure has two useful states. When Q=1 and 𝑄 =0, it is in the set state
(or 1-state).
 When Q=0 and 𝑄 =1, it is in the clear state (or 0-state). The outputs Q and 𝑄 are complements of
each other and are referred to as the normal and complement outputs, respectively. The binary state
of the flip-flop is taken to be the value of the normal output.

When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and 𝑄
outputs go to 0. This condition violates the fact that both outputs are complements of each other. In
normal operation this condition must be avoided by making sure that 1's are not applied to both inputs
simultaneously.

The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the
state of the flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1
and 𝑄 to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1.
This condition should be avoided in normal operation.

Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure below consists of a basic NOR flip-flop and two AND
gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless
of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs
passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes
both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is
indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop
remains a 1 longer than the transition to 0 at the end of the pulse.

JK Flip-Flop:

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level “1”.

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type
is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note
that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied
to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches
to Q=0 and vice versa.

A clocked JK flip-flop is shown in Figure below. Output Q is ANDed with K and CP inputs so
that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput 𝑄 is
ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if 𝑄 was previously
1.

Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a
1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous
transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the
propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a
master-slave or edge-triggered construction. The same reasoning also applies to the T flip-flop
presented next.

NC= No Change

JK Flip Flop is similar to RS flip flop with the feedback which enables only one of its input
terminals. It eliminates the invalid condition which arises in the RS flip flop and put the input
terminal either to set or reset condition one at a time.

When both the J and K inputs are at logic “1” at the same time and the clock input is pulsed HIGH,
the circuit toggle from its SET state to a RESET or visa versa. When both the terminals are HIGH
the JK flip-flop acts as a T type toggle flip-flop.

JK flip-flop has a drawback of timing problem known as “RACE”. The condition of RACE arises
if the output Q changes its state before the timing pulse of the clock input has time to go in OFF
state.

The timing pulse period (T) should be kept as short as possible to avoid the problem of timing.

This condition is not possible always thus a much-improved flip-flop named Master Salve JK Flip
Flop was developed. This eliminates all the timing problems by using two RS flip-flop connected in
series. One is for the “MASTER “ circuit, which triggers on the leading edge of the clock pulse.
The other is called the “SLAVE” circuit, which triggers when the clock pulse is at the falling edge.

JK Master slave Flip-Flop:

In SR Flip-Flop the input combination S=R=1 is not allowed.

JK FF is modified version of SR FF.
Due to feedback from slave FF output to master, J=K=1 is allowed.
J=K=1, toggle, action in FF.
This finds application in counter.

D Flip-Flop:

The D flip-flop shown in Figure below is a modification of the clocked SR flip-flop. The D input
goes directly into the S input and the complement of the D input goes to the R input. The D input is
sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state
(unless it was already set). If it is 0, the flip-flop switches to the clear state.

Logic diagram of D Flip Flap

D C Q 𝑄
0 1 0 1
1 1 1 0
X 0 Q 𝑄

T Flip-Flop:

The T flip-flop is a single input version of the JK flip-flop. As shown in Figure below, the T flip-
flop is obtained from the JK type if both inputs are tied together. The output of the T flip-flop
"toggles" with each clock pulse.

T C Q+ 𝑄
0 1 Q 𝑄
1 1 𝑄 Q
X 0 Q 𝑄