SEQUENTIAL LOGIC

Dr. M Rambabu
Course Code: 24CSEN1001
Course Name: Digital Logic Circuits
Date: April 1, 2025

1 Sequential Circuits
Introduction
The digital circuits considered thus far have been combinational; that is, the output is entirely
dependent on the current inputs. Although every digital system is likely to have some combinational
circuits, most systems encountered in practice also include storage elements, which require that the
system be described in terms of sequential logic. First, we need to understand what distinguishes
sequential logic from combinational logic.

1.1 Sequential Circuits

A block diagram of a sequential circuit is shown in Figure 1. It consists of combinational circuits
where storage elements are connected to form feedback paths. The storage elements are devices
capable of storing binary information. The binary information stored in these elements at any
given time defines the state of the sequential circuit at that time. The sequential circuit receives
binary information from external inputs that, together with the present state of the storage elements,
determine the binary value of the outputs. These external inputs also determine the condition for
changing the state in the storage elements. The block diagram demonstrates that the outputs in a
sequential circuit are a function not only of the inputs but also of the present state of the storage
elements. The next state of the storage elements is also a function of external inputs and the present
state. Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
In contrast, the outputs of combinational logic depend only on the present values of the inputs.

Figure 1: Block diagram of a sequential circuit

There are two main types of sequential circuits, and their classification is a function of the timing
of their signals. A synchronous sequential circuit is a system whose behavior can be defined from
the knowledge of its signals at discrete instants of time. The behavior of an asynchronous sequential
circuit depends upon the input signals at any instant of time and the order in which the inputs

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change. The storage elements commonly used in asynchronous sequential circuits are time-delay
devices. The storage capability of a time-delay device varies with the time it takes for the signal to
propagate through the device. In practice, the internal propagation delay of logic gates is of sufficient
duration to produce the needed delay, so that actual delay units may not be necessary. In gate-type
asynchronous systems, the storage elements consist of logic gates whose propagation delay provides
the required storage. Thus, an asynchronous sequential circuit may be regarded as a combinational
circuit with feedback. Because of the feedback among logic gates, an asynchronous sequential circuit
may become unstable at times. The instability problem imposes many difficulties on the designer.
A synchronous sequential circuit employs signals that affect the storage elements at only discrete
instants of time. Synchronization is achieved by a timing device called a clock generator, which
provides a clock signal having the form of a periodic train of clock pulses. The clock signal is
commonly denoted by the identifiers clock and clk. The clock pulses are distributed throughout
the system in such a way that storage elements are affected only with the arrival of each pulse. In
practice, the clock pulses determine when computational activity will occur within the circuit, and
other signals (external inputs and otherwise) determine what changes will take place affecting the
storage elements and the outputs. For example, a circuit that is to add and store two binary numbers
would compute their sum from the values of the numbers and store the sum at the occurrence of
a clock pulse. Synchronous sequential circuits that use clock pulses to control storage elements are
called clocked sequential circuits and are the type most frequently encountered in practice. They
are called synchronous circuits because the activity within the circuit and the resulting updating of
stored values is synchronized to the occurrence of clock pulses. The design of synchronous circuits is
feasible because they seldom manifest instability problems, and their timing is easily broken down
into independent discrete steps, each of which can be considered separately.

Figure 2: Synchronous clocked sequential circuit

The storage elements (memory) used in clocked sequential circuits are called flip-flops. A flip-flop
is a binary storage device capable of storing one bit of information. In a stable state, the output
of a flip-flop is either 0 or 1. A sequential circuit may use many flip-flops to store as many bits
as necessary. The block diagram of a synchronous clocked sequential circuit is shown in Figure
2. The outputs are formed by a combinational logic function of the inputs to the circuit or the
values stored in the flip-flops (or both). The value that is stored in a flip-flop when the clock pulse
occurs is also determined by the inputs to the circuit or the values presently stored in the flip-flop
(or both). The new value is stored (i.e., the flip-flop is updated) when a pulse of the clock signal

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occurs. Prior to the occurrence of the clock pulse, the combinational logic forming the next value of
the flip-flop must have reached a stable value. Consequently, the speed at which the combinational
logic circuits operate is critical. If the clock (synchronizing) pulses arrive at a regular interval, as
shown in the timing diagram in Figure 2, the combinational logic must respond to a change in the
state of the flip-flop in time to be updated before the next pulse arrives. Propagation delays play an
important role in determining the minimum interval between clock pulses that will allow the circuit
to operate correctly. The state of the flip-flops can change only during a clock pulse transition—for
example, when the value of the clock signal changes from 0 to 1. When a clock pulse is not active,
the feedback loop between the value stored in the flip-flop and the value formed at the input to the
flip-flop is effectively broken because the flip-flop outputs cannot change even if the outputs of the
combinational circuit driving their inputs change in value. Thus, the transition from one state to
the next occurs only at predetermined intervals dictated by the clock pulses.

2 Storage Elements: Definition, Types, and Differences

What is a Storage Element?
A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states. The major differences
among various types of storage elements are in the number of inputs they possess and in the manner
in which the inputs affect the binary state.
Storage elements that operate with signal levels (rather than signal transitions) are referred to
as latches, whereas those controlled by a clock transition are called flip-flops. Latches are said to
be level-sensitive devices, while flip-flops are edge-sensitive devices.
The two types of storage elements are related because latches are the basic circuits from which
all flip-flops are constructed. Although latches are useful for storing binary information and for
the design of asynchronous sequential circuits, they are not practical for use in synchronous
sequential circuits. However, because they are the building blocks of flip-flops, we will consider
the fundamental storage mechanism used in latches before considering flip-flops.

Types of Storage Elements

The classification of storage elements is depicted in the taxonomy diagram below:

Storage
Elements

Sequential
Elements

Flip-Flops Latches

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Differences Between Storage Elements
Feature Flip-Flop Latch
Triggering Method Edge-triggered Level-sensitive
Clock Dependency Requires a clock Does not require a clock
Speed Slower due to clock dependency Faster due to direct response
Usage Used in synchronous circuits Used in asynchronous circuits

3 Storage Elements: SR Latch

Introduction to SR Latch
A sequential circuit stores information and operates based on past and present inputs. The most
fundamental storage element in sequential logic is the **latch**, which serves as a basic building
block for flip-flops. Among various latches, the **SR (Set-Reset) latch** is widely studied as it
provides a simple way to store a single bit of information.

3.1 SR Latch Using NOR Gates

The SR latch can be implemented using two cross-coupled **NOR gates**, as shown in **Figure
3**.

Figure 3: SR Latch using NOR Gates

### Operation: The SR latch has two inputs: - **S (Set)**: Used to store a logic **1**. -
**R (Reset)**: Used to store a logic **0**. - Two outputs, **Q** and **Q’**, where Q′ is the
complement of Q.
### Truth Table for SR Latch (NOR Implementation)

S R Previous Q Q (Next State) Q’ (Next State)

0 0 0 0 1
0 0 1 1 0
0 1 X 0 1
1 0 X 1 0
1 1 X Undefined Undefined

Table 1: Truth Table of SR Latch using NOR Gates

### Key Observations: - **Set State (S = 1, R = 0):** The latch sets Q = 1 and Q′ = 0. -
**Reset State (S = 0, R = 1):** The latch resets Q = 0 and Q′ = 1. - **Hold Condition (S = 0, R =

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0):** The latch retains its previous state. - **Invalid State (S = 1, R = 1):** Both outputs become
0, violating the requirement that Q and Q′ must be complements. This condition is **forbidden**
in practical applications.

3.2 SR Latch Using NAND Gates

An alternative way to implement an SR latch is using two **NAND gates**, as shown in **Figure
4**.

Figure 4: SR Latch using NAND Gates

### Operation: - Unlike the NOR-based SR latch, the NAND-based latch operates with **nor-
mally high inputs** (logic 1). - To change states, an input is temporarily pulled **low (0)** instead
of being set **high (1)**.
### Truth Table for SR Latch (NAND Implementation)

S R Previous Q Q (Next State) Q’ (Next State)

1 1 0 0 1
1 1 1 1 0
1 0 X 1 0
0 1 X 0 1
0 0 X Undefined Undefined

Table 2: Truth Table of SR Latch using NAND Gates

### Key Differences from NOR-based SR Latch: - The NAND latch is often called an **S’R’
latch** because its inputs are active-low. - The **forbidden condition** occurs when both inputs
are **0** instead of **1**, making it the complement of the NOR latch behavior.

3.3 SR Latch with Enable (Gated SR Latch)

To control when the SR latch can change states, an **enable input (En)** is introduced, forming a
**gated SR latch** as shown in **Figure 5**.
### Functionality: - The **enable (En)** input must be **high (1)** for the latch to respond
to S and R. - When **En = 0**, the latch maintains its state regardless of S and R. - When **En
= 1**, the latch operates like a normal SR latch.
### Truth Table for Gated SR Latch
### Importance of Gated SR Latch: - Eliminates unintended changes due to noise. - Used as
a basic component in **flip-flops** and **registers**. - Prevents **metastability** by controlling
when state transitions occur.

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 Figure 5: Gated SR Latch

En S R Previous Q Q (Next State) Q’ (Next State)

0 X X 0 0 1
0 X X 1 1 0
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 X 0 1
1 1 0 X 1 0
1 1 1 X Undefined Undefined

Table 3: Truth Table of Gated SR Latch

Key points
The **SR Latch** is the foundation of **sequential logic design**. It allows storing **one bit of
information** and has variations like: - **NOR-based SR Latch** (active-high inputs). - **NAND-
based SR Latch** (active-low inputs). - **Gated SR Latch** (controlled by an enable signal).
Despite its simple design, the **forbidden state** (S = R = 1 in NOR latch or S = R = 0 in
NAND latch) limits its practical use, leading to the development of **flip-flops** that ensure stable
and predictable outputs.