Technical Article

µModule Data Acquisition

Solution Eases
Engineering Challenges
for a Diverse Set of
Precision Applications
Maithil Pachchigar, System Applications Engineer

Data Acquisition System-Level Challenges R&D budgets and time to market (TTM) become challenging. Hardware designers
are demanding advanced precision data conversion performance and increased
System architects and circuit-level hardware designers spend significant research
robustness for complex designs in an ever-shrinking form factor amid thermal
and development (R&D) resources to develop high performance, discrete linear,
and printed circuit board (PCB) density limitations. Heterogeneous integration
and precision signal chain blocks for their end application (such as test and mea-
via system-in-package (SiP) technology continues to advance key trends within
surement, industrial automation, healthcare, or aerospace and defense) to measure
the electronics industry, including the move to higher density, increased func-
and protect, condition and acquire, or synthesize and drive. This article will focus
tionality, enhanced performance, and longer mean-time-to-failure. This article will
on a precision data acquisition subsystem, as shown in Figure 1.
illustrate how Analog Devices is leveraging heterogeneous integration to change
The electronic industry’s dynamics are rapidly evolving and there is less time to the precision conversion playing field and provide solutions that make a significant
build and prototype analog circuits to verify their functionality as the control of application impact.

AO0 Amp DAC

Channel
Protector

AOn Amp DAC

Power Management Power
Bus

FIFO
Fault
Voltage
Protected
Reference
Mux

Buffer
AI0
AI1 Sequencer Data Synchronization Data
PGIA ADC and Control Timing Interface
Isolation Bus
AIn
ADC
Driver

Data Acquisition Subsystem

On-Board
Memory
Triggers, Channel
GPIO Protector

Figure 1. High level data acquisition system block diagram.

VISIT ANALOG.COM
System designers face logistical challenges such as component selection and that, the gain error drift is also influenced by a choice of resistor type such as a
design optimization for final prototypes and technical challenges such as driving thin film, low temperature coefficient resistor, while sourcing matched resistors
the ADC inputs, protecting ADC inputs from overvoltage events, minimizing system is challenging amid cost and board space constraints.
power, and achieving higher system throughput with low power microcontrollers
In addition, the generation of odd, bipolar supplies is inconvenient for many
and/or digital isolators. With increased focus on system software and applications
designers due to the extra cost and real estate constraints on their PCBs.
to differentiate their system solution, OEMs are assigning more resources to soft-
Designers also need to carefully select the optimal passive components, including
ware development instead of hardware development. This is resulting in increased
an RC low-pass filter (which is placed between the ADC driver output and the ADC
pressure on hardware development to reduce design iterations.
inputs) as well as decoupling capacitor for the successive approximation register (SAR)
System designers developing data acquisition signal chains typically require ADC dynamic reference node. An RC filter helps limit the noise at the ADC inputs
high input impedance to allow direct interface with a variety of sensors, which and reduces the effect of kickbacks coming from the capacitive DAC input
could have varying common-mode voltages and unipolar or bipolar single-ended of a SAR ADC. The C0G or NP0 type capacitors and reasonable value of series
or differential input signals present. Let’s take a holistic view of the typical signal resistance should be chosen to keep the amplifier stable and limit its output
chain implemented using discrete components and understand some of the current. Finally, the PCB layout is extremely critical for preserving signal integrity
system designer’s major technical pain points with the illustration in Figure 2. and achieving the expected performance from the signal chain.
The key portion of the precision data acquisition subsystem is shown, where the
20 V p-p output of the instrumentation amplifier is applied to the noninverting Easing the Customer’s Design Journey
input of a fully differential amplifier (FDA). This FDA provides necessary signal Many system designers end up implementing different signal chain architecture
conditioning, including level shifting, attenuating the signal, and setting the output for the same applications. However, one size does not fit all, so Analog Devices, Inc.
swing between 0 V and 5 V with a 2.5 V common mode, opposite in phase, result- (ADI) has focused on common sections of signal chain, signal conditioning, and
ing in a 10 V p-p differential signal to the ADC inputs to maximize its dynamic digitization by providing more complete signal chain µModule® solutions with
range. The in-amp is powered with dual supplies of ±15 V, whereas the FDA advanced performance that bridge a gap between standard discrete components
is powered from +5 V/–1 V and the ADC is powered from a 5 V supply. The ratio and highly integrated customer specific ICs to solve their major pain points.
of feedback resistors (RF1 = RF2) to gain resistors (RG1 = RG2) sets the FDA gain of The ADAQ4003 is a SiP solution that provides the best balance between R&D cost
0.5. The noise gain (NG) of the FDA is defined as: and form factor reduction while accelerating time to prototypes.
2 The ADAQ4003 µModule precision data acquisition solution incorporates multiple
NG = (1)
(ß1 + ß2) common signal processing and conditioning blocks as well as critical passive
Where β1 and β2 are feedback factors: components laid out into a single device using ADI’s advanced SiP technology (see
Figure 5). The ADAQ4003 includes low noise, an FDA, a stable reference buffer, and
RG1 RG2
ß1 = and ß2 = (2) a high resolution 18-bit, 2 MSPS SAR ADC.
RG1 + RF1 RG2 + RF2
The ADAQ4003 simplifies the signal chain design and the development cycle of a
+15 V
+10 V precision measurement system by transferring component selection, optimization,
RG2 = 2R 3.33 V p-p RF2 = R
+5 V and layout from the designer to the device itself and solves all major issues discussed
In-Amp
1.67 VCM in the previous section. The precision resistor array around the FDA is built using
+5 V 0V 5V
+5 V
ADI’s proprietary iPassives® technology, which takes care of circuit imbalance,
−10 V +VREF
−15 V reduces parasitics, helps achieve superior gain matching up to 0.005%, and has
+2.5 VCM FDA ADC optimized drift performance (1 ppm/°C). The iPassives technology also offers a
-5 V size advantage compared with discrete passives, which minimizes temperature
-1 V
1.67 VCM +5 V 0V dependent error sources and reduces the system-level calibration burden. The
RG1 = 2R 3.33 V p-p RF1 = R
fast settling and wide common-mode input range of the FDA, along with precision
0V
performance for configurable gain options (0.45, 0.52, 0.9, 1, or 1.9), allow gain or
Figure 2. Simplified schematic of a typical data acquisition signal chain. attenuation adjustments as well as fully differential or single-ended-to-differential input.

This section will present how the circuit imbalance (that is, β1 ≠ β2) or mismatch The ADAQ4003 includes a single-pole RC filter between the ADC driver and the ADC,
in feedback and gain resistors (RG1, RG2, RF1, RF2) around the FDA influences key which has been designed to maximize settling time and input signal bandwidth.
specifications such as SNR, distortion, linearity, gain error, drift, and input All the necessary decoupling capacitors for the voltage reference node and power
common-mode rejection ratio. The differential output voltage of the FDA depends on supplies are also included to simplify bill of materials (BOM). The ADAQ4003 also
VOCM, so when feedback factors β1 and β2 are not equal, any imbalance in output houses a reference buffer configured in unity gain to optimally drive the dynamic
amplitude or phase produces an undesirable common-mode component in the input impedance of the SAR ADC reference node and the corresponding decou-
output, which is amplified by its noise gain and causes a redundant noise and pling capacitor. A 10 µF on the REF pin is a critical requirement to help replenish
offset in the differential output of the FDA. Therefore, it’s imperative that the the charge of an internal capacitive DAC during the bit decision process and vital
ratio of gain/feedback resistors matches well. In other words, the combination to achieving peak conversion performance. With the inclusion of the reference
of input source impedance and RG2 (RG1) should match (that is, β1 = β2) to avoid buffer, the user can implement a much lower power reference source than many
the signal distortion, mismatch in the common-mode voltage of each output traditional SAR ADC-based signal chains because the reference source drives a
signal, and prevent the increase in common-mode noise coming from the FDA. high impedance node instead of the dynamic load of the SAR capacitor array. The
One of the ways to counter-balance differential offset and avoid output distor- user has the flexibility to choose the reference buffer input voltage that matches
tion is to add an external resistor in series with a gain resistor (RG1). Not only the desired analog input range.

2 μMODULE DATA ACQUISITION SOLUTION EASES ENGINEERING CHALLENGES FOR A DIVERSE SET OF PRECISION APPLICATIONS
Small Form Factor Eases PCB Layout and on a separate power layer with as large of a trace as possible is especially crucial
Enables High Channel Density to provide low impedance paths and reduce the effects of glitches on the power
supply lines and avoid the EMI type issue.
The 7 mm × 7 mm BGA package of the ADAQ4003 offers at least a 4 times footprint
reduction compared to a traditional discrete signal chain (as shown in Figure 3),
enabling small form factor instruments without sacrificing performance.

4×
Reduction

Figure 4. An ADAQ4003 FFT with shorted inputs, with the performance unchanged before and
after removing the external decoupling capacitors for various rails.
Figure 3. Size comparison of the ADAQ4003 µModule device vs. a discrete signal chain solution.
Driving the ADAQ4003 Using a High
The printed circuit board layout is critical for preserving signal integrity and
Impedance PGIA
achieving the expected performance from the signal chain. The pinout of the
ADAQ4003 eases the layout and allows its analog signals on the left side and its As previously discussed, high input impedance front ends are typically required
digital signals on the right side. In other words, this allows the designers to to directly connect with various types of sensors. The majority of instrumenta-
keep the sensitive analog and digital sections separate and confined to certain tion and programmable gain instrumentation amplifiers (PGIAs) have single-
areas of the board and avoid crossover of digital and analog signals to mitigate ended outputs, which cannot directly drive the fully differential data acquisition
radiating noise. The ADAQ4003 incorporates all the necessary (low equivalent signal chain. However, the LTC6373 PGIA offers fully differential outputs, low
series resistance (ESR) and low equivalent series inductance (ESL)) decoupling noise, low distortion, and high bandwidth, which can directly drive the ADAQ4003
ceramic capacitors for the reference (REF) and power supply (VS+, VS−, VDD, and VIO) without sacrificing precision performance, making it suitable to many signal
pins. These capacitors provide a low impedance path to ground at high frequen- chain applications. The LTC6373 is dc-coupled on the input and the output with
cies to handle transient currents. programmable gain settings (using the A2, A1, and A0 pins).

There are no external decoupling capacitors required and, in the absence of In Figure 5, the LTC6373 is used in a differential input to differential output configu-
these capacitors, there is no known performance impact or any EMI issue. This ration and dual supplies of ±15 V. The LTC6373 can also be used in a single-ended
performance impact was verified on the ADAQ4003 evaluation board by removing input to differential output configuration if required. The LTC6373 directly drives
the external decoupling capacitors on the output of reference and LDO regulators the ADAQ4003 with its gain set as 0.454. The VOCM pin of the LTC6373 is connected
that generate the on-board rails (REF, VS+, VS−, VDD, and VIO). Figure 4 shows to ground and its outputs swing between −5.5 V and +5.5 V (opposite in phase).
that any spurs are buried well below −120 dB in the noise floor regardless of The FDA of the ADAQ4003 level shifts the outputs of the LTC6373 to match the
whether the external decoupling capacitors are used or removed. The ADAQ4003’s desired input common mode of the ADAQ4003 and provides the signal amplitude
small form factor enables the high channel density PCB layout while mitigating necessary to utilize the maximum 2 × VREF peak-to-peak differential signal
thermal challenges. However, the placement of individual components and rout- range of the ADC inside the ADAQ4003 μModule device. Figure 6 and Figure 7 show
ing of various signals on the PCB is crucial. The symmetrical routing of input and the SNR and THD performance using various gain settings of the LTC6373, while
output signals while keeping the power supply circuitry away from the analog signal path Figure 8 shows the INL/DNL performance of ±0.65 LSB/±0.25 LSB for the circuit
configuration shown in Figure 5.

VISIT ANALOG.COM 3
 VS+ = 5.5 V VREF = 5 V REF_OUT VDD = 1.8 V

ADAQ4003
(Gain = 0.454)
PD_REF
10 µF 2.2 µF
+15 V 0.1 µF 10 kΩ
VCMO
Used to 10 kΩ
+5.5 V OUT+ VIO
(+5.5 V)/G V+ Set G
R1K– 1 kΩ 0.1 μF
V+OUT
–5.5 V R1K1– 1 kΩ 33 Ω

A2
SDI

A1
(–5.5 V)/G

A10
– 1.1 kΩ +
IN– – 1 nF SCK
VOCM LTC6373 VCMO ADC Driver ADC
V-IN IN+ + SDO
(+5.5 V)/G 1.1 kΩ 1 nF
+ –
DGND CNV
+5.5 V 1 kΩ 33 Ω
V+IN CAP
(–5.5 V)/G R1K+ 1 kΩ
V –

–5.5 V OUT–
–15 V 0.1 µF
180 pF
VCMO PD_AMP MODE GND
ADCIN+ ADCIN–
VS– = GND

Figure 5. LTC6373 driving ADAQ4003 (gain = 0.454, 2 MSPS).

95
fIN = 1 kHz
fIN = 5 kHz
93 fIN = 10 kHz

91
SNR (dB)

89

87

85
0.5 1 2 4 8 16
PGIA Gain

Figure 6. SNR vs. the LTC6373 gain setting, with the LTC6373 driving the ADAQ4003
(gain = 0.454, 2 MSPS).

-92 Figure 8. INL/DNL performance, with the LTC6373 (gain = 1) driving the ADAQ4003
fIN = 1 kHz (gain = 0.454).
fIN = 5 kHz
-97 fIN = 10 kHz
ADAQ4003 µModule Application Use Case: ATE
-102 This section will focus on how the ADAQ4003 makes a great fit for source measure-
ment units (SMUs) and device power supplies (DPSs) for ATE. These modular instruments
THD (dB)

-107 are used to test a wide variety of chip types for the rapidly growing smartphone,
5G, automotive, and IoT markets. These precision instruments have a sink/source
-112 capability, which requires a control loop for each channel that takes care of
the programmed voltage and current regulation, and they demand high accuracy
-117 (especially fine linearity), speed, wide dynamic range (to measure µA/µV signal levels),
monotonicity, and a small form factor to accommodate the increased number
-122 of channels in parallel. The ADAQ4003 offers breakthrough precision performance,
0.5 1 2 4 8 16
LTC6373 Gain reduces the end system component count, and allows for improved channel density
Figure 7. THD vs. the LTC6373 gain setting, with the LTC6373 driving the ADAQ4003 amid board space constraints while easing their calibration burden and thermal
(gain = 0.454, 2 MSPS). challenges for these types of dc measurement scalable test instruments. The
ADAQ4003’s high precision combined with fast sampling rate reduces noise, and
no latency makes it ideal for control loop applications to provide an optimal step
response and fast settling to improve test efficiency. The ADAQ4003 helps ease

4 μMODULE DATA ACQUISITION SOLUTION EASES ENGINEERING CHALLENGES FOR A DIVERSE SET OF PRECISION APPLICATIONS
 Intergrated SMU_PMU_Subsystem

Driver
SP Setpoint I-V Amp
Isolated DAC Clamping
Power and HI
Compliance
CMP Compliance
Control
DAC
SP CMP
Host HI SNS
Control Logic FB FB
Microprocessor VREF Current Sense
In-Amp
Amp Guard
Data
Isolation I ADC
Guard SNS
ADC
Driver

V ADC LO SNS
ADC LO
Driver Voltage Sense
In-Amp
ADAQ4003

Figure 9. Source measurement unit simplified block diagram.

the design burden by eliminating buffers for distributing the reference voltage by a factor of 1024× at an output data rate of 1.953 kSPS, it offers an unbeatable
on instruments due to their own drift and for board space constraints. In addition, dynamic range of ~130 dB for a gain of 0.454 and 0.9, which can precisely detect
the drift performance and aging determine the accuracy of a test instrument, so very small amplitude µV signals. Figure 10 shows the dynamic range and SNR of
the deterministic drift of the ADAQ4003 reduces the cost of recalibration and the ADAQ4003 for various oversampling rates and input frequencies of 1 kHz and 10 kHz.
instrument’s downtime. The ADAQ4003 meets these requirements, pushes instru-
135
ments’ capability to measure lower voltage and current ranges, and helps them to Dynamic Range SNR: fIN = 1 kHz
G = 0.454
optimize their control loop for a variety of load conditions, which directly translate 130
G = 0.9
G = 0.9
G = 0.454
into an improvement in operating specifications, test efficiency, throughput, 125
G = 1.9 G = 1.9

and cost for the instruments. The high test throughput and shorter test times of SNR: fIN = 10 kHz
Dynamic Range, SNR (dB)

120
these instruments directly translate into a lower test cost for end users. The SMU G = 0.9
G = 0.454
high level block diagram is shown in Figure 9 and its corresponding signal chain is 115 G = 1.9

shown in Figure 5. 110

The high throughput rate enables oversampling of the ADAQ4003 to achieve the 105
lowest rms noise and detect small amplitude signals over the wide bandwidth.
100
Oversampling the ADAQ4003 by a factor of four provides one additional bit of
resolution ( this is only possible because the ADAQ4003 provides sufficient 95 G = Gain
DR = Dynamic Rate
linearity—see Figure 8) or a 6 dB increase in dynamic range—in other words, the 90
0 2 4 8 16 32 64 128 256 512 1024
DR improvement due to this oversampling is defined as: ΔDR = 10 × log10 (OSR) in Oversampling Rates (OSR)
dB. The ADAQ4003 typical dynamic range is 100 dB at 2 MSPS for a 5 V reference Figure 10. ADAQ4003 dynamic range, with SNR vs. the oversampling rate (OSR) for various
with its inputs shorted to ground. Therefore, when the ADAQ4003 is oversampled input frequencies.

VISIT ANALOG.COM 5
 Reduce PCB Reduce Mfg Improves Design Reduces/Removes
Assembly Cost Technical Support Reuse Efficiency Calibration

Signal Chain
µModule
Devices Reduce = + + +
Total Cost of
Ownership

Fewer Componants to More of Signal Chain Enables Platform Temperature Error

Pick and Place $/Comp Covered by Data Sheet Design Approach Phase Error
Reduced Setup Cost Improves Repeatability Gain Error
and Yield

Figure 11. Reduction in total cost of ownership using signal chain µModule technology.

Conclusion
This article presented a few key aspects and technical challenges associated with About the Author
designing precision data acquisition systems and how Analog Devices is leveraging Maithil Pachchigar is a system applications engineer in the Precision
its domain expertise in linear and converters to develop the highly differentiated Technology and Platforms Group at Analog Devices in Wilmington,
ADAQ4003 signal chain µModule solution to solve some of the toughest engineering Massachusetts. Since joining Analog Devices in 2010, he has been focused
problems. The ADAQ4003 eases engineering burdens such as component selec- on the precision converters portfolio and supporting customers in the
tion and building production-ready prototypes, while enabling system designers instrumentation, industrial, and healthcare segments. Having worked in
to deliver distinguished system solutions to their end customers faster. The the semiconductor industry since 2005, he has authored and co-authored
ADAQ4003 µModule device’s breakthrough precision performance combined with numerous technical articles. Maithil received his B.E. in electronics engi-
a small form factor adds greater value for a wide range of applications focused neering from S.V. National Institute of Technology, India in 2003, M.S.E.E.
on precision data conversion for applications as diverse as automated test equip- degree from San Jose State University in 2006, and M.B.A. from Silicon Valley
ment (SMU, DPS), electronic test and measurement (impedance measurement), University in 2010. He can be reached at [email protected].
healthcare (vital sign monitoring, diagnostics, imaging) and aerospace (aviation),
as well some industrial uses (machine automation input/output modules). μModule
solutions such as the ADAQ4003 significantly reduce the total cost of ownership for
system designers (as illustrated in Figure 11 in each of the areas) and reduce the Engage with the ADI technology experts in our online support community.
PCB assembly cost, increase manufacturing support by improving lot-to-lot yield, Ask your tough design questions, browse FAQs, or join a conversation.
enable design reuse for scalable/modular platforms, and simplify the calibration
burden in their end application, while accelerating their TTM.

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