1

EXPERIMENT NO. :11

MOD-10 RIPPLE(ASYNCHRONOUS) COUNTER

AIM:
To construct asynchronous(ripple) mod-10 counter using flip-flops.

OBJECTIVE:
• Students will study how to construct a MOD 10 ripple counter.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1

3. IC TRAINER KIT - 1

4. Connecting wires - as
required

PRINCIPLE:

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and
counting. Counters are generally made up of flip-flops and logic gates. Digital counters are
classified as sequential circuits. The main types of flip-flops used are J-K flip-flops or T flip-
flops, which are J-K flip-flops with both J and K inputs tied together.
Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or output of previous stage ie the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time
all flip flops are not activated at same time which results in asynchronous operation.
The modulus is the number of unique states through which the counter will sequence.
The maximum possible number of states of a counter is 2n where ‘n’ is the number of flip-
flops. Counters can be designed to have a number of states in their sequence that is less than
 2

the maximum of 2n . This type of sequence is called a truncated sequence. One common
modulus for counters with truncated sequences is 10 (Modules10). A decade counter with a
count sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state
sequence produces the BCD code. To obtain a truncated sequence, it is necessary to force the
counter to recycle before going through all of its possible states. A decade counter requires 4
flip-flops. If we take the modulo-16 ripple counter and modified it with additional logic gates
it can be made to give a decade (divide-by-10) counter output for use in standard decimal
counting and arithmetic circuits. Such counters are generally referred to as Decade Counters.
A decade counter requires resetting to zero when the output count reaches the decimal value
of 10, ie. when DCBA = 1010 . One way to make the counter recycle after the count of 9
(1001) is to decode the count ‘10’ (1010) with a NAND gate and connect the output of the
NAND gate to the clear (CLR) inputs of the flip-flops.
This type of asynchronous counter counts upwards on each leading edge of the input
clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs
Q1 and Q3 are now equal to logic "1" and the output from the NAND gate changes state from
logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs
of all the J-K Flip-flops. This causes all of the Q outputs to be reset back to binary "0000" on
the count of 10. Once QB and QD are both equal to logic "0" the output of the NAND gate
returns back to a logic level "1" and the counter restarts again from "0000". We now have a
decade or Modulo-10 counter.
Similarly we can construct a MOD-N ripple counter by clearing the selected flip flops
when it counts N. Students are advised to construct a MOD-12 or MOD-6 counter as an
extended experiment.

PIN DIAGRAM:
IC 7476:(Negative edge triggered Dual JK flpflop with active low PRESET and CLEAR
inputs)
 3

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

DESIGN:
Design procedure of Mod N asynchronous counter
Usually the count N may not be a power of 2.The general procedure for designing a ripple
counter is as follows.
• Find the number of flip flop ‘n’ such that 2n > N
• Connect the n flipflops as a ripple counter.
• Find the binary representation of N
• Put a NAND gate. Each input to the NAND gate is a flip flop output Q which
becomes 1 at the count N.
• The output of the NAND gate s connected to the clear pin of all the flip flops(because
clear input is active LOW in IC 7476)
Example. Design a Mod 10 ripple counter
Binary of decimal 10 is ‘1010’ ie output Q3 and Q1 are ‘1’.
Hence they are connected to the inputs of a NAND gate and the output of NAND is
connected to clear input of all flip flops.

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

 4

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per truth table.
3. Observe the output and verify the truth table.

RESULT:
A MOD 10 RIPPLE/ASYNCHRONOUS counter is constructed and verified the truth
table.

Inference :

1. Using Clear input we can reset a counter.

2. We can construct any MOD-N counter by clearing the appropriate flip flops.
3. Can construct Mod-N counter where N cannot be written as power of 2
eg Mod-3,Mod-5,Mod-7,Mod-9,Mod-11,Mod-13 etc
4. Student can construct a single circuit for Mod-N counter
 5

Experiment No. 12
SYNCHRONOUS COUNTERS
AIM:
To construct synchronous mod-8 counters using JK flipflops.
OBJECTIVES:
Students will get an idea about
• Understanding the operation and characteristics of synchronous counters
• Analyze counter circuits
• Determine the sequence of a counter
• Determine the modulus of a counter sequences
• Understand different applications of flip flops.
• Realize the frequency division of signals.
COMPONENTS AND EQUIPMENTS:
Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1

3. IC TRAINER KIT - 1

4. CONNECTING WIRES As required

THEORY:
A synchronous counter, in contrast to an asynchronous counter, is one whose output bits
change state simultaneously, in synchronous with the clock signal with no ripple. The”
clock" pulses are applied to all the flip-flops in counter simultaneously. Depending on the
way in which the counting progresses ,the synchronous and asynchronous counters are
classified into (i)up counters (ii)down counters(iii) up/down counters
A synchronous binary counter counts from 0 to 2n-1, where ‘n’ is the number of bits/flip-
flops in the counter. Each flip-flop is used to represent one bit. Modulus (MOD) is the
number of states it counts in a complete cycle before it goes back to the initial state.
Up Counter:
The binary output is taken from the Q outputs of the flip-flops. In FF0 the J and K inputs are
permanently wired to logic 1, so Q0 will change state (toggle) on each clock pulse. This
provides the ‘ones’ count for the least significant bit (LSB).
On FF1 the J1 and K1 inputs are both connected to Q0 so that FF1 output will only be in
toggle mode when Q0 is also at logic 1. As this only happens on alternate clock pulses,
Q1 will only toggle on even numbered clock pulses giving a ‘twos’ count on the Q1 output.
FF2 is put into toggle mode by making J2 and K2 logic 1,only whenQ0 and Q1 are at logic 1.
In the first flip-flop, J = K = 1 .In subsequent flipflops, J = K, but the logical value
is determined by an AND gate. Thus,J1=K1=Q0 and J2=K2 = Q1·Q0
 6

Down Counter
As every Q output on the JK flip-flops has its complement on , to convert the up counter
into the down counter, take the JK inputs for FF1 from the output of FF0 instead of the Q
output. The AND gate takes its inputs from the outputs of FF0 and FF1.
PROCEDURE:
1. Test all the ICs manually/ using IC tester.
2. Connections are made as in the logic circuit diagram and give VCC and the ground.
3. Connect the clock signal (<16Hz) input and output to LEDs.
4. Observe the count and verify the truth table.
DESIGN
A simple way of implementing the logic for each bit of an ascending counter is for each bit to
toggle when all of the less significant bits are at a logic high state. For example, bit 1 toggles
when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles
when bit 2, bit 1 and bit 0 are all high; and so on
A summary of steps used in the design of this counter follows. In general, these steps can be
applied to any sequential circuit:
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition, The
transition table is always the same for a given type of flip-flop.
4. Transfer the J & K states from the transition table to Karnaugh maps. There is a Karnaugh
map for each input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each flipflop
input.
6. Implement the expressions with combinational logic, and combine with the flip-flops to
create the counter

FUNCTION TABLE
3 bit (mod -8) synchronous up counter using JK flipflop

CLOCK Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8(recycles) 0 0 0
 7

CIRCUIT DIAGRAM:
3 bit (mod -8) synchronous up counter using JK flipflop

FUNCTION TABLE
3 bit (mod -8) synchronous down counter using JK flipflop

CLOCK Q2 Q1 Q0
pulse
Initially 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8(recycles) 1 1 1

3 bit (mod -8) synchronous down counter using JK flipflop

RESULT:
1. Studied 3 bit synchronous up counter .
2. Studied 3 bit synchronous down counter.
INFERENCE:
After studying this section, students should be able to:
 8

1. Understand the operation of synchronous counters. The count sequence is controlled using
logic gates.
2. Describe common control features used in synchronous counters such as Preset and Clear.
3. To count the number of times that a certain event takes place; the occurrence of event to be
counted is represented by the input signal to the counter
4. To control a fixed sequence of actions in a digital system
5. To generate timing signals
6. To generate clocks of different frequencies

Experiment No :13

JOHNSON COUNTER

AIM:
To construct a Johnson Counter and verify the truth table.

OBJECTIVE:
• To construct a Johnson counter.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. IC TRAINER KIT - 1
3. Connecting wires - as
required

PRINCIPLE:
A shift register counter is basically a shift register with the serial output connected back to
the serial input to produce special sequences. These devices are often classified as counters
because they exhibit a specified sequence of states. Two of the most common types of shift
register counters, the Johnson counter and the ring counter.
JohnsonCounter
The Johnson digital counter or Twisted Ring Counter is a synchronous shift register
with feedback from the inverted output ( ) of the last flip-flop. of the last flip flop is
connected back to the input D of the first flip-flop. This inversion of Q before it is fed back to
input D causes the counter to “count” in a special way. The main benefit of this type of
counter is that it only needs half the number of flip flops compared to that of standard ring
counter to represent many states. So an n-stage Johnson counter gives a sequence
 9

of 2n different states and can therefore be treated as a “Mod 2n counter” whereas an n-stage
ring counter has only n states that is “Mod n counter”.
It can be implemented using D-type flip-flops (or JK-type flip-flops). The output of each flip
flop is connected to the input of the next. The complementary output of the last flipflop is
connected to the first input.

In order to make Q1 high to begin, we should keep = 0 for a time period which is less

than the clock duration. After that keep = 1 for proper working.

PIN DIAGRAM AND INTERNAL LOGIC DIAGRAM OF IC 7474

LOGIC DIAGRAM FOR JOHNSON COUNTER

 10

TRUTH TABLE:

CLK QA QB QC QD
1 0 0 0 0
2 1 0 0 0
3 1 1 0 0
4 1 1 1 0
5 1 1 1 1
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1

PROCEDURE:

Connections are given as per circuit diagram.

(i) In the beginning, clear all flip flops using CLR input.

(ii) In order to make Q1 high to begin, we should keep = 0 for a time

period which is less than the clock duration. After that keep = 1 fo.r
proper working
(iii) Observe the output and verify the truth table.

RESULT:
Constructed a Johnson counter and the truth table is verified.
Inference :
1. Many beautiful patterns can be generated using Johnson counter.
2.
 11

Experiment No:114
RING COUNTER

AIM:
To construct a Ring Counter and verify the truth table.

OBJECTIVE:
• To construct a Ring counter.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. IC TRAINER KIT - 1
3. Connecting wires - as
required

PRINCIPLE:
A ring counter is formed by feeding the output of a shift register to its own input. Here the last
output ie. QD in a shift register is connected back to the serial input. The data pattern
enclosed within the shift register will re-circulate with respect to the clock pulse. Ring
counter is one of the shift register applications. A ring counter has N states where ‘N’ is the
number of flip-flops.

The synchronous Ring Counter is preset so that exactly one data bit in the register is
set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is
firstly applied to all the flip-flops together in order to “RESET” their outputs to a logic “0”
level and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before
the clock pulses are applied. This then places a single logic “1” value into the circuit of the
ring counter.
So on each successive clock pulse, the counter circulates the same data bit between
the four flip-flops over and over again around the “ring” every fourth clock cycle. But in
order to cycle the data correctly around the counter we must first “load” the counter with a
suitable data pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would
make the ring counter invalid.
 12

PIN DIAGRAM
IC 7474(positive edge triggered dual D flipflop with active LOW ,PRESET and CLEAR
inputs)

TRUTH TABLE:
Clock FFA FFB FFC FFD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0

LOGIC DIAGRAM

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at flipflop A, B, C and D respectively.

(i) 3. In the beginning, clear all flip flops using input by applying ‘0’ to all
clear inputs. After that, keep it at logic state ‘1’. In order to make Q A high to
 13

begin, we should keep of flipflop A at “ 0 “ for a time period which is

less than the clock duration. After that keep = 1 for proper working
For this,keep the mode input M = 1, apply one clock pulse. (<16Hz).

4. Now the mode M is made 0 and clock pulses are applied one by one and
the truth table is verified.

5.Observe the output and verify the truth table.

RESULT:

Constructed a Ring counter and the truth table is verified.

Inference :

1. Many beautiful patterns can be generated using Ring counter.