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Lan v3 1

The document provides detailed notes on the PCB layout and design for a circuit involving an ATtiny461A microcontroller. It includes specifications for power supply, I/O connections, analog comparator modules, and ADC configurations, along with soldering and coding instructions. Additionally, it references external resources for further technical information and guidelines.

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sarkcess099
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0% found this document useful (0 votes)
12 views1 page

Lan v3 1

The document provides detailed notes on the PCB layout and design for a circuit involving an ATtiny461A microcontroller. It includes specifications for power supply, I/O connections, analog comparator modules, and ADC configurations, along with soldering and coding instructions. Additionally, it references external resources for further technical information and guidelines.

Uploaded by

sarkcess099
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VBF

2 TP
TP TP
1 0V TP
VJ VJ VL VOUT
1%

2
2
1
1 SDA 0V VCQ3
VGM1 2
VBQ3 0V

3
1 1%
PCINT12
TP
0V 2
TP 0V
PB1
Power Switching TP
with ground debouncing capacitor
0V
and RC snubber (see notes 7 and 8).
0V 0V 0V
Parts not soldered to board
Jack Power Detect FET Driver ADC2 AIN1

PCB LAYOUT NOTES TP


OC1B
PWM IN Iled
1%
5%
See section 2.1 of AVR042 http://www.atmel.com/Images/doc2521.pdf (ADC3) ADC1 VBGND
See AVR040 Section 4.7: Current Loops and Signal Grounding
5V OUTPUT INPUT UNREGULATED IN
1%
Vbatt Ibatt

DESIGN NOTES
1%
(ADC9) ADC0
1. Download ATtiny461A datasheet here: http://www.atmel.com/Images/doc8197.pdf
5V 300uA min I_supply: 1%
2. ATtiny461 is shipped with the CKDIV8 fuse programmed so that I/O CLK is 1 MHz. 20uA min for the shunt regulator 0V
ADC4
GND
We should not need to change the I/O clock. But if we do, see Table 6-13. Any value between ~ 150uA min for the AREF pin
CLKPR = (1<<CLKPCE); 4.7k (I~500uA) and ~ 50uA min for pin AIN0 (1000 times
CLKPR = 0; 0V 0V 0V 8.2k (I~300uA) analog comparator I_in_leakage) VdegC
5V Channel Gain Signal
3. I2C (See section 13.3.4 Two-wire Mode) is for debugging: AREF
Regulated 5V Supply

VDD
Connect SCL (from Arduino) to USCK (AVRISP mkII header). 2.5V,1.5% ADC8-ADC9 x1 VdegC

2
Connect SDA (from Arduino) to MOSI (AVRISP mkII header). 3
1%
0V ADC4-ADC3 x1 Vbatt
4. Ideally, the programming header is shrouded and polarized: Mouser 517-30306-5002HB AIN0 ADC8 VOUT
but this is too expensive so we use Mouser 649-78548-406HLF. Vtrip=175mV ADC2-ADC1 x20 Iled

1
Inserting the programming header backwards is perfectly safe: ADC2 1%
the programmer blinks orange (instead of steady green) to indicate something is wrong. 0V ADC1-ADC0 x32 Ibatt

GND
(See section 18.6 Serial Programming) pin 3 is not connection to ADC2
PB0 (MOSI) MOSI Serial Data in internally is for trace routing
PB1 (MISO) MISO Serial Data out connected 0V 0V
ADC Differential Channels
PB2 (USCK) USCK Serial Clock in

5. PB7 (RESET)
Temperature Sensor
(See Table 10-6) The reset pin can only be used for external reset and debug. 2.5V Ref (for ADC)
The other functionality is not available without high-voltage programmng.
175mV Ref (for Comparator) Anti-Aliased, Double-Ended Feedback Signals to ADC Differential Input Channels
6. ANALOG COMPARATOR MODULE
(See Table 19-10)
Analog comparator input offset voltage is 10 to 40 mV.
General Notes:
PIN UTILIZATION
Analog comparator input leakage current is +/- 50nA.
SDA 1 20 ADC0
PB0 PA0
7. PA3 (AREF/PCINT3) 1. Board Dimensions: 2" x 2.3"
(see Fig. 20-42 of the ATtiny461/V [not A] datasheet). PB1 2 19 ADC1 PB0 is SDA (i2c), MOSI (programmer), and switch detect.
PB1 PA1
AREF draws 150uA for Vcc=5V. PB1 is LED enable and MISO (programmer). 2. Mounting holes are for #2-56, McMaster# 92949A082. Tighten with 0.05" hex drive,
SCL 3 18 ADC2 PB2 is SCL (i2c) and USCK (programmer) McMaster# 7122A13.
PB2 PA2
8. ADC MODULE
(See Table 19-8): OC1B 4
PB3 PA3
17 AREF PB3 is OC1B PWM output 3. Solder directly to jack, battery, and switch and
The input impedance at the AREF pin is 35 kohms. terminate with off-board connectors J2B, J3B, and J5B.
The input impedance at the analog input pins is 100 Mohms (when disconnected from S/H capacitor). PB4 is PCINT12 plug/power detect LED wiring is terminated with J4B for connection to
ADC input signals must be between 0V and AVCC. this board; connection to the daughterboard is J6B.
ADC differential signals must be between 0V and AREF. 5V 5 16 PB5 is ADC8 (the positive end of the VdegC analog signal)
VCC AGND
AREF must be between 2.0V and AVCC-1V. 0V PB6 is ADC9 (the negative end of the VdegC analog signal) 4. Fuse F1 is held by clips F1B and F1C. The microcontroller is held by socket U1B.
Bandwidth of differential signals must not exceed 4 kHz.
6 15 5V PB7 is RESET 5. I2C pull-up resistors are provided by connection from an Arduino to the SCL and SDA
GND AVCC
header pins on the 2x03. There is no circuitry required on the lantern PCB for
0V PA7 is AIN1 (analog comparator input from LED current sense signal) implementing I2C. The Arduino's internal pull-ups should be sufficient.
PA6 is AIN0 (analog comparator input from 175mV reference)

CODING NOTES
1. (See Table 15-1):
PCINT12

ADC8
7

8
PB4

PB5
PA4

PA5
14

13
ADC1 (ADC3)

ADC4
PA5 is ADC4 (the positive end of the Vbatt analog signal)
PA4 is ADC3 (the negative end of the Vbatt analog signal)
6. 1% tolerance is indicated where it is necessary. In general, all resistors on the BOM are
1% because there is no price difference between 1% and 5%.

First ADC conversion after ADMUX is updated takes 25 ADC clock cycles. PA3 is AREF (2.5V) 7. If substituted, R19 must be low inductance: either metal film or carbon composition.
Subsequent conversions (without changes to ADMUX) take 13 ADC clock cycles. (ADC9) ADC0 9 12 AIN0 PA2 is ADC2 (the positive end of the Iled analog signal
PB6 PA6
PA1 is ADC1 (the positive end of the Ibatt analog signal, 8. RC snubber values tested by PM on 2/15/2012 on Ghana 2010 design.
2. (See Section 15.11.2): RESET 10 11 AIN1 and the negative for the Iled analog signal)
PB7 PA7
ADC = Gain*1024*(Vp - Vn)/Vref PA0 is ADC0 (the negative end of the Ibatt analog signal)

3. Gain is 1x, 8x, 20x, or 32x.


(See Table 15.5 for differential channel and gain combinations) 5V

(See section 15.13.3 ADMUX Register) Channel selection is by


bits 4:0 of ADMUX and bit "MUX5" of ADCSRB.
Soldering Notes:
(See section 15.13.4 ADCSRB Register) PB1 1 2 5V
MISO VTG 1. Solder D3, R9, and R10 before M1.
"BIN"=0 for unipolar; "GSEL"=1 for x8/x32, =0 for x1/x20
SCL 3 4 SDA 2. Bend M1 (part number face down) before soldering.
USCK MOSI
RESET 5 6 3. Solder in groups to avoid clogged holes.
RESET GND
4. Parts RsBATT, R2, U4 are difficult to solder.
PM to add thermal pads.
0V 5. Don't mix up Q4 and U4.

10/16/23 14:03 f=0.65 /Users/tcumberbatch/Documents/SociaLite/Circuits/LAN_V3_1 Alberta/lan_v3_1.sch (Sheet: 1/1)

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