A

1
Basics of Microprocessor

Syllabus
Evolution of Microprocessor and types.
Silent features of 8085 Microprocessor, architecture of 8085 (Block diagram), register
organization, limitations of 8-bit Microprocessor.

Statistical Analysis

Year Marks Allotted to this Chapter

Summer 08 6 Marks

Winter 08 12 Marks

Summer 09 12 Marks

Winter 09 12 Marks

Summer 10 08 Marks
 Basics of Microprocessor
1-2
Microprocessor &Programming (MSBTE)

1.1 Evolution of Microprocessor and Types

suitable examples.
w 09
Q. Describe the evolution of microprocessor with
S 10
Q. Give evolution of microprocessor
the Intel Architecture [IA] can through the
be traced back
The developments lcading to

SOSS and S0s0 8-bit microprocessors to the 4004 4-bit microprocessor (the first
microprocessor. designed by Intel in 1969).197
the 8085 and 8080
The developments leading to the IA can be traced back through
Intel in
microprocessors to the 4004 microprocessor (the first microprocessor, designed by
1969).
However. he first actual processor in the 1A family is the 8086, quickly followed by a
more cost effective version for smaller systems, the 8088.
The object code programs created for these processors starting in 1978 will still execute on
the latest members of the IA family.

The8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving
a 1-MByte address space.
The 8088 is identical except for a smaller external
data bus of 8 bits.
These processors introduced IA
can act as
segmentation, but only in "Real Mode"; 16-bit registers
pointers address into segments of up to 64 KBytes in size.
to
The four segment
registers hold the(effectively) 20-bit base addresses of the currently
active segments: up to 256
KBytes can be addressed without
and a total address
range of I MByte is available.
switching between segments,
The Intel 80286
processor introduced the Protected Mode into the lA.
This new mode uses the segment register contents as
tables selectors or pointers into descriptor
The descriptors
provide 24-bit base addresses,
of up to 16
MBytes, support for virtual allowing maximum physical
a
basis, and various memory memory size
protection mechanisms. management on a segment
These include swapping
segment limit checking,
up to four
privilege levels to protect read-only and execute-only segment options, and
desired) from application or user operating system code (in several
Furthermore, hardware task programs. subdivisions, if
system to protect switching and the local
The Intel 386TM
application user or descriptor tables allow the
programs from each
operands for calculationsprocessor introduced 32-bit other. operating
and for addressing. registers into the
The lower half of
of the an
each 32-bit regi_ter retni architecture, for use both as
 Basics of Microprocessor
MCroprocessor &Programming (MSBTE) 1-3

A new vrtual-8086 mode was provided to vield greater efficiency when exceu
programs created for the 8086 and 8088 processors on the new 32-bit machine.
The 32-bit addressing was supported with an extemal 32-bit address bus, giving a GBy
address space. and also allowed each segment to be as large as 4 GBytes.
The ornginal mstructions were enhanced with new 32-bit operand and addressing torms
and completely new instructions were provided. including thosc for bit manipulation.
The Intel 386T processor also introduced paging into the lA. with the fixed 4-KByte page
size providing a method for virtual memory management that was significantly superior
compared to using segments for the purpose.
Furthermore, the ability to define segments as large as the 4 GBytes physical address
space. together with paging, allowed the creation of protected "lat model"t addressing
used
systems in the architecture, including complete implementations of the widely
mainframe operating system UNIX.
The Intel 486TM processor added more parallel execution capability by (basically)
into five
expanding the Intel 386"M processor's Instruction Decode and Execution Units too
pipelined stages, where each stage (when needed) operates in parallel with the others up
on

five instructions in different stages of execution.

An 8-Kbyte on-chip LI cache was added to the Intel 486TM processor to greatly increase
the percent of instructions that could execute at the scalar rate of one per clock.
math Unit
The Intel 486TM processor also for the first time integrated the floating-point
instructions to support more
onto the same chip as the CPU and added new pins, bits, and

complex and powerful systems (L2, cache support and multiprocessor support).
features designed to
Late in the Intel 486TM processor generation, Intel incorporated
support energy savings and other system management
capabilities into the lA mainstream
with the Intel 486TM SL Enhanced processors.
its own dedicated
The features include the new System Management Mode, triggered by
management features (such as power
interrupt pin, which allows complex system
within the PC).
management of various subsystems
features allow the CPU itself to execute at a
The Stop Clock and Auto Halt Power down
to be shut down (with state preserved) to save even
reduced clock rate to save power, or
more power.
achieve superscalar
The Intel Pentium® processor added
a second execution pipeline to
known as and v, together can execute two instructions per
performance (two pipelines, u
clock).
with 8 Kbytes devoted to code. and another
The on-chip LI cache has also been doubled,
8 Kbytes devoted to data.
efficient write-back mode. as well as the write-
The data cache uses to support the more
through mode that is used by the Intel 486TM processor.
 Basics of Microprocessor
1-4
Microprocessor & Programming (MSBTE)
increase performance in
has been added to
Branch prediction with an on-chip branch table
looping constructs.
efficient, and to allow
Extensions have been added to make the
virtual-8086 mode more

for 4-MByte as well as 4-KByte pages.

internal data paths of 128 and
256. bits have been
The main registers still
are 32 bits, but
has been
burstable external data bus
added to speed internal data transfers, and the
increased to 64 bits.
been added to support
The Advanced Programmable Interrupt Controller (APIC) has
new pins and a special
mode (dual
systems with multiple Pentium® processors, and
processing) has been designed in to support glue less two processor systems.
The Intel Pentium® Pro processor introduced Dynamic Execution.
It has a three-way superscalar architecture, which means that it can execute three
instructions per CPU clock.
The Pentium® Pro processor provides Dynamic Execution (micro-data flow analysis, out
of-order execution, superior branch prediction, and speculative execution) in a superscalar
implementation the power of the Pentium® Pro processor is further enhanced by its
caches.

t hasthe same two on-chip 8-KByte LI caches as does the Pentium® processor, and also
has a 256-KByte L2 cache that is in the same
package as, and closely coupled to, the CPU,
using a dedicated 64-bit ("backside") full clock speed bus.
The Pentium® Pro processor also has an
expanded 36-bit address bus, giving a maximum
physical address space of 64 GBytes effective version for smaller systems.
The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit
a
1-MByte address space. addressing giving
These processors introduced
segmentation, but only in "Real Mode": 16-bit
act as pointers to address into
segments of up to 64 KBytes in size. registers can
The four segment registers hold the
active segments; up to 256 KBytes can(effectively)
20-bit base addresses of the
be addressed without currently
and a total address range of 1
MByte is available. switching between segments,
A brief history
First microprocessor was developed by Intel in
Intel 4004 was a 4 bit 1971-4004
technology and microprocessor with 45 instructions
speed of 50 K instructions per second P Channel MOSFET
Later ( ENIAC).
microprocessor was 8008 as an 8 bit
8080 was 10x faster than 8008 and microprocessor then 8080 and Motorolla 6800.
TTL
MITS Altair Compatible (easy interfacing).
was developed 8800 in T974. The
Gates BASIC
Interpreter was written by B1l
 crOPI OCessor & Programming (MSBTE) Basics of Microprocesso
MICr 1-5

Assembler program written of

comp. o
was
by Digital Research Corporation (Author
Dr-DOS).
In 1977. Intel developed 8085 microprocessor with Internal clock generator, igher
frequency at reduced cost and integration.

There are 200 million 8085's around the world!.

In 1978 Intel was developed 8086+8088 microprocessors 16 bit and 20 bit address lines
which can addressed 1 M-Byte of memory, small instruction cache (4-6 bytes) enabled
pre-fetch of instructions.
IBM decided to use 8088 in PC.
In 1983 80286 released. identical to 8086 except the addressing and higher clock speed.
32 bit microprocessor era, in 1986 major overhaul on 80286 architecture 80386 DX with
32bit data +32 bit address (4 G bytes).
In 1989, Intel was developed 80486 = 80386 +80387co processor + 8KB cache.

In 1993. Pentium (80586) was introduced by Intel includes 2 execution engines.

Pentium Pro included 256K Level 2 cache mechanism as well as Level 1 cache.
Also 3 execution engines which can execute at the same time and can conflict and still
execute in parallel.
The address bus was expended to 36.
Pentium 2 included L2 cache on its circuit board (called slot).
Later Pentium 3 and 4 released with several architectural and technological innovations.

1.2 Silent Features of Intel 8085 Microprocessor

8 bit microprocessor, i.e. 8085 uP can read or write or perform arithmetic and logical
operations on 8 bit data at a time
transistors.
Single chip NMOS device implemented with 6200
Requires a single +5Volt power supply.
Provides on-chip clock generator, so 8085 gP does not require external clock generator,

require external tuned circuit like RC, LC crystal.

or
but
TTL clock.
Requires 2 phases, 50% duty cycle
On chip bus controller
modes.
Provides 74 instructions with five addressing
Maximum clock frequency is 3 MHz and minimum clock frequency is 500 KHz.
Provides 16 address line. so 8085 uP can access 2 = 64 Kbytes of memory.

Provides 5 level hardware interrupts and 8 software interrupts.

 Basics of Microprocessor
Microprocessor & Programming (MSBTE) 1-6

can be accessed.
Can generate 8 bit 1l/0 address, so 2= 256 input and 256 output port
Provide two serial 1/0 lines, so serial peripheral can be interfaced directly with 8085 uP.

1.3 Pin Diagram and Description

Q. List maskable and non-maskable interrupts of 8085 microprocessor. W-08

The 8085 is implemented in 40 pin Dual Inline Package [DIP] shown in Fig. 1.1.

(a) ADo-AD: Multiplexed Address/Data Bus

These are 8 bit bidirectional tri-state pins to carry address as well as data in time
shared mode.
The lower order 8 bit address signals are multiplexed with data bus.
In earlier clock cycle of machine cycle, these lines carry lower order 8 bit address of
16 bit address and in later clock cycle, these lines cany 8 bit data.

EVoc
39 HOLD
RESET OUT 3 88 HLDA
37 CLK(OUT)
38 RESET N
TRAP 6 55 READY
S o 31701 to
RST7.5 B10M
RSTS.5
RSTS.5
INTR
10 8085 61 WA
CPU
NTA 30 ALE
AD
AD13 28 A15
AD21 2 A4
AD3 25 A3
AD 18
25 A12
AD 24 A1
AD 23 A1o
AD,13
GND 23 A
Fig. 1.1: Pin
diagram of 8085
(b) Ag-As: Address Bus
These are 8 bit output, tri-state signals used
16 bit address. to
cary higher order address signals or
These are non
multiplexed unidirectional tri-state
address line.
MIcroprocessor &Programming (MSBTE) 1-7 Basics of Microprocessor

Ic) ALE Address Latch Enable

ALCL
This is an
output signal used to inform that the
order 8 bit address of 16 bit address when ALE
content on AD -AD; lines iS lOwet

goes high. dot

When ALE is low, it indicates the AL
content onAD -AD, lines is 8 bit data.
ALE signal is used to address
separate signals from the data signals i.e. AurA7 and
Do-D, from ADg-AD;.

(d0/M: Input Output/ Memory:

This is an output status signal use to give the status of operation performed with
memory or /o by microprocessor.

When
J/o devico
1O/M, is low, themicroprocessor is performing operation related to memory
and when 1O/M is high, the microprocessor is performing operaiion related to /0
device.
(e S and So : Status signals
These are output status signals used to give the status of operation perfermed by the
microprocessor
These generally used in
are not small system, but be used
can to generateyadvance
control signals for large system.
These signals specify four different conditions as given Table 1.1.
Table 1.1

8085 Machine Cycle Status

IO/M S So Status Control Signal Used
0 Op-code fetch
RD low
0 Memory Read RD low
0 0 1 Memory Write
WR low
0 1/O Read
RD low
1 0 1/O Write
WR-low
1 1 Interrupt Acknowledge INTA low
Z Halt
Z
RD and WR High Impedance
X X Hold INTA = High
Z X X Reset
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Microprocessor &Programming (MSBTE)

( RD:Read
This is an active low output control signal used to read data from memory or l/0 device

generated by the microprocessor.

(g) WR:Write
This is an active low output control signal used to write data to memory or VO device
generated by the microprocessor.
(h) READY
This is an active high input control signal and used by the microprocessor to check
whether a peripheral is ready or not for data transfer.
If READY pin is high, then the_microprocessor
completes the operation and
proceeds for next operation. READY1 ) Teady to qive enNes o p e r .
READY= o h e y pesfo there otd eper
When READY pin is low, the microproces[or will wait until it goes high.
This is signal is used to synchronize slower peripheral with faster processor.
() TRAP
This is an active high, edge & level triggered, non maskable highest priority
interrupt.
When TRAP occurs, then
microprocessor start execution from 0024H automatically.
) RST 7.5, RST 6.5, RST 5.5: Restart
Interrupts:
These are active high, maskable
6.5 and RST 5.5 are interrupts. RST 7.5 is edge triggered interrupt. RST
level triggered interrupts.
When RST 7.5, RST 6.5 and
RST 5.5 occurs, then
the
program control to vector address
003CH, 0034H and 002C microprocessor transfet
(k) INTR and INTA :
respectively.
Interrupt request and acknowledge
INTR is an active
high,
level triggered general purpose interrupt.
When INTR occurs, the
T
INTA.
microprocessor generate interrupt
acknowledge signa
Using INTA, a CALL instruction
tothe interrupt service
routine.
along with vector address can be inserted to Jump
HOLD and HLDA
HOLD is an active high
input
signal used by the other
microprocessor gaining the control
for
of master controller to uest
When address, data requ
currentmicroprocessor receives HOLD and control buses.
machine cycle 1.e. request signal, then
system. operation and release bus microprocessor s
control for other compi
master in
 Aicroprocessor & Programming (MSBTE)
1-9 Basics of Microprocessor
Microprocessor also generates HLDA
signal
receiving HOLD signal.
to acknowledge requesting device ater

(m) RESET IN: Reset input

This is an active low input reset signal used to reset
When this microprocessor.
signal
is received
by the
counter i.e. 0000 and makes microprocessor, microprocessor clears progranm
execution from memory location 0000H address, data and
control lines tri-stated and start
onwards.
After reset the status
of internal registers and flags are
unpredictable.
(n) RESET OUT: Reset output:
This is active high output
signal generated by the
signal and used as a system to reset other devices inmicroprocessor after
the system.
receiving RESET

(o) SID and SOD Serial input data and serial

SID and SOD
output data
active high input and output serial
are an
port pins respectively.
SID pin is used to accept one bit data
under the software control.
When RIM instruction is executed, the SID
pin data is loaded at D; position of
accumulator
When SIM instruction is executed, the SOD
status of D; and D, bits of the accumulator.
pin is set or reset
depending on the

(P) X, and Xa

These are clock input pins, connected to the crystal, LC or RC circuit. k 3

The crystal frequency is divided by two and used as operating frequency.
(g) CLK OUT
This an output clock signal and used as a system clock.
The internal operating frequency is available this
on pin and used to
operate other
devices in the system with same speed.

1.4 Architecture of Intel 8085 [Block Diagram]

Q. State the function of the
program counter and stack pointer of 8085.
QState the function of following of 8085 S-08, S-09
)Accumulator i) Temp. Register () Flag S-08
Register (iv) ALU
.Describe the function of the following block of 8085.
() ALU i) Timing and Control Unit (i) Instruction decoder
State the function of program counter and stack W-08, S-09
pointer of 8085. S-09
Q.Draw neat labeled architecture
of 8085 indicating different signals of all the blocks. W-09
 BasicsS or MIcropre

1-10
MiCroprooessor& Programming (MSBTE)
them into 8 bit and 16 bit registers. W-09
LiSt al registers of 8085 microprocessor and categories
the function of
instruction register,
Draw the block diagram of 8085 microprocessor. Explain S-10
program counter and stack pointer

INTA RST65 TRAP

SID SOD
INTR RSTS 5 RST7 5
Serial Vo
Interrupt Control Control

8 blt Internal date bus

W8) (8)
Instruction
Acoumulator Temporary Flag Temp. reg Temp.reeg
(8) register (8 Flip-Flop (8) Register (8) B
reg.(8) reg.(8)
D E
reg. (8) reg.(8)
Instruction H register
Anthmetic reg. (8) array
ogic decoder and reg. (8)
unit machine Stack Pointer (16)
(ALU) cycle
(8) Encoding9 Program Counter (16)
Incremented/ decrementer
address
latoh (16)
Power+5V-

Supply 1GND- Timing and Control

Address Address/ Data
GIK
buffer (8) buffer (8)
Gen Control Status DMA Reset
Cik Out RD WA ALe So S, l0/M |HLDA Reset out
Ready Reset in
As A15 AD7-ADo
Hold Address bus Address / Data bus

Fig. 1.2: Block diagram of 8085 microprocessor

The architecture of the Intel 8085 is shown in
different group as given as follows
Fig.1.2. This architecture is divided in
(a) Arithmetic and logical group.
(b) Register group.
(c) Interupt control group. (d) Serial /O group.
(e) Instruction register, decode, timing and control group.
1.4.1 Arithmetic and
Logical Group
This group consists of ALU,
accumulator, temporary register and
(a) Arithmetic and logical unit flag register.
The 8 bit ALU
perform arithmetic operations such as
logical operation such as ANDing,
ORing and XORing etc.addition, subtraction, an
on 8 bit data at a
It takes operand from the 8
bit time.
temporary register and 8 bit
accumulator.
Microprocessor &Programming (MSBTE) 1-11 Basics of Microprocessor

After
performing operation. the result is placed in accumulator only.
(b) Accumulator
he accumulator is 8 bit general_purpose register and one of the two operands
registers for ALU.
It is also called
as A register and available for the user to store data temporarily
After performing operation, ALU
places result in accumulator.
Accumulator is one default operand register out of two operands where another
operand may be in another register or memory.
(c) Temporary register
This is 8 bittemporary register and not available for the user.
It is used in accumulator based instruction to store second
operand temporarily.
In arithmetic
operation, one operand is taken from accumulator and second,from
temporary register.
(d) Flag register
The ALU includes five flip-flops, which are set or reset after an operation according
to the conditions of the result in the accumulator and other registers.
They are called Zero(Z). Carry (CY). Sign (S). Parity (P). and Auxiliary Carry (AC)
flags.
It is an 8 bit register and not available for the user. It provides status of the resultof
different operation performed by the ALU.
The flag register is connected to ALU.
So, this register will get affected only when microprocessor perform arithmetic or
logical operations. The flag register consists of flip flop and output of the flip flop is
not available outside the microprocessor.
The state of the flip flop can only be transferred to stack and then can be loaded in
general purpose register from the stack.
The different flags and their position in the flag register i.e. format in Fig. 1.3.
DD DsDDDDDo

Carry flag
Parity flag
Auxliary carry flag
Zero flag
Sign flag
Fig. 1.3: Format of flag register of 8085 register
 Microprocessor& Programming (MSBTE) 1-12
Basics of Microprocessor

CY Carry flag

fS e t operation
an
to
performed in ALU generates carry from D, bit to next stage. the Y flag
a
which acts as 9th bit of result of addition and barrow flag for the subtraction.

T there is no carry/barrow out of the most significant bit D, of the result, then the CY flag

is reset.
P:Parity flag:
nis bit Is used to indicate parity of the result. If the result contains even numbers of one s,

this flag is set to 1.

If the result contains odd numbers of the one's, then this flag is reset to 0.
AC Auxiliary camy flag:
lf an operation performed in the ALU generates a carry from D3 to D4 then AC flag is set
toI else reset to 0 i.e. carryy generated from lower nibble to higher nibble.
This is not a general purpose flag, it is used only by the microprocessor to perform binary
to BCD conversion.
Z:Zero fiag:
If the result of the operation performed by the ALU is 0, then z flag is set to I else reset 0.
When this flag is set, then result i.e. the content of A register is O.
S: Sign flag
In sign magnitude number, the sign of the number is indicated by most significant bit D,
of 8 bit number.
The sign flag is a copy of the D, bit to indicate that result of operation performed by the
ALU is negative.
So, when result is negative this flag will be set to 1 else reset to 0 for positive result.

1.4.2 Register Group:

This group consists of three types of the registers
(a) Temporary register
(b)
(b) General purpose registers
(C) Special purpose registers
(a) Temporary register: 2
The 8085 microprocessor provides two 8 bit
available for the user. temporary registers i.e. W & Z and not

They are used by the

microprocessor itself for internal
operand, immediate operand or address of the memory. operation such as to store
T General purpose registers:
The 8085 provides 6 general purpose register of 8 bit each
i.e. B, C, D, E, H and L.
Microprocessor &Programming (MSBTE) 1-13
Basics of Microprocessor

Ihese register are available for the user and can be used to store 8 bit data or can De
used to fom a register pair such BC, DE, HL to store 16 bit data.
(c) Special purpose registers:
The 8085 has three special purpose registers i.e. program counter PC, stack pointer SP an
increment/decrement latch.
Program counter PC: A
It is a 16 bit register used to sequencing of the execution of the program.
This register always point to the memory location from which the next instruction 1s to be
fetched and executed.
When the microprocessor performs the operation of fetching instruction, the PC contents
isautomatically incremented by one to point next instruction.
So. program counter keeps track for execution of the program,
On reset, the program counter is loaded with 00001H and start execution of the program
from the address 0000H onwards.
Stack pointer SP omaL

It is a 16 bit register usedto address stack location.

Stack is user definereserved pertionof memory where data can be stored temporarily.
SP always points current top of stack.
Increment & decrement latch:
It is a 16 bit register to increment or decrement the contents of program counter and stack
pointer register.
1.4.3 Interrupt Control Group/ havdwa ve intesaups ecoy cdd w

OThis block accepts different interrupt request input such as TRAP, RST 7.5, RST 6.5,
RST 5.5, INTR and INTA.
When valid interrupt request is present, it informs to control logic to take action to each
signal.
In response to TRAP, RST 7.5. RST 6.5 and RST 5.5, program control is transferred to
corresponding vector address.
But for INTR, it generates INTA signal to acknowledge the same and expects that the
external device should send op-code_of CALL instruction along with vector address, so
that the program control can be transferTred and action can be taken for the interrupt
request.
1.4.4 Serial VO Control GroupP:

The serial data transfer is implemented in 8085 by using SID and SOD pins. The data can
be accepted from SID pin or the data can be transferred on SOD pin under software
control by serial IQcontrol block.
 Basics of MicroprOcessor
Microprocessor &
Programming (MsBTE) 1-14
in instruction set of 8085 i.e
petorm serial data transfer. two instructions are provided
RIM and SIM.
1.4.5 Instruction Register, Decoder and Control Group:

Instruction register IR
temporarily i.e. latest
t i s 8 bit registerused to store the current instruction of a program
Sruction sent here from memory prior to exccution
and not available for the user.
When microprocessor read op-code from the memory, it is loaded in the instruction

register and then transfer to decoder for decoding.

Instruction decoder ID
It accepts an op-code of the instruction from the instruction register, decode it and give

information the control logic.

to
The information include what operation is to be performed, who is going to performed
how many operand bytes the instruction has etc.

Timing and control unit

It accepts information from the instruction decoder and generates different control signals.
This block accepts clock input to perform sequencing and synchronizing operation by
ste
generating different status and control signals.

1.5 8085 System Bus

Typical system uses a number of buses, collection of wires, which transmit binary
numbers, one bit per wire.
A typical microprocessor communicates with memory and other devices (input and
output) using three buses i.e. Address Bus, Data Bus and Control Bus.

Address bus:/ 1 brts

One wire for each bit, therefore 16 bits 16 wires. Binary number carried alerts
=

to 'open the designated box of memory. Data

memory
(binary) can then be in
put or taken out.
The Address Bus consists of 16 wires; therefore its "width" is 16
bits.
A 16 bit binary number allows 2 different numbers, or 64K different numbers, 1.e.
0000000000000000 up to 1111111111111111.
Because memory consists of location of 8 bit each. each
with a unique address. the size of
the address bus determines the size of memory, which
can be used.
To communicate with memory the
microprocessor sends an address on the address bus,
e.g. 0000000000000011 (3 im decimal). to the
memory.
The memory selects location number 5 tor
reading or writing data,
Address bus is unidirectional, 1.e. numbers only sent from
other way. microprocessor to memory. Do
 Basics of Microproces
sor
Mirroproressor & Programiming (MSBTE) 1-15
Date bus

Data bus carries data'. in binary form, between uP and other external units, Su h
memory or peripherals
S1ze determined by size of location in memory and data bus size helps determine
performance of microprocessor.
The Data bus typically consists of 8 wires and it isbi-directional.
Therefore. 2" combinations of binary digits are
possible.
. D a t a bus is used to transmit "data", i.e. information, results of arithmetic, etc, between
memory and the microprocessor.
Therefore, larger number has to be broken down into chunks of 255, this slows
microprocessor
Data bus also carries instructions from memory to the microprocessor.
Size of the bus therefore limits the number of possible instructions to 256, each specifñed
by a separate number.
Control bus:
Control bus has various lines which have specific functions for coordinating and
controlling microprocessor operations e.g. Read/Not Write line; single binarydigit
Microprocessor can not function correctly without these vitalcontrol signals.
The Control bus carries control signals partly unidirectional, partly bi-directional and
control signals are things like "read or write"
This tells memory that the microprocessor is reading data from a location, specified on the
address bus, or writing to a location specified on the address bus.
Various other signals control and coordinate the operation of the system.

-
1.6 Demultiplexing of ADo-AD, of 8085

QExplain de-multiplexing of address and data bus? Which signal is used to de-multiplex the
address/data bus with reference to 8085 microprocessor W-08
In the 8085 microprocessor, the higher order address lines i.e Ag-As are directlyy
available, but the lower order address lines are multiplexed with data busintime sharing,

Hence, the de-multiplexing of address/data bus is required i.e. separation of address and
data bus.
I n earlier clock cycle state of every machine cycle, the contents on AD,-AD, is the lower
order address i.e. A-Ay and at the same time, the ALE also goes high for half of T, state.
Later clock cycle state, the 8085 remove the contents of AD-AD, lines and use same lines
as a data lines [data bus] for next clock cycle state onwards.
 Microprocessor &
Programming (MSTE) -16 Basics of Microprocessor

Hence, the de-multiplexing of address/data bus

can be implemented by using tri-state octal latch
74LS373 and this latch can be controlled by ALE G
using ALE signal of 8085 as shown in following Latch
Fig. 1.4. ADo-AD 74373 AA
When ALE goes high, the address will
signals
be latched in the octal latch 74LS373 and 8085
output Microprocessor
of the latch will be provided on Ag-A7.
When ALE goes low, the latch will be disabled
Do-D7
and the AD,-AD, be used data bus
can as D,-D.
Fig.1.4 De-multiplexng of AD,-AD,

1.7 Limitation of 8 bit Microprocessor

Q. State the limitations of 8085
microprocessor S-09
As we have studied 8 bit microprocessor i.e. Intel 8085, following limitation can be discussed.
In 8 bit microprocessor, microprocessor can perform any arithmetic or logical operation
only on 8 bit data at a time. For multi-byte numbers, microprocessor takes more time, as
ALU is 8 bit.
Due to the 16 address lines, we can address
only up to 64kbyte of memory, so we can not
use Intel 8085 in IBM Standard PC.
Because, in IBM architecture standard, minimum
640kbyte of memory is required.
8085 has multiplexed address and data bus, so extra hardware is
address signals from the data signals. It is required to separate
the
required compulsorily, because other device in
microprocessor based system have separate address lines and data lines.
8085 reads one instruction time. Unless first instruction
at a
gets executed completely,
microprocessor can not read second instruction from memory as 8085 has
instruction register. So, pipelining of the instruction only one
execution can not be achieved:
Flag register has limited flags. There is no
condition of result of arithmetic operation on flag in flag register to indicate overflow
signed magnitude numbers. In
magnitude number, most significant bit is sign bit. signed
Interrupts are very limited in 8085. Normally in
interrupts are required to perform large microprocessor based system, more
data transfer between
in interrupt driven I/O. I/O peripheral and microprocessor
.

Operating frequency is less, so the speed of execution is

slow,.
While reading or writing 16 bit or more
bytes of data from the
microprocessor needs more operation [machine] memory or 1/O device, the
cycles. So, data transfer speed is slow.
Using 8085, we can not design multi-processor
system.
 Basics of Microprocessor
Microprocessor &Programming (MSBTE) 1-17

Due to limited 8 bit size of the all register, we can store limited data bytes in n c

microprocessor memory.
There is no
memory management unit.
Only 256 input and 256 output devices can be interface with 8085, as I/0 address is 8 bit.

Review Questions

Q. 1 Describe the function of following blocks of 8085. (8 Marks)

a) General purpose register (Section 1.4.2)
b) ALU (Section 1.4.1)
c) Timing and control unit (Section 1.4.5)
d) Instruction decoder and machine cycle encoding. (Section 1.4.5)
Q.2 What is de-multiplexing of the address and data bus? Which signal is used to de-multiplex the
address and data bus. (Section 1.3) (4 Marks)
Q.3 State the vector addresses of all hardware interrupts of 8085 microprocessor.
(4 Marks)
(Section 1.3)
Q.4 Draw the format of the flag register of 8085 microprocessor and describe the condition which
set and reset these flags. (Section 1.4.1(d)) (8 Marks)
Q.5 Describe INTR interrupt. (Section 1.3(k)) (4 Marks)
Q.6 List maskable and non-maskable interrupts of 8085 microprocessor.
(4 Marks)
(Sections 1.3(i) and G))
Q.7 Explain why (4 Marks)
a) 8085 microprocessor is 8 bit CPU ? (Section 1.7)
b) Memory capacity of 8085 microprocessor is 64K bytes ? (Section 1.7)
c)RESET IN signal is essential for microprocessor ? (Section 1.3(m))
d) First instruction is executed after rest operation from the memory location 0000H?

(Section 1.3)
Q.8 Draw the flag register format and explain in brief various flags related to 8085.
(4 Marks)
(Section 1.4.1(d))
Q.9 Describe TRAP interrupt. (Section 1.3(i)) (4 Marks)
Q. 10 Draw the neat labeled architecture of 8085
indicating different signals of the all the blocks.
(Section 1.4) (8 Marks)
Q.11 Describe the function of SID and SOD
pins of 8085 microprocessor. (Section 1.3) (4 Marks)
Q.12 List all registers of the 8085 microprocessor and categorize them into 8 bit and 16 bit registers.
(Section 1.4) (4 Marks)
Q.13 State the function of RESET IN and READY pins of 8085 microprocessor.
(Section 1.3) (4 Marks)
Microprocessor & Programming (MSBTE) 1-18
aasics of Microprocessor
1.8 MSBTE Questions and Answers

Summer 2008 Total Marks 06

Q.1 State the function of the program counter and stack pointer of 8085. (Section 1.4)
(2 Marks)
Q.2 State the function of following of 8085 (Section 1.4) 4 Marks)
) Accumulator ) Temp. Register
(ii) Flag Register (iv) ALU

Winter 2008 Total Marks 12

Q. 3 List maskable and non-maskable interrupts of 8085 microprocessor. (Section 1.3) (2 Marks)
Q.4 Describe the function of the following block of 8085.
0 ALU )Timing and Control Unit (ii) Instruction decoder (Section 1.4) (6 Marks
Q.5 Explain de-multiplexing of address and data bus? Which signal is used to de-mutiplex the
address/data bus with reference to 8085 microprocessor ? (Section 1.6)
(4Marks)
Summer 2009 Total Marks 12
Q. 6 State limitations of 8085 microprocessor. (Section 1.7) (2 Marke)
Q.7 Statethe function offollowing biocks in 8085 microprocessor
ALU ) Timing and Control Unit (i) Instruction decoder (Section 1.4) (6 Marks)
Q. 8 State the function of the program counter and stack pointer of 8085. (Section 1.4) (4 Marks)

Winter 2009 - Total Marks 12

Q9 Describe evolution of microprocessor with suitable examples. (Section 1.1) (2 Marks)

Q.10 Draw neat labeled architecture of 8085 indicating different signals of all the blocks.
(Section 1.4) (6 Marks)
Q.11 List all registers of 8085 microprocessor and categories them into 8 bit and 16 bit
registers.
(Section 1.4) (4 Marks)

Summer 2010 - Total Marks 08

Q. 12 Give evolution of microprocessor. (Section 1.1) (2 Marks)

o.13 Draw the block diagram of 8085 microprocessor. Explain er

the function of instruction reg
program counter and stack pointer. (Section 1.4) (6 Marks)