Microprocessor (8085) And Its Applications 2.

11

2.4 INSTRUCTION FORMAT OF 8085

The 8085 has 74 basic instructions and 246 total instructions. The instruction set of 8085 is
defined by the manufacturer INTEL Corporation. Each instruction of 8085 has one-byte opcode.
With 8-bit binary code, we can generate 256 different binary codes. In this, 246 codes have been
used for opcodes of 8085 instructions.
The size of 8085 instruction can be one-byte, two bytes or three bytes. The one-byte instruction
has an opcode alone and the two-byte instruction has an opcode followed by an eight bit address or
data. The three-byte instruction has an opcode followed by 16-bit address or data. While storing
the three-byte instruction in memory, the sequence of storage is, opcode first followed by low byte
of address or data and then high byte of address or data. The format of 8085 instructions are
shown in Fig. 2.11.
7 6 5 4 3 2 1 0
One-byte instruction : opcode

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Two-byte instruction : opcode 8-bit data/address

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Three-byte instruction : opcode low byte data/address high byte data/address

Fig. 2.11 : Format of 8085 instructions.

2.5 ADDRESSING MODES

Every instruction of a program has to operate on a data. The method of specifying the
data to be operated by the instruction is called Addressing. The 8085 supports the following five
addressing modes:
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

Immediate Addressing

In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction .
Example : MVI B, 3EH
Move the data 3EH given in the instruction to B-register.
Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this
addressing mode, the program instructions and data can be stored in different memory blocks.
Example : LDA 1050H
Load the data available in memory location 1050H in accumulator.
2. 12 Chapter 2 Instruction Set Of 8085

Register Addressing
In register addressing mode, the instruction specifies the name of the register in which the data is available.
Example : MOV A, B
Move the content of B-register to A-register.
Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register in which the address of the
data is available. Here the data will be in memory and the address will be in a register pair.
Example : MOV A, M
The memory data addressed by HL pair is moved to A-register.
Implied Addressing
In implied addressing mode, the instruction itself specifies the data to be operated.
Example : CMA

Complement the content of accumulator.

2.6 INSTRUCTION SET

The 8085 instructions can be classified into the following five functional groups.
Group I - Data Transfer Instructions : Includes the instructions that moves (copies)
data between registers or between memory location and register. In all data
transfer operations, the content of source register or memory is not altered.
Hence the data transfer is copying operation.
Group II - Arithmetic Instructions : Includes the instructions which performs addition,
subtraction, increment or decrement operations. The flag conditions are altered
after execution of an instruction in this group.
Group III - Logical Instructions : The instructions which performs the logical operations
like AND, OR, EXCLUSIVE-OR, complement, compare and rotate instructions
are grouped under this heading. The flag conditions are altered after execution
of an instruction in this group.

Group IV - Branching Instructions : The instructions that are used to transfer the
program control from one memory location to another memory location are
grouped under this heading.

Group V - Machine Control instructions : Includes the instructions related to interrupts

and the instruction used to halt program execution.
The 74 basic instructions of 8085 are listed in Table-2.1. The opcode of each instruction,
size, machine cycles, number of T-state and the total number of instructions in each type are also
shown in Table-2.1. The instructions affecting the status flag are listed in Table-2.2.
Microprocessor (8085) And Its Applications 2. 13

TABLE - 2.1 : SUMMARY OF 8085 INSTRUCTION SET

S.No. Mnemonic Opcode No.of Machine No.of Total no. of

bytes cycles T states instructions

Group I : Data transfer instructions

1. MOV Rd, Rs 0 1 DD D SS S 1 F 4T 49

2. MOV Rd, M 0 1 DD D 1 1 0 1 F, R 7T 7

3. MOV M, Rs 0 1 1 1 0 SSS 1 F, W 7T 7

4. MVI Rd, d8 0 0 DD D 1 1 0 2 F, R 7T 7

5. MVI M, d8 00 11 0 11 0 2 F, R, W 10T 1

6. LDA addr16 00 11 1 01 0 3 F, R, R, R 13T 1

7. LDAX rp 0 0 RP 1 0 1 0 1 F, R 7T 2

8. LXI rp, d16 0 0 RP 0 0 0 1 3 F, R, R 10T 4

9. LHLD addr16 00 10 1 01 0 3 F,R,R,R,R 16T 1

10. STA addr16 00 11 0 01 0 3 F, R, R,W 13T 1

11. STAX rp 0 0 RP 0 0 1 0 1 F, W 7T 2

12. SHLD addr16 00 10 0 01 0 3 F,R,R,W,W 16T 1

13. SPHL 11 11 1 00 1 1 S 6T 1

14. XCHG 11 10 1 01 1 1 F 4T 1

15. XTHL 11 10 0 01 1 1 F,R,R,W,W 16 T 1

16. PUSH rp 1 1 RP 0 1 0 1 1 S, W, W 12T 3

17. PUSH PSW 11 11 0 10 1 1 S, W, W 12T 1

18. POP rp 1 1 RP 0 0 0 1 1 F, R, R 10T 3

19. POP PSW 11 11 0 00 1 1 F, R, R 10T 1

20. IN addr8 11 01 1 01 1 2 F, R, I 10T 1

21. OUT addr8 11 01 0 01 1 2 F, R, O 10T 1

Group II : Arithmetic instructions

22. ADD reg 1 0 0 0 0 S SS 1 F 4T 7

23. ADD M 10 0 00 11 0 1 F, R 7T 1
2. 14 Chapter 2 Instruction Set Of 8085

Table - 2.1 continued...

S.No. Mnemonic Opcode No.of Machine No.of Total no. of
bytes cycles T states instructions

24. ADI d8 1 1 0 0 0 1 10 2 F, R 7T 1

25. ADC reg 1 0 0 0 1 S SS 1 F 4T 7

26. ADC M 1 0 0 0 1 1 10 1 F, R 7T 1

27. ACI d8 1 1 0 0 1 1 10 2 F, R 7T 1

28. DAA 0 0 1 0 0 1 11 1 F 4T 1

29. DAD rp 0 0 R P1 0 01 1 F, B, B 10T 4

30. SUB reg 1 0 0 1 0 S SS 1 F 4T 7

31. SUB M 1 0 0 1 0 1 10 1 F, R 7T 1

32. SUI d8 1 1 0 1 0 1 10 2 F, R 7T 1

33. SBB reg 1 0 0 1 1 S SS 1 F 4T 7

34. SBB M 1 0 0 1 1 1 10 1 F, R 7T 1

35. SBI d8 1 1 0 1 1 1 10 2 F, R 7T 1

36. INR reg 0 0 S SS 1 00 1 F 4T 7

37. INR M 00 1 10 100 1 F, R, W 10T 1

38. INX rp 0 0 R P0 0 1 1 1 S 6T 4

39. DCR reg 0 0 S SS 1 0 1 1 F 4T 7

40. DCR M 00 1 10 101 1 F, R, W 10T 1

41. DCX rp 0 0 R P1 0 1 1 1 S 6T 4

Group III : Logical instructions

42. ANA reg 1 0 1 0 0 SS S 1 F 4T 7

43. ANA M 1 0 1 0 0 11 0 1 F, R 7T 1

44. ANI d8 1 1 1 0 0 11 0 2 F, R 7T 1

45. ORA reg 1 0 1 1 0 SS S 1 F 4T 7

46. ORA M 1 0 1 1 0 11 0 1 F, R 7T 1

47. ORI d8 1 1 1 1 0 11 0 2 F, R 7T 1
Microprocessor (8085) And Its Applications 2. 15

Table - 2.1 continued...

S.No. Mnemonic Opcode No.of Machine No.of Total no. of

bytes cycles T states instructions

48. XRA reg 1 0 1 0 1 SSS 1 F 4T 7

49. XRA M 10 1 0 1110 1 F,R 7T 1

50. XRI d8 11 1 0 1110 2 F, R 7T 1

51. CMP reg 1 0 1 1 1 SSS 1 F 4T 7

52. CMP M 10 1 1 1110 1 F, R 7T 1

53. CPI d8 11 1 1 1110 2 F, R 7T 1

54. CMA 00 1 0 1111 1 F 4T 1

55. CMC 00 1 1 1111 1 F 4T 1

56. STC 00 1 1 0111 1 F 4T 1

57. RLC 00 0 0 0111 1 F 4T 1

58. RAL 00 0 1 0111 1 F 4T 1

59. RRC 00 0 0 1111 1 F 4T 1

60. RAR 00 0 1 1111 1 F 4T 1

Group IV : Branching instructions

61. JMP addr16 1 10 0 0011 3 F,R,R 10T 1

62. J<condition>
addr16 1 1 C C C0 1 0 3 F,R/F,R,R 7T/10T 8

63. CALL addr16 1 10 0 1101 3 S,R,R,W,W 18T 1

64. C<condition> S, R or
addr16 1 1 C C C1 0 0 3 S,R,R,W,W 9T/18T 8

65. RET 1 10 0 1001 1 F,R,R 10T 1

66. R<condition> 1 1 C C C0 0 0 1 S/S,R,R 6T/12T 8

67. RST n 1 1 N N N1 1 1 1 S,W,W 12T 8

68. PCHL 1 11 0 1001 1 S 6T 1

2. 16 Chapter 2 Instruction Set Of 8085

Table - 2.1 continued...

S.No. Mnemonic Opcode
No.of Machine No.of Total no. of
bytes cycles T states instructions
Group V : Machine control instructions

69. SIM 0 0 110 0 0 0 1 F 4T 1

70. RIM 0 0 100 0 0 0 1 F 4T 1

71. DI 1 1 110 0 1 1 1 F 4T 1

72. EI 1 1 111 0 1 1 1 F 4T 1

73. HLT 0 1 110 1 1 0 1 F,B 5T 1

74. NOP 0 0 000 0 0 0 1 F 4T 1

246

Meanings of various symbols used in Table - 2.1.

Symbol Meaning
rp, RP Register pair
Rs, SSS Source register
Rd, DDD Destination register
M Memory
d8 8-bit data
d16 16-bit data
addr8 8-bit address
addr16 16-bit address
reg Register
PSW Program status word
n, NNN Type number of restart instruction
<condition>, CCC Flag condition
F 4T-Opcode fetch cycle
S 6T-Opcode fetch cycle
R Memory read cycle
W Memory write cycle
I IO read cycle
O IO write cycle
B Bus idle cycle

Flag condition can be any one of the conditions given below :

Z → Zero flag = 1 M → Sign flag = 1
NZ → Zero flag = 0 P → Sign flag = 0
C → Carry flag = 1 PE → Parity flag = 1
NC → Carry flag = 0 PO → Parity flag = 0
Microprocessor (8085) And Its Applications 2. 17

The binary codes for the symbols used in opcode of 8085 instructions are given below:
Register DDD or SSS Register RP
B 000 BC 00
C 001 DE 01
D 010 HL 10
E 011 SP 11
H 100
L 101
A 111

Flag condition CCC n NNN

NZ 000 0 000
Z 001 1 001
NC 010 2 010
C 011 3 011
PO 100 4 100
PE 101 5 101
P 110 6 110
M 111 7 111

TABLE - 2.2 : 8085 INSTRUCTIONS AFFECTING THE STATUS FLAGS

Status flags
Instructions
CF AF ZF SF PF
ACI d8 + + + + +
ADC reg + + + + +
ADC M + + + + +
ADD reg + + + + +
ADD M + + + + +
ADI d8 + + + + +
ANA reg 0 1 + + +
ANA M 0 1 + + +
ANI d8 0 1 + + +
CMC +
CMP reg + + + + +
CMP M + + + + +
CPI d8 + + + + +
DAA + + + + +
DAD rp +
DCR reg + + + +
DCR M + + + +
INR reg + + + +
INR M + + + +
ORA reg 0 0 + + +
ORA M 0 0 + + +
2. 18 Chapter 2 Instruction Set Of 8085

Table - 2.2 continued...

Status flags
Instructions
CF AF ZF SF PF
ORI d8 0 0 + + +
RAL +
RAR +
RLC +
RRC +
SBB reg + + + + +
SBB M + + + + +
SBI d8 + + + + +
STC +
SUB reg + + + + +
SUB M + + + + +
SUI d8 + + + + +
XRA reg 0 0 + + +
XRA M 0 0 + + +
XRI d8 0 0 + + +

Note :
+ → Indicates that the particular flag is affected.
0 → Indicates that the particular flag is always zero.
1 → Indicates that the particular flag is always one.
TABLE - 2.3 : MEANING/EXPANSION OF MNEMONICS USED IN AN 8085 INSTRUCTION SET

S.No. Mnemonic Meaning

1. ACI Add the immediate data and the carry to the accumulator.
2. ADC Add the register/memory and the carry to the accumulator.
3. ADD Add the register/memory to the accumulator.
4. ADI Add the immediate data to the accumulator.
5. ANA AND register/memory with the accumulator.
6. ANI AND immediate data with the accumulator.
7. CALL Call a subroutine/procedure.
8. CC Call on carry.
9. CM Call on minus.
10. CMA Complement accumulator.
11. CMC Complement carry.
12. CMP Compare register/memory with accumulator.
13. CNC Call on no carry.
14. CNZ Call on not zero.
Microprocessor (8085) And Its Applications 2. 19

Table - 2.3 continued...

S.No. Mnemonic Meaning
15. CP Call on positive.
16. CPE Call on parity even.
17. CPI Compare immediate data with the accumulator.
18. CPO Call on parity odd.
19. CZ Call on zero.
20. DAA Decimal adjust accumulator after addition.
21. DAD Double addition.
22. DCR Decrement the register/memory.
23. DCX Decrement the register pair.
24. DI Disable interrupt.
25. EI Enable interrupt.
26. HLT Halt program execution.
27. IN Input data from specified port to accumulator.
28. INR Increment the register/memory.
29. INX Increment the register pair.
30. JC Jump on carry.
31. JM Jump on minus.
32. JMP Jump to specified address to get the next instruction.
33. JNC Jump on no carry.
34. JNZ Jump on not zero.
35. JP Jump on positive.
36. JPE Jump on parity even.
37. JPO Jump on parity odd.
38. JZ Jump on zero.
39. LDA Load the accumulator.
40. LDAX Load accumulator indirectly using the address in the specified
register pair.
41. LHLD Load HL direct.
42. LXI Load the immediate data in the register pair.
43. MOV Move (copy) the content of register/memory to another
register/memory.
44. MVI Move the immediate data to register/memory.
45. NOP No operation.
46. ORA OR register/memory with accumulator.
47. ORI OR immediate data with accumulator.
48. OUT Output the content of accumulator to specified port.
49. PCHL Move the content of HL to PC.
2. 20 Chapter 2 Instruction Set Of 8085

Table - 2.3 continued...

S.No. Mnemonic Meaning
50. POP Move the top of stack to the specified register pair.
51. PUSH Push the content of the specified register pair to top of stack.
52. RAL Rotate the accumulator left along with carry.
53. RAR Rotate the accumulator right along with carry.
54. RC Return on carry.
55. RET Return from subroutine/procedure to calling program.
56. RIM Read interrupt mask status.
57. RLC Rotate accumulator left to carry.
58. RM Return on minus.
59. RNC Return on no carry.
60. RNZ Return on not zero.
61. RP Return on positive.
62. RPE Return on parity even.
63. RPO Return on parity odd.
64. RRC Rotate accumulator right to carry.
65. RST Restart the program execution from the specified vector
address.
66. RZ Return on zero.
67. SBB Subtract register/memory and the carry (borrow) from
accumulator.
68. SBI Subtract the immediate data and the carry (borrow) from
accumulator.
69. SHLD Store HL direct.
70. SIM Set interrupt mask.
71. SPHL Move HL to SP.
72. STA Store accumulator.
73. STAX Store accumulator indirectly by using the address in specified
register pair.
74. STC Set carry.
75. SUB Subtract register/memory from accumulator.
76. SUI Subtract the immediate data from accumulator.
77. XCHG Exchange DE and HL.
78. XRA Exclusive-OR register/memory with accumulator.
79. XRI Exclusive-OR the immediate data with accumulator.
80. XTHL Exchange the top of stack and HL.
 APPENDIX I :8085A Instructions in Hexadecimal Order

OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC

IN HEX IN HEX IN HEX

00 NOP 2B DCX H 56 MOV D, M

01 LXI B, d16 2C INR L 57 MOV D, A
02 STAX B 2D DCR L 58 MOV E, B
03 INX B 2E MVI L, d8 59 MOV E, C
04 INR B 2F CMA 5A MOV E, D
05 DCR B 30 SIM 5B MOV E, E
06 MVI B, d8 31 LXI SP, d16 5C MOV E, H
07 RLC 32 STA addr16 5D MOV E, L
08 --- 33 INX SP 5E MOV E, M
09 DAD B 34 INR M 5F MOV E, A
0A LDAX B 35 DCR M 60 MOV H, B
0B DCX B 36 MVI M, d8 61 MOV H, C
0C INR C 37 STC 62 MOV H, D
0D DCR C 38 --- 63 MOV H, E
0E MVI C, d8 39 DAD SP 64 MOV H, H
0F RRC 3A LDA addr16 65 MOV H, L
10 --- 3B DCX SP 66 MOV H, M
11 LXI D, d16 3C INR A 67 MOV H, A
12 STAX D 3D DCR A 68 MOV L, B
13 INX D 3E MVI A, d8 69 MOV L, C
14 INR D 3F CMC 6A MOV L, D
15 DCR D 40 MOV B, B 6B MOV L, E
16 MVI D, d8 41 MOV B, C 6C MOV L, H
17 RAL 42 MOV B, D 6D MOV L, L
18 --- 43 MOV B, E 6E MOV L, M
19 DAD D 44 MOV B, H 6F MOV L, A
1A LDAX D 45 MOV B, L 70 MOV M, B
1B DCX D 46 MOV B, M 71 MOV M, C
1C INR E 47 MOV B, A 72 MOV M, D
1D DCR E 48 MOV C, B 73 MOV M, E
1E MVI E, d8 49 MOV C, C 74 MOV M, H
1F RAR 4A MOV C, D 75 MOV M, L
20 RIM 4B MOV C, E 76 HLT
21 LXI H, d16 4C MOV C, H 77 MOV M, A
22 SHLD addr16 4D MOV C, L 78 MOV A, B
23 INX H 4E MOV C, M 79 MOV A, C
24 INR H 4F MOV C, A 7A MOV A, D
25 DCR H 50 MOV D, B 7B MOV A, E
26 MVI H, d8 51 MOV D, C 7C MOV A, H
27 DAA 52 MOV D, D 7D MOV A, L
28 --- 53 MOV D, E 7E MOV A, M
29 DAD H 54 MOV D, H 7F MOV A, A
2A LHLD addr16 55 MOV D, L 80 ADD B
A. 2 Appendix

Appendix I continued...

OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC

IN HEX IN HEX IN HEX

81 ADD C AC XRA H D7 RST 2

82 ADD D AD XRA L D8 RC
83 ADD E AE XRA M D9 ---
84 ADD H AF XRA A DA JC addr16
85 ADD L B0 ORA B DB IN addr8
86 ADD M B1 ORA C DC CC addr16
87 ADD A B2 ORA D DD ---
88 ADC B B3 ORA E DE SBI d8
89 ADC C B4 ORA H DF RST 3
8A ADC D B5 ORA L E0 RPO
8B ADC E B6 ORA M E1 POP H
8C ADC H B7 ORA A E2 JPO addr16
8D ADC L B8 CMP B E3 XTHL
8E ADC M B9 CMP C E4 CPO addr16
8F ADC A BA CMP D E5 PUSH H
90 SUB B BB CMP E E6 ANI d8
91 SUB C BC CMP H E7 RST 4
92 SUB D BD CMP L E8 RPE
93 SUB E BE CMP M E9 PCHL
94 SUB H BF CMP A EA JPE addr16
95 SUB L C0 RNZ EB XCHG
96 SUB M C1 POP B EC CPE addr16
97 SUB A C2 JNZ addr16 ED ---
98 SBB B C3 JMP addr16 EE XRI d8
99 SBB C C4 CNZ addr16 EF RST 5
9A SBB D C5 PUSH B F0 RP
9B SBB E C6 ADI d8 F1 POP PSW
9C SBB H C7 RST 0 F2 JP addr16
9D SBB L C8 RZ F3 DI
9E SBB M C9 RET F4 CP addr16
9F SBB A CA JZ addr16 F5 PUSH PSW
A0 ANA B CB --- F6 ORI d8
A1 ANA C CC CZ addr16 F7 RST 6
A2 ANA D CD CALL addr16 F8 RM
A3 ANA E CE ACI d8 F9 SPHL
A4 ANA H CF RST 1 FA JM addr16
A5 ANA L D0 RNC FB EI
A6 ANA M D1 POP D FC CM addr16
A7 ANA A D2 JNC addr16 FD ---
A8 XRA B D3 OUT addr8 FE CPI d8
A9 XRA C D4 CNC addr16 FF RST 7
AA XRA D D5 PUSH D -- ---
AB XRA E D6 SUI d8 -- ---

d8 → 8-bit data addr16 → 16-bit address

d16 → 16-bit data M → Memory
addr8 → 8-bit address PSW → Program Status Word
 APPENDIX II : 8085 Instructions in Alphabetical Order

OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC

IN HEX IN HEX IN HEX

CE ACI d8 E4 CPO addr16 0A LDAX B

8F ADC A CC CZ addr16 1A LDAX D
88 ADC B 27 DAA 2A LHLD addr16
89 ADC C 09 DAD B 01 LXI B,addr16
8A ADC D 19 DAD D 11 LXI D,addr16
8B ADC E 29 DAD H 21 LXI H,addr16
8C ADC H 39 DAD SP 31 LXI SP,addr16
8D ADC L 3D DCR A 7F MOV A,A
8E ADC M 05 DCR B 78 MOV A,B
87 ADD A 0D DCR C 79 MOV A,C
80 ADD B 15 DCR D 7A MOV A,D
81 ADD C 1D DCR E 7B MOV A,E
82 ADD D 25 DCR H 7C MOV A,H
83 ADD E 2D DCR L 7D MOV A,L
84 ADD H 35 DCR M 7E MOV A,M
85 ADD L 0B DCX B 47 MOV B,A
86 ADD M 1B DCX D 40 MOV B,B
C6 ADI d8 2B DCX H 41 MOV B,C
A7 ANA A 3B DCX SP 42 MOV B,D
A0 ANA B F3 DI 43 MOV B,E
A1 ANA C FB EI 44 MOV B,H
A2 ANA D 76 HLT 45 MOV B,L
A3 ANA E DB IN addr8 46 MOV B,M
A4 ANA H 3C INR A 4F MOV C,A
A5 ANA L 04 INR B 48 MOV C,B
A6 ANA M 0C INR C 49 MOV C,C
E6 ANI d8 14 INR D 4A MOV C,D
CD CALL addr16 1C INR E 4B MOV C,E
DC CC addr16 24 INR H 4C MOV C,H
FC CM addr16 2C INR L 4D MOV C,L
2F CMA 34 INR M 4E MOV C,M
3F CMC 03 INX B 57 MOV D,A
BF CMP A 13 INX D 50 MOV D,B
B8 CMP B 23 INX H 51 MOV D,C
B9 CMP C 33 INX SP 52 MOV D,D
BA CMP D DA JC addr16 53 MOV D,E
BB CMP E FA JM addr16 54 MOV D,H
BC CMP H C3 JMP addr16 55 MOV D,L
BD CMP L D2 JNC addr16 56 MOV D,M
BE CMP M C2 JNZ addr16 5F MOV E,A
D4 CNC addr16 F2 JP addr16 58 MOV E,B
C4 CNZ addr16 EA JPE addr16 59 MOV E,C
F4 CP addr16 E2 JPO addr16 5A MOV E,D
EC CPE addr16 CA JZ addr16 5B MOV E,E
FE CPI d8 3A LDA d16 5C MOV E,H
A. 4 Appendix

Appendix II continued...
OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC
IN HEX IN HEX IN HEX

5D MOV E,L C1 POP B 97 SUB A

5E MOV E,M D1 POP D 90 SUB B
67 MOV H,A E1 POP H 91 SUB C
60 MOV H,B F1 POP PSW 92 SUB D
61 MOV H,C C5 PUSH B 93 SUB E
62 MOV H,D D5 PUSH D 94 SUB H
63 MOV H,E E5 PUSH H 95 SUB L
64 MOV H,H F5 PUSH PSW 96 SUB M
65 MOV H,L 17 RAL D6 SUI d8
66 MOV H,M 1F RAR EB XCHG
6F MOV L,A D8 RC AF XRA A
68 MOV L,B C9 RET A8 XRA B
69 MOV L,C 20 RIM A9 XRA C
6A MOV L,D 07 RLC AA XRA D
6B MOV L,E F8 RM AB XRA E
6C MOV L,H D0 RNC AC XRA H
6D MOV L,L C0 RNZ AD XRA L
6E MOV L,M F0 RP AE XRA M
77 MOV M,A E8 RPE EE XRI d8
70 MOV M,B E0 RPO E3 XTHL
71 MOV M,C 0F RRC
72 MOV M,D C7 RST 0
73 MOV M,E CF RST 1
74 MOV M,H D7 RST 2
75 MOV M,L DF RST 3
3E MVI A, d8 E7 RST 4
06 MVI B, d8 EF RST 5
0E MVI C, d8 F7 RST 6
16 MVI D, d8 FF RST 7
1E MVI E, d8 C8 RZ
26 MVI H, d8 98 SBB B
2E MVI L, d8 99 SBB C
36 MVI M, d8 9A SBB D
00 NOP 9B SBB E
B7 ORA A 9C SBB H
B0 ORA B 9D SBB L
B1 ORA C 9E SBB M
B2 ORA D DE SBI d8
B3 ORA E 22 SHLD addr16
B4 ORA H 30 SIM
B5 ORA L F9 SPHL
B6 ORA M 32 STA addr16
F6 ORI d8 02 STAX B
D3 OUT addr8 12 STAX D
E9 PCHL 37 STC

d8 → 8-bit data addr16 → 16-bit address

d16 → 16-bit data M → Memory
addr8 → 8-bit address PSW → Program Status Word
APPENDIX III : List of Microprocessors Released By INTEL

MICROPROCESSOR DATE OF NUMBER OF CLOCK SPEED

INTRODUCTION TRANSISTORS

4004 15th Nov, 1971 2,300 400 kHz

8008 Apr, 1972 3,500 500-800 kHz
8080 Apr, 1974 4,500 2 MHz
8085 Mar, 1976 6,500 5 MHz
th
8086 8 Jun, 1978 29,000 5/8/10 MHz
8088 Jun, 1979 29,000 5/8 MHz
80186 1982 .... 10/12 MHz
80286 Feb, 1982 134,000 6/10/12 MHz
th
INTEL386 DX 17 Oct, 1985 275,000 16/20/25/33 MHz
th
INTEL386 SX 16 Jun, 1988 275,000 16/20/25/33 MHz
INTEL386 SL 15th Oct, 1990 855,000 20/25 MHz
INTEL486 DX 10th Apr, 1989 1.2 million 25/33/50 MHz
th
INTEL486 SX 16 Sep, 1991 900,000 16/20/25 MHz
st
INTEL486 SX 21 Sep, 1992 1.185 million 33 MHz
th
INTEL486 SL 4 Nov, 1992 1.4 million 20/25/33 MHz
INTELDX 2 3rd Mar, 1992 1.2 million 50/66 MHz
INTELDX 4 7th Mar, 1994 3.2 million 75/100 MHz
nd
Pentium 22 Mar, 1993 3.1 million 60/66 MHz
th
Pentium 7 Mar, 1994 3.2 million 75/90/100/120 MHz
Pentium Jun, 1995 3.3 million 133/150/166/200 MHz
st
Pentium Pro 1 Nov, 1995 5.5 million 150/166/180/200 MHz
Pentium (MMX) 8th Jan, 1997 4.5 million 166/200/233 MHz
th
Mobile Pentium (MMX) 9 Sep, 1997 4.5 million 200/233/266/300 MHz
th
Pentium II 7 May, 1997 7.5 million 233/266/300/333/350/400/
450 MHz
Mobile Pentium II 2nd Apr, 1998 7.5 million 233/266/300 MHz
th
Mobile Pentium II 25 Jan, 1999 27.4 million 333/366/400 MHz
th
Pentium II Xeon 29 Jun, 1998 7.5 million 400/450 MHz
th
Celeron 15 Apr, 1998 7.5 million 266/300 MHz
Celeron 24th Aug, 1998 19 million 333 MHZ to 2.7 GHz
Mobile Celeron 25th Jan, 1999 18.9 million 266 MHz to 2.4 GHz
th
Pentium III 26 Feb, 1999 9.5 million 450/500/550/600 MHZ
A. 6 Appendix

Appendix III continued...

MICROPROCESSOR DATE OF NUMBER OF CLOCK SPEED

INTRODUCTION TRANSISTORS

Pentium III 25th Oct, 1999 28 million 500 MHz to 1 GHz

th
Pentium III Xeon 17 Mar, 1999 9.5 million 500/550 MHz
th
Pentium III Xeon 25 Oct, 1999 28 million 600 to 900 MHz
th
Mobile Pentium III 25 Oct, 1999 28 million 400 MHz to 1 GHz
th
Mobile Pentium III 30 Jul, 2001 44 million 1/1.06/1.13/1.2/1.33 GHz
Pentium 4 20th Nov, 2000 42 million 1.4/1.5/1.6/1.7/1.8/1.9/2 GHz
Pentium 4 27th Aug, 2001 55 million 2 to 2.8 GHz
th
Pentium 4 (HT Technology) 14 Nov, 2002 55 million 2.4 to 3.3 GHz
th
Mobile Pentium 4 4 Mar, 2002 55 million 1.5 to 3.2 GHz
st
INTEL Xeon 21 May, 2001 42 million 1.4/1.5/1.7/2 GHz
INTEL Xeon 9th Jan, 2002 52 million 1.8/2/2.2/2.4/2.6/2.8 GHz
INTEL Xeon 18th Nov, 2002 108 million 1.4 to 3.2 GHz
INTEL Itanium May, 2001 25 million 733/800 MHz
th
INTEL Itanium 2 8 Jul, 2002 220 million 900 MHz/1 GHz
th
INTEL Itanium 2 30 Jun, 2003 410 million 1/1.4/1.5 GHz
INTEL Pentium-M 12th Mar, 2003 77 million 900 MHz to 1.7 GHz

Note : The date mentioned here is the date of introduction of the lowest clock version of the
processor. For the date of introduction of higher clock version of a processor please refer
to INTEL website www.intel.com.