International Conference AUTOMATICS AND INFORMATICS`2023, October 05 - 07, 2023, Varna, Bulgaria (ICAI'23)

Memristor-Based Neural Network Implementation

with Adjustable Synaptic Weights in LTSPICE
Valeri Mladenov Georgi Tsenov Stoyan Kirilov
Dept. Fundamentals of Electrical Dept. Fundamentals of Electrical Dept. Fundamentals of Electrical
Engineering Engineering Engineering
Technical University of Sofia Technical University of Sofia Technical University of Sofia
Sofia, Bulgaria Sofia, Bulgaria Sofia, Bulgaria
[email protected] [email protected] [email protected]

Abstract — The memristors are innovative electronic neural networks could be applied, in the cases where is
elements with nano-sized structure and with very good memory required simultaneously both very low power consumption,
and switching abilities. They have very low power consumption high speed and real-time signal processing and can help the
and a good compatibility to CMOS integrated chips, and they direct porting of trained classical neural networks into
could be used in neural networks, memories, and many other hardware. During the early 1990s, a problem occurred in the
schematics. In this paper an LTSPICE model of artificial neural realization of optoelectronic analog neural networks, related
network with memristor-based synapses is proposed. In this to impossibility of realizing negative synaptic weights [19].
2023 International Conference Automatics and Informatics (ICAI) | 979-8-3503-1291-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICAI58806.2023.10339092

network, each synapse is realized with only one memristor, thus To overcome this limitation, an appropriate solution was
providing a higher reduction in circuit complexity and with
proposed: scaling the input signals and weights in the range
main benefit of that individual memristor resistance value can
be adjusted with external control voltage signals. The summing
between 0 and 1, and applying “logsig” activation function
and scaling component implementations are based on op-amps instead of the standard “tansig” function [20]. A modified
and memristors. We use the most common logarithmic- learning algorithm was applied to enable operation with
sigmoidal activation function and it is realized by a voltage- positive synaptic weights. All input signals and the respective
controlled source. The operation of the proposed memristor weights were limited to positive values and the weights are
neural network is analyzed and simulated in both LTSPICE and scaled and limited between the limits of zero and unity. When
MATLAB, and the derived results are compared and verified trying to scale or transfer the synaptic weights of a neural net,
successfully. The proposed memristor-based neural network is trained with positive and negative weights to the range
a significant step for engineering low power complex networks between 0 and 1, there arises a lack of the corresponding
in very high-density integrated circuits and chips. outputs. Therefore, it becomes necessary to train the neural
network applying a modified algorithm. In the context of
Keywords — memristor, neural network, activation function, circuit realization the result is that an already trained classical
modelling and simulation, electrical engineering, artificial neural network could not be used. But, with the use of
intelligence, LTSPICE, MATLAB memristors this limitation can be remedied. The first physical
memristor element [21], based on titanium dioxide is invented
I. INTRODUCTION
in Hewlett-Packard research labs by Stanley Williams [10],
Neural networks are architectures that have been inspired [22]. Some metal oxides, as hafnium dioxide, tantalum oxide,
from the electro-chemical communication between neural niobium oxide and many others are applied for
cells in the human brain and other similar biological unities implementations of memristors [23], [24]. Some useful
[1], [2]. The application of neural networks provides properties of memristors are their switching and memory
parallelism, energy effectiveness and potential usage in low- effects, very low power dissipation, high switching rate, nano-
power electronic modules [3], [4]. Neuromorphic chips have sizes and a very good compatibility to CMOS integrated chips
the ability to realize complex computations fast and [25], [26]. Memristors are successfully applicable in memory
effectively while dissipating minimal power. In the past, arrays, reconfigurable electronic circuits, neural networks, and
optical neural networks were dominant solution for realizing many others [27], [28].The utilization of memristors in neural
analogue neural networks, using light instead of electrical networks is a novel trend and after a performed literature
signals to make the neural computations, image and video overview for the generation of a synapse
processing, and for other applications [5], [6], [7]. In the recent [3],[9],[25],[26],[27],[34],[35],[36],[37],[38],[39] we found
years some of the newest advancements in the neuromorphic that usually three or more memristors are used, and two or
computing field are the neural networks that are based on more operational amplifiers are applied. This is related to a
memristor logic [8], [9]. The memristors are two-terminal and very high growth increase of the number of electronic
passive electronic elements, having the ability to store and components and the respective complexity of the hardware
retain the electric charges passed through them [10], [11]. The implemented neural networks increases too. As described, in
resistance of memristors can be altered by pulses with specific the optical neural network implementation only positive
amplitudes and durations and therefore, the memristors could weights could have been used, requiring a different modified
function as tunable resistors [12]. They could be utilized in training algorithms. With memristor-based weight
analogue electric circuits neural network implementations, coefficients the added benefit of such neural networks is that
and are associated with single unit computing and memory positive and negative synaptic weights could be implemented,
accumulation [13], [14], [15]. Memristors could accumulate resulting on the option to apply directly classical feedforward
amounts of information, proportional to the change of their multilayer or deep neural network architectures. Our
resistance [16], [17], [18]. In machine learning and artificial motivation for new contribution was to check and try to
intelligence analog implementation the memristor-based design, simulate and verify if potential implementations of

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403
 neural networks with reduced complexity are possible for [10], Joglekar and Biolek [12] is represented by the following
synaptic circuits and realized with the use of only one system of equations [12], [14]:
memristor per synapse. With memristor logic we can have v
tunable gain coefficient values with adjustable resistance i=
levels. With use of inverting summing operational amplifier RON x + ROFF (1 − x ) (1)
we can have negative weight realization with a certain x& = k ⋅ i ⋅ f ( x )
amplification ratio in respect to resistance ratios. This where RON and ROFF are the respective ON-state and OFF-state
provides the possibility to use such a model and realize each resistances, k is a physical constant, dependent on memristor
synapse by the use of a single memristor, expressively parameters [12], and f(x) is a window function applied for
reducing the complexity, and with both positive and negative restriction of state variable x [14]. A widely applied window
weights, with both positive and negative inputs, providing the is those proposed by Biolek [12]:
ability for direct application of the classical feedforward 2p
multilayer or deep learning neural networks in an electronic f B ( i, x ) = 1 −  x − stp ( −i )  (2)
implementations. Here, p is an integer positive exponent and stp is the
For verification of this idea a simulation model needs to be classical Heaviside step function [12]. The model of
implemented and the best simulation environment is an Lehtonen-Laiho is a frequently used one, it has a good
Simulation Programs for Integrated Circuits Emphasis accuracy and operates at high-frequency signals. It is
(SPICE) software products [29], LTSPICE is the preferable represented by Eq. (3) [13]:
environment for electronic circuit analyses and simulations it
the late years, due to its free license, big company support and i = χ exp ( γ v ) − 1 + x n ⋅ β ⋅ sinh (α v )
updates, user-friendly interface, and a very good convergence dx (3)
[30]. Due to this, LTSPICE is used in the present work. The = a ⋅ v m ⋅ f B ( i, x )
main purpose of this paper is to suggest a simple memristor- dt
based neural network with positive and negative synaptic where the coefficients α, β, n, χ, γ, m and a are used for its
weights, with minimal number of electronic elements in the adjustment, according to experimental i-v relations [13]. In
LTSPICE environment. For the realization of this objective to [15], a simple model, based on Biolek memristor model and
simplify the model, every neuron has two major types of Hann window, is presented, and j is a physical constant [15].
inputs, one for the positive and one for negative weights v
respectively. This procedure is performed with application of i=
RON x + ROFF (1 − x )
memristors and op-amps, where the respective synapses are (4)
realized by single memristor elements. The activation dx 1
= j ⋅ i ⋅ 1 − cos ( 2π x ) 
functions are realized by voltage-controlled sources in dt 2
LTSPICE. For model verification and comparisons an
example trained neural network with six inputs, three neurons
in one hidden layer and two neurons in output layer is created
and analyzed in both LTSPICE and MATLAB environments.
The rest of the paper is organized as follows. Section 2
presents memristor operation, modeling and memristor-based
neural networks. The used simple LTSPICE memristor model
is described in Section 3. The proposed memristor-based
neural network in LTSPICE is presented in Section 4, with
included analysis and verification of the derived results,
followed with Conclusion and References sections.
II. MEMRISTORS, MODELING AND MEMRISTOR-BASED
NEURAL NETWORKS
For better understanding of the following paragraphs, a
brief overview on the basic aspects of the operation and
modeling of memristors is first provided.
A. A short description of memristor operation
The switching and memory properties of memristors are Fig. 1 a) A schematic of a memristor-based neural network; b) A block
related to their capability to allow alterations of their schematic of a neuron with memristor synapses
resistance, which is proportional to state variable, when
external voltage or current signals are applied [12], [31]. As A simple memristor-based neural network is presented in
written in [], the state variable x expresses the ratio between Fig. 1 a) for explanation of its structure and functioning. A
the length of the doped layer and those of the overall detailed diagram of a neuron with memristor-based synapses
memristor. The state variable is between zero and unity [32]. is shown in Fig. 1 b). The input signals are presented as x1,
x1, … and xn. They are applied to memristor synapses, having
B. Memristor Modeling weights denoted as w1, w2, … and wn. Each synapse is
Each model of memristor contains two equations [12]. The realized by a memristor, which resistance is related to the
first one expresses the i-v relation, and the second one relates respective synaptic weight w. The signals obtained after the
the time derivative of the memristor state variable and the synapses are applied to a summing scheme, implemented
current (or the voltage). A collection of frequently used metal- with memristors and op-amps, operating as linear resistors.
oxide memristor models, such as these of Williams-Strukov The signal gained after the adder is denoted as y_in and is

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404
 applied to a log-sig activation function, implemented by a
voltage-dependent voltage source. The output signal of the
memristor-based neuron is presented by y.
The neural network contains input nodes for applying the
input signals, a hidden layer and an output layer [20], [33].
The operation of the discussed memristor-based neural
network is related to a feed-forward and back-error correction
algorithm [20]. Various activation functions could be used
after the adder. Flat and differentiable transfer functions, such Fig. 2 Current-voltage characteristics of applied memristor model at different
as logarithmic-sigmoidal and tangent-sigmoidal expressions frequencies: a) f1 = 600 Hz; b) f2 = 3 kHz; c) f3 = 200 kHz
are regularly used. A relay transfer function is also used in
neural networks. Linear activation functions are also applied IV. THE PROPOSED LTSPICE MODEL OF MEMRISTOR-BASED
in neural networks, especially in the neurons of the output NEURAL NETWORK. ANALYSIS AND SIMULATIONS OF THE
layers, using a gain factor. In the next section, a modified PROPOSED NEURAL NETWORK
version of an enhanced model of memristor [32] is presented. In order for the schematic to work properly we need to
III. THE APPLIED LTSPICE MEMRISTOR MODEL scale all input voltage signals to the memristors in the upper
range of the activation threshold, that is 0.2 V. In order to ease
The first equation of the modified model is based on the computations and not to reach 0.2 in border cases we scale
Biolek memristor model [12]. The second one is founded on and rescale all memristor inputs to be set at 100 mV maximal
Lehtonen-Laiho model and utilizes a sine window sin2(πx). voltage levels, that will guarantee that we will always use the
v memristors in normal operation in their resistor mode range.
i=
RON x + ROFF (1 − x ) For some junctions, where we will always have a higher than
(5) 0.2 V signals we use memristors with their cut of value that
dx provides 16000 Ohm value, regardless of voltage. In this
= k ⋅ v m .sin 2 (π x ) ⋅ stp ( v − vthr )
dt aspect the input voltages will be in the -0.1V to 0.1V range.
The used voltage activation threshold is vthr = 0.2 V. The The resulting signals after the sigmoidal activation function,
minimal resistance value is 100 Ohm, while maximal is are between 0 and 1V and we scale them down with 0.1
16kOhm. When the voltage is at levels -0.2 to 0.2 Volts the coefficient resulting of voltages in -0.1 to 0.1 V in the inputs
memristors act as a common resistance, while when the input of the hidden layers, where with multiplication of weight
signals are above activation threshold the memristor coefficients with 10, results in one to one weight mapping
resistance is changed [12]. The utilized memristor model is from a trained neural network to a electronic implementation
analyzed for sinusoidal and impulse signals for soft-switching analogue circuit model.
and hard-switching modes. Using (5), LTSPICE memristor In Fig. 3, a principal schematic of the applied memristor-
model is obtained. It corresponds to the math model, based neuron is presented for description of its structure and
representing the i-v relation and state equation. The LTSPICE operation. A neuron in LTSPICE is shown in Fig. 4.
code of the discussed memristor model is given below for
additional explanations.
1 .subckt A14m te be
2 .params ron=100 roff=16e3 m=3 k=10 mm=1e-21 m0=300 vthr=0.2
3 C1 Y 0 {1}
4 .IC V(Y)={(roff-m0)/(roff-ron)}
5 R1 Y 0 10G
6 G2 0 Y value={((k*pow(V(te,be),m))*((pow(sin(pi*V(Y)),2)))*
(stpp((abs(V(te,be))-vthr),mm)))}
7 G1 te be value={V(te,be)*((1/(ron*(V(Y))+roff*(1-V(Y)))))}
8 .func stpp(x,p)={0.5*(1+(x/sqrt(pow(x,2)+p)))}
9 .ends A14m
The first row represents the name of the model, denoted
by A14m. The terminals are depicted as te (top electrode) and Fig. 3 A memristor-based neuron with positive and negative synaptic weights
be (bottom electrode). The parameters RON, ROFF, m, k and vthr In Fig. 4, the structure of an artificial neuron in LTSPICE
are put at the next row. The initial value of the voltage of is presented.
integrating capacitor C1 is proportional to the respective
memristance. The fifth row represents the additional resistor
Rad of 10 GΩ, connected in parallel to capacitor C1. The
controlled source G2 in the sixth row expresses the time
derivative of memristor state variable x. The source G1
presents the memristor current. The code finishes with
command “ends” [18], [30]. The code is included in a library,
available at https://github.com/mladenovvaleri/Advanced-
Memristor-Modeling-in-LTSpise [18].
The model is analyzed at sinusoidal signals with an
amplitude of 1.3 V and different frequencies. The derived i-v
relationships are presented in Fig. 2 for confirmation of
correct operation of model. When the signal’s frequency
increases, then a decrease of surface of i-v loop is detected.
This is in agreement with main memristors’ patterns [12]. Fig. 4 LTSPICE schematic model of a neuron

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405
 In order to verify the model, we first train a neural network enough, but still simple enough to signal trace and analyze the
with specific design features and architecture, that is simple structure as shown on Fig. 5. On Fig. 6 we present the resulting
for visualization and for comparison. For this purpose, we LTSPICE model of the proposed memristor-based neural
used the interactive example from playground.tensorflow.org network with 6 inputs connected to 3 hidden neurons and with
to train a neural network with 6 dimensional input space, with 2 output units.
3 hidden neurons and with 2 output neurons as a complex

Fig. 5 The trained neural network model of the example that is to be implemented in LTSPICE

Fig. 6 LTSPICE model of the proposed memristor-based neural network

Out1 Out2
Table2 Sum1 Sum2 Sum3 Tf1 Tf2 Tf3 Sum4 Sum5
(TF4) (TF5)
LTSPICE -0.9754V 9.5241V 2.2586V 0.2738V 0.9999V 0.9054V 1.0936V -0.8920V 0.7491V 0.2907V
MATLAB -0.9754V 9.5388V 2.2589V 0.2738V 0.9999V 0.9054V 1.0943V -0.8921V 0.7492V 0.2907V

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406
 In Table 1 are presented the levels of the output signals, and U18 correspond to v1 and v2, while U19 – U22 are related to
and all relevant resulting signals in LTSPICE, comparing v3 – v6. The op-amps U3 and U6 are supplied by DC voltage of
them to the results derived in MATLAB. 3 Volts. The feedback memristors M7, M8 and M9 are can be
Table 1 Input signals, synaptic weights and output signals
replaced by memristor blocks if higher resistance base to the
ratio value is demanded, by containing two or more
memristors connected in series and to avoid the corresponding
voltage to exceed the activation threshold if a certain below
16KΩ values are desired. The exact number of the memristors
in a block could be calculated, using the levels and number of
input signals, the synaptic weights and the feedback resistors.
The activation function is realized by a voltage-controlled
voltage source.
The neuron is analyzed for several definite cases, and the
levels of the input signals are presented in Table 2. The
weights of the synapses and the corresponding resistances of
memristors M1 – M6 are presented in Table 2. the time
diagrams of the input signals are presented in Fig. 7 a) for
visual expression and comparison. The corresponding
diagrams of the signals after the adders are shown in Fig. 7 b)
and the output signals – in Fig. 7 c). Observing the results, a
very good matching between the output signals is established.

The input signals are denoted with v1 – v6 in Fig. 6. The

respective synaptic weights are represented by the memristors
M1 – M6. For the first neuron, the memristors M1 – M5 are
related to negative weights, while memristors M5 – M6 realize
positive weights. The synapses are attached to inverting inputs
of op-amps. The memristors M7, M8 and M9 are used for
realization of feedbacks of the op-amps. We will set them
specifically at 16 kΩ, because they will be put on voltages a)
higher than the cutoff threshold value and the gain coefficient
(weight) value will be obtained by rations in respect to this
resistance value. The output signal of op-amp 2 is applied to
the inverting input of op-amp 1 through the memristor M8.
Applying Kirchhoff’s laws, the output voltage of op-amp 1 is
obtained as follows:
M7 M
vout _ OA1 = − v1 − 7 v2 −
M1 M2
(6)
M7  M9 M M M 
− v3 − 9 v4 − 9 v5 − 9 v6  b)
M8  M3 M4 M5 M3 
Using that M9 = M8 = 16 kΩ, the next expression follows:
M7 M M M M M
vout _ OA1 = − v1 − 7 v2 + 7 v3 + 7 v4 + 7 v5 + 7 v6
M1 M2 M3 M4 M5 M6
where the coefficients before the signals v1 – v6 are the
synaptic weights:
M7 M
w1 = − ; w2 = − 7
M1 M2
(7)
M M M M c)
w3 = 7 ; w4 = 7 ; w5 = 7 ; w6 = 7
M3 M4 M5 M6 Fig. 7 Analysis of proposed memristor-based neural network a) Time
diagrams of input signals v1 – v6 ; b) graphs of signals after the adders; c) the
signals after the activation functions
It is evident that w1 and w2 are negative, while w3 – w6 are
positive synaptic weights. The implementation of the In Table 2 are presented the resulting voltages in the
considered memristor neuron in LTSPICE environment is LTSPICE as shown on Fig. 8 and compared with calculated in
represented in Fig. 4 for additional description and discussions MATLAB expected voltage levels. We have observed and the
and it is related to the circuit given in Fig. 3. The input signals results in the table confirm it that the simulations show almost
are realized by pulse voltage sources V7 – V12. The sources U17 identical results in respect to the theoretically expected ones.

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407
 V. CONCLUSION [17] Solovyeva, E. B., Azarov, V. A., "Comparative Analysis of Memristor
Models with a Window Function Described in LTspice," 2021 IEEE
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