STM32L083x8 STM32L083xB

STM32L083xZ
Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 192KB
Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs, AES
Datasheet - production data

Features
FBGA FBGA

• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 to 125 °C temperature range LQFP48 (7 x 7 mm) UFQFPN48 UFBGA100 TFBGA64
LQFP64 (10x10 mm) (7x7 mm) 7x7 mm
– 0.29 µA Standby mode (3 wakeup pins) 5x5 mm
LQFP100 (14x14 mm)
– 0.43 µA Stop mode (16 wakeup lines)
– 0.86 µA Stop mode + RTC + 20-Kbyte RAM – Support contrast adjustment
retention – Support blinking mode
– Down to 93 µA/MHz in Run mode – Step-up converted on board
– 5 µs wakeup time (from Flash memory)
• Rich Analog peripherals
– 41 µA 12-bit ADC conversion at 10 ksps
– 12-bit ADC 1.14 Msps up to 16 channels (down
• Core: Arm® 32-bit Cortex®-M0+ with MPU to 1.65 V)
– From 32 kHz up to 32 MHz max. – 2 x 12-bit channel DACs with output buffers
– 0.95 DMIPS/MHz (down to 1.8 V)
• Memories – 2x ultra-low-power comparators (window mode
– Up to 192-Kbyte Flash memory with ECC (2 and wake up capability, down to 1.65 V)
banks with read-while-write capability) • Up to 24 capacitive sensing channels supporting
– 20-Kbyte RAM touchkey, linear and rotary touch sensors
– 6 Kbytes of data EEPROM with ECC • 7-channel DMA controller, supporting ADC, SPI,
– 20-byte backup register I2C, USART, DAC, Timers, AES
– Sector protection against R/W operation • 11x peripheral communication interfaces
• Up to 84 fast I/Os (78 I/Os 5V tolerant) – 1x USB 2.0 crystal-less, battery charging
• Reset and supply management detection and LPM
– Ultra-safe, low-power BOR (brownout reset) – 4x USART (2 with ISO 7816, IrDA), 1x UART
with 5 selectable thresholds (low power)
– Ultra-low-power POR/PDR – Up to 6x SPI 16 Mbits/s
– Programmable voltage detector (PVD) – 3x I2C (2 with SMBus/PMBus)
• Clock sources • 11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
– 1 to 25 MHz crystal oscillator timer, 1x SysTick, 1x RTC, 2x 16-bit basic for DAC,
– 32 kHz oscillator for RTC with calibration and 2x watchdogs (independent/window)
– High speed internal 16 MHz factory-trimmed RC
(+/- 1%) • CRC calculation unit, 96-bit unique ID
– Internal low-power 37 kHz RC • True RNG and firewall protection
– Internal multispeed low-power 65 kHz to • Hardware Encryption Engine AES 128-bit
4.2 MHz RC
• All packages are ECOPACK2
– Internal self calibration of 48 MHz RC for USB
Table 1. Device summary
– PLL for CPU clock
Reference Part number
• Pre-programmed bootloader
– USB, USART supported STM32L083x8 STM32L083V8

• Development support STM32L083xB STM32L083CB, STM32L083VB, STM32L083RB

– Serial wire debug supported STM32L083xZ STM32L083CZ, STM32L083VZ, STM32L083RZ
• LCD driver for up to 4x52 or 8x48 segments

November 2019 DS10671 Rev 5 1/149

This is information on a product in full production. www.st.com
Contents STM32L083xx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 25
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11 Liquid crystal display (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.13.1 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.13.2 VLCD voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 29
3.16 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18.1 General-purpose timers (TIM2, TIM3, TIM21 and TIM22) . . . . . . . . . . . 31
3.18.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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3.18.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.18.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 34
3.19.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 35
3.19.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 35
3.19.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 36
3.22 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 66
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.16 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.18 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.21 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.4 TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.5 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.6 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Ultra-low-power STM32L083xxx device features and peripheral counts . . . . . . . . . . . . . . 11
Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16
Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Capacitive sensing GPIOs available on STM32L083xx devices . . . . . . . . . . . . . . . . . . . . 30
Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. STM32L083xx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. STM32L083xx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Alternate functions port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 18. Alternate functions port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 19. Alternate functions port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 20. Alternate functions port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 21. Alternate functions port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 22. Alternate functions port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 23. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 24. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 26. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 27. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 29. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 30. Current consumption in Run mode, code with data processing running from
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31. Current consumption in Run mode vs code type,
code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. Current consumption in Run mode, code with data processing running from RAM . . . . . . 71
Table 33. Current consumption in Run mode vs code type,
code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 34. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 35. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 36. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 37. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 38. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 77
Table 39. Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 40. Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 41. Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 81
Table 42. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 43. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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Table 45. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 46. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. 16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 48. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 49. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 50. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 51. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 52. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 53. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 54. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 92
Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 64. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 65. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 66. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 67. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 68. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 70. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 71. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 72. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 73. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 74. SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 75. SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 76. SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 77. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 78. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 79. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 80. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 81. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 84. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 128
Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 87. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 134
Table 88. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 137
Table 89. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 90. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 91. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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List of figures

Figure 1. STM32L083xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3. STM32L083xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 4. STM32L083xx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5. STM32L083xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6. STM32L083xx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. STM32L083xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. STM32L083xx UFQFPN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 12. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 14. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 15. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16. IDD vs VDD, at TA= 25 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 17. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 18. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 23. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 24. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 25. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA) . . . . . . . . . . . . 105
Figure 31. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 106
Figure 32. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 35. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 36. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 37. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 38. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 39. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 124
Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 41. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball

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List of figures STM32L083xx

grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 44. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 130
Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 131
Figure 47. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 48. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 50. TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 136
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 137
Figure 53. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 54. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 55. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 56. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 57. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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1 Introduction

The ultra-low-power STM32L083xx are offered in 6 different package types from 48 to 100
pins. Depending on the device chosen, different sets of peripherals are included, the
description below gives an overview of the complete range of peripherals proposed in this
family.
These features make the ultra-low-power STM32L083xx microcontrollers suitable for a wide
range of applications:
• Gas/water meters and industrial sensors
• Healthcare and fitness equipment
• Remote control and user interface
• PC peripherals, gaming, GPS equipment
• Alarm system, wired and wireless sensors, video intercom
This STM32L083xx datasheet should be read in conjunction with the STM32L0x3xx
reference manual (RM0367).
For information on the Arm®(a) Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description STM32L083xx

2 Description

The ultra-low-power STM32L083xx microcontrollers incorporate the connectivity power of

the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm Cortex-M0+
32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-
speed embedded memories (up to 192 Kbytes of Flash program memory, 6 Kbytes of data
EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and
peripherals.
The STM32L083xx devices provide high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage
adaptation and several low-power modes.
The STM32L083xx devices offer several analog features, one 12-bit ADC with hardware
oversampling, two DACs, two ultra-low-power comparators, AES, several timers, one low-
power timer (LPTIM), four general-purpose 16-bit timers and two basic timer, one RTC and
one SysTick which can be used as timebases. They also feature two watchdogs, one
watchdog with independent clock and window capability and one window watchdog based
on bus clock.
Moreover, the STM32L083xx devices embed standard and advanced communication
interfaces: up to three I2Cs, two SPIs, one I2S, four USARTs, a low-power UART
(LPUART), and a crystal-less USB. The devices offer up to 24 capacitive sensing channels
to simply add touch sensing functionality to any application.
The STM32L083xx also include a real-time clock and a set of backup registers that remain
powered in Standby mode.
Finally, their integrated LCD controller has a built-in LCD voltage generator that allows to
drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L083xx devices operate from a 1.8 to 3.6 V power supply (down
to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR
option. They are available in the -40 to +125 °C temperature range. A comprehensive set of
power-saving modes allows the design of low-power applications.

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2.1 Device overview

Table 2. Ultra-low-power STM32L083xxx device features and peripheral counts
STM32L083 STM32L083 STM32L083 STM32L083 STM32L083 STM32L083 STM32L083
Peripheral
V8 CB VB RB CZ VZ RZ

Flash memory (Kbytes) 64 Kbytes 128 Kbytes 192 Kbytes

Data EEPROM (Kbytes) 3 Kbytes 6 Kbytes

RAM (Kbytes) 20 Kbytes

AES 1

General-
4
purpose
Timers
Basic 2

LPTIMER 1

RTC/SYSTICK/IWDG/WWDG 1/1/1/1

SPI/I2S 6(4)(1)/1

I2 C 3
Commu-
nication USART 4
interfaces
LPUART 1

USB/(VDD_USB) 1/(1)

GPIOs 84 40 84 51 40 84 51

Clocks:
1/1/1/1/1
HSE/LSE/HSI/MSI/LSI

12-bit synchronized ADC 1 1 1 1 1

Number of channels 16 10 16 10 16

12-bit DAC 2
Number of channels 2

1 1 1 1
LCD 1 1 1
4x52 or 4x52 or 4x52 or 4x32 or
COM x SEG 4x18 4x32 or 8x28 4x18
8x48 8x48 8x48 8x28(2)

Comparators 2

Capacitive sensing
24 17 24 24 17 24 24
channels

Max. CPU frequency 32 MHz

Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 to 3.6 V without BOR option

Ambient temperature: –40 to +125 °C

Operating temperatures
Junction temperature: –40 to +130 °C
LQFP100, LQFP48, LQFP100, LQFP48, LQFP100, LQFP64,
Packages LQFP64
UFBGA100 UFQFPN48 UFBGA100 UFQFPN48 UFBGA100 TFBGA64

1. 4 SPI interfaces are USARTs operating in SPI master mode.

2. On TFBGA64, only 4x31 or 8x27 COMxSEG are available.

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Description STM32L083xx

Figure 1. STM32L083xx block diagram

Temp
SWD SWD sensor

FLASH
EEPROM
BOOT ADC1 AINx

MISO, MOSI,
FIREWALL SPI1
CORTEX M0+ CPU SCK, NSS
Fmax:32MHz RAM
USART1 RX, TX, RTS,
MPU DBG A CTS, CK
P
DMA1 TIM21 2ch
NVIC B
2
EXTI
TIM22 2ch

BRIDGE
COMP1 INP, INM, OUT
TSC
PA[0:15] GPIO PORT A
COMP2 INP, INM, OUT

PB[0:15] GPIO PORT B CRC

IN1, IN2,
BRIDGE LPTIM1 ETR, OUT

PC[0:15] GPIO PORT C RNG DP, DM, OE,

RAM 1K USB 2.0 FS CRS_SYNC,
VDD_USB
PD[0:15] GPIO PORT D TIM6 DAC1 OUT1
AHB: Fmax 32MHz

AES

TIM7 DAC2 OUT1

PE[0:15] GPIO PORT E
SCL, SDA,
I2C1
SMBA
WWDG
PH[0:1], [9:10] GPIO PORT H
I2C2 SCL, SDA

A SCL, SDA,
I2C3
P SMBA
B
1 RX, TX, RTS,
USART2
CTS, CK
HSI 48M CRS
OSC_IN, HSE HSI 16M RX, TX, RTS,
USART4
OSC_OUT CTS, CK
LSI IWDG RX, TX, RTS,
PLL USART5
CTS, CK
MSI RTC RX, TX, RTS,
LPUART1 CTS
MISO/MCK,
SPI2/I2S MOSI/SD,
BCKP REG
SCK/CK, NSS/
WKUPx RESET & CLK WS
TIM2 4ch

OSC32_IN, LSE
OSC32_OUT TIM3 4ch
PVD_IN
LCD COMx, SEGx,
VREF_OUT LCD_VLCDx
PMU
NRST

VDDA

VDD REGULATOR

MSv35432V1

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2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary
core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 ultra-low-power series are the best solution for applications such as
gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.

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Functional overview STM32L083xx

3 Functional overview

3.1 Low-power modes

The ultra-low-power STM32L083xx support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
• Range 1 (VDD range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
• Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
• Range 3 (full VDD range), with a maximum CPU frequency limited to 4.2 MHz
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
• Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the low-
speed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Low-
power run mode, the clock frequency and the number of enabled peripherals are both
limited.
• Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.

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• Stop mode without RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.
• Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
• Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire VCORE domain is powered off. The
PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode. The LCD is not stopped automatically by entering Stop
mode.

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Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply
range
Operating power supply
range(1)
DAC and ADC Dynamic voltage
USB
operation scaling range

ADC only, conversion Range 2 or

VDD = 1.65 to 1.71 V Not functional
time up to 570 ksps range 3
ADC only, conversion Range 1, range 2 or
VDD = 1.71 to 1.8 V(2) Functional(3)
time up to 1.14 Msps range 3
Conversion time up to Range1, range 2 or
VDD = 1.8 to 2.0 V(2) Functional(3)
1.14 Msps range 3
Conversion time up to Range 1, range 2 or
VDD = 2.0 to 2.4 V Functional(3)
1.14 Msps range 3
Conversion time up to Range 1, range 2 or
VDD = 2.4 to 3.6 V Functional(3)
1.14 Msps range 3
1. GPIO speed depends on VDD voltage range. Refer to Table 62: I/O AC characteristics for more information
about I/O speed.
2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
3. To be USB compliant from the I/O voltage standpoint, the minimum VDD_USB is 3.0 V.

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

Range 1
32 kHz to 16 MHz (0ws)
8 MHz to 16 MHz (1ws)
Range 2
32 kHz to 8 MHz (0ws)
32 kHz to 4.2 MHz (0ws) Range 3

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Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (1)(2)
Stop Standby
Low- Low-
IPs Run/Active Sleep power power
Wakeup Wakeup
run sleep
capability capability

CPU Y -- Y -- -- --
Flash memory O O O O -- --
RAM Y Y Y Y Y --
Backup registers Y Y Y Y Y Y
EEPROM O O O O -- --
Brown-out reset
O O O O O O O O
(BOR)
DMA O O O O -- --
Programmable
Voltage Detector O O O O O O -
(PVD)
Power-on/down
Y Y Y Y Y Y Y Y
reset (POR/PDR)
High Speed (3)
O O -- -- --
Internal (HSI)
High Speed
O O O O -- --
External (HSE)
Low Speed Internal
O O O O O O
(LSI)
Low Speed
O O O O O O
External (LSE)
Multi-Speed
O O Y Y -- --
Internal (MSI)
Inter-Connect
Y Y Y Y Y --
Controller
RTC O O O O O O O
RTC Tamper O O O O O O O O
Auto WakeUp
O O O O O O O O
(AWU)
LCD O O O O O --
USB O O -- -- -- O --
(4)
USART O O O O O O --
(4)
LPUART O O O O O O --
SPI O O O O -- --
I2C O O -- -- O(5) O --
ADC O O -- -- -- --

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Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (continued)(1)(2)
Stop Standby
Low- Low-
IPs Run/Active Sleep power power
Wakeup Wakeup
run sleep
capability capability

DAC O O O O O --
Temperature
O O O O O --
sensor
Comparators O O O O O O --
16-bit timers O O O O -- --
LPTIMER O O O O O O
IWDG O O O O O O O O
WWDG O O O O -- --
Touch sensing
O O -- -- -- --
controller (TSC)
SysTick Timer O O O O --
GPIOs O O O O O O 2 pins
Wakeup time to
0 µs 0.36 µs 3 µs 32 µs 3.5 µs 50 µs
Run mode
0.4 µA (No 0.28 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V

Down to Down to 0.8 µA (with 0.65 µA (with

Consumption RTC) V =1.8 V RTC) VDD=1.8 V
140 µA/MHz 37 µA/MHz Down to Down to DD
VDD=1.8 to 3.6 V
(from Flash (from Flash 8 µA 4.5 µA 0.4 µA (No 0.29 µA (No
(Typ)
memory) memory) RTC) VDD=3.0 V RTC) VDD=3.0 V
1 µA (with RTC) 0.85 µA (with
VDD=3.0 V RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.

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3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power

run, Low-power sleep and Stop modes.

Table 6. STM32L0xx peripherals interconnect matrix

Low- Low-
Interconnect Interconnect
Interconnect action Run Sleep power power Stop
source destination
run sleep

Timer input channel,

TIM2,TIM21,
trigger from analog Y Y Y Y -
TIM22
signals comparison
COMPx
Timer input channel,
LPTIM trigger from analog Y Y Y Y Y
signals comparison
Timer triggered by other
TIMx TIMx Y Y Y Y -
timer
Timer triggered by Auto
TIM21 Y Y Y Y -
wake-up
RTC
Timer triggered by RTC
LPTIM Y Y Y Y Y
event
Clock source used as
All clock input channel for RC
TIMx Y Y Y Y -
source measurement and
trimming
the clock recovery
CRS/HSI48 system trims the HSI48 Y Y - - -
USB based on USB SOF
USB_SOF is channel
TIM3 Y Y - - -
input for calibration
Timer input channel and
TIMx Y Y Y Y -
trigger
GPIO Timer input channel and
LPTIM Y Y Y Y Y
trigger
ADC,DAC Conversion trigger Y Y Y Y -

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3.3 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
• a simple architecture that is easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-
bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L083xx are compatible with all Arm tools and
software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L083xx embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a Non-Maskable Interrupt (NMI)
• provides zero jitter interrupt option
• provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load-
multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

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3.4 Reset and supply management

3.4.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
• VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
• VDD_USB = 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
VDD_USB must be above 3.0V. If USB is not used this pin must be tied to VDD or VSS.
On packages without VDD_USB pin, VDD_USB voltage is internally connected to VDD
voltage.

3.4.2 Power supply supervisor

The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

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3.4.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.
• MR is used in Run mode (nominal regulation)
• LPR is used in the Low-power run, Low-power sleep and Stop modes
• Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

3.5 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
• Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
• System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
– 1-25 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able
to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.
• Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the LCD controller and the
real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
• RTC and LCD clock source
The LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever
the system clock.
• USB clock source
A 48 MHz clock trimmed through the USB SOF or LSE supplies the USB interface.

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• Startup clock
After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
• Clock security system (CSS)
This feature can be enabled by software. If an HSE clock failure occurs, the master
clock is automatically switched to HSI and a software interrupt is generated if enabled.
Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.
• Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.

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Figure 2. Clock tree

@V33 Enable Watchdog
Watchdog LS Legend:
LSI RC LSI tempo HSE = High-speed external clock signal
HSI = High-speed internal clock signal
RTCSEL
LSI = Low-speed internal clock signal
RTC2 enable LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal
RTC
LSE OSC LSE tempo
LCD enable

LSU LSD LSD LSD

@V18 1 MHz
LCDCLK
@V33 MCOSEL ADC enable
LSI
MSI RC ADCCLK
MSI LSE
Level shifters
@V18 / 1,2,4,8,16 MCO
not deepsleep
/ 2,4,8,16
@V33 CK_PWR
not deepsleep
HSI16 RC
ck_rchs HSI16
Level shifters / 1,4 not (sleep or FCLK
@V18 deepsleep)
System
Clock not (sleep or HCLK
deepsleep)
/8
MSI SysTick
@V33 Timer
HSI16 AHB
HSE OSC PRESC
HSE PCLK1 to APB1
Level shifters PLLSRC / 1,2,…, 512 32 MHz peripherals
@V18 @V33
PLLCLK APB1 max.
ck_pllin PLL PRESC
LSU / 1,2,4,8,16
X
@V33 Peripheral
3,4,6,8,12,16,
clock enable
24,32,48 to TIMx
1 MHz Clock / 2,3,4 If (APB1 presc=1) x1
Detector Level shifters
else x2)
@VDDCORE Peripheral
LSD HSE present or not Clock clock enable
PCLK2 to APB2
Dedicated 48MHz PLL output Source 32 MHz peripherals
APB2 max.
HSI48MSEL
Control
PRESC
/ 1,2,4,8,16
Peripheral
@V33
clock enable
to TIMx
RC 48MHz HSI48 If (APB2 presc=1) x1
Level shifters else x2)
@V18 Peripheral
LSI
clock enable
Clock SYSCLK
Recovery
System LPTIMCLK
Peripheral
LSE
clock enable
HSI16

PCLK Peripheral LPUART/

clock enable UARTCLK

I2CCLK
usb_en 48MHz
USBCLK

rng_en
48MHz RNG

MSv35411V1

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3.6 Low-power real-time clock and backup registers

The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
• Two programmable alarms with wake up from Stop and Standby mode capability
• Periodic wakeup from Stop and Standby with programmable resolution and period
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
• 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 37 kHz)
• The high-speed external clock

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 29 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 84 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 13 other lines are connected to PVD, RTC,
USB, USARTs, I2C, LPUART, LPTIMER or comparator events.

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3.8 Memories
The STM32L083xx devices have the following features:
• 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
• The non-volatile memory is divided into three arrays:
– 64, 128 or 192 Kbytes of embedded Flash program memory
– 6 Kbytes of data EEPROM
– Information block containing 32 user and factory options bytes plus Kbytes of
system memory
Flash program and data EEPROM are divided into two banks. This allows writing in one
bank while running code or reading data from the other bank.
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
• Level 0: no protection
• Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
• Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the non-
volatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the
volatile data segment (RAM).
The whole non-volatile memory embeds the error correction code (ECC) feature.

3.9 Boot modes

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:
• Boot from Flash memory
• Boot from System memory
• Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USB (PA11, PA12), USART1(PA9, PA10) or USART2(PA2, PA3). See STM32™
microcontroller system memory boot mode AN2606 for details.

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3.10 Direct memory access (DMA)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: AES, SPI, I2C, USART, LPUART,
general-purpose timers, DAC, and ADC.

3.11 Liquid crystal display (LCD)

The LCD drives up to 8 common terminals and 48 segment terminals to drive up to 384
pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode
• VLCD rails decoupling capability

3.12 Analog-to-digital converter (ADC)

A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L083xx device. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference, VLCD voltage measurement).
Three channels, PA0, PA4 and PA5, are fast channels, while the others are standard
channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~240 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).

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Functional overview STM32L083xx

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

3.13 Temperature sensor

The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Table 7. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TSENSE_CAL1 temperature of 30 °C, 0x1FF8 007A - 0x1FF8 007B
VDDA= 3 V
TS ADC raw data acquired at
TSENSE_CAL2 temperature of 130 °C 0x1FF8 007E - 0x1FF8 007F
VDDA= 3 V

3.13.1 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available
for ADC). The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.

Table 8. Internal voltage reference measured values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 25 °C 0x1FF8 0078 - 0x1FF8 0079
VDDA = 3 V

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3.13.2 VLCD voltage monitoring

This embedded hardware feature allows the application to measure the VLCD supply voltage
using the internal ADC channel ADC_IN16. As the VLCD voltage may be higher than VDDA,
and thus outside the ADC input range, the ADC input is connected to LCD_VLCD1 (which
provides 1/3VLCD when the LCD is configured 1/3Bias and 1/4VLCD when the LCD is
configured 1/4Bias or 1/2Bias).

3.14 Digital-to-analog converter (DAC)

Two 12-bit buffered DACs can be used to convert digital signal into analog voltage signal
output. An optional amplifier can be used to reduce the output signal impedance.
This digital Interface supports the following features:
• One data holding register (for each channel)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channels with independent or simultaneous conversions
• DMA capability (including the underrun interrupt)
• External triggers for conversion
• Input reference voltage VREF+
Six DAC trigger inputs are used in the STM32L083xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.

3.15 Ultra-low-power comparators and reference voltage

The STM32L083xx embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
• One comparator with ultra low consumption
• One comparator with rail-to-rail inputs, fast or slow mode.
• The threshold can be one of the following:
– DAC output
– External I/O pins
– Internal reference voltage (VREFINT)
– submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).

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3.16 Touch sensing controller (TSC)

The STM32L083xx provide a simple solution for adding capacitive sensing functionality to
any application. These devices offer up to 24 capacitive sensing channels distributed over 8
analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.

Table 9. Capacitive sensing GPIOs available on STM32L083xx devices

Capacitive sensing Pin Capacitive sensing Pin
Group Group
signal name name signal name name

TSC_G1_IO1 PA0 TSC_G5_IO1 PB3

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4
1 5
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
(1)
TSC_G2_IO1 PA4 TSC_G6_IO1 PB11
TSC_G2_IO2 PA5 TSC_G6_IO2 PB12
2 6
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
TSC_G3_IO1 PC5 TSC_G7_IO1 PC0
TSC_G3_IO2 PB0 TSC_G7_IO2 PC1
3 7
TSC_G3_IO3 PB1 TSC_G7_IO3 PC2
TSC_G3_IO4 PB2 TSC_G7_IO4 PC3
TSC_G4_IO1 PA9 TSC_G8_IO1 PC6
TSC_G4_IO2 PA10 TSC_G8_IO2 PC7
4 8
TSC_G4_IO3 PA11 TSC_G8_IO3 PC8
TSC_G4_IO4 PA12 TSC_G8_IO4 PC9
1. This GPIO offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling
capacitor I/O.

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3.17 AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26).
• Key scheduler
• Key derivation for decryption
• 128-bit data block processed
• 128-bit key length
• 213 clock cycles to encrypt/decrypt one 128-bit block
• Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR)
supported by hardware.
The AES can be served by the DMA controller.

3.18 Timers and watchdogs

The ultra-low-power STM32L083xx devices include three general-purpose timers, one low-
power timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer.
Table 10 compares the features of the general-purpose and basic timers.

Table 10. Timer feature comparison

DMA
Counter Capture/compare Complementary
Timer Counter type Prescaler factor request
resolution channels outputs
generation

TIM2, Up, down, Any integer between

16-bit Yes 4 No
TIM3 up/down 1 and 65536
TIM21, Up, down, Any integer between
16-bit No 2 No
TIM22 up/down 1 and 65536
TIM6, Any integer between
16-bit Up Yes 0 No
TIM7 1 and 65536

3.18.1 General-purpose timers (TIM2, TIM3, TIM21 and TIM22)

There are four synchronizable general-purpose timers embedded in the STM32L083xx
device (see Table 10 for differences).

TIM2, TIM3
TIM2 and TIM3 are based on 16-bit auto-reload up/down counter. It includes a 16-bit
prescaler. It features four independent channels each for input capture/output compare,
PWM or one-pulse mode output.
The TIM2/TIM3 general-purpose timers can work together or with the TIM21 and TIM22
general-purpose timers via the Timer Link feature for synchronization or event chaining.
Their counter can be frozen in debug mode. Any of the general-purpose timers can be used
to generate PWM outputs.
TIM2/TIM3 have independent DMA request generation.

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These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

TIM21 and TIM22

TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit
prescaler. They have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work together and be synchronized with the TIM2/TIM3,
full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.

3.18.2 Low-power Timer (LPTIM)

The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one shot mode
• Selectable software / hardware input trigger
• Selectable clock source
– Internal clock source: LSE, LSI, HSI or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode

3.18.3 Basic timer (TIM6, TIM7)

These timers can be used as a generic 16-bit timebase.

3.18.4 SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.

3.18.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.

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3.18.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.19 Communication interfaces

3.19.1 I2C bus

Up to three I2C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes.
Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to
400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with
configurable mask) are also supported as well as programmable analog and digital noise
filters.

Table 11. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of Programmable length from 1 to 15

≥ 50 ns
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Wakeup from Stop on address
Variations depending on
Drawbacks match is not available when digital
temperature, voltage, process
filter is enabled.

In addition, I2C1 and I2C3 provide hardware support for SMBus 2.0 and PMBus 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1/I2C3 also have a clock domain
independent from the CPU clock, allowing the I2C1/I2C3 to wake up the MCU from Stop
mode on address match.
Each I2C interface can be served by the DMA controller.
Refer to Table 12 for an overview of I2C interface features.

Table 12. STM32L083xx I2C implementation

I2C features(1) I2C1 I2C2 I2C3

7-bit addressing mode X X X

10-bit addressing mode X X X
Standard mode (up to 100 kbit/s) X X X
Fast mode (up to 400 kbit/s) X X X

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Table 12. STM32L083xx I2C implementation (continued)

I2C features(1) I2C1 I2C2 I2C3

Fast Mode Plus with 20 mA output drive I/Os (up to 1

X X(2) X
Mbit/s)
Independent clock X - X
SMBus X - X
Wakeup from STOP X - X
1. X = supported.
2. See Table 16: STM32L083xx pin definition on page 42 for the list of I/Os that feature Fast Mode Plus
capability

3.19.2 Universal synchronous/asynchronous receiver transmitter (USART)

The four USART interfaces (USART1, USART2, USART4 and USART5) are able to
communicate at speeds of up to 4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE)
signals, multiprocessor communication mode, master synchronous communication and
single-wire half-duplex communication mode. USART1 and USART2 also support
SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto
baud rate feature and has a clock domain independent from the CPU clock, allowing to
wake up the MCU from Stop mode using baudrates up to 42 Kbaud.
All USART interfaces can be served by the DMA controller.
Table 13 for the supported modes and features of USART interfaces.

Table 13. USART implementation

USART modes/features(1) USART1 and USART2 USART4 and USART5

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode(2) X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wakeup from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection (4 modes) X -
Driver Enable X X
1. X = supported.
2. This mode allows using the USART as an SPI master.

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3.19.3 Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock. It can wake up the
system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop
mode are programmable and can be:
• Start bit detection
• Or any received data frame
• Or a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.

3.19.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The USARTs with synchronous capability can also be used as SPI master.
One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or
slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output
channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the
I2S interfaces is configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
The SPIs can be served by the DMA controller.
Refer to Table 14 for the differences between SPI1 and SPI2.

Table 14. SPI/I2S implementation

SPI features(1) SPI1 SPI2

Hardware CRC calculation X X

I2S mode - X
TI mode X X
1. X = supported.

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3.19.5 Universal serial bus (USB)

The STM32L083xx embed a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up to 1 Kbyte and suspend/resume support. It requires a
precise 48 MHz clock which can be generated from the internal main PLL (the clock source
must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming
mode. The synchronization for this oscillator can be taken from the USB data stream itself
(SOF signalization) which allows crystal-less operation.

3.20 Clock recovery system (CRS)

The STM32L083xx embed a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.

3.21 Cyclic redundancy check (CRC) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.

3.22 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.

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4 Pin descriptions

Figure 3. STM32L083xx LQFP100 pinout

BOOT0

PA15
PA14
PC12
PC11
PC10
PB7
PB6
VDD

PE 1

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB5
PB4
PB3
PE0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD_USB
PE3 2 74 VSS
PE4 3 73 VDD
PE5 4 72 PA13
PE6 5 71 PA12
VLCD 6 70 PA 11
PC13 7 VDD69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
PH9 10 66 PC9
PH10 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB 15
PA0 23 53 PB 14
PA1 24 52 PB 13
PA2 25 51 PB 12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE 10
PE 11
PE 12
PE 13
PE 14
PE 15
PB 10
PB 11
PA6
PA7
PA3

VSS
VDD

PB0
PB1
PB2
PC4
PC5

PE7
PE8
PE9

VDD
PA4
PA5
VSS

MSv35413V2

1. The above figure shows the package top view.

2. The I/O pins supplied by VDD_USB are shown in grey.

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Figure 4. STM32L083xx UFBGA100 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

C PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDD PA10

PC14-
D OSC32 PE6 VSS PA9 PA8 PC9
_IN
PC15-
E OSC32 VLCD VSS PC8 PC7 PC6
_OUT
PH0-
F PH9 VSS VSS
OSC_IN
PH1- VDD_
G OSC_ PH10 USB VDD
OUT

PC0 NRST VDD PD15 PD14 PD13

H

J VSSA PC1 PC2 PD12 PD11 PD10

K VREF
PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13
-

L VREF PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12
+

M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

MSv35414V3

1. The above figure shows the package top view.

2. The I/O pins supplied by VDD_USBare shown in grey.

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Figure 5. STM32L083xx LQFP64 pinout

BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VLCD 1 48 VDD_USB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0 -OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3

PA4
PA5
PA6
PA7

PB0
PB1
PB2
PC4
PC5

PB10
PB11
VDD
VSS

VDD
VSS
MS31485V3

1. The above figure shows the package top view.

2. The I/O pins supplied by VDD_USB are shown in grey.

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Pin descriptions STM32L083xx

Figure 6. STM32L083xx TFBGA64 ballout

1 2 3 4 5 6 7 8

PC14-
A OSC32 PC13 PB9 PB4 PB3 PA15 PA14 PA13
_IN

PC15-
BOOT
B OSC32 VLCD PB8 PD2 PC11 PC10 PA12
0
_OUT

PH0-
VSS PB7 PB5 PC12 PA10 PA9 PA11
C OSC_IN

PH1-
D OSC_ VDD PB6 VSS VSS VSS PA8 PC9
OUT

VDD_
E NRST PC1 PC0 VDD VDD
USB
PC7 PC8

VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14

F

G VREF PA0 PA3 PA6 PB1 PB2 PB10 PB13

+

H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12

MSv37829V2

1. The above figure shows the package top view.

2. the I/O pins supplied by VDD_USB are shown in grey.

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Figure 7. STM32L083xx LQFP48 pinout

BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VLCD 1 36 VDD_USB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 LQFP48 31 PA10
NRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24

PB10
PB11
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2

VDD
VSS
MS31484V3

1. The above figure shows the package top view.

2. The I/O pins supplied by VDD_USB are shown in grey.

Figure 8. STM32L083xx UFQFPN48

BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VLCD 1 36 VDD_USB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10

VSS
VDD
PA3
PA4
PA5
PA6
PA7

PB11

MSv62439V1

1. The above figure shows the package top view.

2. The I/O pins supplied by VDD_USB are shown in grey.

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Table 15. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and
Pin name
after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
I/O structure TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions

Table 16. STM32L083xx pin definition

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type

Pin name
UFBGA100

Note
TFBGA64

LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

- - - 1 B2 PE2 I/O FT - LCD_SEG38, TIM3_ETR -

TIM22_CH1,
- - - 2 A1 PE3 I/O FT - -
LCD_SEG39, TIM3_CH1
- - - 3 B1 PE4 I/O FT - TIM22_CH2, TIM3_CH2 -
- - - 4 C2 PE5 I/O FT - TIM21_CH1, TIM3_CH3 -
- - - 5 D2 PE6 I/O FT - TIM21_CH2, TIM3_CH4 RTC_TAMP3/WKUP3
1 1 B2 6 E2 VLCD S - -
RTC_TAMP1/RTC_TS/
2 2 A2 7 C1 PC13 I/O FT - -
RTC_OUT/WKUP2

42/149 DS10671 Rev 5

STM32L083xx Pin descriptions

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

PC14-
3 3 A1 8 D1 OSC32_IN I/O FT - - OSC32_IN
(PC14)
PC15-
4 4 B1 9 E1 OSC32_OUT I/O TC - - OSC32_OUT
(PC15)
- - - 10 F2 PH9 I/O FT - - -
- - - 11 G2 PH10 I/O FT - - -
PH0-OSC_IN
5 5 C1 12 F1 I/O TC - USB_CRS_SYNC OSC_IN
(PH0)
PH1-
6 6 D1 13 G1 OSC_OUT I/O TC - - OSC_OUT
(PH1)
7 7 E1 14 H2 NRST I/O - - - -
LPTIM1_IN1,
LCD_SEG18,
EVENTOUT,
- 8 E3 15 H1 PC0 I/O FTf - ADC_IN10
TSC_G7_IO1,
LPUART1_RX,
I2C3_SCL
LPTIM1_OUT,
LCD_SEG19,
EVENTOUT,
- 9 E2 16 J2 PC1 I/O FTf - ADC_IN11
TSC_G7_IO2,
LPUART1_TX,
I2C3_SDA
LPTIM1_IN2,
LCD_SEG20,
- 10 F2 17 J3 PC2 I/O FTf - ADC_IN12
SPI2_MISO/I2S2_MCK,
TSC_G7_IO3
LPTIM1_ETR,
LCD_SEG21,
- 11 - 18 K2 PC3 I/O FT - ADC_IN13
SPI2_MOSI/I2S2_SD,
TSC_G7_IO4

DS10671 Rev 5 43/149

57
Pin descriptions STM32L083xx

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

8 12 F1 19 J1 VSSA S - - - -
- - - 20 K1 VREF- S - - - -
- - G1 21 L1 VREF+ S - - - -
9 13 H1 22 M1 VDDA S - - - -
TIM2_CH1,
TSC_G1_IO1,
COMP1_INM,
USART2_CTS,
10 14 G2 23 L2 PA0 I/O TC - ADC_IN0,
TIM2_ETR,
RTC_TAMP2/WKUP1
USART4_TX,
COMP1_OUT
EVENTOUT,
LCD_SEG0, TIM2_CH2,
TSC_G1_IO2,
11 15 H2 24 M2 PA1 I/O FT - USART2_RTS/ COMP1_INP, ADC_IN1
USART2_DE,
TIM21_ETR,
USART4_RX
TIM21_CH1,
LCD_SEG1, TIM2_CH3,
TSC_G1_IO3, COMP2_INM,
12 16 F3 25 K3 PA2 I/O FT -
USART2_TX, ADC_IN2
LPUART1_TX,
COMP2_OUT
TIM21_CH2,
LCD_SEG2, TIM2_CH4,
13 17 G3 26 L3 PA3 I/O FT - TSC_G1_IO4, COMP2_INP, ADC_IN3
USART2_RX,
LPUART1_RX
- 18 C2 27 E3 VSS S - - - -
- 19 D2 28 H3 VDD S - - - -
SPI1_NSS,
COMP1_INM,
(1) TSC_G2_IO1,
14 20 H3 29 M3 PA4 I/O TC COMP2_INM,
USART2_CK,
ADC_IN4, DAC_OUT1
TIM22_ETR

44/149 DS10671 Rev 5

STM32L083xx Pin descriptions

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

SPI1_SCK, TIM2_ETR, COMP1_INM,

15 21 F4 30 K4 PA5 I/O TC - TSC_G2_IO2, COMP2_INM,
TIM2_CH1 ADC_IN5, DAC_OUT2
SPI1_MISO,
LCD_SEG3, TIM3_CH1,
TSC_G2_IO3,
16 22 G4 31 L4 PA6 I/O FT - LPUART1_CTS, ADC_IN6
TIM22_CH1,
EVENTOUT,
COMP1_OUT
SPI1_MOSI,
LCD_SEG4, TIM3_CH2,
TSC_G2_IO4,
17 23 H4 32 M4 PA7 I/O FT - ADC_IN7
TIM22_CH2,
EVENTOUT,
COMP2_OUT
EVENTOUT,
- 24 H5 33 K5 PC4 I/O FT - LCD_SEG22, ADC_IN14
LPUART1_TX
LCD_SEG23,
- 25 H6 34 L5 PC5 I/O FT - LPUART1_RX, ADC_IN15
TSC_G3_IO1
EVENTOUT,
LCD_VLCD3,
18 26 F5 35 M5 PB0 I/O FT - LCD_SEG5, TIM3_CH3,
ADC_IN8, VREF_OUT
TSC_G3_IO2
LCD_SEG6, TIM3_CH4,
TSC_G3_IO3,
19 27 G5 36 M6 PB1 I/O FT - ADC_IN9, VREF_OUT
LPUART1_RTS/
LPUART1_DE
LPTIM1_OUT,
20 28 G6 37 L6 PB2 I/O FT - TSC_G3_IO4, LCD_VLCD2
I2C3_SMBA
LCD_SEG45,
USART5_CK/
- - - 38 M7 PE7 I/O FT - -
USART5_RTS/
USART5_DE

DS10671 Rev 5 45/149

57
Pin descriptions STM32L083xx

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

LCD_SEG46,
- - - 39 L7 PE8 I/O FT - -
USART4_TX
TIM2_CH1,
LCD_SEG47,
- - - 40 M8 PE9 I/O FT - -
TIM2_ETR,
USART4_RX
TIM2_CH2,
- - - 41 L8 PE10 I/O FT - LCD_SEG40, -
USART5_TX
TIM2_CH3,
- - - 42 M9 PE11 I/O FT - LCD_VLCD1
USART5_RX
- - - 43 L9 PE12 I/O FT - TIM2_CH4, SPI1_NSS LCD_VLCD3
- - - 44 M10 PE13 I/O FT - LCD_SEG41, SPI1_SCK -
LCD_SEG42,
- - - 45 M11 PE14 I/O FT - -
SPI1_MISO
LCD_SEG43,
- - - 46 M12 PE15 I/O FT - -
SPI1_MOSI
LCD_SEG10,
TIM2_CH3, TSC_SYNC,
21 29 G7 47 L10 PB10 I/O FT - LPUART1_TX, -
SPI2_SCK, I2C2_SCL,
LPUART1_RX
EVENTOUT,
LCD_SEG11,
TIM2_CH4,
22 30 H7 48 L11 PB11 I/O FT - TSC_G6_IO1, -
LPUART1_RX,
I2C2_SDA,
LPUART1_TX
23 31 D6 49 F12 VSS S - - -
24 32 E5 50 G12 VDD S - - -

46/149 DS10671 Rev 5

STM32L083xx Pin descriptions

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

SPI2_NSS/I2S2_WS,
LCD_SEG12,
LPUART1_RTS/
25 33 H8 51 L12 PB12 I/O FT - LPUART1_DE, LCD_VLCD1
TSC_G6_IO2,
I2C2_SMBA,
EVENTOUT
SPI2_SCK/I2S2_CK,
LCD_SEG13, MCO,
26 34 G8 52 K12 PB13 I/O FTf - TSC_G6_IO3, -
LPUART1_CTS,
I2C2_SCL, TIM21_CH1
SPI2_MISO/I2S2_MCK,
LCD_SEG14, RTC_OUT,
TSC_G6_IO4,
27 35 F8 53 K11 PB14 I/O FTf - -
LPUART1_RTS/
LPUART1_DE,
I2C2_SDA, TIM21_CH2
SPI2_MOSI/I2S2_SD,
28 36 F7 54 K10 PB15 I/O FT - LCD_SEG15, -
RTC_REFIN
LPUART1_TX,
- - - 55 K9 PD8 I/O FT - -
LCD_SEG28
LPUART1_RX,
- - - 56 K8 PD9 I/O FT - -
LCD_SEG29
- - - 57 J12 PD10 I/O FT - LCD_SEG30 -
LPUART1_CTS,
- - - 58 J11 PD11 I/O FT - -
LCD_SEG31
LPUART1_RTS/
- - - 59 J10 PD12 I/O FT - LPUART1_DE, -
LCD_SEG32
- - - 60 H12 PD13 I/O FT - LCD_SEG33 -
- - - 61 H11 PD14 I/O FT - LCD_SEG34 -

DS10671 Rev 5 47/149

57
Pin descriptions STM32L083xx

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

USB_CRS_SYNC,
- - - 62 H10 PD15 I/O FT - -
LCD_SEG35
TIM22_CH1,
LCD_SEG24,
- 37 F6 63 E12 PC6 I/O FT - -
TIM3_CH1,
TSC_G8_IO1
TIM22_CH2,
LCD_SEG25,
- 38 E7 64 E11 PC7 I/O FT - -
TIM3_CH2,
TSC_G8_IO2
TIM22_ETR,
LCD_SEG26,
- 39 E8 65 E10 PC8 I/O FT - -
TIM3_CH3,
TSC_G8_IO3
TIM21_ETR,
LCD_SEG27,
- 40 D8 66 D12 PC9 I/O FTf - USB_NOE/TIM3_CH4, -
TSC_G8_IO4,
I2C3_SDA
MCO, LCD_COM0,
USB_CRS_SYNC,
29 41 D7 67 D11 PA8 I/O FTf - -
EVENTOUT,
USART1_CK, I2C3_SCL
MCO, LCD_COM1,
TSC_G4_IO1,
30 42 C7 68 D10 PA9 I/O FTf - -
USART1_TX, I2C1_SCL,
I2C3_SMBA
LCD_COM2,
31 43 C6 69 C12 PA10 I/O FTf - TSC_G4_IO2, -
USART1_RX, I2C1_SDA
SPI1_MISO,
EVENTOUT,
(2)
32 44 C8 70 B12 PA11 I/O FT TSC_G4_IO3, USB_DM
USART1_CTS,
COMP1_OUT

48/149 DS10671 Rev 5

STM32L083xx Pin descriptions

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

SPI1_MOSI,
EVENTOUT,
(2) TSC_G4_IO4,
33 45 B8 71 A12 PA12 I/O FT USB_DP
USART1_RTS/
USART1_DE,
COMP2_OUT
SWDIO, USB_NOE,
34 46 A8 72 A11 PA13 I/O FT - -
LPUART1_RX
- - - 73 C11 VDD S - - -
35 47 D5 74 F11 VSS S - - -
36 48 E6 75 G11 VDD_USB S - - -
SWCLK, USART2_TX,
37 49 A7 76 A10 PA14 I/O FT - -
LPUART1_TX
SPI1_NSS,
LCD_SEG17,
TIM2_ETR, EVENTOUT,
38 50 A6 77 A9 PA15 I/O FT - USART2_RX, -
TIM2_CH1,
USART4_RTS/
USART4_DE
LPUART1_TX,
LCD_COM4/LCD_SEG2
- 51 B7 78 B11 PC10 I/O FT - -
8/LCD_SEG48,
USART4_TX
LPUART1_RX,
LCD_COM5/LCD_SEG2
- 52 B6 79 C10 PC11 I/O FT - -
9/LCD_SEG49,
USART4_RX
LCD_COM6/LCD_SEG3
0/LCD_SEG50,
- 53 C5 80 B10 PC12 I/O FT - -
USART5_TX,
USART4_CK
TIM21_CH1,
- - - 81 C9 PD0 I/O FT - -
SPI2_NSS/I2S2_WS

DS10671 Rev 5 49/149

57
Pin descriptions STM32L083xx

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

- - - 82 B9 PD1 I/O FT - SPI2_SCK/I2S2_CK -

LPUART1_RTS/
LPUART1_DE,
LCD_COM7/LCD_SEG3
- 54 B5 83 C8 PD2 I/O FT - -
1/LCD_SEG51,
TIM3_ETR,
USART5_RX
USART2_CTS,
- - - 84 B8 PD3 I/O FT - LCD_SEG44, -
SPI2_MISO/I2S2_MCK
USART2_RTS/
- - - 85 B7 PD4 I/O FT - USART2_DE, -
SPI2_MOSI/I2S2_SD
- - - 86 A6 PD5 I/O FT - USART2_TX -
- - - 87 B6 PD6 I/O FT - USART2_RX -
USART2_CK,
- - - 88 A5 PD7 I/O FT - -
TIM21_CH2
SPI1_SCK, LCD_SEG7,
TIM2_CH2,
TSC_G5_IO1,
39 55 A5 89 A8 PB3 I/O FT - EVENTOUT, COMP2_INM
USART1_RTS/
USART1_DE,
USART5_TX
SPI1_MISO,
LCD_SEG8, TIM3_CH1,
TSC_G5_IO2,
40 56 A4 90 A7 PB4 I/O FTf - COMP2_INP
TIM22_CH1,
USART1_CTS,
USART5_RX, I2C3_SDA

50/149 DS10671 Rev 5

STM32L083xx Pin descriptions

Table 16. STM32L083xx pin definition (continued)

Pin number
LQFP48/UFQFPN48

I/O structure
Pin type
UFBGA100 Pin name
TFBGA64

Note
LQFP100
LQFP64

(function Alternate functions Additional functions

after reset)

SPI1_MOSI,
LCD_SEG9,
LPTIM1_IN1,
I2C1_SMBA,
41 57 C4 91 C5 PB5 I/O FT - TIM3_CH2/TIM22_CH2, COMP2_INP
USART1_CK,
USART5_CK,
USART5_RTS/
USART5_DE
USART1_TX, I2C1_SCL,
42 58 D3 92 B5 PB6 I/O FTf - LPTIM1_ETR, COMP2_INP
TSC_G5_IO3
USART1_RX,
I2C1_SDA, LPTIM1_IN2,
43 59 C3 93 B4 PB7 I/O FTf - COMP2_INP, PVD_IN
TSC_G5_IO4,
USART4_CTS
44 60 B4 94 A4 BOOT0 I - - -
LCD_SEG16,
45 61 B3 95 A3 PB8 I/O FTf - -
TSC_SYNC, I2C1_SCL
LCD_COM3,
46 62 A3 96 B3 PB9 I/O FTf - EVENTOUT, I2C1_SDA, -
SPI2_NSS/I2S2_WS
LCD_SEG36,
- - - 97 C3 PE0 I/O FT - -
EVENTOUT
LCD_SEG37,
- - - 98 A2 PE1 I/O FT - -
EVENTOUT
47 63 D4 99 D3 VSS S - - - -
48 64 E4 100 C4 VDD S - - - -
1. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
2. These pins are powered by VDD_USB. For all characteristics that refer to VDD, VDD_USB must be used instead.

DS10671 Rev 5 51/149

57
 Pin descriptions
52/149
Table 17. Alternate functions port A
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/I2S2/
SPI1/SPI2/I2S2/ I2C1/2/
USART1/2/
LPUART1/ I2C1/USART1/2 LPUART1/
Port LPUART1/USB/ SPI1/SPI2/I2S2/ SPI2/I2S2/I2C2/ I2C3/LPUART1/
USART5/USB/L I2C1/TSC/ /LPUART1/ USART4/
LPTIM1/TSC/ I2C1/LCD/ USART1/ COMP1/2/
PTIM1/TIM2/3/E EVENTOUT TIM3/22/ UASRT5/TIM21
TIM2/21/22/ TIM2/21 TIM2/21/22 TIM3
VENTOUT/ EVENTOUT /
EVENTOUT/
SYS_AF EVENTOUT
SYS_AF

PA0 - - TIM2_CH1 TSC_G1_IO1 USART2_CTS TIM2_ETR USART4_TX COMP1_OUT

USART2_RTS/
PA1 EVENTOUT LCD_SEG0 TIM2_CH2 TSC_G1_IO2 TIM21_ETR USART4_RX -
USART2_DE
PA2 TIM21_CH1 LCD_SEG1 TIM2_CH3 TSC_G1_IO3 USART2_TX - LPUART1_TX COMP2_OUT
PA3 TIM21_CH2 LCD_SEG2 TIM2_CH4 TSC_G1_IO4 USART2_RX - LPUART1_RX -
DS10671 Rev 5

PA4 SPI1_NSS - - TSC_G2_IO1 USART2_CK TIM22_ETR - -

PA5 SPI1_SCK - TIM2_ETR TSC_G2_IO2 TIM2_CH1 - -
PA6 SPI1_MISO LCD_SEG3 TIM3_CH1 TSC_G2_IO3 LPUART1_CTS TIM22_CH1 EVENTOUT COMP1_OUT
PA7 SPI1_MOSI LCD_SEG4 TIM3_CH2 TSC_G2_IO4 - TIM22_CH2 EVENTOUT COMP2_OUT
Port A

USB_CRS_
PA8 MCO LCD_COM0 EVENTOUT USART1_CK - - I2C3_SCL
SYNC
PA9 MCO LCD_COM1 - TSC_G4_IO1 USART1_TX - I2C1_SCL I2C3_SMBA
PA10 - LCD_COM2 - TSC_G4_IO2 USART1_RX - I2C1_SDA -
PA11 SPI1_MISO - EVENTOUT TSC_G4_IO3 USART1_CTS - - COMP1_OUT
USART1_RTS/
PA12 SPI1_MOSI - EVENTOUT TSC_G4_IO4 - - COMP2_OUT
USART1_DE
PA13 SWDIO - USB_NOE - - - LPUART1_RX -

STM32L083xx
PA14 SWCLK - - - USART2_TX - LPUART1_TX -
USART4_RTS/
PA15 SPI1_NSS LCD_SEG17 TIM2_ETR EVENTOUT USART2_RX TIM2_CH1 -
USART4_DE
 Table 18. Alternate functions port B

STM32L083xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/I2S2/
SPI1/SPI2/I2S2/
USART1/2/ I2C1/2/
LPUART1/ I2C1/USART1/2/
Port LPUART1/USB/ SPI1/SPI2/I2S2/I SPI2/I2S2/I2C2/ LPUART1/ I2C3/LPUART1/
USART5/USB/L I2C1/TSC/ LPUART1/
LPTIM1/TSC/ 2C1/LCD/ USART1/ USART4/ COMP1/2/
PTIM1/TIM2/3/E EVENTOUT TIM3/22/
TIM2/21/22/ TIM2/21 TIM2/21/22 UASRT5/TIM21/ TIM3
VENTOUT/ EVENTOUT
EVENTOUT/ EVENTOUT
SYS_AF
SYS_AF

PB0 EVENTOUT LCD_SEG5 TIM3_CH3 TSC_G3_IO2 - - - -

LPUART1_RTS/
PB1 - LCD_SEG6 TIM3_CH4 TSC_G3_IO3 - - -
LPUART1_DE

PB2 - - LPTIM1_OUT TSC_G3_IO4 - - - I2C3_SMBA

USART1_RTS/
PB3 SPI1_SCK LCD_SEG7 TIM2_CH2 TSC_G5_IO1 EVENTOUT USART5_TX -
USART1_DE
DS10671 Rev 5

PB4 SPI1_MISO LCD_SEG8 TIM3_CH1 TSC_G5_IO2 TIM22_CH1 USART1_CTS USART5_RX I2C3_SDA

USART5_CK,
TIM3_CH2/
PB5 SPI1_MOSI LCD_SEG9 LPTIM1_IN1 I2C1_SMBA USART1_CK USART5_RTS/ -
TIM22_CH2
USART5_DE

PB6 USART1_TX I2C1_SCL LPTIM1_ETR TSC_G5_IO3 - - - -

PB7 USART1_RX I2C1_SDA LPTIM1_IN2 TSC_G5_IO4 - - USART4_CTS -
Port B

PB8 - LCD_SEG16 - TSC_SYNC I2C1_SCL - - -

SPI2_NSS/
PB9 - LCD_COM3 EVENTOUT - I2C1_SDA - -
I2S2_WS

PB10 - LCD_SEG10 TIM2_CH3 TSC_SYNC LPUART1_TX SPI2_SCK I2C2_SCL LPUART1_RX

PB11 EVENTOUT LCD_SEG11 TIM2_CH4 TSC_G6_IO1 LPUART1_RX - I2C2_SDA LPUART1_TX

LPUART1_RTS/
PB12 SPI2_NSS/I2S2_WS LCD_SEG12 TSC_G6_IO2 I2C2_SMBA EVENTOUT -
LPUART1_DE

Pin descriptions
PB13 SPI2_SCK/I2S2_CK LCD_SEG13 MCO TSC_G6_IO3 LPUART1_CTS I2C2_SCL TIM21_CH1 -
SPI2_MISO/ LPUART1_RTS/
PB14 LCD_SEG14 RTC_OUT TSC_G6_IO4 I2C2_SDA TIM21_CH2 -
I2S2_MCK LPUART1_DE

SPI2_MOSI/
PB15 LCD_SEG15 RTC_REFIN - - - - -
53/149

I2S2_SD
 Table 19. Alternate functions port C

Pin descriptions
54/149 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/I2S2/
USART1/2/ SPI1/SPI2/I2S2/ I2C1/2/
I2C1/USART1/2/ SPI2/I2S2
Port LPUART1/USB/ SPI1/SPI2/I2S2/I2C1/ LPUART1/ LPUART1/ I2C3/LPUART1/
I2C1/TSC/ LPUART1/ /I2C2/
LPTIM1/TSC/ LCD/ USART5/USB/ USART4/ COMP1/2/
EVENTOUT TIM3/22/ USART1/
TIM2/21/22/ TIM2/21 LPTIM1/TIM2/3 UASRT5/TIM21/E TIM3
EVENTOUT TIM2/21/22
EVENTOUT/ /EVENTOUT/SYS_AF VENTOUT
SYS_AF

PC0 LPTIM1_IN1 LCD_SEG18 EVENTOUT TSC_G7_IO1 LPUART1_RX I2C3_SCL

PC1 LPTIM1_OUT LCD_SEG19 EVENTOUT TSC_G7_IO2 LPUART1_TX I2C3_SDA

SPI2_MISO/
PC2 LPTIM1_IN2 LCD_SEG20 TSC_G7_IO3
I2S2_MCK

SPI2_MOSI/
PC3 LPTIM1_ETR LCD_SEG21 TSC_G7_IO4
I2S2_SD
DS10671 Rev 5

PC4 EVENTOUT LCD_SEG22 LPUART1_TX

PC5 LCD_SEG23 LPUART1_RX TSC_G3_IO1

PC6 TIM22_CH1 LCD_SEG24 TIM3_CH1 TSC_G8_IO1

PC7 TIM22_CH2 LCD_SEG25 TIM3_CH2 TSC_G8_IO2

Port C

PC8 TIM22_ETR LCD_SEG26 TIM3_CH3 TSC_G8_IO3

PC9 TIM21_ETR LCD_SEG27 USB_NOE/TIM3_CH4 TSC_G8_IO4 I2C3_SDA

LCD_COM4/LCD_SEG
PC10 LPUART1_TX USART4_TX
28/LCD_SEG48

LCD_COM5/LCD_SEG
PC11 LPUART1_RX USART4_RX
29/LCD_SEG49

LCD_COM6/LCD_SEG
PC12 USART5_TX USART4_CK
30/LCD_SEG50

PC13

PC14

STM32L083xx
PC15
 Table 20. Alternate functions port D

STM32L083xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/I2S2/
SPI1/SPI2/I2S2/
USART1/2/ I2C1/2/
LPUART1/ I2C1/USART1/2/ SPI2/I2S2
Port LPUART1/USB/ LPUART1/
SPI1/SPI2/I2S2/I2C1/ USART5/USB/ I2C1/TSC/ LPUART1/ /I2C2/ I2C3/LPUART1/
LPTIM1/TSC/ USART4/
LCD/TIM2/21 LPTIM1/TIM2/3 EVENTOUT TIM3/22/ USART1/ COMP1/2/TIM3
TIM2/21/22/ UASRT5/TIM21/E
/EVENTOUT/ EVENTOUT TIM2/21/22
EVENTOUT/ VENTOUT
SYS_AF
SYS_AF

PD0 TIM21_CH1 SPI2_NSS/I2S2_WS - - - - - -

PD1 - SPI2_SCK/I2S2_CK - - - - - -
LCD_COM7/
LPUART1_RTS/
PD2 LCD_SEG31/ TIM3_ETR - - - USART5_RX -
LPUART1_DE
LCD_SEG51

SPI2_MISO/
PD3 USART2_CTS LCD_SEG44 - - - - -
I2S2_MCK
DS10671 Rev 5

USART2_RTS/
PD4 SPI2_MOSI/I2S2_SD - - - - - -
USART2_DE

PD5 USART2_TX - - - - - - -

PD6 USART2_RX - - - - - - -
Port D

PD7 USART2_CK TIM21_CH2 - - - - - -

PD8 LPUART1_TX LCD_SEG28 - - - - - -

PD9 LPUART1_RX LCD_SEG29 - - - - - -

PD10 - LCD_SEG30 - - - - - -

PD11 LPUART1_CTS LCD_SEG31 - - - - - -

LPUART1_RTS/
PD12 LCD_SEG32 - - - - - -
LPUART1_DE

PD13 - LCD_SEG33 - - - - - -

Pin descriptions
PD14 - LCD_SEG34 - - - - - -

PD15 USB_CRS_SYNC LCD_SEG35 - - - - - -

55/149
 Table 21. Alternate functions port E

Pin descriptions
56/149 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/I2S2/
SPI1/SPI2/I2S2/
USART1/2/ I2C1/2/
LPUART1/ I2C1/USART1/2/ SPI2/I2S2
Port LPUART1/USB/ LPUART1/
SPI1/SPI2/I2S2/I2C1 USART5/USB/ I2C1/TSC/ LPUART1/ /I2C2/ I2C3/LPUART1/
LPTIM1/TSC/ USART4/
/LCD/TIM2/21 LPTIM1/TIM2/3 EVENTOUT TIM3/22/ USART1/ COMP1/2/TIM3
TIM2/21/22/ UASRT5/TIM21/
/EVENTOUT/ EVENTOUT TIM2/21/22
EVENTOUT/ EVENTOUT
SYS_AF
SYS_AF

PE0 - LCD_SEG36 EVENTOUT - - - - -

PE1 - LCD_SEG37 EVENTOUT - - - - -

PE2 - LCD_SEG38 TIM3_ETR - - - - -

PE3 TIM22_CH1 LCD_SEG39 TIM3_CH1 - - - - -

PE4 TIM22_CH2 - TIM3_CH2 - - - - -

PE5 TIM21_CH1 - TIM3_CH3 - - - - -

DS10671 Rev 5

PE6 TIM21_CH2 - TIM3_CH4 - - - - -

USART5_CK,
PE7 - LCD_SEG45 - - - - USART5_RTS/ -
Port E

USART5_DE

PE8 - LCD_SEG46 - - - - USART4_TX -

PE9 TIM2_CH1 LCD_SEG47 TIM2_ETR - - - USART4_RX -

PE10 TIM2_CH2 LCD_SEG40 - - - - USART5_TX -

PE11 TIM2_CH3 - - - - - USART5_RX -

PE12 TIM2_CH4 - SPI1_NSS - - - - -

PE13 - LCD_SEG41 SPI1_SCK - - - - -

PE14 - LCD_SEG42 SPI1_MISO - - - - -

PE15 - LCD_SEG43 SPI1_MOSI - - - - -

STM32L083xx
 Table 22. Alternate functions port H

STM32L083xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/SPI2/
SPI1/SPI2/I2S2/
I2S2/USART1/2/ I2C1/2/
LPUART1/ I2C1/USART1/2/ I2C3/
Port LPUART1/USB/ SPI2/I2S2/I2C2/ LPUART1/
SPI1/SPI2/I2S2 USART5/USB/ I2C1/TSC/ LPUART1/ LPUART1/
LPTIM1/TSC/ USART1/ USART4/
/I2C1/LCD/TIM2/21 LPTIM1/TIM2/3/ EVENTOUT TIM3/22/ COMP1/2/
TIM2/21/22/ TIM2/21/22 UASRT5/TIM21/
EVENTOUT/ EVENTOUT TIM3
EVENTOUT/ EVENTOUT
SYS_AF
SYS_AF

PH0 USB_CRS_SYNC - - - - - - -
Port H

PH1 - - - - - - - -
DS10671 Rev 5

Pin descriptions
57/149
Memory mapping STM32L083xx

5 Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.

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STM32L083xx Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

MCU pin MCU pin

C = 50 pF
VIN

ai17851c ai17852c

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Electrical characteristics STM32L083xx

6.1.6 Power supply scheme

Figure 11. Power supply scheme

Standby-power circuitry
(OSC32,RTC,Wake-up
logic, RTC backup
registers)

Level shifter
OUT
IO
GP I/Os Logic Kernel logic
IN
(CPU,
Digital &
VDD Memories)

VDD
Regulator
N × 100 nF
+ 1 × 10 μF
VSS
VDDA
VDDA
VREF
VREF+
100 nF Analog:
+ 1 μF 100 nF ADC/ RC,PLL,COMP,
VREF- DAC ….
+ 1 μF

VSSA

VLCD
VSS LCD
VSS
USB
VDD_USB transceiver

MSv33790V1

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6.1.7 Optional LCD power supply scheme

Figure 12. Optional LCD power supply scheme

VDD VSEL

VDD Step-up
N x 100 nF Converter
+ 1 x 10 μF

Option 1 VLCD

100 nF LCD
VLCD

Option 2
CEXT

VSS

MSv33791V1

1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.

6.1.8 Current consumption measurement

Figure 13. Current consumption measurement scheme

VDDA
IDD

NxVDD

N × 100 nF
+ 1 × 10 μF
NxVSS

MSv34711V1

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Electrical characteristics STM32L083xx

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 23: Voltage characteristics,
Table 24: Current characteristics, and Table 25: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.

Table 23. Voltage characteristics

Symbol Definition Min Max Unit

External main supply voltage

VDD–VSS –0.3 4.0
(including VDDA, VDD_USB, VDD)(1)
Input voltage on FT and FTf pins VSS −0.3 VDD+4.0
V
Input voltage on TC pins VSS −0.3 4.0
VIN(2)
Input voltage on BOOT0 VSS VDD + 4.0
Input voltage on any other pin VSS − 0.3 4.0
|ΔVDD| Variations between different VDDx power pins - 50
Variations between any VDDx and VDDA power
|VDDA-VDDx| - 300
pins(3) mV
Variations between all different ground pins
|ΔVSS| - 50
including VREF- pin
VREF+ –VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
Electrostatic discharge voltage
VESD(HBM) see Section 6.3.11
(human body model)
1. All main power (VDD,VDD_USB, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 24 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. VDD_USB is independent
from VDD and VDDA: its value does not need to respect this rule.

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Table 24. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD(2) Total current into sum of all VDD power lines (source)(1) 105
ΣIVSS(2) Total current out of sum of all VSS ground lines (sink) (1)
105
ΣIVDD_USB Total current into VDD_USB power lines (source) 25
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
(1)
IVSS(PIN) Maximum current out of each VSS ground pin (sink) 100
Output current sunk by any I/O and control pin except FTf
16
pins
IIO
Output current sunk by FTf pins 22
Output current sourced by any I/O and control pin -16
mA
Total output current sunk by sum of all IOs and control pins
90
except PA11 and PA12(2)
ΣIIO(PIN) Total output current sunk by PA11 and PA12 25
Total output current sourced by sum of all IOs and control
-90
pins(2)
Injected current on FT, FTf, RST and B pins -5/+0(3)
IINJ(PIN)
Injected current on TC pin ± 5(4)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 23 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 23: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 25. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

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Electrical characteristics STM32L083xx

6.3 Operating conditions

6.3.1 General operating conditions

Table 26. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 32

fPCLK1 Internal APB1 clock frequency - 0 32 MHz
fPCLK2 Internal APB2 clock frequency - 0 32
BOR detector disabled 1.65 3.6
VDD Standard operating voltage BOR detector enabled, at power-on 1.8 3.6 V
BOR detector disabled, after power-on 1.65 3.6
Analog operating voltage (DAC not
VDDA Must be the same voltage as VDD(1) 1.65 3.6 V
used)
Analog operating voltage (all
VDDA Must be the same voltage as VDD(1) 1.8 3.6 V
features)

VDD_ Standard operating voltage, USB USB peripheral used 3.0 3.6
V
USB domain(2) USB peripheral not used 0 3.6

Input voltage on FT, FTf and RST 2.0 V ≤VDD ≤3.6 V -0.3 5.5
pins(3) 1.65 V ≤VDD ≤2.0 V -0.3 5.2
VIN V
Input voltage on BOOT0 pin - 0 5.5
Input voltage on TC pin - -0.3 VDD+0.3
UFBGA100 - 351
LQFP100 - 488

Power dissipation at TA = 85 °C TFBGA64 - 313

(range 6) or TA = 105 °C (range 7) (4) LQFP64 - 435
LQFP48 - 370
UFQFPN48 714
PD mW
UFBGA100 - 88
LQFP100 - 122

Power dissipation at TA = 125 °C TFBGA64 - 78

(range 3) (4) LQFP64 - 109
LQFP48 93
UFQFPN48 -- 179

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STM32L083xx Electrical characteristics

Table 26. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Maximum power dissipation (range 6) –40 85

TA Temperature range Maximum power dissipation (range 7) –40 105
Maximum power dissipation (range 3) –40 125
°C
Junction temperature range (range 6) -40 °C ≤TA ≤85 ° –40 105
TJ Junction temperature range (range 7) -40 °C ≤TA ≤105 °C –40 125
Junction temperature range (range 3) -40 °C ≤TA ≤125 °C –40 130
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and normal operation.
2. VDD_USB must respect the following conditions:
- When VDD is powered-on (VDD < VDD_min), VDD_USB should be always lower than VDD.
- When VDD is powered-down (VDD < VDD_min), VDD_USB should be always lower than VDD.
- In operating mode, VDD_USB could be lower or higher VDD.
- If the USB is not used, VDD_USB must range from VDD_min to VDD_max to be able to use PA11 and PA12 as standard I/Os.
- If the USB is not used and PA11/PA12 are not used as standard I/Os, VDD_USB must be connected to a VSS or VDD power
supply voltage (VDD_USB must not be left floating).
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 90: Thermal characteristics on
page 142).

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Electrical characteristics STM32L083xx

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 26.

Table 27. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

BOR detector enabled 0 - ∞

VDD rise time rate
BOR detector disabled 0 - 1000
tVDD(1) µs/V
BOR detector enabled 20 - ∞
VDD fall time rate
BOR detector disabled 0 - 1000
VDD rising, BOR enabled - 2 3.3
TRSTTEMPO(1) Reset temporization ms
VDD rising, BOR disabled(2) 0.4 0.7 1.6

Power-on/power down reset Falling edge 1 1.5 1.65

VPOR/PDR
threshold Rising edge 1.3 1.5 1.65
Falling edge 1.67 1.7 1.74
VBOR0 Brown-out reset threshold 0
Rising edge 1.69 1.76 1.8
Falling edge 1.87 1.93 1.97
VBOR1 Brown-out reset threshold 1
Rising edge 1.96 2.03 2.07
Falling edge 2.22 2.30 2.35
VBOR2 Brown-out reset threshold 2
Rising edge 2.31 2.41 2.44
Falling edge 2.45 2.55 2.6
VBOR3 Brown-out reset threshold 3
Rising edge 2.54 2.66 2.7
Falling edge 2.68 2.8 2.85
VBOR4 Brown-out reset threshold 4
Rising edge 2.78 2.9 2.95
V
Programmable voltage detector Falling edge 1.8 1.85 1.88
VPVD0
threshold 0 Rising edge 1.88 1.94 1.99
Falling edge 1.98 2.04 2.09
VPVD1 PVD threshold 1
Rising edge 2.08 2.14 2.18
Falling edge 2.20 2.24 2.28
VPVD2 PVD threshold 2
Rising edge 2.28 2.34 2.38
Falling edge 2.39 2.44 2.48
VPVD3 PVD threshold 3
Rising edge 2.47 2.54 2.58
Falling edge 2.57 2.64 2.69
VPVD4 PVD threshold 4
Rising edge 2.68 2.74 2.79
Falling edge 2.77 2.83 2.88
VPVD5 PVD threshold 5
Rising edge 2.87 2.94 2.99

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Table 27. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Falling edge 2.97 3.05 3.09

VPVD6 PVD threshold 6 V
Rising edge 3.08 3.15 3.20
BOR0 threshold - 40 -
Vhyst Hysteresis voltage All BOR and PVD thresholds mV
- 100 -
excepting BOR0
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.

6.3.3 Embedded internal reference voltage

The parameters given in Table 29 are based on characterization results, unless otherwise
specified.

Table 28. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 25 °C 0x1FF8 0078 - 0x1FF8 0079
VDDA= 3 V

Table 29. Embedded internal reference voltage(1)

Symbol Parameter Conditions Min Typ Max Unit

VREFINT out(2) Internal reference voltage – 40 °C < TJ < +125 °C 1.202 1.224 1.242 V
TVREFINT Internal reference startup time - - 2 3 ms
VDDA and VREF+ voltage during
VVREF_MEAS - 2.99 3 3.01 V
VREFINT factory measure
Including uncertainties
Accuracy of factory-measured
AVREF_MEAS due to ADC and - - ±5 mV
VREFINT value(3)
VDDA/VREF+ values
TCoeff(4) Temperature coefficient –40 °C < TJ < +125 °C - 25 100 ppm/°C
ACoeff(4) Long-term stability 1000 hours, T= 25 °C - - 1000 ppm
VDDCoeff(4) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V
ADC sampling time when
TS_vrefint(4)(5) reading the internal reference - 5 10 - µs
voltage
Startup time of reference
TADC_BUF(4) - - - 10 µs
voltage buffer for ADC
Consumption of reference
IBUF_ADC(4) - - 13.5 25 µA
voltage buffer for ADC
IVREF_OUT(4) VREF_OUT output current(6) - - - 1 µA
CVREF_OUT(4) VREF_OUT output load - - - 50 pF

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Electrical characteristics STM32L083xx

Table 29. Embedded internal reference voltage(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Consumption of reference
ILPBUF(4) voltage buffer for VREF_OUT - - 730 1200 nA
and COMP
VREFINT_DIV1(4) 1/4 reference voltage - 24 25 26
%
VREFINT_DIV2(4) 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(4) 3/4 reference voltage - 74 75 76
1. Refer to Table 41: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
4. Guaranteed by design.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.

6.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 26: General operating
conditions unless otherwise specified.
The MCU is placed under the following conditions:
• All I/O pins are configured in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time and prefetch is adjusted depending on fHCLK
frequency and voltage range to provide the best CPU performance unless otherwise
specified.
• When the peripherals are enabled fAPB1 = fAPB2 = fAPB
• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
• The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 43: High-speed external user clock characteristics
• For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins
• For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise
The parameters given in Table 51, Table 26 and Table 27 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 26.

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Table 30. Current consumption in Run mode, code with data processing running from
Flash memory
fHCLK
Symbol Parameter Condition Typ Max(1) Unit
(MHz)

1 190 250
Range3,
Vcore=1.2 V 2 345 380 µA
VOS[1:0]=11
4 650 670
fHSE = fHCLK up to 4 0,8 0,86
Range2,
16MHz included,
Vcore=1.5 V 8 1,55 1,7
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL ON)(2) 16 2,95 3,1
mA
8 1,9 2,1
Range1,
IDD (Run Supply current in Run Vcore=1.8 V 16 3,55 3,8
from Flash mode code executed VOS[1:0]=01
32 6,65 7,2
memory) from Flash memory
0,065 39 130
Range3,
MSI clock source Vcore=1.2 V 0,524 115 210 µA
VOS[1:0]=11
4,2 700 770
Range2,
Vcore=1.5 V 16 2,9 3,2
HSI clock source VOS[1:0]=10
mA
(16MHz) Range1,
Vcore=1.8 V 32 7,15 7,4
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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Electrical characteristics STM32L083xx

Table 31. Current consumption in Run mode vs code type,

code with data processing running from Flash memory
Symbol Parameter Conditions fHCLK Typ Unit

Dhrystone 650
CoreMark 655
Range 3,
Fibonacci 485
VCORE=1.2 V, 4 MHz µA
Supply VOS[1:0]=11 while(1) 385
IDD current in while(1), 1WS,
fHSE = fHCLK up to 375
(Run Run mode, prefetch OFF
16 MHz included, fHSE
from code
= fHCLK/2 above 16 Dhrystone 6,65
Flash executed
MHz (PLL ON)(1)
memory) from Flash CoreMark 6,9
memory Range 1,
Fibonacci 6,75
VCORE=1.8 V, 32 MHz mA
VOS[1:0]=01 while(1) 5,8
while(1), prefetch
5,5
OFF
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Figure 14. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS

3.50

3.00

2.50
IDD (mA)

2.00

1.50

1.00

0.50
VDD (V)
0
1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C

MSv37843V1

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Figure 15. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS

3.50

3.00

2.50
IDD (mA)

2.00

1.50

1.00

0.50
VDD (V)
0
1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C

MSv37844V1

Table 32. Current consumption in Run mode, code with data processing running from RAM
fHCLK
Symbol Parameter Condition Typ Max(1) Unit
(MHz)

1 175 230
Range3,
Vcore=1.2 V 2 315 360 µA
VOS[1:0]=11
4 570 630
fHSE = fHCLK up to 4 0,71 0,78
Range2,
16 MHz included,
Vcore=1.5 V 8 1,35 1,6
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL ON)(2) 16 2,7 3
mA
8 1,7 1,9
Range1,
Supply current in Run Vcore=1.8 V 16 3,2 3,7
IDD (Run mode code executed VOS[1:0]=01
from RAM) from RAM, Flash 32 6,65 7,1
memory switched off 0,065 38 98
Range3,
MSI clock Vcore=1.2 V 0,524 105 160 µA
VOS[1:0]=11
4,2 615 710
Range2,
Vcore=1.5 V 16 2,85 3
HSI clock source VOS[1:0]=10
mA
(16 MHz) Range1,
Vcore=1.8 V 32 6,85 7,3
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.

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Electrical characteristics STM32L083xx

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Table 33. Current consumption in Run mode vs code type,

code with data processing running from RAM(1)
Symbol Parameter Conditions fHCLK Typ Unit

Dhrystone 570
Range 3, CoreMark 670
VCORE=1.2 V, 4 MHz µA
Supply current in VOS[1:0]=11 Fibonacci 410
Run mode, code fHSE = fHCLK up to
IDD (Run while(1) 375
executed from 16 MHz included,
from
RAM, Flash fHSE = fHCLK/2 above Dhrystone 6,65
RAM)
memory switched 16 MHz (PLL ON)(2)
Range 1, CoreMark 6,95
off
VCORE=1.8 V, 32 MHz mA
VOS[1:0]=01 Fibonacci 5,9
while(1) 5,2
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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Table 34. Current consumption in Sleep mode

Symbol Parameter Condition fHCLK (MHz) Typ Max(1) Unit

1 43,5 110
Range3,
Vcore=1.2 V 2 72 140
VOS[1:0]=11
4 130 200
fHSE = fHCLK up to 4 160 220
Range2,
16 MHz included,
Vcore=1.5 V 8 305 380
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL ON)(2) 16 590 690
8 370 460
Range1,
Supply current in Vcore=1.8 V 16 715 840
Sleep mode, Flash VOS[1:0]=01
memory switched 32 1650 2000
OFF 0,065 18 93
Range3,
MSI clock Vcore=1.2 V 0,524 31,5 110
VOS[1:0]=11
4,2 140 230
Range2,
Vcore=1.5 V 16 665 850
HSI clock source VOS[1:0]=10
(16 MHz) Range1,
Vcore=1.8 V 32 1750 2100
IDD VOS[1:0]=01
µA
(Sleep) 1 57,5 130
Range3,
Vcore=1.2 V 2 84 160
VOS[1:0]=11
4 150 220
fHSE = fHCLK up to 4 170 240
Range2,
16MHz included,
Vcore=1.5 V 8 315 400
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL ON)(2) 16 605 710
8 380 470
Range1,
Supply current in Vcore=1.8 V 16 730 860
Sleep mode, Flash VOS[1:0]=01
memory switched 32 1650 2000
ON 0,065 29,5 110
Range3,
MSI clock Vcore=1.2 V 0,524 44,5 120
VOS[1:0]=11
4,2 150 240
Range2,
Vcore=1.5 V 16 680 930
HSI clock source VOS[1:0]=10
(16MHz) Range1,
Vcore=1.8 V 32 1750 2200
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.

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2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Table 35. Current consumption in Low-power run mode

fHCLK
Symbol Parameter Condition Typ Max(1) Unit
(MHz)

TA = − 40 to 25°C 9,45 12

MSI clock = 65 kHz, TA = 85°C 14 58

0,032
fHCLK= 32 kHz TA = 105°C 21 64
TA = 125°C 36,5 160

All peripherals TA = − 40 to 25°C 14,5 18

OFF, code
MSI clock = 65 kHz, TA = 85°C 19,5 60
executed from 0,065
RAM, Flash fHCLK = 65kHz TA = 105°C 26 65
memory switched
TA = 125°C 42 160
OFF, VDD from
1.65 to 3.6 V TA = − 40 to 25°C 26,5 30
TA = 55°C 27,5 60
MSI clock=131 kHz,
TA = 85°C 0,131 31 66
fHCLK= 131 kHz
TA = 105°C 37,5 77
Supply
IDD current in TA = 125°C 53,5 170
µA
(LP Run) Low-power TA = − 40 to 25°C 24,5 34
run mode
MSI clock = 65 kHz, TA = 85°C 30 82
0,032
fHCLK= 32 kHz TA = 105°C 38,5 90
TA = 125°C 58 120
TA = − 40 to 25°C 30,5 40
All peripherals
OFF, code MSI clock = 65 kHz, TA = 85°C 36,5 88
executed from 0,065
fHCLK= 65 kHz TA = 105°C 45 96
Flash memory,
VDD from 1.65 V TA = 125°C 64,5 120
to 3.6 V
TA = − 40 to 25°C 45 56
TA = 55°C 48 96
MSI clock =
131 kHz, TA = 85°C 0,131 51 110
fHCLK= 131 kHz
TA = 105°C 59,5 120
TA = 125°C 79,5 150
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.

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Figure 16. IDD vs VDD, at TA= 25 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
IDD (mA)

4,5E-02

4,0E-02

3,5E-02

3,0E-02

2,5E-02

2,0E-02

1,5E-02

1,0E-02

5,0E-03

0 VDD (V)
1,65 1,8 2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6

-40
25
55
85
105
125

MSv37845V2

Table 36. Current consumption in Low-power sleep mode

Max
Symbol Parameter Condition Typ (1) Unit

MSI clock = 65 kHz,

fHCLK= 32 kHz, TA = − 40 to 25°C 4,7 -
Flash memory OFF
TA = − 40 to 25°C 17 24

MSI clock = 65 kHz, TA = 85°C 19,5 30

fHCLK= 32 kHz TA= 105°C 23 47
TA= 125°C 32,5 70
All peripherals
Supply current in OFF, code TA= − 40 to 25°C 17 24
IDD
Low-power sleep executed from TA= 85°C 20 31 µA
(LP Sleep) MSI clock = 65 kHz,
mode Flash memory, VDD
fHCLK= 65 kHz TA = 105°C 23,5 47
from 1.65 to 3.6 V
TA = 125°C 32,5 70
TA= − 40 to 25°C 19,5 27
TA = 55°C 20,5 28
MSI clock = 131kHz,
TA = 85°C 22,5 33
fHCLK= 131 kHz
TA = 105°C 26 50
TA= 125°C 35 73
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.

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Table 37. Typical and maximum current consumptions in Stop mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = − 40 to 25°C 0,43 1,00

TA = 55°C 0,735 2,50
IDD (Stop) Supply current in Stop mode TA= 85°C 2,25 4,90 µA
TA = 105°C 5,3 13,00
TA = 125°C 12,5 28,00
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.

Figure 17. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive

1.6E-02

1.4E-02

1.2E-02

1.0E-02

8.0E-03
IDD (mA)

6.0E-03

4.0E-03

2.0E-03
VDD (V)
0
1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C

MSv37846V1

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Figure 18. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF

1.4E-02

1.2E-02

1.0E-02

8.0E-03

6.0E-03
IDD (mA)

4.0E-03

2.0E-03
VDD (V)
0
1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C

MSv37847V1

Table 38. Typical and maximum current consumptions in Standby mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = − 40 to 25°C 0,855 1,70

TA = 55 °C - 2,90
Independent watchdog
TA= 85 °C - 3,30
and LSI enabled
TA = 105 °C - 4,10

IDD Supply current in Standby TA = 125 °C - 8,50

µA
(Standby) mode TA = − 40 to 25°C 0,29 0,60
TA = 55 °C 0,32 1,20
Independent watchdog
TA = 85 °C 0,5 2,30
and LSI OFF
TA = 105 °C 0,94 3,00
TA = 125 °C 2,6 7,00
1. Guaranteed by characterization results at 125 °C, unless otherwise specified

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Table 39. Average current consumption during Wakeup

Current
Symbol parameter System frequency consumption Unit
during wakeup

HSI 1
HSI/4 0,7
IDD (Wakeup from Supply current during Wakeup from
MSI clock = 4,2 MHz 0,7
Stop) Stop mode
MSI clock = 1,05 MHz 0,4
MSI clock = 65 KHz 0,1
mA
IDD (Reset) Reset pin pulled down - 0,21

IDD (Power-up) BOR ON - 0,23

IDD (Wakeup from With Fast wakeup set MSI clock = 2,1 MHz 0,5
StandBy) With Fast wakeup disabled MSI clock = 2,1 MHz 0,12

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On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
• all I/O pins are in input mode with a static value at VDD or VSS (no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked OFF
– with only one peripheral clocked on

Table 40. Peripheral current consumption in Run or Sleep mode(1)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Peripheral Range 1, Range 2, Range 3, Low-power Unit

VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V sleep and
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 run

CRS 2.5 2 2 2
DAC1/2 4 3.5 3 2.5
I2C1 11 9.5 7.5 9
I2C3 11 9 7 9
LCD1 4 3.5 3 2.5
LPTIM1 10 8.5 6.5 8
LPUART1 8 6.5 5.5 6
SPI2 9 4.5 3.5 4
µA/MHz
APB1 USART2 14.5 12 9.5 11
(fHCLK)
USART4 5 4 3 5
USART5 5 4 3 5
USB 8.5 4.5 4 4.5
TIM2 10.5 8.5 7 9
TIM3 12 10 8 11
TIM6 3.5 3 2.5 2
TIM7 3.5 3 2.5 2
WWDG 3 2 2 2

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Table 40. Peripheral current consumption in Run or Sleep mode(1) (continued)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Peripheral Range 1, Range 2, Range 3, Low-power Unit

VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V sleep and
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 run

ADC1(2) 5.5 5 3.5 4

SPI1 4 3 3 2.5
USART1 14.5 11.5 9.5 12
TIM21 7.5 6 5 5.5 µA/MHz
APB2
TIM22 7 6 5 6 (fHCLK)

FIREWALL 1.5 1 1 0.5

DBGMCU 1.5 1 1 0.5
SYSCFG 2.5 2 2 1.5
GPIOA 3.5 3 2.5 2.5
GPIOB 3.5 2.5 2 2.5
Cortex- GPIOC 8.5 6.5 5.5 7 µA/MHz
M0+ core
(fHCLK)
I/O port GPIOD 1 0.5 0.5 0.5
GPIOE 8 6 5 6
GPIOH 1.5 1 1 0.5
CRC 1.5 1 1 1
FLASH 0(3) 0(3) 0(3) 0(3)
DMA1 10 8 6.5 8.5 µA/MHz
AHB
RNG 5.5 1 0.5 0.5 (fHCLK)

TSC 3 2.5 2 3
(3)
AES 0 0(3) 0(3) 0(3)
µA/MHz
All enabled 204 162 130 202
(fHCLK)
µA/MHz
PWR 2.5 2 2 1
(fHCLK)
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Current consumption is negligible and close to 0 µA.

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Table 41. Peripheral current consumption in Stop and Standby mode(1)

Typical consumption, TA = 25 °C
Symbol Peripheral Unit
VDD=1.8 V VDD=3.0 V

IDD(PVD / BOR) - 0.7 1.2

IREFINT - - 1.7
- LSE Low drive(2) 0.11 0,13
- LSI 0.27 0.31
- IWDG 0.2 0.3

- LPTIM1, Input 100 Hz 0.01 0,01 µA

- LPTIM1, Input 1 MHz 11 12

- LPUART1 - 0,5

- RTC 0.16 0,3

- LCD1 (static duty) 0.15 0.15

µA
- LCD1 (1/8 duty) 1.6 2.6

1. LCD, LPTIM, LPUART peripherals can operate in Stop mode but not in Standby mode.
2. LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN
and OSC32_OUT.-

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
• Sleep mode: the clock source is the clock that was set before entering Sleep mode
• Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 26.

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Table 42. Low-power mode wakeup timings

Symbol Parameter Conditions Typ Max Unit

tWUSLEEP Wakeup from Sleep mode fHCLK = 32 MHz 7 8

fHCLK = 262 kHz Number
7 8
tWUSLEEP_ Wakeup from Low-power sleep mode, Flash memory enabled of clock
fHCLK = 262 kHz cycles
LP fHCLK = 262 kHz
9 10
Flash memory switched OFF
fHCLK = fMSI = 4.2 MHz 5.0 8
Wakeup from Stop mode, regulator in Run
fHCLK = fHSI = 16 MHz 4.9 7
mode
fHCLK = fHSI/4 = 4 MHz 8.0 11
fHCLK = fMSI = 4.2 MHz
5.0 8
Voltage range 1
fHCLK = fMSI = 4.2 MHz
5.0 8
Voltage range 2
fHCLK = fMSI = 4.2 MHz
5.0 8
Voltage range 3
fHCLK = fMSI = 2.1 MHz 7.3 13
Wakeup from Stop mode, regulator in low-
tWUSTOP fHCLK = fMSI = 1.05 MHz 13 23
power mode
fHCLK = fMSI = 524 kHz 28 38 µs

fHCLK = fMSI = 262 kHz 51 65

fHCLK = fMSI = 131 kHz 100 120
fHCLK = MSI = 65 kHz 190 260
fHCLK = fHSI = 16 MHz 4.9 7
fHCLK = fHSI/4 = 4 MHz 8.0 11
fHCLK = fHSI = 16 MHz 4.9 7
Wakeup from Stop mode, regulator in low-
fHCLK = fHSI/4 = 4 MHz 7.9 10
power mode, code running from RAM
fHCLK = fMSI = 4.2 MHz 4.7 8
Wakeup from Standby mode
fHCLK = MSI = 2.1 MHz 65 130
FWU bit = 1
tWUSTDBY
Wakeup from Standby mode
fHCLK = MSI = 2.1 MHz 2.2 3 ms
FWU bit = 0

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6.3.6 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 19.

Table 43. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

CSS is ON or
1 8 32 MHz
User external clock source PLL is used
fHSE_ext
frequency CSS is OFF,
0 8 32 MHz
PLL not used
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSE)
OSC_IN high or low time 12 - -
tw(HSE)
- ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance - 2.6 - pF
DuCy(HSE) Duty cycle 45 - 55 %
IL OSC_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
1. Guaranteed by design.

Figure 19. High-speed external clock source AC timing diagram

VHSEH
90%
10%
VHSEL

tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE

EXTER NAL fHSE_ext

IL
CLOCK SOURC E OSC _IN
STM32Lxx

ai18232c

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Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 26.

Table 44. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext 1 32.768 1000 kHz
frequency
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3VDD
voltage
tw(LSE)
OSC32_IN high or low time 465 - -
tw(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time - - 10
tf(LSE)
CIN(LSE) OSC32_IN input capacitance - - 0.6 - pF
DuCy(LSE) Duty cycle - 45 - 55 %
IL OSC32_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
1. Guaranteed by design, not tested in production

Figure 20. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL

tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE

EXTER NAL fLSE_ext

OSC32_IN IL
CLOCK SOURC E
STM32Lxx

ai18233c

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 45. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 45. HSE oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 1 25 MHz

RF Feedback resistor - - 200 - kΩ
Maximum critical crystal µA
Gm Startup - - 700
transconductance /V
tSU(HSE)
(2) Startup time VDD is stabilized - 2 - ms

1. Guaranteed by design.
2. Guaranteed by characterization results. tSU(HSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.

Figure 21. HSE oscillator circuit diagram

fHSE to core
Rm

CO RF
Lm
CL1
Cm OSC_IN
gm
Resonator
Consumption
control
Resonator

STM32
OSC_OUT
CL2

ai18235b

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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 46. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 46. LSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min(2) Typ Max Unit

fLSE LSE oscillator frequency - 32.768 - kHz

LSEDRV[1:0]=00
- - 0.5
lower driving capability
LSEDRV[1:0]= 01
- - 0.75
Maximum critical crystal medium low driving capability
Gm µA/V
transconductance LSEDRV[1:0] = 10
- - 1.7
medium high driving capability
LSEDRV[1:0]=11
- - 2.7
higher driving capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. Guaranteed by characterization results. tSU(LSE) is the startup time measured from the moment it is enabled (by software)
to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 22. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

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6.3.7 Internal clock source characteristics

The parameters given in Table 47 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 26.

High-speed internal 16 MHz (HSI16) RC oscillator

Table 47. 16 MHz HSI16 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 Frequency VDD = 3.0 V - 16 - MHz

HSI16 user- Trimming code is not a multiple of 16 - ± 0.4 0.7 %

(1)(2)
TRIM trimmed resolution Trimming code is a multiple of 16 - - ± 1.5 %
VDDA = 3.0 V, TA = 25 °C -1(3) - 1(3) %
VDDA = 3.0 V, TA = 0 to 55 °C -1.5 - 1.5 %

Accuracy of the VDDA = 3.0 V, TA = -10 to 70 °C -2 - 2 %

ACCHSI16
(2) factory-calibrated VDDA = 3.0 V, TA = -10 to 85 °C -2.5 - 2 %
HSI16 oscillator
VDDA = 3.0 V, TA = -10 to 105 °C -4 - 2 %
VDDA = 1.65 V to 3.6 V
-5.45 - 3.25 %
TA = − 40 to 125 °C
HSI16 oscillator
tSU(HSI16)(2) - - 3.7 6 µs
startup time
HSI16 oscillator
IDD(HSI16)(2) - - 100 140 µA
power consumption
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.

Figure 23. HSI16 minimum and maximum value versus temperature

4.00%

3.00%

2.00%

1.00%
1.65V min
0.00%
3V typ
-60 -40 -20 0 20 40 60 80 100 120 140
-1.00% 3.6V max
1.65V max
-2.00%
3.6V min
-3.00%

-4.00%

-5.00%

-6.00%
MSv34791V1

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High-speed internal 48 MHz (HSI48) RC oscillator

Table 48. HSI48 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 Frequency - 48 - MHz

(2) (2)
TRIM HSI48 user-trimming step 0.09 0.14 0.2 %
DuCy(HSI48) Duty cycle (2) (2)
45 - 55 %
Accuracy of the HSI48
ACCHSI48 oscillator (factory calibrated TA = 25 °C -4(3) - 4(3) %
before CRS calibration)
tsu(HSI48) HSI48 oscillator startup time - - 6(2) µs
HSI48 oscillator power
IDDA(HSI48) - 330 380(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

Table 49. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

fLSI(1) LSI frequency 26 38 56 kHz

LSI oscillator frequency drift
DLSI(2) -10 - 4 %
0°C ≤TA ≤ 85°C
tsu(LSI)(3) LSI oscillator startup time - - 200 µs
(3)
IDD(LSI) LSI oscillator power consumption - 400 510 nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.

Multi-speed internal (MSI) RC oscillator

Table 50. MSI oscillator characteristics

Symbol Parameter Condition Typ Max Unit

MSI range 0 65.5 -

MSI range 1 131 -
kHz
MSI range 2 262 -
Frequency after factory calibration, done at
fMSI MSI range 3 524 -
VDD= 3.3 V and TA = 25 °C
MSI range 4 1.05 -
MSI range 5 2.1 - MHz
MSI range 6 4.2 -

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Table 50. MSI oscillator characteristics (continued)

Symbol Parameter Condition Typ Max Unit

ACCMSI Frequency error after factory calibration - ±0.5 - %

MSI oscillator frequency drift
- ±3 -
0 °C ≤TA ≤85 °C
MSI range 0 − 8.9 +7.0
MSI range 1 − 7.1 +5.0

DTEMP(MSI)(1) MSI range 2 − 6.4 +4.0 %

MSI oscillator frequency drift
MSI range 3 − 6.2 +3.0
VDD = 3.3 V, − 40 °C ≤TA ≤110 °C
MSI range 4 − 5.2 +3.0
MSI range 5 − 4.8 +2.0
MSI range 6 − 4.7 +2.0
MSI oscillator frequency drift
DVOLT(MSI)(1) - - 2.5 %/V
1.65 V ≤VDD ≤3.6 V, TA = 25 °C
MSI range 0 0.75 -
MSI range 1 1 -
MSI range 2 1.5 -
IDD(MSI)(2) MSI oscillator power consumption MSI range 3 2.5 - µA
MSI range 4 4.5 -
MSI range 5 8 -
MSI range 6 15 -
MSI range 0 30 -
MSI range 1 20 -
MSI range 2 15 -
MSI range 3 10 -
MSI range 4 6 -
tSU(MSI) MSI oscillator startup time µs
MSI range 5 5 -
MSI range 6,
Voltage range 1 3.5 -
and 2
MSI range 6,
5 -
Voltage range 3

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Table 50. MSI oscillator characteristics (continued)

Symbol Parameter Condition Typ Max Unit

MSI range 0 - 40
MSI range 1 - 20
MSI range 2 - 10
MSI range 3 - 4
MSI range 4 - 2.5
tSTAB(MSI)(2) MSI oscillator stabilization time µs
MSI range 5 - 2
MSI range 6,
Voltage range 1 - 2
and 2
MSI range 3,
- 3
Voltage range 3
Any range to
- 4
range 5
fOVER(MSI) MSI oscillator frequency overshoot MHz
Any range to
- 6
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.

6.3.8 PLL characteristics

The parameters given in Table 51 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 26.

Table 51. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max(1)

PLL input clock(2) 2 - 24 MHz

fPLL_IN
PLL input clock duty cycle 45 - 55 %
fPLL_OUT PLL output clock 2 - 32 MHz
PLL input = 16 MHz
tLOCK - 115 160 µs
PLL VCO = 96 MHz
Jitter Cycle-to-cycle jitter - ± 600 ps
IDDA(PLL) Current consumption on VDDA - 220 450
µA
IDD(PLL) Current consumption on VDD - 120 150
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.

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6.3.9 Memory characteristics

RAM memory

Table 52. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode(1) STOP mode (or RESET) 1.65 - - V

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).

Flash memory and data EEPROM

Table 53. Flash memory and data EEPROM characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

Operating voltage
VDD - 1.65 - 3.6 V
Read / Write / Erase

Programming time for Erasing - 3.28 3.94

tprog ms
word or half-page Programming - 3.28 3.94
Average current during
the whole programming / - 500 700 µA
erase operation
IDD Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
- 1.5 2.5 mA
programming / erase
operation
1. Guaranteed by design.

Table 54. Flash memory and data EEPROM endurance and retention
Value
Symbol Parameter Conditions Unit
Min(1)

Cycling (erase / write)

10
Program memory
TA = -40°C to 105 °C
Cycling (erase / write)
100
EEPROM data memory
NCYC(2) kcycles
Cycling (erase / write)
0.2
Program memory
TA = -40°C to 125 °C
Cycling (erase / write)
2
EEPROM data memory

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Table 54. Flash memory and data EEPROM endurance and retention (continued)
Value
Symbol Parameter Conditions Unit
Min(1)

Data retention (program memory) after

30
10 kcycles at TA = 85 °C
TRET = +85 °C
Data retention (EEPROM data memory)
30
after 100 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
tRET(2) TRET = +105 °C years
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
10
Data retention (program memory) after
200 cycles at TA = 125 °C
TRET = +125 °C
Data retention (EEPROM data memory)
after 2 kcycles at TA = 125 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.

6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.

Table 55. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, LQFP100, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 32 MHz 3B
induce a functional disturbance
conforms to IEC 61000-4-2
VDD = 3.3 V, LQFP100, TA = +25
Fast transient voltage burst limits to be
°C,
VEFTB applied through 100 pF on VDD and VSS 4A
fHCLK = 32 MHz
pins to induce a functional disturbance
conforms to IEC 61000-4-4

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Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 56. EMI characteristics

Max vs.
Monitored frequency
Symbol Parameter Conditions Unit
frequency band range at
32 MHz

0.1 to 30 MHz -7
VDD = 3.6 V,
30 to 130 MHz 14 dBµV
SEMI Peak level TA = 25 °C,
LQFP100 package 130 MHz to 1 GHz 9
compliant with IEC 61967-2
EMI Level 2 -

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6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 57. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

TA = +25 °C,
Electrostatic discharge
VESD(HBM) conforming to 2 2000
voltage (human body model)
ANSI/JEDEC JS-001
V
Electrostatic discharge TA = +25 °C,
VESD(CDM) voltage (charge device conforming to C4 500
model) ANSI/ESD STM5.3.1.
1. Guaranteed by characterization results.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 58. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +125 °C conforming to JESD78A II level A

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6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 59.

Table 59. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 -0 NA(1)

Injected current on PA0, PA4, PA5, PC15,
-5 0
IINJ PH0 and PH1 mA
Injected current on any other FT, FTf pins -5 (2) NA(1)
Injected current on any other pins -5 (2) +5
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.

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6.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the conditions summarized in Table 26. All I/Os are CMOS and TTL
compliant.
Table 60. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit

TC, FT, FTf, RST

- - 0.3VDD
VIL Input low level voltage I/Os
BOOT0 pin - - 0.14VDD(1)
V
VIH Input high level voltage All I/Os 0.7 VDD - -

I/O Schmitt trigger voltage hysteresis Standard I/Os - 10% VDD(3) -

Vhys (2)
BOOT0 pin - 0.01 -
VSS ≤VIN ≤VDD
All I/Os except for
- - ±50
PA11, PA12, BOOT0
and FTf I/Os
nA
VSS ≤VIN ≤VDD,
- - -50/+250
PA11 and PA12 I/Os
VSS ≤VIN ≤VDD
- - ±100
FTf I/Os
Ilkg Input leakage current (4) VDD≤VIN ≤5 V
All I/Os except for - - 200
PA11, PA12, BOOT0
and FTf I/Os nA

VDD≤VIN ≤5 V
- - 500
FTf I/Os
VDD≤VIN ≤5 V
PA11, PA12 and - - 10 µA
BOOT0
RPU Weak pull-up equivalent resistor(5) VIN = VSS 25 45 65 kΩ
RPD (5)
Weak pull-down equivalent resistor VIN = VDD 25 45 65 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Guaranteed by characterization.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
3. With a minimum of 200 mV. Guaranteed by characterization results.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).

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Figure 24. VIH/VIL versus VDD (CMOS I/Os)

VIL/VIH (V) V DD (all p

ins
= 0.7 0.59 /1
ts V IHmin
9 V DD+ 15, PH0
iremen =0 .3 , PC
requ V IHmin t BOOT0 0.38 for
ard p +
Ss tand exce 5V DD H0/1
CMO = 0.4 ,P
VIHmin 2.0 V IHmin 0, PC15
T
BOO

V DD
= 0.3
1.3 V ILmax
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0 2.7 3.0 3.3 3.6

MSv34789V1

Figure 25. VIH/VIL versus VDD (TTL I/Os)

VIL/VIH (V) pins

9 (all
V D+0.5 , PH0/1
9 D
15
= 0.3 , PC
V IHmin t BOOT0 0.38 for
p +
TTL standard requirements VIHmin = 2 V exce = 0.45V DD PH0/1
,
VIHmin 2.0 V IHmin 0, PC15
T
BOO

V DD
= 0.3
1.3 V ILmax
Input range not
guaranteed

VILmax 0.8
0.7 TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0 2.7 3.0 3.3 3.6

MSv34790V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard VOL/VOH specifications given in Table 61.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 24).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 24).

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Output voltage levels

Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 26. All I/Os are CMOS and TTL compliant.

Table 61. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O

VOL(1) CMOS port(2), - 0.4
pin
IIO = +8 mA
Output high level voltage for an I/O 2.7 V ≤ VDD ≤ 3.6 V
VOH(3) VDD-0.4 -
pin
TTL port(2),
(1) Output low level voltage for an I/O
VOL IIO =+ 8 mA - 0.4
pin
2.7 V ≤VDD ≤ 3.6 V
TTL port(2),
(3)(4) Output high level voltage for an I/O
VOH IIO = -6 mA 2.4 -
pin
2.7 V ≤VDD ≤ 3.6 V
Output low level voltage for an I/O IIO = +15 mA
VOL(1)(4) - 1.3 V
pin 2.7 V ≤VDD ≤ 3.6 V
Output high level voltage for an I/O IIO = -15 mA
VOH(3)(4) VDD-1.3 -
pin 2.7 V ≤VDD ≤ 3.6 V
Output low level voltage for an I/O IIO = +4 mA
VOL(1)(4) - 0.45
pin 1.65 V ≤VDD < 3.6 V
Output high level voltage for an I/O IIO = -4 mA
VOH(3)(4) VDD-0.45 -
pin 1.65 V ≤VDD ≤ 3.6 V
IIO = 20 mA
- 0.4
Output low level voltage for an FTf 2.7 V ≤VDD ≤ 3.6 V
VOLFM+(1)(4)
I/O pin in Fm+ mode IIO = 10 mA
- 0.4
1.65 V ≤VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 24.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 24. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN).
4. Guaranteed by characterization results.

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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 62, respectively.
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 26.

Table 62. I/O AC characteristics(1)

OSPEEDRx[1:0]
Symbol Parameter Conditions Min Max(2) Unit
bit value(1)

CL = 50 pF, VDD = 2.7 V to 3.6 V - 400

fmax(IO)out Maximum frequency(3) kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 100
00
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 125
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 320
CL = 50 pF, VDD = 2.7 V to 3.6 V - 2
fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 0.6
01
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 30
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 65
CL = 50 pF, VDD = 2.7 V to 3.6 V - 10
Fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 2
10
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 13
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 28
CL = 30 pF, VDD = 2.7 V to 3.6 V - 35
Fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 10
11
tf(IO)out CL = 30 pF, VDD = 2.7 V to 3.6 V - 6
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 17
fmax(IO)out Maximum frequency(3) - 1 MHz
tf(IO)out Output fall time CL = 50 pF, VDD = 2.5 V to 3.6 V - 10
ns
Fm+ tr(IO)out Output rise time - 30
configuration(4) fmax(IO)out Maximum frequency(3) - 350 KHz
tf(IO)out Output fall time CL = 50 pF, VDD = 1.65 V to 3.6 V - 15
ns
tr(IO)out Output rise time - 60
Pulse width of external
- tEXTIpw signals detected by the - 8 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 26.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed
description of Fm+ I/O configuration.

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Figure 26. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

EXTERNAL tr(IO)out tf(IO)out

OUTPUT
ON CL T

Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.

ai14131d

6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU , except when it is internally driven low (see Table 63).
Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 26.

Table 63. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) (1) NRST input low level voltage - VSS - 0.8

VIH(NRST)(1) NRST input high level voltage - 1.4 - VDD
IOL = 2 mA V
- -
NRST output low level 2.7 V < VDD < 3.6 V
VOL(NRST)(1) 0.4
voltage IOL = 1.5 mA
- -
1.65 V < VDD < 2.7 V
NRST Schmitt trigger voltage
Vhys(NRST)(1) - - 10%VDD(2) - mV
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 45 65 kΩ
resistor(3)
VF(NRST)(1) NRST input filtered pulse - - - 50 ns
VNF(NRST) (1) NRST input not filtered pulse - 350 - - ns
1. Guaranteed by design.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.

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Figure 27. Recommended NRST pin protection

([WHUQDO
UHVHWFLUFXLW  9''

538
1567  ,QWHUQDOUHVHW
)LOWHU

—)

069

1. The reset network protects the device against parasitic resets.

2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 63. Otherwise the reset will not be taken into account by the device.

6.3.15 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions
summarized in Table 26: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 64. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for Fast channel 1.65 - 3.6

VDDA V
ADC ON Standard channel 1.75(1) - 3.6
VREF+ Positive reference voltage - 1.65 VDDA V
VREF- Negative reference voltage - - 0 -

Current consumption of the 1.14 Msps - 200 -

ADC on VDDAand VREF+ 10 ksps - 40 -
IDDA (ADC) µA
Current consumption of the 1.14 Msps - 70 -
ADC on VDD(2) 10 ksps - 1 -
Voltage scaling Range 1 0.14 - 16
fADC ADC clock frequency Voltage scaling Range 2 0.14 - 8 MHz
Voltage scaling Range 3 0.14 - 4
fS(3) Sampling rate 12-bit resolution 0.01 - 1.14 MHz
fADC = 16 MHz,
- - 941 kHz
fTRIG(3) External trigger frequency 12-bit resolution
- - - 17 1/fADC
VAIN Conversion voltage range - 0 - VREF+ V

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Table 64. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

See Equation 1 and

RAIN(3) External input impedance - - 50 kΩ
Table 65 for details

RADC(3)(4) Sampling switch resistance - - - 1 kΩ

Internal sample and hold

CADC(3) - - - 8 pF
capacitor
fADC = 16 MHz 5.2 µs
tCAL(3)(5) Calibration time
- 83 1/fADC
1.5 ADC 1.5 ADC
ADC clock = HSI16 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register write
WLATENCY(6) fPCLK
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 = 16 MHz 0.266 µs
fADC = fPCLK/2 8.5 1/fPCLK
tlatr(3) Trigger conversion latency fADC = fPCLK/4 = 8 MHz 0.516 µs
fADC = fPCLK/4 16.5 1/fPCLK
fADC = fHSI16 = 16 MHz 0.252 - 0.260 µs
ADC jitter on trigger
JitterADC fADC = fHSI16 - 1 - 1/fHSI16
conversion
fADC = 16 MHz 0.093 - 10.03 µs
tS(3) Sampling time
- 1.5 - 160.5 1/fADC
tUP_LDO(3)(5) Internal LDO power-up time - - - 10 µs
tSTAB(3)(5) ADC stabilization time - 14 1/fADC
fADC = 16 MHz,
0.875 - 10.81 µs
Total conversion time 12-bit resolution
tConV (3)
(including sampling time) 14 to 173 (tS for sampling +12.5
12-bit resolution 1/fADC
for successive approximation)
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 65: RAIN max for fADC = 16 MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 40: Peripheral current
consumption in Run or Sleep mode).
3. Guaranteed by design.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 65: RAIN max for
fADC = 16 MHz.
5. This parameter only includes the ADC timing. It does not take into account register access latency.
6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the
conversion is complete and has the same latency.

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Equation 1: RAIN max formula

TS
R AIN < ---------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )

The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 65. RAIN max for fADC = 16 MHz(1)

RAIN max for standard channels (kΩ)
RAIN max for
Ts tS
fast channels VDD > 1.65 V VDD > 1.65 V
(cycles) (µs) VDD > VDD > VDD > VDD > VDD >
(kΩ) and and
2.7 V 2.4 V 2.0 V 1.8 V 1.75 V
TA > −10 °C TA > 25 °C

1.5 0.09 0.5 < 0.1 NA NA NA NA NA NA

3.5 0.22 1 0.2 < 0.1 NA NA NA NA NA
7.5 0.47 2.5 1.7 1.5 < 0.1 NA NA NA NA
12.5 0.78 4 3.2 3 1 NA NA NA NA
19.5 1.22 6.5 5.7 5.5 3.5 NA NA NA < 0.1
39.5 2.47 13 12.2 12 10 NA NA NA 5
79.5 4.97 27 26.2 26 24 < 0.1 NA NA 19
160.5 10.03 50 49.2 49 47 32 < 0.1 < 0.1 42
1. Guaranteed by design.

Table 66. ADC accuracy(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - 2 4

EO Offset error - 1 2.5
EG Gain error - 1 2 LSB
EL Integral linearity error - 1.5 2.5
ED Differential linearity error - 1 1.5
Effective number of bits 10.2 11
1.65 V < VDDA = VREF+ < 3.6 V,
ENOB Effective number of bits (16-bit mode range 1/2/3 bits
11.3 12.1 -
oversampling with ratio =256)(4)
SINAD Signal-to-noise distortion 63 69 -
Signal-to-noise ratio 63 69 -
SNR Signal-to-noise ratio (16-bit mode dB
70 76 -
oversampling with ratio =256)(4)
THD Total harmonic distortion - -85 -73

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Table 66. ADC accuracy(1)(2)(3) (continued)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - 2 5

EO Offset error - 1 2.5
EG Gain error - 1 2 LSB
EL Integral linearity error - 1.5 3
1.65 V < VREF+ <VDDA < 3.6 V,
ED Differential linearity error - 1 2
range 1/2/3
ENOB Effective number of bits 10.0 11.0 - bits
SINAD Signal-to-noise distortion 62 69 -
SNR Signal-to-noise ratio 61 69 - dB
THD Total harmonic distortion - -85 -65
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.

Figure 28. ADC accuracy characteristics

VSSA EG (1) Example of an actual transfer curve

4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET EO = offset error: maximum deviation
(3)
7 between the first actual transition and
(1)
6 the first ideal one.
EG = gain error: deviation between the last
5
EO EL
ideal transition and the last actual one.
4 ED = differential linearity error: maximum
3 deviation between actual steps and the ideal ones.
ED
EL = integral linearity error: maximum deviation
2
between any actual transition and the end point
1 LSB IDEAL
1 correlation line.

0
1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA

MS19880V2

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Figure 29. Typical connection diagram using the ADC

VDDA

VT Sample and hold ADC

converter
RAIN(1) RADC
AINx 12-bit
IL±50nA converter
Cparasitic VT
VAIN
CADC

MSv34712V1

1. Refer to Table 64: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 30 or Figure 31,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed as close as possible to the chip.

Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32Lxx

VREF+

1 μF // 100 nF VDDA

1 μF // 100 nF

VSSA / VREF–

MS39601V1

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Figure 31. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32Lxx

VREF+/VDDA

1 μF // 100 nF

VREF–/VSSA

MS39602V1

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6.3.16 DAC electrical characteristics

Data guaranteed by design, not tested in production, unless otherwise specified.

Table 67. DAC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 - 3.6 V

VREF+ must always be

VREF+ Reference supply voltage 1.8 - 3.6 V
below VDDA
VREF- Lower reference voltage - VSSA V
No load, middle code
Current consumption on VREF+ (0x800) - 130 220
IDDVREF+(1) supply µA
VREF+ = 3.3 V No load, worst code
- 220 350
(0x000)
No load, middle code
Current consumption on VDDA - 210 320
(0x800)
IDDA (2) supply, µA
VDDA = 3.3 V No load, worst code
- 320 520
(0xF1C)
RL
connected 5 - -
DAC output to VSSA
RL(3) Resistive load kΩ
ON R L
connected 25 - -
to VDDA
CL(3) Capacitive load DAC output buffer ON - - 50 pF
RO Output impedance DAC output buffer OFF 12 16 20 kΩ

DAC output buffer ON 0.2 - VDDA – 0.2 V

VDAC_OUT Voltage on DAC_OUT output

VREF+ –
DAC output buffer OFF 0.5 - mV
1LSB

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Table 67. DAC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

CL ≤ 50 pF, RL ≥ 5 kΩ
- 1.5 3
DAC output buffer ON
DNL(2) Differential non linearity(4)
No RLOAD, CL ≤ 50 pF
- 1.5 3
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
- 2 4
DAC output buffer ON
INL(2) Integral non linearity(5)
No RLOAD, CL ≤ 50 pF LSB
- 2 4
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
- ±10 ±25
DAC output buffer ON
Offset(2) Offset error at code 0x800 (6)
No RLOAD, CL ≤ 50 pF
- ±5 ±8
DAC output buffer OFF
No RLOAD, CL ≤ 50 pF
Offset1(2) Offset error at code 0x001(7) - ±1.5 ±5
DAC output buffer OFF
VDDA = 3.3V
VREF+= 3.0 V
-20 -10 0
TA = 0 to 50 ° C
Offset error temperature DAC output buffer OFF
dOffset/dT(2) µV/°C
coefficient (code 0x800) VDDA = 3.3V
VREF+= 3.0 V
0 20 50
TA = 0 to 50 ° C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
- +0.1 / -0.2% +0.2 / -0.5%
DAC output buffer ON
Gain(2) Gain error(8) %
No RLOAD, CL ≤ 50 pF
- +0 / -0.2% +0 / -0.4%
DAC output buffer OFF
VDDA = 3.3V
VREF+= 3.0 V
-10 -2 0
TA = 0 to 50 ° C
Gain error temperature DAC output buffer OFF
dGain/dT(2) µV/°C
coefficient VDDA = 3.3V
VREF+= 3.0 V
-40 -8 0
TA = 0 to 50 ° C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
- 12 30
DAC output buffer ON
TUE(2) Total unadjusted error LSB
No RLOAD, CL ≤ 50 pF
- 8 12
DAC output buffer OFF

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Table 67. DAC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Settling time (full scale: for a

12-bit code transition between
tSETTLING the lowest and the highest CL ≤ 50 pF, RL ≥ 5 kΩ - 7 12 µs
input codes till DAC_OUT
reaches final value ±1LSB
Max frequency for a correct
DAC_OUT change (95% of
Update rate CL ≤ 50 pF, RL ≥ 5 kΩ - - 1 Msps
final value) with 1 LSB
variation in the input code
Wakeup time from off state
tWAKEUP (setting the ENx bit in the DAC CL ≤ 50 pF, RL ≥ 5 kΩ - 9 15 µs
Control register)(9)
VDDA supply rejection ratio
PSRR+ CL ≤ 50 pF, RL ≥ 5 kΩ - -60 -35 dB
(static DC measurement)
1. Guaranteed by characterization results.
2. Guaranteed by design, not tested in production.
3. Connected between DAC_OUT and VSSA.
4. Difference between two consecutive codes - 1 LSB.
5. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
6. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
7. Difference between the value measured at Code (0x001) and the ideal value.
8. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
9. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 32. 12-bit buffered/non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL

12-bit
digital to DAC_OUTx
analog
converter
CL

MSv45341V1

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

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6.3.17 Temperature sensor characteristics

Table 68. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TS_CAL1 0x1FF8 007A - 0x1FF8 007B
temperature of 30 °C, VDDA= 3 V
TS ADC raw data acquired at
TS_CAL2 0x1FF8 007E - 0x1FF8 007F
temperature of 130 °C, VDDA= 3 V

Table 69. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 1.48 1.61 1.75 mV/°C
V130 Voltage at 130°C ±5°C(2) 640 670 700 mV
IDDA(TEMP)(3) Current consumption - 3.4 6 µA
tSTART(3) Startup time - - 10
µs
TS_temp(4)(3) ADC sampling time when reading the temperature 10 - -
1. Guaranteed by characterization results.
2. Measured at VDD = 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design.
4. Shortest sampling time can be determined in the application by multiple iterations.

6.3.18 Comparators

Table 70. Comparator 1 characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 3.6 V

Comparator 1 input voltage
VIN - 0.6 - VDDA V
range
tSTART Comparator startup time - - 7 10
(2)
µs
td Propagation delay - - 3 10
Voffset Comparator offset - - ±3 ±10 mV
Comparator offset variation in VDDA = 3.6 V, VIN+ = 0 V,
dVoffset/dt 0 1.5 10 mV/1000 h
worst voltage stress conditions VIN- = VREFINT, TA = 25 ° C
ICOMP1 Current consumption(3) - - 160 260 nA
1. Guaranteed by characterization.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage not included.

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Table 71. Comparator 2 characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 - 3.6 V

VIN Comparator 2 input voltage range - 0 - VDDA V
Fast mode - 15 20
tSTART Comparator startup time
Slow mode - 20 25
1.65 V ≤VDDA ≤2.7 V - 1.8 3.5
td slow Propagation delay(2) in slow mode µs
2.7 V ≤VDDA ≤3.6 V - 2.5 6
1.65 V ≤VDDA ≤2.7 V - 0.8 2
td fast Propagation delay(2) in fast mode
2.7 V ≤VDDA ≤3.6 V - 1.2 4
Voffset Comparator offset error - ±4 ±20 mV
VDDA = 3.3V, TA = 0 to 50 ° C,
V- = VREFINT,
dThreshold/ Threshold voltage temperature ppm
3/4 VREFINT, - 15 30
dt coefficient /°C
1/2 VREFINT,
1/4 VREFINT.
Fast mode - 3.5 5
ICOMP2 Current consumption(3) µA
Slow mode - 0.5 2
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage (required for comparator operation) is not included.

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6.3.19 Timer characteristics

TIM timer characteristics
The parameters given in the Table 72 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 72. TIMx characteristics(1)

Symbol Parameter Conditions Min Max Unit

1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 32 MHz 31.25 - ns

Timer external clock frequency on CH1 0 fTIMxCLK/2 MHz

fEXT
to CH4 fTIMxCLK = 32 MHz 0 16 MHz
ResTIM Timer resolution - 16 bit
16-bit counter clock period when - 1 65536 tTIMxCLK
tCOUNTER internal clock is selected (timer’s
prescaler disabled) fTIMxCLK = 32 MHz 0.0312 2048 µs

- - 65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz - 134.2 s
1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.

6.3.20 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm) : with a bit rate up to 100 kbit/s
• Fast-mode (Fm) : with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The I2C timing requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual for details). The SDA and SCL I/O requirements
are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.
When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
All I2C SDA and SCL I/Os embed an analog filter (see Table 73 for the analog filter
characteristics).

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The analog spike filter is compliant with I2C timings requirements only for the following
voltage ranges:
• Fast mode Plus: 2.7 V ≤VDD ≤3.6 V and voltage scaling Range 1
• Fast mode:
– 2 V ≤VDD ≤3.6 V and voltage scaling Range 1 or Range 2.
– VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF.
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note: In Standard mode, no spike filter is required.

Table 73. I2C analog filter characteristics(1)

Symbol Parameter Conditions Min Max Unit

Range 1 100(3)
Maximum pulse width of spikes that
tAF Range 2 50(2) - ns
are suppressed by the analog filter
Range 3 -
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 26.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 74. SPI characteristics in voltage Range 1 (1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode 16
Slave mode - -
16
receiver

fSCK Slave mode

SPI clock frequency Transmitter - - 12(2) MHz
1/tc(SCK)
1.71<VDD<3.6V
Slave mode
Transmitter - - 16(2)
2.7<VDD<3.6V
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency

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Table 74. SPI characteristics in voltage Range 1 (1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Slave mode, SPI

tsu(NSS) NSS setup time 4*Tpclk - -
presc = 2
Slave mode, SPI
th(NSS) NSS hold time 2*Tpclk - -
presc = 2
tw(SCKH) Tpclk+
SCK high and low time Master mode Tpclk-2 Tpclk
tw(SCKL) 2

tsu(MI) Master mode 0 - -

Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 7 - -
Data input hold time
th(SI) Slave mode 3.5 - - ns
ta(SO Data output access time Slave mode 15 - 36
tdis(SO) Data output disable time Slave mode 10 - 30
Slave mode
- 18 41
1.65 V<VDD<3.6 V
tv(SO)
Data output valid time Slave mode
- 18 25
2.7 V<VDD<3.6 V
tv(MO) Master mode - 4 7
th(SO) Slave mode 10 - -
Data output hold time
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be
achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

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Table 75. SPI characteristics in voltage Range 2 (1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode 8
Slave mode Transmitter
fSCK 8
SPI clock frequency 1.65<VDD<3.6V - - MHz
1/tc(SCK)
Slave mode Transmitter
8(2)
2.7<VDD<3.6V
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
tw(SCKH)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tw(SCKL)
tsu(MI) Master mode 0 - -
Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 11 - -
Data input hold time ns
th(SI) Slave mode 4.5 - -
ta(SO Data output access time Slave mode 18 - 52
tdis(SO) Data output disable time Slave mode 12 - 42

tv(SO) Slave mode - 20 56.5

Data output valid time
tv(MO) Master mode - 5 9
th(SO) Slave mode 13 - -
Data output hold time
th(MO) Master mode 3 - -
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

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Table 76. SPI characteristics in voltage Range 3 (1)

Symbol Parameter Conditions Min Typ Max Unit

fSCK Master mode 2

SPI clock frequency - - MHz
1/tc(SCK) Slave mode 2(2)
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
tw(SCKH)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tw(SCKL)
tsu(MI) Master mode 1.5 - -
Data input setup time
tsu(SI) Slave mode 6 - -
th(MI) Master mode 13.5 - -
Data input hold time ns
th(SI) Slave mode 16 - -
ta(SO Data output access time Slave mode 30 - 70
tdis(SO) Data output disable time Slave mode 40 - 80

tv(SO) Slave mode - 30 70

Data output valid time
tv(MO) Master mode - 7 9
th(SO) Slave mode 25 - -
Data output hold time
th(MO) Master mode 8 - -
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

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Figure 33. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 34. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Figure 35. SPI timing diagram - master mode(1)

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)

ai14136d

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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I2S characteristics

Table 77. I2S characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S Main clock output - 256 x 8K 256xFs (2) MHz

Master data: 32 bits - 64xFs
fCK I2S clock frequency MHz
Slave data: 32 bits - 64xFs
I2S clock frequency duty
DCK Slave receiver 30 70 %
cycle
tv(WS) WS valid time Master mode - 15
th(WS) WS hold time Master mode 11 -
tsu(WS) WS setup time Slave mode 6 -
th(WS) WS hold time Slave mode 2 -
tsu(SD_MR) Master receiver 0 -
Data input setup time
tsu(SD_SR) Slave receiver 6.5 -
ns
th(SD_MR) Master receiver 18 -
Data input hold time
th(SD_SR) Slave receiver 15.5 -
tv(SD_ST) Slave transmitter (after enable edge) - 77
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 8
th(SD_ST) Slave transmitter (after enable edge) 18 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 1.5 -
1. Guaranteed by characterization results.
2. 256xFs maximum value is equal to the maximum clock frequency.

Note: Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.

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Figure 36. I2S slave timing diagram (Philips protocol)(1)

1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 37. I2S master timing diagram (Philips protocol)(1)

1. Guaranteed by characterization results.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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USB characteristics
The USB interface is USB-IF certified (full speed).

Table 78. USB startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB transceiver startup time 1 µs

1. Guaranteed by design.

Table 79. USB DC electrical characteristics

Symbol Parameter Conditions Min.(1) Max.(1) Unit

Input levels

VDD USB operating voltage - 3.0 3.6 V

VDI(2) Differential input sensitivity I(USB_DP, USB_DM) 0.2 -
VCM(2) Differential common mode range Includes VDI range 0.8 2.5 V
VSE(2) Single ended receiver threshold - 1.3 2.0

Output levels

VOL(3) Static output level low RL of 1.5 kΩ to 3.6 V(4) - 0.3

V
(3) (4)
VOH Static output level high RL of 15 kΩ to VSS 2.8 3.6
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
4. RL is the load connected on the USB drivers.

Figure 38. USB timings: definition of data signal rise and fall time

Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

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Table 80. USB: full speed electrical characteristics

Driver characteristics(1)

Symbol Parameter Conditions Min Max Unit

tr Rise time(2) CL = 50 pF 4 20 ns
(2)
tf Fall Time CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).

6.3.21 LCD controller

The devices embed a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.

Table 81. LCD controller characteristics

Symbol Parameter Min Typ Max Unit

VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.6 -
VLCD1 LCD internal reference voltage 1 - 2.73 -
VLCD2 LCD internal reference voltage 2 - 2.86 -
VLCD3 LCD internal reference voltage 3 - 2.98 - V
VLCD4 LCD internal reference voltage 4 - 3.12 -
VLCD5 LCD internal reference voltage 5 - 3.26 -
VLCD6 LCD internal reference voltage 6 - 3.4 -
VLCD7 LCD internal reference voltage 7 - 3.55 -
Cext VLCD external capacitance 0.1 - 2 µF
Supply current at VDD = 2.2 V - 3.3 -
ILCD(1) µA
Supply current at VDD = 3.0 V - 3.1 -
RHtot(2) Low drive resistive network overall value 5.28 6.6 7.92 MΩ
RL(2) High drive resistive network total value 192 240 288 kΩ
V44 Segment/Common highest level voltage - - VLCD V

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Table 81. LCD controller characteristics (continued)

Symbol Parameter Min Typ Max Unit

V34 Segment/Common 3/4 level voltage - 3/4 VLCD -

V23 Segment/Common 2/3 level voltage - 2/3 VLCD -
V12 Segment/Common 1/2 level voltage - 1/2 VLCD -
V
V13 Segment/Common 1/3 level voltage - 1/3 VLCD -
V14 Segment/Common 1/4 level voltage - 1/4 VLCD -
V0 Segment/Common lowest level voltage 0 - -
Segment/Common level voltage error
ΔVxx(3) - - ± 50 mV
TA = -40 to 85 ° C
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design.
3. Guaranteed by characterization results.

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.

7.1 LQFP100 package information

Figure 39. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline

SEATING PLANE
C

0.25 mm
A2
A

A1

c
GAUGE PLANE

ccc C

A1
K
L
D1
L1
D3

75 51

76 50
b

E1
E3

100 26
PIN 1 1 25
IDENTIFICATION
e 1L_ME_V5

1. Drawing is not to scale. Dimensions are in millimeters.

Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059

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Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package

mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat

recommended footprint
75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

ai14906c
1. Dimensions are expressed in millimeters.

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Device marking for LQFP100

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 41. LQFP100 marking example (package top view)

Product identification(1)
STM32L083

VZT6 R Revision code

Date code

Y WW

Pin 1
indentifier

MSv37842V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.2 UFBGA100 package information

Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline

Z Seating plane

ddd Z

A4 A3 A2 A1 A
E1 X
A1 ball A1 ball
identifier index area E
e Z

A
Z

D1 D

e
Y
M

12 1
BOTTOM VIEW Øb (100 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
A0C2_ME_V5

1. Drawing is not to scale.

Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 0.0094
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -

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Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data (continued)
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint

Dpad
Dsm

A0C2_FP_V1

Table 84. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm

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Device marking for UFBGA100

The following figure gives an example of topside marking versus ball A 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 44. UFBGA100 marking example (package top view)

Product identification(1)
STM32L

083VZI6

Date code

Y WW

Ball 1
indentifier Revision code

MSv40301V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.3 LQFP64 package information

Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE
C

A2
A
0.25 mm
GAUGE PLANE

A1

c
ccc C

A1
D K
D1 L
D3 L1
48 33

32
49

E1
E3

E
64 17

PIN 1 1 16
IDENTIFICATION e
5W_ME_V3

1. Drawing is not to scale.

Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -

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Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

48 33

0.3
49 0.5 32

12.7

10.3

10.3
64 17

1.2
1 16

7.8

12.7

ai14909c

1. Dimensions are expressed in millimeters.

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Device marking for LQFP64

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 47. LQFP64 marking example (package top view)

Product identification(1) Revision code

STM32L

083RZT6

Date code
Y WW
Pin 1 identifier

MSv37840V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.4 TFBGA64 package information

Figure 48. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline

A E1
E e F

H
F

D D1
Øb (64 balls) e
Ø eee M C B A
Ø fff M C
B A

1 8

TOP VIEW A1 ball A1 ball BOTTOM VIEW

index area identifier

C Seating plane

ddd C

A4
A2 A1 A
SIDE VIEW
R8_ME_V4

1. Drawing is not to scale.

Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.200 - - 0.0472
A1 0.150 - - 0.0059 - -
A2 - 0.200 - - 0.0079 -
A4 - - 0.600 - - 0.0236
b 0.250 0.300 0.350 0.0098 0.0118 0.0138
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 - 3.500 - - 0.1378 -
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 - 3.500 - - 0.1378 -
e - 0.500 - - 0.0197 -
F - 0.750 - - 0.0295 -

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Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint

Dpad
Dsm

R8_FP_V1

Table 87. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values

Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 1.125 mm
Pad trace width 0.100 mm

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Device marking for TFBGA64

The following figure gives an example of topside marking versus ball A 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 50. TFBGA64 marking example (package top view)

Product identification(1)
E083RZH6

Date code = Year + week

Y WW
Revision
code

Ball A1 R

MSv37818V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.5 LQFP48 package information

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

SEATING
PLANE
C

A2
A

A1

c
0.25 mm
GAUGE PLANE
ccc C

D K

A1
L
D1 L1
D3
36 25

37 24

E1
E3

E
48 13
PIN 1
IDENTIFICATION 1 12

e 5B_ME_V2

1. Drawing is not to scale.

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Table 88. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint

0.50
1.20

0.30
36 25
37 24

0.20
7.30
9.70 5.80

7.30

48 13
1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

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Device marking for LQFP48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 53. LQFP48 marking example (package top view)

Product identification(1)
STM32L

083CBT6

Date code

Y WW Revision code
Pin 1
indentifier
R

MSv40302V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.6 UFQFPN48 package information

Figure 54. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.

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Table 89. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 55. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

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Device marking for UFQFPN48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 56. UFQFPN48 marking example (package top view)

Product identification(1)
STM32L083

CZU6

Date code

Y WW
Revision code
Pin 1
indentifier
R

MSv63964V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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7.7 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 90. Thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient
54
LQFP48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
28
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
46
LQFP64 - 10 x 10 mm / 0.5 mm pitch
ΘJA °C/W
Thermal resistance junction-ambient
64
TFBGA64 - 5 x 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
41
LQFP100 - 14 x 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
57
UFBGA100 - 7 x 7 mm / 0.5 mm pitch

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Figure 57. Thermal resistance

4000

3500
UFQFPN48
3000
LQFP48

LQFP64
2500
PD (mW) TFBGA64
2000 LQFP100
UFBGA100
1500

1000

500

0
125 100 75 50 25 0

Temperature (°C)
MSv35433V5

7.7.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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8 Ordering information
Example: STM32 L 083 R Z T 6 D TR

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
L = Low power

Device subfamily
083 = USB + LCD + AES

Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins

Flash memory size

8 = 64 Kbytes
B = 128 Kbytes
Z = 192 Kbytes

Package
T = LQFP
H = TFBGA
I = UFBGA
U = UFQFPN

Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C

Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled

Packing
TR = tape and reel
No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

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9 Revision history

Table 91. Document revision history

Date Revision Changes

03-Aug-2015 1 Initial release

Added UFBGA100 package.
Changed confidentiality level to public.
Updated datasheet status to “production data”.
Modified ultra-low-power platform features on cover page.
Changed LCD_VLCD1 into LCD_VLCD2 in Section 3.13.2: VLCD
voltage monitoring.
In Section 6: Electrical characteristics, updated notes related to
values guaranteed by characterization.
26-Oct-2015 2 Updated |ΔVSS| definition to include VREF- in Table 23: Voltage
characteristics.
Added ΣVDD_USB and updated ΣIIO(PIN) in Figure 24: Current
characteristics.
Updated Table 56: EMI characteristics.
Updated fTRIG and VAIN maximum value, added VREF+ and VREF- in
Table 64: ADC characteristics.
Updated Figure 56: UFQFPN48 marking example (package top
view).

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Table 91. Document revision history (continued)

Date Revision Changes

Updated number of SPIs on cover page and in Table 2: Ultra-low-

power STM32L083xxx device features and peripheral counts.
Changed minimum comparator supply voltage to 1.65 V on cover
page. Added minimum DAC supply voltage on cover page.
Added number of fast and standard channels in Section 3.12:
Analog-to-digital converter (ADC).
Updated Section 3.19.2: Universal synchronous/asynchronous
receiver transmitter (USART) and Section 3.19.4: Serial peripheral
interface (SPI)/Inter-integrated sound (I2S) to mention the fact that
USARTs with synchronous mode feature can be used as SPI master
interfaces.
Added baudrate allowing to wake up the MCU from Stop mode in
Section 3.19.2: Universal synchronous/asynchronous receiver
22-Mar-2016 3 transmitter (USART) and Section 3.19.3: Low-power universal
asynchronous receiver transmitter (LPUART).
Section 6.3.15: 12-bit ADC characteristics:
– Table 64: ADC characteristics:
Distinction made between VDDA for fast and standard channels;
added note 1.
Added note 4. related to RADC.
Updated fTRIG..
Updated tS and tCONV.
– Updated equation 1 description.
– Updated Table 65: RAIN max for fADC = 16 MHz for fADC = 16 MHz
and distinction made between fast and standard channels.
Updated RO and added Note 2. in Table 67: DAC characteristics.
Added Table 71: USART/LPUART characteristics.

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Table 91. Document revision history (continued)

Date Revision Changes

Memories and I/Os moved after Core in Features.

Removed column "I/O operation" from Table 3: Functionalities
depending on the operating power supply range and added note
related to GPIO speed.
Updated VDD_USB in Section 3.4.1: Power supply schemes.
In Section 4: Pin descriptions, renamed USB_OE into USB_NOE.
In Section 5: Memory mapping, replaced memory mapping
schematic by reference to the reference manual.
Added mission profile compliance with JEDEC JESD47 in
Section 6.2: Absolute maximum ratings.
Updated minimum and maximum values of I/O weak pull-up
equivalent resistor (RPU) and weak pull-down equivalent resistor
(RPD) in Table 60: I/O static characteristics.
Updated minimum and maximum values of NRST weak pull-up
equivalent resistor (RPU) in Table 63: NRST pin characteristics.
12-Sep-2017 4 Added note 2. related to the position of the external capacitor below
Figure 27: Recommended NRST pin protection.
Updated RAIN in Table 64: ADC characteristics.
Updated Figure 32: 12-bit buffered/non-buffered DAC and added
note below figure.
Updated tAF maximum value for range 1 in Table 73: I2C analog filter
characteristics.
Removed Table 90: USART/LPUART characteristics.
NSS timing waveforms updated in Figure 33: SPI timing diagram -
slave mode and CPHA = 0 and Figure 34: SPI timing diagram - slave
mode and CPHA = 1(1).
Updated Figure 48: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin
profile fine pitch ball grid array package outline.
Added reference to optional marking or inset/upset marks in all
package device marking sections. Updated note below marking
schematics.

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Revision history STM32L083xx

Table 91. Document revision history (continued)

Date Revision Changes

Updated Arm logo and added Arm word mark notice in Section 1:
Introduction.
Removed Cortex logo.
Updated Table 5: Functionalities depending on the working mode
(from Run/active down to standby) to change I2C functionality to
disabled in Low-power Run and Low-power Sleep modes.
Updated VDD_USB description in Section 3.4.1: Power supply
schemes.
Replaced LCD_VLCD2 by LCD_VLCD1 in Section 3.13.2: VLCD
voltage monitoring.
Changed USARTx_RTS, USARTx_RTS_DE into
USARTx_RTS/USARTx_DE, and LPUART1_RTS,
LPUART1_RTS_DE into LPUART1_RTS/LPUART1_DE in
Section 4: Pin descriptions and in all alternate function tables. In
Table 16: STM32L083xx pin definition changed PB2 and PB12/PE11
14-Nov-2019 5 additional functions to LCD_VLCD2 and LCD_VLCD1, respectively.
Updated VDD_USB and note 2. in Table 26: General operating
conditions.
Removed R10K and R400K from Table 70: Comparator 1
characteristics.
Updated tAF maximum value for range 1 in Table 73: I2C analog filter
characteristics.
Updated paragraph introducing all package marking schematics to
add the new sentence “The printed markings may differ depending
on the supply chain.”
Updated Figure 48: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin
profile fine pitch ball grid array package outline, Figure 49: TFBGA64
– 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ,grid
array recommended footprint and Figure 87: TFBGA64
recommended PCB design rules (0.5 mm pitch BGA).

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