The City College of New York

Grove School of Engineering

Department of Electrical Engineering
160 Convent Ave, New York, NY 10031

EE 45700 – Digital Integrated Circuits

[EE 45700_LEC D_21109_Spring 2024]

4 Bit Binary Synchronous

Up Counter

Instructor:
Bruce Kim

Submitted by:
Paniz Peiravani

Date Submitted: April19, 2024

4 Bit Binary Synchronous Up Counter Paniz Peiravani

Table of Contents
Section1: Executive Summary ......................................................................................... 3
Section 2: Introduction and Background ....................................................................... 3
Section 3: Electric Circuit Schematics ............................................................................ 6
Section 4: Detailed Electric Layouts ............................................................................. 10
Section 5: LTSPICE code and parasitic extractions with calculation analysis ......... 20
Section 6: IRSIM Logic Simulations and Measurements ........................................... 25
Section 7: Measurements in LTSPICE for delays ....................................................... 29
Section 8: Measurements of power, delay, chip area, timing, number of transistors
for the layout ................................................................................................................... 30
Power ........................................................................................................................ 30
Delay ......................................................................................................................... 30
Chip Area ................................................................................................................. 31
Timing ...................................................................................................................... 31
Numebr of transsitro for layout............................................................................. 32
Section 9: Pathwave ADS simulations for RC circuits ................................................ 33
Section 10: Conclusion .................................................................................................... 35
References ........................................................................................................................ 36

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Section1: Executive Summary

The purpose of this project is to design a 4-bit Binary Synchronous Up Counter
using Electric software. Specifically, we aim to create a 4-bit up binary ripple counter
that counts from 0000 to 1111. We designed our 4-bit Binary Synchronous Up Counter
using JK flip-flop master-slave with two AND gates to generate the required counter
output. Additionally, we incorporated preset and clear functionalities to prevent unknown
states that could lead to incorrect counter operation. After designing our JK flip-flop, we
cascaded it to create a 4-bit JK flip-flop. To ensure the proper functionality of our design,
we performed DRC checks for our schematic, as well as both Well check and DRC for
layout to make sure our design works properly. Furthermore, we used IRSIM and
LTSpice to validate our design by comparing waveforms to the truth table. We will
continue to use LTSpice to further validate our designs and extract parasitic elements in
our layout. Finally, we performed calculations for various measurements in our design,
such as delay, power dissipation, chip area, timing, and number of transistors. For this
project based on the requirement we used 175nm or 𝞴=1 for our design.

Section 2: Introduction and Background

A 4-bit Binary Synchronous Up Counter is a digital electronic circuit that counts
from 0, 0000, to 15, 1111, in binary and repeats the sequence. Our flip flop design should
have three given inputs for the circuit which are clock, preset, and clear. As the counter is
synchronous, all the flip-flops share the same clock signal. This means that our output bits
will change simultaneously on the rising edge of the clock signal. Preset or clear ensures an
initial state for the clock. The clear resets the values of our flip-flops, setting everything to
logic low, and preset sets all output signals to logic high.
For this project we are using JK F/F. As you can see in Figure 1, our JK has J, K,
Clock “CLK’ as an input as well as Preset “PRE” and Clear “CLR” and Q and 𝑄̅ as an
output. You can see the full schematic design of our JK F/F in Figure ? As you can see on
Figure 1, to design our JK F/F we need have 4 three input NAND gates, 4 two input NAND
gates, and an inverter.

Figure 1 – JK F/F (Storr, 2022)

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Before we started to design our 4bit JK F/F, we first needed to know the truth table of our
gates to be able to check the functionality of our design. Below you can see the truth table
for 3 input NAND and 2 input NAND gates.

Table 1 – 3 input NAND Gate (Sinha, 2024)

A B C Output
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Table 2 - 2 input NAND Gate (Sinha, 2024)

A B Output
0 0 0
0 1 0
1 0 0
1 1 1

Once we designed our JK F/F, we will compare the IRSIM waveform for both schematic
and layout with JK F/F waveform to make sure our design works properly. You can see
both JK F/F waveform and truth table below in Figure 2.

Figure 2 - JK F/F waveform with preset and clear and truth table (Electrical4U, 2020)

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Once we designed our JK F/F and checked that our design worked properly, we started to
cascade our JK F/F to make our 4-bit Binary Synchronous Up Counter. As you can see
on Figure 3, to create our 4-bit JK F/F we needed 4 JK F/F and 2, two input AND gates.

Figure 3 - 4-bit Binary Synchronous Up Counter (Storr, 2024)

Since we needed to have two input AND gate, we needed to know the truth table for the
AND gate first. You can see the truth table of the AND gate on Table 3.

Table 3 - Two Input AND Gate Truth Table (Sinha, 2024)

A B Output
0 0 0
0 1 0
1 0 0
1 1 1

Once we designed our 4bit binary synchronous up counter, we checked our design by
comparing our LTSpice and IRSIM waveform to Figure 4 which is for 4bit binary
synchronous up counter timing diagram for JK F/F. As you can see closely on the
waveform, you can see the requirement is at timing should be at the rising edge.

Figure 4 - 4-bit Synchronous Counter Waveform Timing Diagram (Storr, 2024)

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Section 3: Electric Circuit Schematics

To design our 4-bit JK F/F, first we designed our requirement gates which are
three input NAND, two input NAND, inverter, and two input AND gates. Below you can
see the schematic of requirements gates.

In Figure 5, you can see our schematic for two input NAND gate with DRC check.

Figure 5 - Two Input NAND Gate

In Figure 6, you can see our schematic for three input NAND gate with DRC check.

Figure 6 - Three Input NAND Gate

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In Figure 7, you can see our schematic for two input AND gate with DRC check.

Figure 7 - Two Input AND Gate

In Figure 8, you can see our schematic for inverter with DRC check.

Figure 8 – Inverter

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Once we had our requirement gates, we started to design our JK F/F. As you can see on
Figure 9, we followed the design for JK F/F which you can see in Figure 1. For instance,
our JK F/F have 4 three input NAND gate, 4 two input NAND, and an inverter. We also
checked our design by checking DRC check.

Figure 9 - JK F/F

Once we had our JK F/F design, we started to design our JK F/F 4–bit binary
synchronous up counter. As you can see on Figure 10 and 11, we cascaded our JK F/F
design to make our design 4bit and added 2 two input AND gate to have final schematic
for 4bit synchronous up counter.

Figure 10 - 4–bit binary synchronous up counter timing diagram for JK F/F

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Figure 11 - 4–bit binary synchronous up counter timing diagram for JK F/F

Below you can see the closer look of our JK F/F 4bit binary synchronous up counter
design. For instance, Figure 12 shows the QA and QB of our design and Figure 13 shows
the QC and QD of our design.

Figure 12 - JK F/F 4–bit binary synchronous up counter showing QA and QB

Figure 13 - JK F/F 4–bit binary synchronous up counter showing QC and QD

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Once we had our completed design, we checked our design by using DRC check.

Figure 14 - DRC Check for 4bit JK F/F 4–bit binary synchronous up counter

Section 4: Detailed Electric Layouts

To start the layout, first, we needed to figure out the stick diagram and Euler’s path of our
gates. Once we had our Euler’s path for gates, then we could design our JK F/F. Below
you can see the stick diagram and Euler’s path of our three input NAND, two input
NAND, and two input AND gates.

On Figure 15, you can see our stick diagram and Euler’s path for two input AND gate.
After we drew our stick diagram, we designed our two input AND gate on the Electric
simulation and checked the DRC and Well Check to make sure our design worked
properly.

Euler’s Path: A-B

Figure 15 - Two Input AND Gate Stick Diagram and Euler’s Path

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Figure 16 - DRC check for our two input AND gate

Figure 17 - Well check for our two input AND gate

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On Figure 18, you can see our stick diagram and Euler’s path for three input NAND gate.
After we drew our stick diagram, we designed our three input NAND gate on the Electric
simulation and checked the DRC and Well Check to make sure our design worked
properly.

Euler’s Path: A-B-C

Figure 18 - Three Input NAND Gate Stick Diagram and Euler’s Path

Figure 19 - DRC check for our three input NAND gate

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Figure 20 - Well check for our three input NAND gate

On Figure 21, you can see our stick diagram and Euler’s path c for two input NAND
gate. After we drew our stick diagram, we designed our two input NAND gate on the
Electric simulation and checked the DRC and Well Check to make sure our design
worked properly.

Euler’s Path: A-B

Figure 21 - Two Input NAND Gate Stick Diagram and Euler’s Path

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Figure 22 - DRC check for our two input NAND gate

Figure 23 - Well check for our two input NAND gate

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Once we had our gates ready, we started to design our JK F/F. Below you can see the JK
F/F with DRC and Well Check.

Figure 24 - JK F/F

On Figure 25, we checked our JK F/F to make sure our design did not have any issue.

Figure 25 - JK F/F DRC Check

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On Figure 26, you can see our JK F/F pass the well check as well.

Figure 26 - JK F/F Well Check

Once we had our design for JK F/F with no error, we canscaded our design to get 4bit
synchrounous up counter JK F/F. We also needed to add 2 two input AND gate to our
desig based on the gate level diagram of the 4-bit synchronous up counter JK F/F.
Below on Figure 27, you can see our layout for 4-bit synchrounous up counter JK F/F.

Figure 27 - 4bit synchrounous up counter JK F/F

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To show you the more closer look of our layout, we took closer look picture of our
layout. You can see the closer look of our layout below.

Figure 28 - 4bit synchronous up counter layout / QA

Figure 29 - 4bit synchronous up counter layout / QB

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Figure 30 - 4bit synchronous up counter layout / QC

Figure 31 - 4bit synchronous up counter layout / QD

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Once we had our layout, we checked our design by checking DRC and Well check to
make sure our design does not have any errors.
On Figure 32, you can see our DRC check.

Figure 32 - Layout DRC Check

On Figure 33, you can see our Well check.

Figure 33 - Layout Well Check

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Section 5: LTSPICE code and parasitic extractions with

calculation analysis
After we checked that our design to make sure it does not have any errors, we started
checking the waveform in LTSpice and comparing them to the example waveform to
make sure that we had the correct output. For instance, thee the waveform should be from
0000 to 1111 and the timing should be at the rising edge of the clock.
To use the IRSIM, first, we need to figure the Spice Code out. You can see our Spice
Code for the schematic on Figure 34.

Figure 34 - Schematic Spice Code

Once we had the Spice Code, we ran our LTSpice for the schematic. You can see our
schematic LTSpice on Figure 35. As you can see below, we have the correct waveform
starting from 0000 to 1111 and the timing is at the rising edge. QD is our Most
Significant Bit and QA is our Least Significant Bit.

1 0 1 01 01 0 10 1 01 0 1 0 1 0 10 10 1 01 0 1 0 1 0 1 01 0 1
1
1
1
1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

Figure 35 - 4-bit Synchronous up counter LTSpice for Schematic

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Below on Figure 36, you can see the Spice Code for our layout.

Figure 36 – Layout Spice Code

Once we had the Spice Code, we ran our LTSpice for the layout. You can see our
schematic LTSpice waveform in Figure 37. As you can see below, the counter started at
1111 due to the PRE initialization. We have the correct waveform starting from 0000 to
1111 and the timing is at the rising edge. QD is our Most Significant Bit and QA is our
Least Significant Bit.

0 10 1 0 1 01 0 1 01 0 1 01 0 1 01 0 1 0 1 0 1 0 1 0 1 01 0 1 01 0 1 01 0 1 01 0 1 01 0 1 01 0 1 01 0 1 01
1
01

1
1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0
1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0
1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 0
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
0 1 0
Figure 37 - 4-bit Synchronous up counter LTSpice for Schematic

1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Once we had our LTSpice and was sure that our waveform were correct, we started the
Parasitic Extraction for the layout. Our aim for the Parasitic extraction is to find the
PMOS Resistance (𝑅𝑃 ), NMOS Resistance (𝑅𝑁 ), Capacitor (C) of our 𝑉𝐼𝑁 and 𝑉𝑂𝑈𝑇 . For
instance, 𝑉𝐼𝑁 are CLK (clock), PRE (preset), CLR (clear) and our 𝑉𝑂𝑈𝑇 are QA, QB, QC,
and QD.
To get the Parasitic extraction first we need to change preference of our library. For
instance, we went to the properties => preference => Parasitic and turned Extract R,
Extract C, and Include Gate in Resistance on which you can see on Figure below.

Figure 38 - Parasitic extraction set up

Then we need to go the Spice/CDL and chang Parasitics to Conservative RC.

Figure 39 - Turn on Conservative RC

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Based on the requirement, we included screenshots of a portions of the Parasitic

extraction to show that we have been able to extract the data successfully.
On Figure 40, you can see the beginning of the Parasitic extraction with NMOS
characteristics.

Figure 40 - Parasitic Extraction for NMOS characteristics.

On Figure 41, you can see the PMOS characteristics we got from Parasitic Extraction.

Figure 41 - PMOS characteristics

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On Figure 42, you can see Parasitic Extraction of Capacitors.

Figure 42 - Parasitic Extraction of Capacitors

On Figure 43, you can see Parasitic Extraction of Resistors.

Figure 43 - Parasitic Extraction of Resistors

To find our resistors and capacitors values we used below methodology.

The Parasiric extraction generalted 4299 lines of results. First we needed to filter the
extraction to be able to do the calculation.

To find the capacitor for both 𝑉𝐼𝑁 and 𝑉𝑂𝑈𝑇 , we did the below methodology:

1. We copy the capacitor section in the Word documents to be able to use the search
feature.
2. We found the capacitor for each signal.
3. Calculate the sum of total capacitance for each signal. Since the capacitors are
more than likely to be in parallel, we added them all together.

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To find the 𝑅𝑃 (PMOS resistor) and 𝑅𝑛 (NMOS resistor) for both 𝑉𝐼𝑁 and 𝑉𝑂𝑈𝑇 , we did
the below methodology:

1. Similar to methodology for capacitors, first we copy the resistor section in the
Word documents to be able to use the search feature.
2. First we need to find whether the resistor is connected to a PMOS or a NMOS to
know if should count it for Rp or Rn.
a. If it is connected to both PMOS and NMOS, then we applied it to
whichever is the source; for instance, left side connection is the source of
the resistor, and the right side is the destination.
b. If the source is something other than a PMOS or NMOS transistor
something like polysilicon, but the destination is a NMOS or PMOS, we
added the resistance to Rn or Rp since that NMOS or PMOS still shares
that resistance.
3. Finally, We calculated the sum of values for each signal. We also needed to check
if the transistor connects to is in parallel or series and added them accordingly.

Based on the Parasitic Extraction we found the following data for 𝑉𝐼𝑁 and 𝑉𝑂𝑈𝑇

Table 4 - Vin Measurment form Parasitics Extraction

Signals - 𝑉𝐼𝑁 𝑅𝑃 (Ω) 𝑅𝑁 (Ω) C (fF)

CLK 43.4 9.61 0.24
PRE 241.1 100.75 11.97
CLR 86.796 29.45 22.55

Table 5 - Vout Measurment form Parasitics Extraction

Signals - 𝑉𝑂𝑈𝑇 𝑅𝑃 (Ω) 𝑅𝑁 (Ω) C (fF)

QA 102.30 33.9 50.6
QB 86.80 52.7 39.75
QC 91.45 43.4 33.73
QD 116.45 21.7 25.55

Section 6: IRSIM Logic Simulations and Measurements

Once we designed our gates, before connecting them to design our JK F/F, we checked
out the waveform by using IRSIM and compared the waveform to the truth table of the
gates to make sure our gates worked correctly. Below you can see IRSIM for two input
NAND, three input NAND, and two input AND.
After those, you can see the IRSIM for our JK F/F and then 4bit synchronous up counter
JK F/F. To check our 4bit synchronous up counter waveform, we compare the waveform
with the waveform in Figure 4 which is on the requirement pdf of the project.

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On Figure 44, you can see the IRSIM for two input NAND gate for the schematic.

A 0 0 1 0 1

B 0 1 0 0 1

Out 1 1 1 1 0
Figure 44 - Two Input NAND Schematic

On Figure 45, you can see the IRSIM for three input NAND gate for the schematic.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Out 1 1 1 1 1 1 1 0
Figure 45 - Three Input NAND Schematic

On Figure 46, you can see the IRSIM for two input AND gate for the schematic.

A 0 1 0 1

B 0 0 1 1

Out 0 0 0 1
Figure 46 - Two Input AND Schematic

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Once we checked our gate to mak sure that they were worked properly, we started to
design our JK F/F. Below you can see the IRSIM for JK F/F schematic and layout
waveform.

On Figure 47, you can see the IRSIM waveform for the JK F/F for schematic.

CLK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Pre 0 1 0

CLR 0 1 0

J 0 1 0 1

K 0 1 0 1

Q 0 1 0 1

1 0 1 0
QBar
Figure 47 - JK F/F Schematic

On Figure 48, you can see the IRSIM waveform for the JK F/F for layout.

CLK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Pre 0 1 0

CLR 0 1 0

J 0 1 0 1

K 0 1 0 1

Q 0 1 0 1

QBar 1 0 1 0

Figure 48 - JK F/F Layout

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Next we checked our 4-bit synchronous up counter JK F/F IRSIM waveform. We

compared our waveform by Figure 4 to make sure our waveform were correct and it was
counting from 0000 to 1111. Also, we needed to check that the timing happened at the
rising edge.
On Figure 49, you can see the IRSIM for 4-bit synchronous up counter JK F/F for
schematic.

10 1 0 1 0 1 0 1 0 1 0 10 10 1 0 1 0 10 1 0 10 1 0 10 1 0 1 0
CLK
CLR 1
10
PRE 1
1
J
K 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
QA
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
QB
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
QC

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
Figure 49 - 4-bit synchronous up counter JK F/F for schematic 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

On Figure 50, you can see the IRSIM for 4-bit synchronous up counter JK F/F for layout.

10 1 0 1 0 1 0 1 0 1 01 0 1 0 1 0 1 0 1 0 1 0 10 1 0 1 0 1 0 10
CLK
CLR 1
10
PRE 1

J 1

K 1
QA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
QB 1 0 0 1 1 0 0 1 1 0 01 1 0 0 1 1

QC 1 0 0 0 0 1 1 1 10 0 0 0 1 1 1 1

QD 1 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1
1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 50 - 4-bit synchronous up counter JK F/F for layout

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As you can see on Figrue 49 and Figure 50 from last page, which are IRSIM layout for
our 4-bit synchronous up counter JK F/F for our schematic and layout, the output
waveform worked perfectly and it counted form 1 “0000” to 15 “1111.

Section 7: Measurements in LTSPICE for delays

Once we had a working layout and schematic, we started to find fall time, rise time, TPHL,
and TPLH. We are also going to find the Propagation Delay, TP. The formula to find
propagation delay is:

𝑇𝑃𝐻𝐿 + 𝑇𝑃𝐿𝐻
𝑇𝑃 =
2

We can find the fall time, rise time, TPHL, and TPLH by using proper Spice code. Below
you can find the Spice code for shcematic and layout that helped us to find the values.

On Figure 51, we can see the Spice code for schematic.

Figure 51 - Spice Code for Schematic

On Figure 52, we can see the Spice code for layout.

Figure 52 - Spice Code for Layout

Once we ran the code for our schematic, we can see the below values. We went to view
and then SPICE error log to saw the values.

Figure 53 - Measurement for Schematic

Figure 54 - Measurement for Layout

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Table 6 - Measurement Table

Rise Time Fall Time TPHL TPLH Propagation

Delay

Schematic 0.259644 ns 0.444021 ns 143.787 ns 256.166 ns 199.9765 ns

Layout 902.677 ns 799.833 ns 1643.19 ns 946.69 ns 1294.94 ns

Section 8: Measurements of power, delay, chip area, timing,

number of transistors for the layout
Power
To find the power, we used the measurements that we found from Parasitic Extraction
from our 𝑉𝑂𝑈𝑇 .
We used the power formula which is 𝑃 = 𝐶𝑉 2 𝑓.
- C = Capacitors
- V = VDD
- F = frequency
The sum of our capacitors are:
50.6 + 39.75 + 33.73 + 25.55 = 149.63 fF = 1.4963 × 10−13 𝐹
Our V is 3.3 and our f is 100ns or 107 Hz.

Power = (1.4963 × 10−13 𝐹) × (3.32 ) × (107 𝐻𝑧) = 𝟏. 𝟐𝟗𝟔𝟖𝟑𝟔𝟕 × 𝟏𝟎−𝟔 𝑾

Delay
To find the delay we added the TPHL and TPLH and then devide them by 2.

𝑇𝑃𝐻𝐿 + 𝑇𝑃𝐿𝐻
𝑇𝑃 =
2
Table 7 - Delay Table

Propagation Delay Schematic Layout

199.9765 ns 1294.94 ns

As you can see the layout propagation delay is longer than schematic. Due to the physical
characteristics of the circuit being considered, the difference in the delays makes sense.

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Chip Area
To find the chip area, first we needed to find the measurement of the layout which you
can see them below.

Figure 55 - Layout Measurment

Width: 800.5 𝞴
Length: 2317.5 𝞴
140,087.5 𝑛𝑚
800.5 × 175 𝑛𝑚 = 140,087.5 𝑛𝑚 = = 140.0875 𝑢𝑚
1000 𝑢𝑚

40,5562.5 𝑛𝑚
2317.5 × 175 𝑛𝑚 = 40,5562.5 𝑛𝑚 = = 405.5625 𝑢𝑚
1000 𝑢𝑚

Total Chip Area = 140.0875 𝑢𝑚 × 405.5625 𝑢𝑚 = 𝟓𝟔, 𝟕𝟕𝟕. 𝟑𝟒𝟓𝟑 𝒖𝒎𝟐

Timing
We could find the rise and fall times by using the values that we found in section 7 from our
Spice code. Below you can find the rise and the fall times:

Table 8 – Rise and Fall Time

Rise Time Fall Time

Schematic 0.259644 ns 0.444021 ns
Layout 902.677 ns 799.833 ns

As you can see the layout’s rise and fall times are much higher. Since the layout is close to a
real-world implementation than the schematic this difference is expected.

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Numebr of transsitro for layout

To find the number of transistors for the layout we could go to Cell => Cell Info =>
Summarize Cell Contents.

Figure 56 - Number of Transistor for Layout

To find the number of transistors for the schematic we could go to Cell => Cell Info =>
Number of Transistors.

Figure 57 - Number of Transistor for Schematic

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Section 9: Pathwave ADS simulations for RC circuits

To use the Pathway ADS Simulation, we had to go to the lab on the second floor of the
Grove building. We tried to use the software four times until we were able to use it. The
first time that we went there the license was expired, the second time there was exam and
we could not use the computers, the third time there was some issue with logging into the
computers and we could not login to the computer. Finally, on the fourth try, we were
able to use the software.

Figure 58 - Erros that we got

Once we could use the software, we started to design our JK F/F. First we design our JK
F/F.

Figure 59 - JK F/F on Pathway

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Then we started to design our RC circuit. First, we search on how we can built our RC
circuit for our JK F/F. Below you can see the design that we found that we could used to
design our JK F/F.

Figure 60 - JK F/F RC Circuit

Below you can see the our RC circuit for our 4bit synchrounous up counter JK F/F. To
design our RC circuit, we used the values for resistor and capacitors that we found from
the Parasitic extraction from our layout.

Figure 61 - 4bit cunchronous up counter JK F/F

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We were also able to run our design without facing any errors.

Figure 62 - Simulating Pathway without Error

Section 10: Conclusion

In this project, we designed and analyzed 4bit synchronous up counter. Through
the processes, we designed JK F/F and then we cascaded our designed to get our 4bit
synchronous up counter JK F/F. We were able to succefully design our 4-bit binary
synchronous up counter that counts from 0000 to 1111 and then restart to count form
0000 again. First, we degined schematic and layout for the requirmetns gates that we
needed to design our final designed and compare the waveform to the truth table to make
sure that our design worked properly. For intansce, we needed two input NAND gate,
three input NAND gate, and two input AND gate. Finally, we designed both schematic
and layout and checked our design by using LTSPice and IRSIM wavefrom and we saw
that our design counting works properly.
Once we had our design we used Parasitic extraction to find the capacitor and
resisitors values to use them for Pathway ADS software to design our RC circuit and to
use them for measuring Power. Finally, we measured rise time, fall time, TPHL, and
TPLH to be able to find the Propagation Delay. We also found number of transisotrs,
timing, and chip area values. We saw that the delay and timing for layout was larger than
schematic which is accurate since layout is close to a real-world implementation than the
schematic.
The motivation for this project was to check our ability to use the Electric
software as well as LTSPice. These are applications that are commonly used in the
industry, so achieving mastery in them would be beneficial. The knowledge we have
gained from this project is valuable and can be applied in future professional careers.
Overall, this project not only reinforced the theoretical understanding of the
digital circuit design of 4-bit binary synchronous up counter but also provided practical,
hands-on experience in the creation of a digital circuit.

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References
[1] W. Storr, “JK Flip Flop and the master-slave JK flip flop tutorial,” Basic Electronics
Tutorials, https://www.electronics-tutorials.ws/sequential/seq_2.html (accessed Apr. 8,
2024).

[2] S. Sinha, “NAND gate – the universal gate - electronics area,” Electronics Area –
Electrical and Electronics Tutorials and Circuits, https://electronicsarea.com/nand-gate-
truth-table/ (accessed Apr. 8, 2024).

[3] Electrical4U, “JK Flip Flop: What is it? (Truth Table & Timing Diagram),”
Electrical4U, https://www.electrical4u.com/jk-flip-flop/ (accessed Apr. 9, 2024).

[4] W. Storr, “Synchronous counter and Decade counter tutorial,” Basic Electronics
Tutorials, https://www.electronics-tutorials.ws/counter/count_3.html (accessed Apr. 12,
2024).

[5] S. Sinha, “Logic and gate – and truth table - electronics area,” Electronics Area -
Electrical and Electronics Tutorials and Circuits, https://electronicsarea.com/logic-and-
gate/ (accessed Apr. 12, 2024).

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