Allen and Holberg - CMOS Analog Circuit Design

IX. HIGH PERFORMANCE CMOS AMPLIFIERS

Contents
IX.1 Improving The Two-Stage Architecture
IX.2 Two-stage Cascode Architecture
IX.3 Folded Cascode Architecture
IX.4 Differential Output Architecture (Class AB)
IX.5 Low power amplifiers
IX.6 Dynamically biased amplifiers
IX.7

Organization

Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS

Chapter 7 Chapter 8 Chapter 9

CMOS Simple CMOS Op High Performance
Comparators Amps OTA's

COMPLEX

CIRCUITS

Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE

Chapter 2 Chapter 3
Chapter 4 Device
CMOS CMOS Device
Characterization
Technology Modeling

DEVICES
Allen and Holberg - CMOS Analog Circuit Design

IX.1 IMPROVING THE TWO-STAGE ARCHITECTURE

Amplifiers Using an MOS Output Stage
PUSH-PULL CMOS OTA
This amplifier is a simple extension of the seven-transistor OTA
studied in Section 8.
VDD

M9 M7
VDD VDD

vOUT
M1 M2
- VDD +
Cc

M8 CL

M6

M3 M4

small-signal equivalent circuit:

Cc
vout

+
C1 r1 v1 CL r2 gm1 Ai
gm1 vi gm6 v1 vi
2
-

1 1
where gm1 = gm2, r1 = g , r 2 =
ds2 + g ds4 g ds6 + g ds7
Allen and Holberg - CMOS Analog Circuit Design

Amplifiers Using an MOS Output Stage - Continued

Network equations:
[g1 + s(C1 + CL)]v1 - sCcv2 = gm1vi
gm1AIvi
[g5 + sCc]v1 + [g2 + s(Cc + CL)]v2 = 2
i7
AI is the current gain from M1 to M7: AI = i
1
-g m6
z=
 AI 
 - 1 Cc
2 
-g1g2
p1 ≈
gm6Cc
-g m6
p2 ≈ C
L
gm1gm6
AV ≈ g g
1 2

To guarantee that the zero stays in the left-half plane, AI > 2

Allen and Holberg - CMOS Analog Circuit Design

Amplifiers Using an MOS Output Stage - Continued

Example:

VDD VDD

M9 M7 M9 M7
VDD VDD VDD VDD

-
M1
VDD
M2 + - M1 M2 +
Cc Cc
CL CL
M8

M6 M6

M3 M4 M3 M4

Push-Pull (AI ≈ 3) Standard (AI = 0)

140

120

100

80
Gain(db)
Push-Pull phase
60
Standard gain
40

20 Push-Pull
gain
Standard phase
0

-20
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency
Allen and Holberg - CMOS Analog Circuit Design

IX.2 Two-Stage Cascode Architecture

Why Cascode Op Amps?
• Control the frequency behavior
• Increase PSRR
• Simplifies design

Where is the Cascode Technique Applied?

• First stage -
Good noise performance
Requires level translation to second stage
Requires Miller compensation
• Second stage -
Self compensating
Reduces the efficiency of the Miller compensation
Increases PSRR
Allen and Holberg - CMOS Analog Circuit Design

Power Supply Rejection Ratio (PSRR)

Definition:
+ +
vdd VDD
- -
+
vout
vin + +
- VSS
vss
-
-

vout
Av(vdd=0) vin (vdd=0)
+
PSRR = A (v =0) = v
dd in out
vdd (vin=0)

Calculation of PSRR:

+ + Addvdd
vdd VDD
v1 vout
- -
vout v2 Av (v1 -v2 )
+ =>
VSS
-

vout = Addvdd + A v(v1-v2) = A ddvdd - Avvout

vout(1 + Av) = A ddvdd Extends bandwidth beyond GB

↓
vout Add A dd 1 vout KAdd A dd
= ≈ = = ≈
vdd 1 + Av Av PSRR+ vdd 1+KAv Av
 Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of Positive PSRR for the Two-Stage OTA

+
+ VDD
vdd
- 1.) The M7 current sink
-
causes VGS6 to act like a
battery.
2.) Therefore, vdd
M3 M4
couples from the source
M6
M1 M2 Cc to gate of M6.
- + vout 3.) The path to the output
is through any capacitance
M5 M7 from gate to drain of M6.
+
VBias
-
+
VSS
-
4.) Resultant circuit

model- vout
+
vdd Cc Rout
-

Must reduce C c ! Vout

Vdd
1
Rout Cc
0dB ω

-60 to Other sources of

-80dB PSRR beside C c
Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA

+
VDD
-

M3 M4
M6
M1 M2 Cc
- + vout

M5 M7

+
VBias
-
? +
vss
+-
VSS
-

Two mechanisms of vss injection:

M5 or M7 iss M5
+
+ + VBias
VBias -
- vss
+
+- vss
VSS -+
- VSS
-

Transconductance injection Capacitance injection

Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA -

Continued
Transconductance injection:
Vout
Path through the input stage: Vss
Not important as long as
20 to
CMRR is high. 40 dB

Path through the output stage:

vout ≈ issRout = gm7 vssRout
0dB ω
1
vout Rout Cout
vss = g m7Rout
Frequency dependence -
 1 
Rout → Rout|| 
sCout

Capacitance injection:
vout
+
Cgd7 Rout
vss
-

Vout
Vss
1
Rout C gd7
0dB ω

-60 to First stage

-80dB transconductance
injection

Reduce Cgd7!
Allen and Holberg - CMOS Analog Circuit Design

Problems with the two-stage OTA:

• Insufficient gain

• Poor stability for large load capacitance

• Poor PSRR

These problems can be addressed using various cascode structures.

We will consider several approaches:

• Cascoding the first stage

• Cascoding the second stage

• Folded cascode
Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode

VDD

M3 M4
VDD VDD

VBP MC2
VDD
VO1
VBN
MC3 MC1

+ -
M1 M2

VBIAS

VSS

ro1 ≈ (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2

Gain ≈ gm2ro1

gmcrdsc
• Overall gain increased by ≈ 2

• Requires voltage translation to drive next stage

• Requires additional biasing for cascode devices

• Common-mode problem at drains of M1 and M2

Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode - Continued

Common-mode improvement:
VDD

M3 M4
VDD VDD

ICM
VBP MC2
VDD
VO1

MC3 MC1

+ M9 -
M1 M2

VBIAS

VSS

Common-mode circuitry (M9) maintains Vds of M1 and M2

A V = gm1ro1

ro1 ≈ (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2

-1
p1 ≈ C r
L o1

gm1
GB ≈ A V|p1| ≈
CL

Output range of this amplifier is poor when used by itself. It needs an

output stage to be practical.
Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode - Continued

Implementation of ICM

VDD

M3 M4

ICM
ICM

VBP VDD
MC2

VSS

VSS VSS
MC1
MC3

vin -vin vin -vin

VSS VSS
2 2 2 2
VSS M1 M2

I5 +ICM

VSS
Allen and Holberg - CMOS Analog Circuit Design

Level Translator for First Stage Cascode

VDD

M4
MT2

M6
MC2
MT1

MC1
Vo

VSS

M2

M7
VBIAS
M5

VSS
Allen and Holberg - CMOS Analog Circuit Design

Improved PSRR For Two-Stage OTA

Use cascode to reject Cc feedforward

VDD

M3 M4
M6
M8
VB1
M9 Cc
vOUT

- M1 M2 +

M5
VB2 M7

VSS

+PSRR is reduced by M9

Disadvantage -
1
Miller pole is larger because R1 ≈
gm9

positive input common mode range is restricted

Allen and Holberg - CMOS Analog Circuit Design

Complete Two Stage Cascode

VDD

M3 M4
MT2

M6
VBP MC2
MT1
ICM
MC1
MC3 Vo

VSS
M9

M1 M2

M7
VBIAS
M5

VSS
Allen and Holberg - CMOS Analog Circuit Design

Second Stage Cascode

VDD

M3 M4
M6

VBP MC6

Comp Vo

VBN MC5
M1 M2

M7
VBIAS
M5

VSS
Allen and Holberg - CMOS Analog Circuit Design

LOAD COMPENSATED CASCODE AMPLIFIER

VDD

M3 M4
M9 VDD VDD
M6
VDD VDD

MC3 MC2
VBP
VBP VDD
VDD - +

M1 M2 MC1
I5
M5 VBN VSS
VBIAS CL
M8 M7

VSS

A V1 = g
gm 2 
gm2
m4
 AV = 2(g ) (g m6 + gm9) Ro
A V2 = 2 (g m6 + g m9 )R o 
1 m4

where
Ro ≈ (g mc2rdsc2)rds6 || (gmc1rdsc1)rds7 and M7 = M8
Or,
 gm1 +g m2
AV =   KR o
 2 
where
W6/L6 W 9/L 9
K=
W4/L4 = W3/L3
Allen and Holberg - CMOS Analog Circuit Design

Design Example

Pertinent design equations:

iOUT
SR = C
L

gm2
AV =
2(gm4) (gm6 + gm7 ) ro

g m2 (g m6 + g m7 )
GB = 2(gm4)CL

I5
Vin(max) = VDD - ß3 - |VT3|(max) + V T1(min)

I5
Vin(min) = VSS + VDS5 + ß1 + VT1(max)

Specifications:

VDD = -VSS = 5V

SR = 5V/µs into CL = 50pf

GB = 5 MHz

AV > 5000

CMR = ±3V

Output swing = ±3V

Allen and Holberg - CMOS Analog Circuit Design

Design Procedure

1.) Design for maximum source/sink current

Isource/sink = C L(SR) = 50pf(5V/µs) = 250 µA

2.) Note that -

S6
Max. IOUT (source) = S I5
4

Max. IOUT (Sink) = Max. IOUT (source) if S3 = S 4,

S9 = S6 and S7 = S 8

3.) Choose I 5 = 100 µA

∴ S 9 = S 6 = 2.5 S 4 = 2.5 S 3

4.) Design for ± 3V output capability

a.) Negative peak

Let VDSC1(sat.) = V DS7(sat.) = 1V

under negative peak conditions, IC1 = I 7 = 250 µA

Divide 2V equally,

2I7 2IC1 2I7 500 µA

∴ 2V = + =2
KN'S7 KN'SC1 KN'S7 = 2 17 µA/V 2 S 7

∴ S 7 = S C1 = 29.4 -> S 8 = S 7 = 29.4

Allen and Holberg - CMOS Analog Circuit Design

b.) Positive peak, divide voltage equally,

2I6 2IC2 2I6

VSD6 = VSDC2 = 1V , --> 2V = + =2
KP'S6 KP'SC2 KP'S6

∴ S 6 = S C2 = 62.5 --> S 3 = S 4 = 25

5.) Design of VBP and V BN

a.) VBN (Assume max. I OUT (sink) conditions)

IOUT(sink) = 250 µA
MC1 -3
VBN -5V
VDSC1 = VGSC1 - V TC1 (ignoring bulk effects)
-4
1 = VGSC1 -1 --> VGSC1 = 2V
M7
∴ V BN = -2V
-5

b.) VBP (Assume max.

IOUT (source) conditions)
+5V

VDSC2 = VGSC2 - |V TC2| (ignoring bulk effects)

+4
VSGC2 = 2V ∴ V BP = +2V
VBP
MC2 IOUT(source)= 250 µA
+3V
Allen and Holberg - CMOS Analog Circuit Design

6.) Check max. Vin influence on S3 (S4)

I5
Vin (max) = VDD - ß3 - |VT03|max + VT1(min)

100 µA
+3 = +5 - - 1.2 + 0.8
KP'S3

100 µA
S3 = µA = 4.88 (Use S 3 = S4 = 25)
8 2 (1.6V) 2
V

With S 3 = 25, V in (max) = 3.89V which exceeds the specification.

7.) Find gm1 (gm2)

a.) AV specification
gm1 g m6 + g m 7
AV =   R II
gm4  2 

gm4 = 2I4Kp'S4 = 141.1 µs

gm6 = 2I6KP'S6 = 353.5 µs
gm7 = 2I7KN'S7 = 353.5 µs
gmc1 = gm7
gmc2 = gm6
1
rds6 = rdsc2 = I λ = 0.4 MΩ
6 P
1
rds7 = rdsc1 =
I7λΝ = 0.8 MΩ
RII ≈ (gmc1rdsc1rds7) || (gmc2rdsc2rds6) = 45.25 MΩ

 gm1   707 µs

∴ 141.1  ( 226.24 MΩ || 56.56 MΩ) > 5000 V/V
  2 
∴ gm1 > 44 µs
Allen and Holberg - CMOS Analog Circuit Design

b.) GB specification
g m1 (g m6 + g m7 )
GB = 2gm4 (50pF) = 10π.10 6 rps

(10π.106)(141.1.10-6)(50.10-12)
gm1 = = 627 µS
707.10-6/2

gm 2
∴ S 1 = S2 = = 231
I5K N '

gm1gm6+gm7 627 707µS

  R II =
141.1  2 (45.25MΩ) = 71,080
AV =
gm4 2 
8.) Find S5 from Vin (min)

I5
Vin (min) = VSS + VDS5 + ß1 + VT1(max)

100 µA
-3 = -5 + VDS5 + µA + 1.2
17 2 S 1
V

100
V DS5 = 0.8 - = 0.8 - 0.1596 = 0.641
(17)(231)

2(100 µA)
VDS5 (sat) = 0.641 = µA
(17 2 )S5
V
2(100µA)
S5 = = 28.6
17µA/V 2(0.641)2

9.) VBIAS -

KN'.28.6
I5 = 2 ( V BIAS + 5 -1) 2 = 100 µA

VBIAS = 0.411 - 4 = -3.359V

Allen and Holberg - CMOS Analog Circuit Design

10.) Summary of design -

S1 = S2 = 231 S7 = S8 = SC1 = 29.4

S3 = S4 = 25 VBP = 2V
S5 = 28.6 VBN = -2V
S6 = S9 = SC2 = SC3 = 62.5 VBIAS = -3.359V

11.) Check on power dissipation

Pdiss = 10(I8 + I5 + I7) = 10(125µA + 100µA + 125µA)

= 3.5mW

12.) Design W's for lateral diffusion and simulate

Allen and Holberg - CMOS Analog Circuit Design

X.3 FOLDED CASCODE ARCHITECTURE

Principle
VDD

1.5 I 1.5 I

VBP M4
M3

I
v+IN vout =gm1 Rout vin
M1 M2 v-IN
I

M5 M6

M7 M8

VSS

Currents in upper current sinks must be greater than I to avoid zero

current in the cascode mirror (M5-M8).

Advantages

Good input CMR.

Good frequency response.

Self compensating.
Allen and Holberg - CMOS Analog Circuit Design

Folded Cascode OP Amp

VDD

VB3
M4
M3

- + VB3 M14
M1 M2 V OUT
M9 Cc
M8

M16
VB1 M5
M15

VB2 M11
M10

M13
M12

VSS

High gain, High speed, cascode amp

GB ≈ 10 MHz, AVDC ≈ 100 dB

Allen and Holberg - CMOS Analog Circuit Design

XI. 4 DIFFERENTIAL OUTPUT OTA'S

Implementation Using Two Differential-In, Singled-Ended Op Amps

+
- - R R
-
+ +

-
+

Conceptual Implementation of Differential In-Out OP Amp

VDD

+ VDD VDD VBIAS

Vin
- +
- Vout
CL CL
Common
mode
feedback

VSS
Allen and Holberg - CMOS Analog Circuit Design

Schematic of a Fully Differential In-Out, FoldedCascode Op Amp

VDD = +5V
MP1A
MP1 VBIAS1

MP2A
VDD VDD VBIAS2
MP2

-
vOUT
CL +
+ CL
MN2A
vIN
VSS VSS VBIAS3
-
MN2

MN1 MN1A
VSS VSS VBIAS4
VSS

MN3
MN3A

VSS = -5V
Allen and Holberg - CMOS Analog Circuit Design

Evolution of Class AB Amplifier

VDD VDD

VB2

v+IN v-IN
vOUT vOUT

v-IN v+IN

VB1

VSS VSS
combine

M17 M12 M11 VB2 M14

v+IN M1 M2 v-IN

v+IN M3 M4 v-IN

M18 VB1 M10 M9 M13

Problem: DC levels of input voltages incompatible

Allen and Holberg - CMOS Analog Circuit Design

M17 M12 M11 M14

M5 M6
v+OUT v+IN M1 M2 v-IN v-OUT

M7 M8
M3 M4

I I
M18 M10 M9 M13

DC problem solved, but amplifier has low gain and requires CM

feedback

M17 M12 M11 M14

VB1 VB3
M16
M5 M6
v+OUT v+IN M1 M2 v-IN v-OUT

VB2 VB4
M8 M15
M3 M4
M7

I I
M18 M10 M9 M13

Gain improved using cascode

Allen and Holberg - CMOS Analog Circuit Design

IX.5 LOW POWER AMPLIFIERS

General
Objective is to minimize the dc power dissipation.
Typical applications are:
1. Battery powered circuits.
2. Biomedical instrumentation.
3. Low power analog "VLSI."

Weak Inversion or Subthreshold Operation

Drain current -

 W  qvGS
iD =   I D exp nkT ( 1 + lv D S)
L  

Small signal parameters -

qiD
gm = nkT , rds ≈ (λiD )-1

Device characteristics -

iD iD
square
law
100nA
100nA

weak exponential
inversion vGS < VT

vDS vGS
1 2 VT
Allen and Holberg - CMOS Analog Circuit Design

Op Amp Operating in Weak Inversion

Consider the two-stage op amp with reduced currents and power

supplieds,
gm2 gm6 1
AV = =
( gds2+gds4) ( gds6+gds7) n2n6( kT/q) 2( l2+l4) ( l6+l7)

where,

gm1 ID1 2ID1  n1kT

GB = C = (n kT/q)C and SR = C = 2GB q 
1  

VDD

M3 M4

M6
C
M1 M2

M7
M5

VSS
Allen and Holberg - CMOS Analog Circuit Design

Design Example

Calculate the gain, unity-gain bandwidth, and slew rate of the previous
two-stage op amp used in weak inversion if:

ID5 = 200nA nP = 1.5 λP = 0.02V-1

L = 10 µm nN = 2.5 λN = 0.01V-1

C = 5pF T = 27˚C

1
AV = (1.5)(2.5)(0.026)(2)(0.1+0.02)(0.01+0.02) = 5698

100.10-9
GB = = 307.69Krps or 48.97KHz
(2.5)(0.026)(5.10-12)
SR = 2(153.85.103)(2.5)(0.026) = 0.04V/µs
If V DD = -V SS = 2.5, the power dissipation is 0.2µW assuming ID7 = I D5.
Allen and Holberg - CMOS Analog Circuit Design

Push-Pull Micropower Op Amp

First stage clamped (low gain, low bias current)-

VDD
M3 M4

M8 M6

M1 M2

CC

VB M5

M9 M7

VSS

Gain enhancement for Push-Pull Micropower Op Amp

M11
M3 M10 M12 M4

M8 M6

M1 M2

CC

M5
VB M13

M9 M7

VSS
Allen and Holberg - CMOS Analog Circuit Design

Push-Pull Cascode Micropower Op Amp

VDD

M3 M4

M8 M6

VB1
M1 M2 VDD
M10

VB2 VSS CC

VB M5 M11

M9 M7

VSS

1 1
+ n
nN P
AV = 2 ≈ 10,000
Vt ( λ P n P + λ N 2 n N 2 )
2

self-compensating
Low power << 1 µW
Allen and Holberg - CMOS Analog Circuit Design

Micropower Op Amp

VDD

M5 M6
M9 M7 M8 M10

M16
va vb M15 M18

M3 M4 100nA
v-1 v+2 vo
M19
M17
M2
VBIAS M14
M11 M12
120nA 20nA 20nA

VSS

Pdiss = |VDD -VSS|(260nA)

vo = vagm9ro - vbgm10ro ≈ g m9ro(va - vb) ; gm9 = gm10

where
ro ≈ (rds10gm18rds18)||(rds12gm19rds19)

and
nP 1 + k
(va - vb) = va - vb = n  1 - k ( v 2 - v 1 )
N 

(See following pages)

Allen and Holberg - CMOS Analog Circuit Design

Small-Signal Analysis

va vb

gm3 v1 1 gm8 vb gm7 va 1 gm4 v2

gm5 gm6

gm3 g m8
va = -v1 g - vb g
m5 m5

gm4 g m7
vb = -v2 - v a
gm6 gm6

v1ggm5
m3
  gm8
 va 
  
-1 -g
m5 
v2gm4
=
 gm7  v 
 gm6  -g
m4
-1
 b

 gm3 gm8

 
v1g -g
m5 m5

 gm4  gm 3 g m4 g m 8
 v2g
m6
-1  -v 1 g + v 2 g g
m5 m5 m6
va = =
 -1
gm8
-g  1-
g m7 g m 8
 m5  gm5 gm6
 gm7 
 -g
m4
-1

Allen and Holberg - CMOS Analog Circuit Design

 gm3

 
-1 v1g
m5

 gm7 gm4  gm 4 g m3 g m 7
 -g
m6
v2g
m6  -v 2 g + v 1 g g
m6 m5 m6
vb = =
 -1
gm8
-g  1-
g m7 g m 8
 m5  gm5 gm6
 gm7 
 -g
m4
-1

 gm3 g m4 g m 8  gm4 g m3 g m 7
 -v1  -  -v2
gm5 gm6
+ v 2 + v 1
 gm5 gm5 gm6  gm6
v a - vb = g m7 g m 8
1- g g
m5 m4

gm3 = gm4 = gmI ; gm5 = gm6 = gmII ; gm7 = gm8 = gmIII

Then

 gmI g mI g mIII  gmI g mI g mIII

 -v1 + v 2  -  -v 2 + v 1 
 gmII gmII2   gmII gmII2 
v a - vb =
g mIII 2
1-
gmII2

gmIII
Define:
gmII = k

gmI  gmI 
v
( 2 - v 1) g ( 1 + k)  
mII  gmII
v a - vb = = ( v 2 - v1)
1 - k2 1 - k

gmI  1 
gmII 1 - k ( v 2 - v 1 )
v a - vb =

Consider dc currents under balanced condititions:

I 4 = I6 + I7

I 3 = I5 + I8
Allen and Holberg - CMOS Analog Circuit Design

 S8  S7
I 8 = I6  S  ; I 7 = I 5  S 
 6  5

I8 S 8
⇒ in W.I. gm is proportional to I
I6 = S6

I 8 S8 I 7 S7
= = k;
I6 S6 I5 = S5 = k

Since under balanced conditions

I 3 = I4 ; I4 = I5

I4 = I6 (1 + k)

I3 = I5 (1 + k)

Again, since gm ∝ I in weak inversion, then

I6
gm4 ∝ I 6(1 + k) or gm4 =
kT (1 + k)
nN
q
and
gm3 ∝ I5(1 + k)

since
I6
gm3 = gm4 = gmI ⇒ gmI =
k T (1 + k)
nN
q
Also
I6
gm4 = gmII =
kT
nN
q
then

gmI  nP 
gmII  n N  (1 + k)
=
Allen and Holberg - CMOS Analog Circuit Design

finally:
nP 1 + k
v a - vb = n  ( v 2 - v 1 )
N 1 - k 

1 + k
≈ 1 - k ( v 2 - v1)

Therefore,

 1+k
vo = gm9 ro 1-k  vid
 
Allen and Holberg - CMOS Analog Circuit Design

OTA CURRENT OVERDRIVE

Need large sinking and source currents without having to have large
quiescent currents.
One possible solution uses "tail current boosting" -
Assume that S 3 = S4 = S11 = S13, S18 = AS17, S15 = S16 = S17 = ..

M11 M13
M3 M4

I1 I2
I2
- +
M1 M2
I1

I2 I2 +I1 +A I2 -I1

A I2 -I1 I10 I19 ≈0

I1 I2 -I1

M15 M16 M17 M18 M9 M10 M19

W18 = AW17
L18 L17
Allen and Holberg - CMOS Analog Circuit Design

Principle in Achieving Current Overdrive

Differential amplifier transconductance characteristics -

iD
I10 (overdrive)

I10 (normal)

I10 (overdrive)
2

I10 (normal)
2

vIN
0
I10 (overdrive) I10 (overdrive)
-
B B
I10 (normal) I10 (normal)
-
B B

Positive feedback -
I10 I10 I10
iOUT (max/min) ≈ 1 - Loop gain = =
g m 1 8 gm 1 3 gm 1 3
1- g 1- g A
m17 gm14 m9
Allen and Holberg - CMOS Analog Circuit Design

A Dynamically Biased Micropower Op Amp

VDD

M12 M13 M14

M8 M3 M4 M5A
M11

I1 I2

- +
M1 M2 VBP
M5B

vOUT

M6B
VBN

I10

M7 M15 M16 M17 M18 M9 M10 M19 M20 M21 M22 M6A

VSS
Allen and Holberg - CMOS Analog Circuit Design

Parametric Overdrive Curves for Dynamically Biased Op Amp

A=2

A = 1.5
IOUT 1
A=1
I10
A = 0.3

A=0

0
0 1 2
vIN/ nVt
Allen and Holberg - CMOS Analog Circuit Design

IX.7 - DYNAMICALLY BIASED AMPLIFIERS

Dynamic circuits take advantage of the fact that many applications
are synchronously clocked resulting in periods of time where the circuits is
not functioning.
Will examine:
- Dynamic or switched resistors
- Dynamically biased amplifiers
- Dynamically biased, push-pull, cascode op amp
Two Phase Clock

φ1

φ1 switches
on

φ1 switches
t/T
off 0 1 2 3 4 5

φ2

φ2 switches
on

φ2 switches t/T
off 0 1 2 3 4 5

A Switched Resistance Realization

φ2 φ1
D
Pretune φ2 G VSS RFET
circuit CG
φ2 φ1
S

Switched resistor
Allen and Holberg - CMOS Analog Circuit Design

A Continuous Time Resistor Realization with Increased Signal Swing

i
+ D

- D1 M1
VC
+ G1 VSS
D2 S1 vDS RFET
M2
G2 +
VSS
VC
S2 -

- S

Implementation of the Continuous Time Switched Resistor Realization

using Dynamic Techniques

φ2 φ1

CG
φ2
VSS

Pretune M2
RFET
circuit
φ2
VSS
CG M1
φ2 φ1

Switched resistor
Allen and Holberg - CMOS Analog Circuit Design

Dynamically Biased Inverter

VDD

CB

M2

iD
φ2 φ2
vOUT

COS
φ1
M1
+

vIN
φ2 VSS
-

During phase 2 the offset and bias of the inverter is sampled and
applied to C OS and C B.

During phase 1 COS is connected in series with the input and

provides offset cancelling plus bias for M1. CB provides the bias for M2.
Allen and Holberg - CMOS Analog Circuit Design

Dynamic, Push-pull, Cascode Op Amp

Simplified schematic -

VDD

+
VB2 φ1 φ2
-
M8 M4

M7 M3
VDD VDD

C2
φ2 φ1
IB v-IN v+IN vOUT

C1

M6 M2
VSS VSS

φ1 φ2
M5 + M1
VB1
-

VSS
Allen and Holberg - CMOS Analog Circuit Design

Dynamic, Push-pull, Cascode Op Amp - Cont'd

Phase 1 Clock Period

VDD

M8

M7
VDD
+ VDD - VB2 - v+IN
C2
-
IB v+IN
C1
v+IN - VSS - VB1
VSS
M6

M5

VSS

Phase 2 Clock Period

VDD

v-IN - v+IN + VDD - VB2 M4

M3 VDD
+
VDD - VB2 - v+IN - C2
v-IN vOUT
v+IN - VSS - VB1 C1
M2
VSS

v-IN - v+IN + VSS + VB1 M1

VSS
Allen and Holberg - CMOS Analog Circuit Design

A Dynamic Op Amp which Operates on Both Clock Phases

VDD

φ2 φ1

M8 φ1 φ2 M4

M7 M3
VDD VDD

C2 C4
φ1 φ2

RB v-IN v+IN vOUT

φ2 φ1

C1 C3
M6 M2
VSS VSS

φ2 φ1

M5 M1
φ1 φ2

VSS

1.6 mW dissipation Settling time = 10 ns into 5 pF

GB ≈ 130 MHz with CL = 2.2 pF 1.5 µm technology
Used with a 28.6 MHz clock to realize a 5th order switched capacitor filter
with a cutoff frequency of 3.5 MHz.