Allen and Holberg - CMOS Analog Circuit Design Page IV.

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IV. CMOS PROCESS CHARACTERIZATION

Contents

IV.1 Measurement of basic MOS level 1 parameters

IV.2 Characterization of the extended MOS model
IV.3 Characterization other active components
IV.4 Characterization of resistance
IV.5 Characterization of capacitance

Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS

Chapter 7 Chapter 8 Chapter 9

CMOS Simple CMOS High Performance
Comparators Opamps Opamps
COMPLEX

CIRCUITS

Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE

Chapter 2 Chapter 3 Chapter 4

CMOS CMOS Device Device
Technology Modeling Characterization

DEVICES

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-1

I. Characterization of the Simple Transistor Model

Determine V T0(V SB = 0), K', γ, and λ.

Terminology:
K'S for the saturation region
K'L for the nonsaturation region

 W eff 
iD = K' S   (v GS - V T ) 2 (1 + λ v DS ) (1)
2L
 eff

 2 
 W eff  v DS
iD = K' L    (v G S - V T ) v D S -  (2)
 L eff   2 

V T = V T0 + γ  2| φ F | + v S B - 2| φ F |  (3)

Assume that vDS is chosen such that the λ vDS << 1

v SB =0 -> V T = V T0 .

Therefore, Eq. (1) simplifies to

 W eff
iD = K’ S   (v GS - V T0 ) 2 (4)
2L
 eff
This equation can be manipulated algebraically to obtain the following
1/2  K' S W eff 1/2
1/2  K' S W eff
iD =  2L  vGS -  2L  VT0 (5)
 eff   eff 
which has the form
y = mx + b (6)
1/2
y = iD (7)

x = v GS (8)

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-2

 K' S W eff 1/2

m=  (9)
 2L eff 
and
 K' S W eff 1/2
b = −  V T0 (10)
 2L eff 
1/2
Plot i D versus vGS and measure slope. to get K'S
1/2
When iD = 0 the x intercept (b') is V T0 .

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-3

Mobility degradation
region

v DS > VDSAT

1/2
( iD )
Weak inversion
region 1/2
 K S′ Weff 
m=  
 2 L eff 

b ′ = VT0
v GS

(a)

v DS = 0 . 1 V

iD
 K L′ Weff 
m=   vDS
 L eff 

vGS

(b)

Figure B.1-1 (a) iD1/2 versus vGS plot used to determine VT0 and K'S. (b) iD versus
vGS plot to determine K'L.

Extract the parameter K'L for the nonsaturation region:

 W eff  W eff  v D S
iD = K' L   v DS v GS - K' L   v DS  V T +  (11)
 L eff   L eff   2 
Plot iD versus vGS as shown in Fig. B.1-1(b), the slope is seen to be

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-4

∆iD  W eff
m = ∆v = K' L   vDS (12)
GS Leff 

Knowing the slope, the term K'L is easily determined to be

 L eff   1 
K' L = m     (13)
 W eff  vDS

W eff, Leff, and vDS must be known.

The approximate value µo can be extracted from the value of K'L

At this point, γ is unknown.

Write Eq. (3) in the linear form where

y = VT (14)

x= 2| φ F | + v SB − 2| φ F | (15)

m=γ (16)
b = V T0 (17)

2|φF| normally in the range of 0.6 to 0.7 volts.

Determine VT at various values of vSB

Plot VT versus x and measure the slope to extract γ

Slope m, measured from the best fit line, is the parameter γ.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-5

1/2
(i D )

VT0 VT1 VT2 VT3

v GS

Figure B.1-2 iD1/2 versus vGS plot at different vSB values to determine γ.

VSB = 3 V
VSB = 2 V
VT
VSB = 1 V
m=γ

VSB = 0 V

0.5 0.5
( vSB + 2 φ F ) − ( 2 φF )

Figure B.1-3 Plot of VT versus f(vSB) to determine γ.

We still need to find λ, ∆L, and ∆W.

λ should be determined for all device lengths that might be used.

Rewrite Eq. (1) is as

iD = i' D λ vDS + i' D (18)

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-6

which is in the familiar linear form where

y = iD (Eq. (1)) (19)

x = v DS (20)

m = λ i'D (21)

b = i'D (Eq. (4) with λ = 0) (22)

Plot iD versus v DS , and measure the slope of the data in the saturation
region, and divide that value by the y-intercept to getλ.

Saturation region
Nonsaturation
region
iD

i'D m = λ i'D

v DS

Figure B.1-4 Plot of iD versus vDS to determine λ.

Calculating ∆L and ∆W.

Consider two transistors, with the same widths but different lengths,
operating in the nonsaturation region with the same vDS. The widths of the
transistors are assumed to be very large so that W ≅ Weff. The large-signal
model is given as
2
K' L W eff  v 
iD = L   DS 
(v - V )v -
T 0 D S  2  (23)
eff  G S

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-7

and
∂ID  K' L W eff
= gm =   VD S (24)
∂V GS  L eff 
The aspect ratios (W/L) for the two transistors are
W1
L1 + ∆L (25)

and
W2
(26)
L2 + ∆L
Implicit in Eqs. (25) and (26) is that ∆L is assumed to be the same for both
transistors. Combining Eq. (24) with Eqs. (25) and (26) gives
K' L W
gm1 = L + ∆ L v DS (27)
1
and
K' L W
gm2 = L + ∆ L v DS (28)
2
where W 1 = W 2 = W (and are assumed to equal the effective width). With
further algebraic manipulation of Eqs. (27) and (28), one can show that,
gm1 L2 + ∆L
= (29)
gm1 - gm2 L2 - L1
which further yields
(L 2 - L 1 ) g m1
L 2 + ∆L = L eff = g (30)
m1 - gm2
L2 and L1 known
gm1 and gm2 can be measured
Similarly for W eff :
(W 1 - W 2 )g m2
W 2 + ∆W = W eff = g (31)
m1 - gm2
Equation (31) is valid when two transistors have the same length but
different widths.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.1-8

One must be careful in determining ∆L (or ∆W) to make the lengths (or
widths) sufficiently different in order to avoid the numerical error due to
subtracting large numbers, and small enough that the transistor model
chosen is still valid for both transistors.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.3-1

II. Transistor Characterization for the Extended Model

Equations (1) and (2) represent a simplified version of the extended model
for a relatively wide MOS transistor operating in the nonsaturation, strong-
inversion region with VSB = 0.

µsCoxW  v2 
 (v  DS + γ v
iD =  GS - V )v -
T DS  2  DS 2| φ F |
L

 2γ 
−  3  [(v DS + 2| φ F |) 1.5 - (2| φ F |)] 1.5 (1)
  
where W and L are effective electrical equivalents (dropping the subscript,
“eff”, for convenience).
 (UCRIT)εsi  UEXP
µs = µo  (2)
Cox[v GS - V T - (UTRA)v DS ] 
Eq. (2) holds when the denominator term in the brackets is less than unity.
Otherwise, µo = µs. To develop a procedure for extracting µo, consider
the case where mobility degradation effects are not being experienced, i.e.,
µs = µo, Eq. (1) can be rewritten in general as
iD = µ o f(C ox , W, L, v GS , V T , v DS , γ , 2|φ F |) (3)
This equation is a linear function of vGS and is in the familiar form of
y = mx + b (4)
where b = 0.

Plot iD versus the function, f(Cox, W , L, v GS , V T , v DS , γ , 2|φ F |) and

measure the slope = µo.

• The data are limited to the nonsaturation region (small vDS ).

• The transistor must be in the strong-inversion region (vGS > VT).
• The transistor must operate below the critical-mobility point.

Keep vGS as low as possible without encroaching on the weak-inversion

region of operation.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.3-2

Region of
variable
mobility

iD

Region of
constant
mobility

Weak-inversion
region

v GS

Figure B.2-1 Plot of iD versus vGS in the nonsaturation region.

Once µo is determined, there is ample information to determine UCRIT

and UEXP. Consider Eqs. (1) and (2) rewritten and combined as follows.
iD = µo[(UCRIT)f2]UEXPf1 (5)
where
 v  2
C ox W 
f1 = L  (v G S - V T )v D S -  2  + γ vDS 2| φ F |
DS

 2γ 
−  3  [(v DS + 2| φ F |) 1.5 - (2| φ F |)] 1.5 (1)
  

and

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Allen and Holberg - CMOS Analog Circuit Design Page IV.3-3

ε si
f2 = (7)
[v GS - V T - (UTRA)v DS ]C o x

The units of f 1 and f 2 are FV2/cm2 and cm/V respectively. Notice that f 2
includes the parameter UTRA, which is an unknown. UTRA is disabled in
most SPICE models.

Equation (5) can be manipulated algebraically to yield

 iD 
log  = log( µo) + UEXP[log(UCRIT)] + UEXP[log(f2)] (8)
 f1 
This is in the familiar form of Eq. (4) with
x = log(f2) (9)

 iD 
y = log f  (10)
 1 

m = UEXP (11)
b = log( µo) + UEXP[log(UCRIT)] (12)

By plotting Eq. (8) and measuring the slope, UEXP can be determined.
The y-intercept can be extracted from the plot and UCRIT can be
determined by back calculation given UEXP, µo, and the intercept, b.

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III. Characterization of Substrate Bipolar

Parameters of interest are: β dc , and JS.

For v BE >> kT/q,

kT  iC 
v BE = q ln  (1)
 JSA E 
and
iE
βdc = i − 1 (2)
B
AE is the cross-sectional area of the emitter-base junction of the BJT.
iE = iB (β dc + 1) (3)
Plot iB as a function of iE and measure the slope to determine β dc.

Once β dc is known, then Eq. (1) can be rearranged and modified as

follows.
k T  iE β d c  kT kT kT
v BE = q ln  − ln(J A ) = ln( α i ) −
1 + β d c q S E q dc E q
ln(JSAE)

Plotting ln[iEβ dc/(1 + β dc)] versus vBE results in a graph where

kT
m = slope = q (5)

and
 k T
b = y-intercept = −  ln(JSA E ) (6)
q 
Since the emitter area is known, JS can be determined directly.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-1

IV. Characterization of Resistive Components

• Resistors
• Contact resistance

Characterize the resistor geometry exactly as it will be implemented in a

design. Because

• sheet resistance is not constant across the width of a resistor

• the effects of bends result in inaccuracies
• termination effects are not accurately predictable

Figure B.5-1 illustrates a structure that can be used to determine sheet

resistance, and geometry width variation (bias).
Force a current into node A with node F grounded while measuring the
voltage drops across BC (Vn) and DE (Vw), the resistors Rn and Rw can
be determined as follows
Vn
Rn = (1)
I
Vw
Rw = (2)
I

The sheet resistance can be determined from these to be

 W n - Bias
RS = Rn   (3)
 Ln 

 W w - Bias
RS = Rw   (3)
 Lw 
where
Rn = resistance of narrow resistor (Ω)

Rw = resistance of wide resistor (Ω)

R S = sheet resistance of material (polysilicon, diffusion etc.

Ω/square)
Ln = drawn length of narrow resistor

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2

Lw = drawn length of wide resistor

W n = drawn width of narrow resistor

W w = drawn width of wide resistor

Bias = difference between drawn width and actual device width

Rw
Rn

A Wn Ww F

Ln
Lw

B C D E

Figure B.5-1 Sheet resistance and bias monitor.

Solving equations (3) and (4) yields

W n - k Ww
Bias = 1 - k (5)

where
RwLn
k=R L (6)
n w
and
 W n - Bias  W w - Bias
RS = Rn   = Rw   (7)
 Ln   Lw 

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3

Determining sheet resistance and contact resistance

10 squares

RA=220 Ω

20 squares

RB=420 Ω

Figure B.5-2 Two resistors used to determine RS and RC.

R A = R 1 + 2R c; R1 = N 1RS (8)
and
R B = R 2 + 2R c; R2 = N 2RS (9)
N1 is the number of squares for R1
RS is the sheet resistivity in Ω/square
Rc is the contact resistance.
RB - RA
RS = N - N (10)
2 1
and
2R c = R A − N 1R S = R B − N 2R S (11)

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4

Voltage coefficient of lightly-doped resistors

V1 − V2 V1 + V2
R= VBIAS =
IR 2

IR
V1 V2

VSS

Figure B.5-3 N-well resistor illustrating back-bias dependence.

27.0

26.5
Resistance (kΩ)

26.0

25.5

25.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

Back bias (volts)

Figure B.5-4 N-well resistance as a function of back-bias voltage

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5

Contact Resistance

Pad 1

Metal pads Diffusion or

polysilicon

Pad 3 Pad 4

Metal pads

Pad 2

Pad 1

RC

R
RC
Pad 4
R
RC

Pad 3
RM
RM

Pad 2

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-1

V. Characterization of Capacitance
MOS capacitors
CGS, CGD, and CGB

Depletion capacitors
CDB and CSB

Interconnect capacitances
Cpoly-field, Cmetal-field, and Cmetal-poly (and perhaps multi-metal
capacitors

SPICE capacitor models

C GS0, C GD0, and C GB0 (at V GS = V GB = 0).

Normally SPICE calculates CDB and CSB using the areas of the drain and
source and the junction (depletion) capacitance, CJ (zero-bias value), that it
calculates internally from other model parameters. Two of these model
parameters, MJ and MJSW, are used to calculate the depletion capacitance
as a function of voltage across the capacitor.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2

C GS0 , C GD0 , and C GB0

CGS0 and CGD0, are modeled in SPICE as a function of the device width,
while the capacitor CGB0 is per length of the device

Measure the CGS of a very wide transistor and divide the result by the
width in order to get CGS0 (per unit width).

Source Drain Source

Gate

Figure B.6-1 Structure for determining CGS and CGD.

Cmeas = W(n)(CGS0 + CGD0) (1)

where
Cmeas = total measured capacitance

W = total width of one of the transistors

n = total number of transistors

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3

For very narrow transistors, the capacitance determined using the previous
technique will not be very accurate because of fringe field and other edge
effects at the edge of the transistor. In order to characterize CGS0 and
CGD0 for these narrow devices, a structure similar to that given in Fig.
B.6-1 can be used, substituting different device sizes. Such a structure is
given in Fig. B.6-3. The equations used to calculate the parasitic
capacitances are the same as those given in Eq. (1).

Metal drain Metal source

Polysilicon
interconnect interconnect
gate

Drain Source Drain Source

Figure B.6-3 Structure for measuring CGS and CGD,

including fringing effects, for transistors having small L.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4

CGB0

Drain
Gate overhang

Gate

Source

FOX FOX
Diffusion source

CGB Cpoly-field

Figure B.6-4 Illustration of gate-to-bulk and poly-field capacitance.

This capacitance is approximated from the interconnect capacitance

Cpoly-field (overhang capacitor is not a true parallel-plate capacitor)
Cmeas
Cpoly-field = L W (F/m2 ) (2)
R R
where
Cmeas = Cmeas = measured value of the polysilicon strip

LR = length of the centerline of the polysilicon strip

WR = width of the polysilicon strip (usually chosen as device length)

Having determined Cpoly-field, CGB0 can be approximated as
CGB0 ≅ 2 (Cpoly-field)(doverhang) = 2C 5 (F/m) (3)
where
doverhang = overhang dimension (see Rule 3D, Table 2.6-1)

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5

C BD and C BS

-MJ -MJSW
 VJ   VJ 
CJ(VJ) = ACJ(0)1 + PB + PCJSW(0)1 +  (4)
 PB
where
VJ = the reverse bias voltage across the junction

CJ(VJ) = bottom junction capacitance at VJ

CJSW(VJ) = junction capacitance of sidewall at VJ

A = area of the (bottom) of the capacitor

P = perimeter of the capacitor
PB = bulk junction potential
The constants CJ and MJ can be determined by measuring a large
rectangular capacitor structure where the contribution from the sidewall
capacitance is minimal. For such a structure, CJ(VJ) can be approximated
as
 VJ  -MJ
CJ(VJ) = ACJ(0)1 + PB (5)

This equation can be rewritten in a way that is convenient for linear

regression.
 VJ 
log[CJ(VJ)] = (−MJ)log 1 +
PB + log[ACJ(0)]
  (6)


Plotting log[CJ(VJ)] versus log[1 + VJ/PB] and determine the slope, −MJ,
and the Y intercept (where Y is the term on the left), Log[ACJ(0)].
Knowing the area of the capacitor, the calculation of the bottom junction
capacitance is straightforward.