Allen/Holberg : Chapter 2 : 1/14/01 1

Chapter 2 CMOS Technology

The two most prevalent integrated-circuit technologies are bipolar and MOS. Within
each of these families are various subgroups as illustrated in Fig. 2.0-1, which shows a
family tree of some of the more widely used silicon integrated-circuit technologies. For
many years the dominant silicon integrated-circuit technology was bipolar, as evidenced
by the ubiquitous monolithic operational amplifier and the TTL (transistor-transistor
logic) family. In the early 1970s MOS technology was demonstrated to be viable in the
area of dynamic random-access memories (DRAMs), microprocessors, and the 4000-
series logic family. By the end of the 1970s, driven by the need for density, it was clear
that MOS technology would be the vehicle for growth in the digital VLSI area. At this
same time, several organizations were attempting analog circuit designs using MOS
[1,2,3,4]. NMOS technology was the early technology of choice for the majority of both
digital and analog MOS designs. The early 1980s saw the movement of the VLSI world
toward silicon-gate CMOS which has been the dominant technology for VLSI digital and
mixed-signal designs ever since [5,6]. Recently, processes that combine both CMOS
and bipolar (BiCMOS) have proven themselves to be both a technological and market
success where the primary market force has been improved speed for digital circuits
(primarily in static random-access memories, SRAMs). BiCMOS has potential as well in
analog design due to the enhanced performance that a bipolar transistor provides in the
context of CMOS technology. This book focuses on the use of CMOS for analog and
mixed-signal circuit design.

SILICON IC TECHNOLOGIES

Bipolar Bipolar/MOS MOS

Junction Dielectric CMOS PMOS NMOS

isolated isolated Al gate

Aluminum Silicon gate Aluminum Silicon gate

gate gate

Figure 2.0-1 Categories of silicon technology

There are numerous references that develop the details of the physics of MOS device
operation [7,8]. Therefore, this book covers only the aspects of this theory which are
pertinent to the viewpoint of the circuit designer. The objective is to be able to appreciate
the limits of the MOS circuit models developed in the next chapter and to understand the
physical constraints on electrical performance.
This chapter covers various aspects of the CMOS process from a physical point of
view. In order to understand CMOS technology, a brief review of the basic
semiconductor fabrication processes is presented, followed by a description of the
Allen/Holberg : Chapter 2 : 1/14/01 2

fabrication steps required to build the basic CMOS process. Next, the pn junction is
presented and characterized. This discussion is followed by a description of how active
and passive components compatible with the CMOS technology are built. Next,
important limitations on the performance of CMOS technology including latch-up,
temperature dependence, and noise are covered. Finally, this chapter deals with the
topological rules employed when drawing the integrated circuit for subsequent
fabrication.
2.1 Basic MOS Semiconductor Fabrication Processes
Semiconductor technology is based on a number of well-established process steps,
which are the means of fabricating semiconductor components. In order to understand the
fabrication process, it is necessary to understand these steps. The process steps described
here include: oxidation, diffusion, ion implantation, deposition, and etching. The means
of defining the area of the semiconductor subject to processing is called
photolithography.
All processing starts with single-crystal silicon material. There are two methods of
growing such crystals [9]. Most of the material is grown by a method based on that
developed by Czochralski in 1917. A second method, called the float zone technique,
produces crystals of high purity and is often used for power devices. The crystals are
normally grown in either a <100> or <111> crystal orientation. The resulting crystals are
cylindrical and have a diameter of 75-200 mm and a length of 1 m. The cylindrical
crystals are sliced into wafers which are approximately 0.5 to 0.7 mm thick for wafers of
size 100 mm to 150 mm respectively [10]. This thickness is determined primarily by the
physical strength requirements. When the crystals are grown, they are doped with either
an n-type or p-type impurity to form a n- or p-substrate. The substrate is the starting
material in wafer form for the fabrication process. The doping level of most substrates is
approximately 1015 impurity atoms/cm3, which roughly corresponds to a resistivity of
3-5 Ω-cm for an n-substrate and 14-16 Ω-cm for a p-substrate [11].
An alternative to starting with a lightly-doped silicon wafer is to use a heavily-doped
wafer that has a lightly-doped epitaxial on top of it where subsequent devices are formed.
Although epi wafers are more expensive, they can provide some benefits by reducing
sensitivity to latchup (discussed later) and reduce interference between analog and digital
circuits on mixed-signal integrated circuits.
The five basic processing steps which are applied to the doped silicon wafer to
fabricate semiconductor components (oxidation, diffusion, ion implantation, deposition,
and etching) will be described in the following paragraphs.
Oxidation
The first basic processing step is oxide growth or oxidation [12]. Oxidation is the
process by which a layer of silicon dioxide (SiO 2) is formed on the surface of the silicon
wafer. The oxide grows both into as well as on the silicon surface as indicated in Fig.
2.1-1. Typically about 56% of the oxide thickness is above the original surface while
about 44% is below the original surface. The oxide thickness, designated tox , can be
grown using either dry or wet techniques, with the former achieving lower defect
densities. Typically oxide thickness varies from less than 150 Å for gate oxides to more
than 10,000 Å for field oxides. Oxidation takes place at temperatures ranging from
700 °C to 1100 °C with the resulting oxide thickness being proportional to the
temperature at which it is grown (for a fixed amount of time).
Allen/Holberg : Chapter 2 : 1/14/01 3

Original silicon surface tox

Silicon dioxide

0.44 tox Silicon substrate

Figure 2.1-1 Silicon dioxide growth at the surface of a silicon wafer.

Diffusion
The second basic processing step is diffusion [13]. Diffusion in semiconductor
material is the movement of impurity atoms at the surface of the material into the bulk of
the material. Diffusion takes place at temperatures in the range of 800 °C to 1400 °C in
the same way as a gas diffuses in air. The concentration profile of the impurity in the
semiconductor is a function of the concentration of the impurity at the surface and the
time in which the semiconductor is placed in a high-temperature environment. There are
two basic types of diffusion mechanisms which are distinguished by the concentration of
the impurity at the surface of the semiconductor. One type of diffusion assumes that there
is an infinite source of impurities at the surface (N 0 cm-3) during the entire time the
impurity is allowed to diffuse. The impurity profile for an infinite-source impurity as a
function of diffusion time is given in Fig. 2.1-2(a). The second type of diffusion assumes
that there is a finite source of impurities at the surface of the material initially. At t = 0
this value is given by N0. However, as time increases, the impurity concentration at the
surface decreases as shown in Fig. 2.1-2(b). In both cases, N B is the pre-diffusion
impurity concentration of the semiconductor.
The infinite-source and finite-source diffusions are typical of predeposition and
drive-in diffusions, respectively. The object of a predeposition diffusion is to place a
large concentration of impurities near the surface of the material. There is a maximum
impurity concentration that can be diffused into silicon depending upon the type of
impurity. This maximum concentration is due to the solid solubility limit which is in the
range of 5 × 1020 to 2 × 1021 atoms/cm 3. The drive-in diffusion follows the deposition
diffusion and is used to drive the impurities deeper into the semiconductor. The crossover
between the pre-diffusion impurity level and the diffused impurities of the opposite type
defines the semiconductor junction. This junction is between a p-type and n-type material
and is simply called a pn junction. The distance between the surface of the semiconductor
and the junction is called the junction depth. Typical junction depths for diffusion can
range from 0.1 µm for predeposition type diffusions to greater than 10 µm for drive-in
type diffusions.
Allen/Holberg : Chapter 2 : 1/14/01 4

N0

t1 < t2 < t3
N(x)
NB
t3
t1 t2

Depth (x)
(a)

N0

t1 < t2 < t3
N(x)

NB

t2 t3
t1

Depth (x)
(b)

Figure 2.1-2 Diffusion profiles as a function of time for (a) infinite-source of

impurities at the surface, and (b) a finite source of impurities at the surface.
Ion Implantation
The next basic processing step is ion implantation and is widely used in the
fabrication of MOS components [14,15]. Ion implantation is the process by which ions of
a particular dopant (impurity) are accelerated by an electric field to a high velocity and
physically lodge within the semiconductor material. The average depth of penetration
varies from 0.1 to 0.6 µm depending on the velocity and angle at which the ions strike the
silicon wafer. The path of each ion depends upon the collisions it experiences. Therefore,
ions are typically implanted off-axis from the wafer so that they will experience
collisions with lattice atoms thus avoiding undesirable channeling of ions deep into the
silicon. An alternative method to address channeling is to implant through silicon dioxide
which randomizes the implant direction before the ions enter the silicon. The ion-
implantation process causes damage to the semiconductor crystal lattice leaving many of
the implanted ions electrically inactive. This damage can be repaired by an annealing
process in which the temperature of the semiconductor after implantation is raised to
around 800 °C to allow the ions to move to electrically active locations in the
semiconductor crystal lattice.
Ion implantation can be used in place of diffusion since in both cases the objective is
to insert impurities into the semiconductor material. Ion implantation has several
advantages over thermal diffusion. One advantage is the accurate control of doping—to
within ±5%. Reproducibility is very good, making it possible to adjust the thresholds of
MOS devices or to create precise resistors. A second advantage is that ion implantation is
Allen/Holberg : Chapter 2 : 1/14/01 5

a room-temperature process, although annealing at higher temperatures is required to

remove the crystal damage. A third advantage is that it is possible to implant through a
thin layer. Consequently, the material to be implanted does not have to be exposed to
contaminants during and after the implantation process. Unlike ion implantation,
diffusion requires that the surface be free of silicon dioxide or silicon nitride layers.
Finally, ion implantation allows control over the profile of the implanted impurities. For
example, a concentration peak can be placed below the surface of the silicon if desired.
Deposition
The fourth basic semiconductor process is deposition. Deposition is the means by
which films of various materials may be deposited on the silicon wafer. These films may
be deposited using several techniques which include deposition by evaporation [16],
sputtering [17], and chemical-vapor deposition (CVD) [18,19]. In evaporation deposition,
a solid material is placed in a vacuum and heated until it evaporates. The evaporant
molecules strike the cooler wafer and condense into a solid film on the wafer surface.
Thickness of the deposited materiel is determined by the temperature and the amount of
time evaporation is allowed to take place (a thickness of 1 µm is typical). The sputtering
technique uses positive ions to bombard the cathode, which is coated with the material to
be deposited. The bombarded or target material is dislodged by direct momentum transfer
and deposited on wafers which are placed on the anode. The types of sputtering systems
used for depositions in integrated circuits include dc, radio frequency (RF), or magnetron
(magnetic field). Sputtering is usually done in a vacuum. Chemical vapor deposition uses
a process in which a film is deposited by a chemical reaction or pyrolytic decomposition
in the gas phase which occurs in the vicinity of the silicon wafer. This deposition process
is generally used to deposit polysilicon, silicon dioxide (SiO2), or silicon nitride (Si3N4).
While the chemical vapor deposition is usually performed at atmospheric pressure, it can
also be done at low pressures where the diffusivity increases significantly. This technique
is called low-pressure chemical-vapor deposition (LPCVD).
Etching
The final basic semiconductor fabrication process considered here is etching.
Etching is the process of removing exposed (unprotected) material. The means by which
some material is exposed and some is not will be considered next in discussing the
subject of photolithography. For the moment, we will assume that the situation illustrated
in Fig. 2.1-3(a) exists. Here we see a top layer called a film and an underlying layer. A
protective layer, called a maski, covers the film except in the area which is to be etched.
The objective of etching is to remove just the section of the exposed film. To achieve
this, the etching process must have two important properties: selectivity, and anisotropy.
Selectivity is the characteristic of the etch whereby only the desired layer is etched with
no effect on either the protective layer (masking layer) or the underlying layer.
Selectivity can quantified as the ratio of the desired layer etch rate to the undesired layer
etch rate as given below.
Desired layer etch rate (A)
SA−B = (1)
Undesired layer etch rate (B)

i
A distinction is made between a deposited masking layer referred to as a “mask” and the
photographic plate used in exposing the photoresist which is called a “photomask.”
Allen/Holberg : Chapter 2 : 1/14/01 6

Anisotropy is the property of the etch to manifest itself in one direction, i.e., a perfectly
anisotropic etchant will etch in one direction only. The degree of anisotropy can be
quantified by the relation given below.
Lateral etch rate
A = 1 − Vertical etch rate (2)

Reality is such that neither perfect selectivity nor perfect anisotropy can be achieved
in practice, resulting in undercutting effects and partial removal of the underlying layer as
illustrated in Fig. 2.1-3(b). As illustrated, the lack of selectivity with respect to the mask
is given by dimension “a.” Lack of selectivity with respect to the underlying layer is
given by dimension “b.” Dimension “c” shows the degree of anisotropy. There are
preferential etching techniques which achieve high degrees of anisotropy and thus
minimize undercutting effects, as well as maintain high selectivity. Materials which are
normally etched include polysilicon, silicon dioxide, silicon nitride, and aluminum.

Mask
Film

Underlying layer
(a)

a
Mask
Film c

b
Underlying layer
(b)

Figure 2.1-3 (a) Portion of the top layer ready for etching. (b) Result of etching
indicating horizontal etching and etching of underlying layer.

There are two basic types of etching techniques. Wet etching uses chemicals to
remove the material to be etched. Hydrofluoric acid (HF) is used to etch silicon dioxide;
phosphoric acid (H3PO 4) is used to remove silicon nitride; nitric acid, acetic acid, or
hydrofluoric acid is used to remove polysilicon, potassium hydroxide is used to etch
silicon; and a phosphoric acid mixture is used to remove metal. The wet-etching
technique is strongly dependent upon time and temperature, and care must be taken with
the acids used in wet etching as they represent a potential hazard. Dry etching or plasma
etching uses ionized gases that are rendered chemically active by an RF-generated
plasma. This process requires significant characterization to optimize pressure, gas flow
rate, gas mixture, and RF power. Dry etching is very similar to sputtering and in fact the
same equipment can be used. Reactive ion etching (RIE) induces plasma etching
accompanied by ionic bombardment. Dry etching is used for submicron technologies
since it achieves anisotropic profiles (no undercutting).
Photolithography
Allen/Holberg : Chapter 2 : 1/14/01 7

Each of the basic semiconductor fabrication processes discussed thus far is only
applied to selected parts of the silicon wafer with the exception of oxidation and
deposition. The selection of these parts is accomplished by a process called
photolithography [12,20,21]. Photolithography refers to the complete process of
transferring an image from a photomask or computer database to a wafer. The basic
components of photolithography are the photoresist material and the photomask used to
expose some areas of the photoresist to ultraviolet (UV) light while shielding the
remainder. All integrated circuits consist of various layers which overlay to form the
device or component. Each distinct layer must be physically defined as a collection of
geometries. This can be done by physically drawing the layer on a large scale and
optically reducing it to the desired size. However, the usual technique is to draw the layer
using a computer-aided design (CAD) system and store the layer description in electronic
data format.
The photoresist is an organic polymer whose characteristics can be altered when
exposed to ultraviolet light. Photoresist is classified into positive and negative
photoresist. Positive photoresist is used to create a mask where patterns exist (where the
photomask is opaque to UV light). Negative photoresist creates a mask where patterns do
not exist (where the photomask is transparent to UV light). The first step in the
photolithographic process is to apply the photoresist to the surface to be patterned. The
photoresist is applied to the wafer and the wafer spun at several thousand revolutions per
minute in order to disperse the photoresist evenly over the surface of the wafer. The
thickness of the photoresist depends only upon the angular velocity of the spinning wafer.
The second step is to “soft bake” the wafer to drive off solvents in the photoresist. The
next step selectively exposes the wafer to UV light. Using positive photoresist, those
areas exposed to UV light can be removed with solvents leaving only those areas that
were not exposed. Conversely, if negative photoresist is used, those areas exposed to UV
light will be made impervious to solvents while the unexposed areas will be removed.
This process of exposing and then selectively removing the photoresist is called
developing. The developed wafer is then “hard baked” at a higher temperature to achieve
maximum adhesion of the remaining photoresist. The hardened photoresist protects
selected areas from the etch plasma or acids used in the etching process. When its
protective function is complete, the photoresist is removed with solvents or plasma
ashing that will not harm underlying layers. This process must be repeated for each layer
of the integrated circuit. Fig. 2.1-4 shows, by way of example, the basic
photolithographic steps in defining a polysilicon geometry using positive photoresist.
Allen/Holberg : Chapter 2 : 1/14/01 8

Photomask

UV Light

Photomask

(a)

Photoresist Polysilicon

Figure 2.1-4 Basic photolithographic steps to define a polysilicon geometry.

(a) Expose (b) Develop (c) Etch (d) Remove photoresist
Allen/Holberg : Chapter 2 : 1/14/01 9

(b)

Polysilicon

Etch
Photoresist

Photoresist

Polysilicon
(c)

Remove
photoresist

Polysilicon

(d)

Figure 2.1-4 Basic photolithographic steps to define a polysilicon geometry (cont'd).

(a) Expose (b) Develop (c) Etch (d) Remove photoresist

The process of exposing selective areas of a wafer to light through a photomask is

called printing. There are three basic types of printing systems used. They are listed
below:

• Contact printing
• Proximity printing
• Projection printing

The simplest and most accurate method is contact printing. This method uses a glass
plate a little larger than the size of the actual wafer with the image of the desired pattern
on the side of the glass that comes in physical contact with the wafer. This glass plate is
commonly called a photomask. The system results in high resolution, high throughput,
and low cost. Unfortunately, because of the direct contact, the photomask wears out and
Allen/Holberg : Chapter 2 : 1/14/01 10

has to be replaced after 10-25 exposures. This method also introduces impurities and
defects, because of the physical contact. For these reasons, contact printing is not used in
modern VLSI.
A second exposure system is called proximity printing. In this system, the photomask
and wafer are placed very close to one another but not in intimate contact. As the gap
between the photomask and the wafer increases, resolution decreases. In general, this
method of patterning is not useful where minimum feature size is below 2 µm. Therefore,
proximity printing is not used in present-day VLSI.
The projection printing method separates the wafer from the photomask by a
relatively large distance. Lenses or mirrors are used to focus the photomask image on the
surface of the wafer. There are two approaches used for projection printing: scanning,
and step and repeat. The scanning method passes light through the photomask which
follows a complex optical path reflecting off multiple mirrors imaging the wafer with an
arc of illumination optimized for minimum distortion. The photomask and wafer scan the
illuminated arc. Minimum feature size for this method is ≈2-3µm.
The projection printing system most used today is step-and-repeat. This method is
applied in two ways: reduction, and non-reduction. Reduction projection printing uses a
scaled image, typically 5X, on the photomask. One benefit of this method is that defects
are reduced by the scale amount. Non-reduction systems do not have this benefit and
thus greater burden for low defect densities is placed on the manufacture of the
photomask itself.
Electron beam exposure systems are often used to generate the photomasks for
projection printing systems because of its high resolution (less than 1 µm). However, the
electron beam can be used to directly pattern photoresist without using a photomask. The
advantages of using the electron beam as an exposure system are accuracy and the ability
to make software changes. The disadvantages are high cost and low throughput.

N-Well CMOS Fabrication Steps

It is important for a circuit designer to understand some of the basic steps involved in
fabricating a CMOS circuit. The fabrication steps of one of the more popular CMOS
silicon-gate processes will be described in detail. The first step in the n-well silicon-gate
CMOS process is to grow a thin silicon-dioxide region on a p- substrate (wafer).
Subsequent to this, the regions where n-wells are to exist are defined in a masking step by
depositing a photoresist material on top of the oxide. After exposing and developing the
photoresist, n-type impurities are implanted into the wafer as illustrated in Fig. 2.1-5(a).
Next, photoresist is removed and a high-temperature oxidation/drive-in step is performed
causing the implanted ions to diffuse into the p- substrate. This is followed by oxide
removal and subsequent growth of a thin pad oxide layer. [The purpose of the pad oxide
is to protect the substrate from stress due to the difference in the thermal expansion of
silicon and silicon nitride.] Then a layer of silicon nitride is deposited over the entire
wafer as illustrated in Fig. 2.1-5(b). Photoresist is deposited, patterned, and developed as
before, and the silicon nitride is removed from the areas where it has been patterned. The
silicon nitride and photoresist remain in the areas where active devices will reside. These
regions where silicon nitride remain are called active area or moat.
Next, a global n-type field (channel stop) implant is performed as illustrated in Fig.
2.1-5(c). The purpose of this is to insure that parasitic p-channel transistors do not turn
on under various interconnect lines. Photoresist is removed, re-deposited and patterned
using the p-type field (channel stop) implant mask followed by a p- field-implant step as
Allen/Holberg : Chapter 2 : 1/14/01 11

shown in Fig. 2.1-5(d). This is to insure that parasitic n-channel transistors do not turn on
under various interconnect lines. Next, to achieve isolation between active regions, a
thick silicon-dioxide layer is grown over the entire wafer except where silicon nitride
exists (silicon nitride impedes oxide growth). This particular way of building isolation
between devices is called LOCOS isolation. One of the non-ideal aspects of LOCOS
isolation is due to the oxide growth encroaching under the edges of the silicon nitride
resulting in a reduced active-area region (the well-known “bird’s beak”). Figure 2.1-4(e)
shows the results of this step. Once the thick field oxide (FOX) is grown, the remaining
silicon nitride is removed and a thin oxide, which will be the gate oxide, is grown
followed by a polysilicon deposition step (Fig. 2. 1-5(f)). Polysilicon is then patterned and
etched, leaving only what is required to make transistor gates and interconnect lines.
At this point, the drain and source areas have not been diffused into the substrate.
Modern processes employ lightly-doped drain/source (LDD) diffusions to minimize
impact ionization. The LDD structure is built by depositing a spacer oxide over the
patterned polysilicon followed by an anisotropic oxide etch leaving spacers on each side
of the polysilicon gate as shown in Fig. 2.1-5(g). To make n+ sources and drains,
photoresist is applied and patterned everywhere n-channel transistors are required; n+ is
also required where metal connections are to be made to n- material such as the n-well.
After developing, the n+ areas are implanted as illustrated in Fig. 2.1-5(h). The
photoresist acts as a barrier to the implant as does the polysilicon and spacer. As a result,
the n+ regions that result are properly aligned with the spacer oxide. The spacer is etched
next, followed by a lighter n - implant (Fig. 2.1-5(i)) producing the higher resistivity
source/drain regions aligned with the polysilicon gate. These steps are repeated for the p-
channel transistors resulting in the cross section illustrated in Fig. 2.1-5(j). Annealing is
performed in order to activate the implanted ions. At this point, as shown in
Fig. 2.1-5(k), n- and p-channel LDD transistors are complete except for the necessary
terminal connections.
In preparation for the contact step, a new, thick oxide layer is deposited over the
entire wafer (Fig. 2.1-5(l)). This layer is typically borophosphosilicate glass (BPSG)
which has a low reflow temperature (and thus provides a more planar surface for
subsequent layers)[22]. Contacts are formed by first defining their location using the
photolithographic process applied in previous steps. Next, the oxide areas where contacts
are to be made are etched down to the surface of the silicon. The remaining photoresist is
removed and metal (aluminum) is deposited on the wafer. First metal (Metal 1)
interconnect is then defined photolithographically and subsequently etched so that all
unnecessary metal is removed. To prepare for a second metal, another interlayer
dielectric is deposited (Fig. 2.1-5(m)). This is usually a sandwich of CVD SiO 2, spun-on
glass (SOG), and CVD SiO2 to achieve planarity. Intermetal connections (via’s) are
defined through the photolithographic process followed by an etch and the second metal
(Metal 2) is then deposited (Fig. 2.1-5(n). A photolithographic step is applied to pattern
the second layer metal, followed by a metal etch step.
In order to protect the wafer from chemical intrusion or scratching, a passivation
layer of SiO 2 or SiN 3 is applied covering the entire wafer. Pad regions are then defined
(areas where wires will be bonded between the integrated circuit and the package
containing the circuit) and the passivation layer removed only in these areas. Figure 2.1-
5(o) shows a cross section of the final circuit.
Allen/Holberg : Chapter 2 : 1/14/01 12

n-well implant

Photoresist SiO2 Photoresist

p- substrate

(a)

Si3N4
SiO2

n-well
p- substrate

(b)

n- field implant

Pad oxide (SiO2)

Photoresist Si3N4 Photoresist

n-well
p- substrate

(c)

p- field implant

Si3N4 Photoresist

n-well
p- substrate

(d)

Figure 2.1-5 The major CMOS process steps.

Allen/Holberg : Chapter 2 : 1/14/01 13

Si3N4

FOX FOX
n-well
p- substrate

(e)

Polysilicon

FOX FOX
n-well
p- substrate

(f)

SiO2 spacer
Polysilicon Photoresist
FOX FOX
n-well
p- substrate

(g)
n+ S/D implant

Polysilicon Photoresist
FOX FOX
n-well
p- substrate

(h)

Figure 2.1-5 The major CMOS process steps (cont'd).

Allen/Holberg : Chapter 2 : 1/14/01 14

n- S/D LDD implant

Polysilicon Photoresist

FOX FOX
n-well
p- substrate

(i)

LDD Diffusion
Polysilicon

FOX FOX
n-well
p- substrate

(j)

n+ Diffusion p+ Diffusion Polysilicon

FOX FOX
n-well
p- substrate

(k)

n+ Diffusion p+ Diffusion Polysilicon

BPSG
FOX FOX
n-well
p- substrate

(l)

Figure 2.1-5 The major CMOS process steps (cont'd).

Allen/Holberg : Chapter 2 : 1/14/01 15

CVD oxide, Spin-on glass (SOG) Metal 1

BPSG
FOX FOX
n-well
p- substrate

(m)

Metal 2
Metal 1

BPSG
FOX FOX
n-well
p- substrate

(n)

Metal 2 Metal 1
Passivation protection layer

BPSG
FOX FOX
n-well
p- substrate

(o)

Figure 2.1-5 The major CMOS process steps (cont'd).

In order to illustrate the process steps in sufficient detail, actual relative dimensions
are not given (i.e., the side-view drawings are not to scale). It is valuable to gain an
appreciation of actual scale thus Fig. 2.1-6 is provided below to illustrate relative
dimensions.
Allen/Holberg : Chapter 2 : 1/14/01 16

8µm

7µm

6µm
Metal 3 Metal 4
5µm

Metal 2 4µm

3µm

Metal 1
2µm

1µm
1µm Polysilicon

Diffusion

Figure 2.1-6 Side view of CMOS integrated circuit.

Thus far, the basic N-Well CMOS process has been described. There are a variety of
enhancements that can be applied to this process to improve circuit performance. These
will be covered in the following paragraphs.

Silicide/Salicide Technology
Silicide technology was born out of the need to reduce interconnect resistivity. For
with it, a low-resistance silicide such as TiSi2, WSi 2, TaSi 2 or several other candidate
silicides, is placed on top of polysilcon so that the overall polysilicon resistance is greatly
reduced without compromising the other salient benefits of using polysilicon as a
transistor gate (well-known work-function and polysilicon-Si interface properties).
Salicide technology (self-aligned silicide)i goes one step further by providing low-
resistance source/drain connections as well as low-resistance polysilicon. Examples of
silicide and salicide transistor cross-sections are illustrated in Fig. 2.1-7[23]. For analog
designs, it is important to have available polysilicon and diffusion resistors that are not
salicided, so a good mixed-signal process should provide a salicide block.

i
The terms silicide and salicide are often interchanged. Moreover, polycide is used to refer to
polysilicon with silicide.
Allen/Holberg : Chapter 2 : 1/14/01 17

Polysilicide Polysilicide
Metal

Silicide

FOX FOX

(a) (b)

Figure 2.1-7 (a) Polycide structure and (b) Salicide structure.

There are many other details associated with CMOS processes that have not yet been
described here. Furthermore, there are different variations on the basic CMOS process
just described. Some of these provide multiple levels of polysilicon as well as additional
layers of metal interconnect. Others provide good capacitors using either two layers of
polysilicon, two layers of metal (MOM capacitors), or polysilicon on top of a heavily
implanted (on the same order as a source or drain) diffusion. Still other processes start
with a n - substrate and implant p-wells (rather than n-wells in an p- substrate). The latest
processes also use shallow trench isolation (STI) instead of LOCOS to eliminate the
problem of oxide encroachment into the width of a transistor. Newer processes also
employ chemical mechanical polishing (CMP) to achieve maximum surface planarity.
2.2 The pn Junction
The pn junction plays an important role in all semiconductor devices. The objective
of this section is to develop the concepts of the pn junction that will be useful to us later
in our study. These include the depletion-region width, the depletion capacitance,
reverse-bias or breakdown voltage, and the diode equation. Further information can be
found in the references [24,25].
Fig. 2.2-1(a) shows the physical model of a pn junction. In this model it is assumed
that the impurity concentration changes abruptly from N D donors in the n-type
semiconductor to NA acceptors in the p-type semiconductor. This situation is called a step
junction and is illustrated in Fig. 2.2-1(b). The distance x is measured to the right from
the metallurgical junction at x = 0. When two different types of semiconductor materials
are formed in this manner, the free carriers in each type move across the junction by the
principle of diffusion. As these free carriers cross the junction, they leave behind fixed
atoms which have a charge opposite to the carrier. For example, as the electrons near the
junction of the n-type material diffuse across the junction they leave fixed donor atoms of
opposite charge (+) near the junction of the n-type material. This is represented in Fig.
2.2-1(c) by the rectangle with a height of qND. Similarly, the holes which diffuse across
the junction from the p-type material to the n-type material leave behind fixed acceptor
atoms that are negatively charged. The electrons and holes that diffuse across the junction
quickly recombine with the free majority carriers across the junction. As positive and
negative fixed charges are uncovered near the junction by the diffusion of the free
carriers, an electric field develops which creates an opposing carrier movement. When
Allen/Holberg : Chapter 2 : 1/14/01 18

the current due to the free carrier diffusion equals the current caused by the electric field,
the pn junction reaches equilibrium. In equilibrium, both vD and iD of Fig. 2.2-1(a) are
zero.

xd
xp xn

p-type n-type
(a) semiconductor semiconductor

iD
+ vD -

Impurity concentration (cm-3)

ND

(b)
0 x

-NA

Depletion charge concentration (cm-3)

qND
xp
(c)
0 xn x

-qNA

Electric Field (V/cm)

(d)
x

E0

Potential (V)

φ0− vD
(e)
x

xd

Figure 2.2-1 PN junction (a) Physical structure (b) Impurity concentration.

(c) Depletion charge concentration (d) Electric field (e) Electrostatic potential

The distance over which the donor atoms have a positive charge (because they have
lost their free electron) is designated as xn in Fig. 2.2-1(c). Similarly, the distance over
Allen/Holberg : Chapter 2 : 1/14/01 19

which the acceptor atoms have a negative charge (because they have lost their free hole)
is x p. In this diagram, x p is a negative number. The depletion region is defined as the
region about the metallurgical junction which is depleted of free carriers. The depletion
region is defined as
xd = xn − xp (1)
Note that xp<0.
Due to electrical neutrality, the charge on either side of the junction must be equal.
Thus,
qNDxn = − qNAxp (2)
where q is the charge of an electron (1.60 × 10-19 C). The electric field distribution in the
depletion region can be calculated using the point form of Gauss’s law.

dE(x) qN
= (3)
dx εsi
By integrating either side of the junction, the maximum electric field that occurs at the
junction, Eo, can be found. This is illustrated in Fig. 2.2-1(d). Therefore, the expression
for Eo is

⌠ Eo ⌠ 0 −qNA qNAxp −qNDxn

E0 = ⌡ dE =  dx = = (4)
0 ⌡xp εsi εsi εsi

where εsi is the dielectric constant of silicon and is 11.7εo (εo is 8.85 × 10-14 F/cm).
The voltage drop across the depletion region is shown in Fig. 2.2-1(e). The voltage is
found by integrating the negative electric field resulting in
−Eo(xn − xp)
φo − vD = 2 (5)

where vD is an applied external voltage and φo is called the barrier potential and is given
as
kT NAND NAND
φo = q ln  2  = Vt ln  2  (6)
 ni   ni 
Here, k is Boltzmann’s constant (1.38 × 10 -23 J/Κ) and ni is the intrinsic concentration of
silicon which is 1.45 × 10 10/cm3 at 300 Κ. At room temperature, the value of Vt is
25.9 mV. It is important to note that the notation for k T/q is Vt rather than the
conventional VT. The reason for this is to avoid confusion with VT which will be used to
designate the threshold voltage of the MOS transistor (see Sec. 2.3). Although the barrier
voltage exists with v D = 0, it is not available externally at the terminals of the diode.
When metal leads are attached to the ends of the diode a metal-semiconductor junction is
formed. The barrier potentials of the metal-semiconductor contacts are exactly equal to
φo so that the open circuit voltage of the diode is zero.
Allen/Holberg : Chapter 2 : 1/14/01 20

Equations (2), (4), and (5) can be solved simultaneously to find the width of the
depletion region in the n-type and p-type semiconductor. These widths are found as
1/2
2ε (φ − vD)NA
xn =  si o  (7)
 qND(NA + ND) 
and
1/2
2ε (φ − vD)ND
xp = −  si o  (8)
 qNA(NA + ND) 
The width of the depletion region, xd, is found from Eqs. (1), (7) and (8) and is
1/2
2ε (NA + ND)
xd =  si  (φo − vD)1/2 (9)
 qNAND 
It can be seen from Eq. (9) that the depletion width for the pn junction of Fig. 2.2-1 is
proportional to the square root of the difference between the barrier potential and the
externally-applied voltage. It can also be shown that xd is approximately equal to xn or xp
for NA >> ND or ND >> NA, respectively. Consequently, the depletion region will extend
further into the lightly-doped semiconductor than it will into the heavily-doped
semiconductor.
It is also of interest to characterize the depletion charge Qj which is equal to the
magnitude of the fixed charge on either side of the junction. The depletion charge can be
expressed from the above relationships as
1/2
2ε qNAND
Qj = |AqNAxp| = AqNDxn = A  si  (φo − vD)1/2 (10)
 NA + ND 
where A is the cross-sectional area of the pn junction.
The magnitude of the electric field at the junction Eo can be found from Eqs. (4) and
(7) or (8). This quantity is expressed as
1/2
 2qNAND 
Eo =   (φo − vD)1/2 (11)
εsi(NA + ND)
Equations (9), (10), and (11) are key relationships in understanding the pn junction.
The depletion region of a pn junction forms a capacitance called the depletion-layer
capacitance. It results from the dipole formed by uncovered fixed charges near the
junction and will vary with the applied voltage. The depletion-layer capacitance Cj can be
found from Eq. (10) using the following definition of capacitance.
1/2
dQj  ε qNAND  1 Cj0
Cj = = A  si  = (12)
dvD 2(NA + ND) (φo − vD )1/2 [1 − (vD/φo)]m
Cj0 is the depletion-layer capacitance when v D = 0 and m is called a grading
coefficient. The coefficient m is 1/2 for the case of Fig. 2.2-1 which is called a step
junction. If the junction is fabricated using diffusion techniques described in Sec. 2.1,
Fig. 2.2-1(b) will become more like the profile of Fig. 2.2-2. It can be shown for this case
that m is 1/3. The range of values of the grading coefficient will fall between 1/3 and 1/2.
Allen/Holberg : Chapter 2 : 1/14/01 21

Fig. 2.2-3 shows a plot of the depletion layer capacitance for a pn junction. It is seen that
when v D is positive and approaches φ o, the depletion-layer capacitance approaches
infinity. At this value of voltage, the assumptions made in deriving the above equations
are no longer valid. In particular, the assumption that the depletion region is free of
charged carriers is not true. Consequently, the actual curve bends over and Cj decreases
as vD approaches φo [26].

ND

0 x

-NA

Figure 2.2-2 Impurity concentration profile for diffused pn junction.

Cj

Cj0

0 φ0 vD

Figure 2.2-3 Depletion capacitance as a function of externally-applied junction voltage.

Example 2.2-1 Characteristics of a pn Junction

Find xp, xn, xd, φo, Cj0, and Cj for an applied voltage of −4 V for a pn diode with a
step junction, NA = 5 × 1015/cm3, ND = 1020/cm3, and an area of 10 µm by 10 µm.
At room temperature, Eq. (6) gives the barrier potential as 0.917 V. Equations (7)
and (8) give xn ≅ 0 and xp = 1.128 µm. Thus, the depletion width is approximately xp or
1.128 µm. Using these values in Eq. (12) we find that Cj0 is 20.3 fF and at a voltage of
− 4 V, Cj is 9.18 fF.

The voltage breakdown of a reverse biased (vD < 0) pn junction is determined by the
maximum electric field Emax that can exist across the depletion region. For silicon, this
maximum electric field is approximately 3 × 10 5 V/cm. If we assume that |vD| > φo, then
substituting Emax into Eq. (11) allows us to express the maximum reverse-bias voltage or
breakdown voltage (BV) as
ε (NA + ND) 2
BV ≅ si
2qNAND Emax (13)
Allen/Holberg : Chapter 2 : 1/14/01 22

Substituting the values of Example 2.2-1 in Eq. (13) and using a value of 3 × 10 5 V/cm
for Emax gives a breakdown voltage of 58.2 volts. However, as the reverse bias voltage
starts to approach this value, the reverse current in the pn junction starts to increase. This
increase is due to two conduction mechanisms that can take place in a reverse-biased
junction between two heavily-doped semiconductors. The first current mechanism is
called avalanche multiplication and is caused by the high electric fields present in the pn
junction; the second is called Zener breakdown. Zener breakdown is a direct disruption of
valence bonds in high electric fields. However, the Zener mechanism does not require the
presence of an energetic ionizing carrier. The current in most breakdown diodes will be a
combination of these two current mechanisms.
If iR is the reverse current in the pn junction and vR is the reverse-bias voltage across
the pn junction, then the actual reverse current iRA can be expressed as
 1 i
iRA = M iR =   R (14)
1 − (v n
R/BV) 
M is the avalanche multiplication factor and n is an exponent which adjusts the sharpness
of the “knee” of the curve shown in Fig. 2.2-4. Typically, n varies between 3 and 6. If
both sides of the pn junction are heavily doped, the breakdown will take place by
tunneling, leading to the Zener breakdown, which generally occurs at voltages less than 6
volts. Zener diodes can be fabricated where an n+ diffusion overlaps with a p+ diffusion.
Note that the Zener diode is compatible with the basic CMOS process although one
terminal of the Zener must be either on the lowest power supply, V SS, or the highest
power supply, VDD.

iR

0 BV vR

Figure 2.2-4 Reverse-bias volgate-current characteristics of the pn junction

illustrating voltage breakdown.

The diode voltage-current relationship can be derived by examining the minority-

carrier concentrations in the pn junction. Fig. 2.2-5 shows the minority-carrier
concentration for a forward-biased pn junction. The majority-carrier concentrations are
much larger and are not shown on this figure. The forward bias causes minority carriers
to move across the junction where they recombine with majority carriers on the opposite
side. The excess of minority-carrier concentration on each side of the junction is shown
by the cross-hatched regions. We note that this excess concentration starts at a maximum
value at x = 0 (x' = 0) and decreases to the equilibrium value as x (x') becomes large. The
value of the excess concentration at x = 0, designated as pn(0), or x' = 0, designated as
np(0), is expressed in terms of the forward-bias voltage vD as
Allen/Holberg : Chapter 2 : 1/14/01 23

vD
pn(0) = pno exp  V  (15)
 t
and
vD
np(0) = npo exp   (16)
 Vt 
where pno and npo are the equilibrium concentrations of the minority carriers in the n-
type and p-type semiconductors, respectively. We note that these values are essentially
equal to the intrinsic concentration squared divided by the donor or acceptor impurity
atom concentration, as shown on Fig. 2.2- 5. As v D is increased, the excess minority
concentrations are increased. If vD is zero, there is no excess minority concentration. If
vD is negative (reverse-biased) the minority-carrier concentration is depleted below its
equilibrium value.

p-type semiconductor Depletion n-type semiconductor

region

np(x') pn(x)
v 
v  pn(0)=pn0 exp  D
np(0) =np0 exp  D  Vt 
 Vt 

n2i
pn0 =
n2i ND
np0 =
NA Excess concentration Excess concentration of holes
of electrons
x' x'=0 x=0 x
Figure 2.2-5 Impurity concentration profile for diffused pn junction.

The current that flows in the pn junction is proportional to the slope of the excess
minority-carrier concentration at x = 0 (x' = 0). This relationship is given by the diffusion
equation expressed below for holes in the n-type material.
dpn (x) 
Jp(x) = −qDp dx x=0 (17)

where the Dp is the diffusion constant of holes in n-type semiconductor. The excess holes
in the n-type material can be defined as
p' n(x) = pn(x) − pno (18)
The decrease of excess minority carriers away from the junction is exponential and can
be expressed as
−x −x
p' n(x) = p' n(0) exp L  = [pn(0) − pno] exp L  (19)
 p  p
where L p is the diffusion length for holes in an n-type semiconductor. Substituting
Eq. (15) into Eq. (19) gives
Allen/Holberg : Chapter 2 : 1/14/01 24

vD −x
p' n(x) = pno exp  V  − 1 exp L  (20)
  t   p
The current density due to the excess-hole concentration in the n-type semiconductor is
found by substituting Eq. (20) in Eq. (17) resulting in
qDppno  vD
Jp(0) = exp  V  − 1 (21)
Lp   t 
Similarly, for the excess electrons in the p-type semiconductor we have
qDnnpo  vD
Jn(0) = exp  V  − 1 (22)
Ln   t 
Assuming negligible recombination in the depletion region leads to an expression for the
total current density of the pn junction given as
Dppno Dnnpo 
J(0) = Jp(0) + Jn(0) = q  + exp vD − 1 (23)
Lp Ln   Vt  
Multiplying Eq. (23) by the pn junction area A gives the total current as
Dppno + Dnnpo exp vD − 1 = I exp vD − 1
iD = qA  (24)
Lp Ln   Vt   s Vt  
Is is a constant called the saturation current. Equation (24) is the familiar voltage-current
relationship that characterizes the pn junction diode.
Example 2.2-2 Calculation of the Saturation Current
Calculate the saturation current of a pn junction diode with NA = 5 × 1015/cm3, ND =
1020/cm3, Dn = 20 cm2/s, Dp = 10 cm2/s, Ln = 10 µm, Lp = 5 µm, and A = 1000 µm2.
From Eq. (24), the saturation current is defined as

Dppno Dnnpo
Is = qA  +
Lp Ln 

pno is calculated from n2i/ND to get 2.103/cm3; npo is calculated from n2i/NA to get 4.205
× 10 4/cm3. Changing the units of area from µm 2 to cm2 results in a saturation current
magnitude of 1.346 × 10-15 A or 1.346 fA.

This section has developed the depletion-region width, depletion capacitance,

breakdown voltage, and the voltage-current characteristics of the pn junction. These
concepts will be very important in determining the characteristics and performance of
MOS active and passive components.
2.3 The MOS Transistor
The structure of an n-channel and p-channel MOS transistor using an n-well
technology is shown in Fig. 2.3-1. The p-channel device is formed with two heavily-
doped p+ regions diffused into a lighter doped n- material called the well. The two p+
regions are called drain and source, and are separated by a distance, L (referred to as the
Allen/Holberg : Chapter 2 : 1/14/01 25

device length). At the surface between the drain and source lies a gate electrode that is
separated from the silicon by a thin dielectric material (silicon dioxide). Similarly, the n-
channel transistor is formed by two heavily doped n+ regions within a lightly doped p-
substrate. It, too, has a gate on the surface between the drain and source separated from
the silicon by a thin dielectric material (silicon dioxide). Essentially, both types of
transistors are four-terminal devices as shown in Fig. 1.2-2(c,d). The B terminal is the
bulk, or substrate, which contains the drain and source diffusions. For an n-well process,
the p-bulk connection is common throughout the integrated circuit and is connected to
V SS (the most negative supply). Multiple n-wells can be fabricated on a single circuit,
and they can be connected to different potentials in various ways depending upon the
application.

p-channel transistor n-channel transistor

Polysilicon
L SiO2 L
)

)
(p+

(n+
p+)

n+)
W W
in (

in (
rce

rce
sou

sou
dra

dra
n+

p+
FOX
n-well p- substrate

Figure 2.3-1 Physical structure of an n-channel and p-channel transistor in an n-well technology.
Allen/Holberg : Chapter 2 : 1/14/01 26

S G D
SiO2
Gate
FOX FOX

Depletion regions B
p- substrate

Figure 2.3-2 Cross-section of an n-channel transistor with all terminals grounded.

vGS vDS
S G D

Gate
FOX FOX
dy
v(y)
inverted channel
y=0 y y=L B
p- substrate y+dy
vSB

Figure 2.3-3 Cross-section of an n-channel transistor with small vDS and vGS > VT.

Figure 2.3-2 shows an n-channel transistor with all four terminals connected to
ground. At equilibrium, the p- substrate and the n+ source and drain form a pn junction.
Therefore a depletion region exists between the n+ source and drain and the p- substrate.
Since the source and drain are separated by back-to-back pn junctions, the resistance
between the source and drain is very high ( >1012 Ω). The gate and the substrate of the
MOS transistor form the parallel plates of a capacitor with the SiO 2 as the dielectric. This
capacitance divided by the area of the gate is designated as Coxi When a positive potential
is applied to the gate with respect to the source a depletion region is formed under the
gate resulting from holes being pushed away from the silicon-silicon dioxide interface.
The depletion region consists of fixed ions which have a negative charge. Using one-
dimensional analysis, the charge density, ρ, of the depletion region is given by
ρ = q(−NA) (1)
Applying the point form of Gauss’s law, the electric field resulting from this charge is

i
The symbol “C” normally has units of farads, however, in the field of MOS devices it often has units
of farads per unit area (e.g., F/m2 ).
Allen/Holberg : Chapter 2 : 1/14/01 27

⌠ρ ⌠− qNA − qNA
E(x) =  dx =  dx = x +C (2)
⌡ε ⌡ εsi εsi
where C is the constant of integration. The constant, C, is determined by evaluating E(x)
at the edges of the depletion region (x = 0 at the Si-SiO 2 interface; x = xd at the boundary
of the depletion region in the bulk).
− qNA
E(0) = E0 = 0 +C=C (3)
εsi

− qNA
E(xd) = 0 = xd + C (4)
εsi

qNA
C= xd (5)
εsi
This gives an expression for E(x)
qNA
E(x) = (xd − x) (6)
εsi

Applying the relationship between potential and electric field yields

⌠ ⌠ ⌠qNA
⌡ dφ = − ⌡E(x) dx = − ⌡ εsi
(xd −x) dx (7)

Integrating both sides of Eq. (7) with appropriate limits of integration gives
φF xd
2
⌠dφ = − ⌠ qNA qNAxd
 (xd − x) dx = − = φF − φs (8)
⌡ ⌡ εsi 2εsi
φs 0

2
qNAxd
= φs− φF (9)
2εsi
where φF is the equilibrium electrostatic potential (Fermi potential) in the semiconductor,
φS is the surface potential of the semiconductor, and xd is the thickness of the depletion
region. For a p-type semiconductor, φF is given as
φF = − Vt ln(NA/ni) (10)
and for an n-type semiconductor φF is given as
φF = Vt ln(ND/ni) (11)
Eq. (9) can be solved for xd assuming that |φs − φF | ≥ 0 to get
Allen/Holberg : Chapter 2 : 1/14/01 28

1/2
2εsi|φs − φF |
xd =   (12)
 qNA 
The immobile charge due to acceptor ions that have been stripped of their mobile holes is
given by
Q = − qNAxd (13)
Substituting Eq. (12) into Eq. (13) gives
1/2
2εsi |φs − φF |
Q ≅ − qNA   =− 2qNAεsi |φs − φF | (14)
 qNA 
When the gate voltage reaches a value called the threshold voltage, designated as VT,
the substrate underneath the gate becomes inverted, i.e., it changes from a p-type to an n-
type semiconductor. Consequently, an n-type channel exists between the source and drain
that allows carriers to flow. In order to achieve this inversion, the surface potential must
increase from its original negative value ( φs = φF), to zero (φs = 0), and then to a positive
value (φs = − φ F ). The value of gate-source voltage necessary to cause this change in
surface potential is defined as the threshold voltage, V T . This condition is known as
strong inversion. The n-channel transistor in this condition is illustrated in Fig. 2.3-3.
With the substrate at ground potential, the charge stored in the depletion region between
the channel under the gate and the substrate is given by Eq. (14) where φ s has been
replaced by − φF to account for the fact that vGS = VT. This charge Qb0 is written as

Qb0 ≅ − 2qNAεsi |−2φF| (15)

If a reverse bias voltage vBS is applied across the pn junction, Eq. (15) becomes

Qb ≅ 2qNAεsi | −2φF + vSB | (16)

An expression for the threshold voltage can be developed by breaking it down into
several components. First, the term φMSi must be included to represent the difference in
the work functions between the gate material and bulk silicon in the channel region. The
term φMS is given by
φMS = φF(substrate) − φF(gate) (17)
where φF(metal) = 0.6 V. Second, a gate voltage of [−2 φ F − (Qb/C ox)] is required to
change the surface potential and offset the depletion layer charge Q b . Lastly, there is
always an undesired positive charge Qss present in the interface between the oxide and
the bulk silicon. This charge is due to impurities and imperfections at the interface and
must be compensated by a gate voltage of −Qss/Cox. Thus, the threshold voltage for the
MOS transistor can be expressed as

i
Historically, this term has been referred to as the metal-to-silicon work function. We will continue
the tradition even when the gate terminal is something other than metal (e.g., polysilicon).
Allen/Holberg : Chapter 2 : 1/14/01 29

−Qss
VT = φMS + −2φF − C  +  C 
Qb
ox  ox 

Qb0 Qss Qb − Qb0

= φMS − 2φF −
Cox − Cox − Cox (18)

The threshold voltage can be rewritten as

VT = VT0 + γ ( |−2φF + vSB| − |−2φF|) (19)

where
Qb0 Qss
VT0 = φMS − 2φF − C − C (20)
ox ox
and the body-factor, body-effect coefficient or bulk-threshold parameter γ is defined as

2qεsiNA
γ = Cox (21)

The signs of the above analysis can become very confusing. Table 2.3-1 attempts to
clarify any confusion that might arise [25].

Table 2.3-1 Signs for the Quantities in the Threshold Voltage Equation.

Parameter N-CHANNEL P-CHANNEL

(p-type substrate) (n-type substrate)
φMS
Metal − −
n+ Si Gate − −
p+ Si Gate + +
φF − +
Qb0,Qb − +
Qss + +
VSB + −
γ + −

Example 2.3-1 Calculation of the Threshold Voltage

Find the threshold voltage and body factor γ for an n-channel transistor with an n+
silicon gate if tox = 200 Å , N A = 3 × 10 16 cm -3, gate doping, ND = 4 × 10 19 cm -3, and if
the positively-charged ions at the oxide-silicon interface per area is 1010 cm-2.
From Eq. (10), φF(substrate) is given as

 3× 1016 
φF(substrate) = −0.0259 ln   = −0.377 V
 1.45 × 1010
Allen/Holberg : Chapter 2 : 1/14/01 30

The equilibrium electrostatic potential for the n+ polysilicon gate is found from Eq. (11)
as

 4 × 1019 
φF(gate) = 0.0259 ln   = 0.563 V
1.45 × 1010

Eq. (17) gives φMS as

φF(substrate) − φF(gate) = −0.940 V.

The oxide capacitance is given as

3.9 × 8.854 × 10-14

Cox = εox/tox = = 1.727 × 10-7 F/cm2
200 × 10-8

The fixed charge in the depletion region, Qb0, is given by Eq. (15) as

Qb0 = − [2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.377 × 3 × 1016]1/2

= − 8.66 × 10-8 C/cm2.

Dividing Qb0 by Cox gives −0.501 V. Finally, Qss/Cox is given as

Qss 1010 × 1.60 × 10-19

= = 9.3 × 10-3 V
Cox 1.727 × 10 -7

Substituting these values in Eq. (18) gives

VT0 = − 0.940 + 0.754 + 0.501 − 9.3 × 10-3 = 0.306 V

The body factor is found from Eq. (21) as

1/2
2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 3 × 1016 
γ = -7 = 0.577 V1/2
1.727 × 10

The above example shows how the value of impurity concentrations can influence
the threshold voltage. In fact, the threshold voltage can be set to any value by proper
choice of the variables in Eq. (18). Standard practice is to implant the proper type of ions
into the substrate in the channel region to adjust the threshold voltage to the desired
value. If the opposite impurities are implanted in the channel region of the substrate, the
threshold for an n-channel transistor can be made negative. This type of transistor is
Allen/Holberg : Chapter 2 : 1/14/01 31

called a depletion transistor and can have current flow between the drain and source for
zero values of the gate-source voltage.
When the channel is formed between the drain and source as illustrated in Fig. 2.3-3,
a drain current iD can flow if a voltage vDS exists across the channel. The dependence of
this drain current on the terminal voltages of the MOS transistor can be developed by
considering the characteristics of an incremental length of the channel designated as dy in
Fig. 2.3-3. It is assumed that the width of the MOS transistor (into the page) is W and that
vDS is small. The charge per unit area in the channel, QI(y), can be expressed as
QI(y) = Cox[vGS − v(y) − VT] (22)
The resistance in the channel per unit of length dy can be written as
dy
dR = (23)
µnQI(y)W
where µn is the average mobility of the electrons in the channel. The voltage drop,
referenced to the source, along the channel in the y direction is
iD dy
dv(y) = iD dR = (24)
µnQI(y)W
or
iD dy = WµnQI(y) dv(y) (25)
Integrating along the channel from y = 0 to y = L gives
L vDS vDS
⌠ ⌠ ⌠
⌡iD dy = ⌡WµnQI(y) dv(y) = ⌡WµnCox[vGS − v(y) − VT] dv(y) (26)
0 0 0
Performing the integration results in the desired expression for iD as

v(y)2 vDS µnCoxW  vDS

2
µnCoxW  
iD = (v − VT)v(y) − 2 = (vGS − VT)vDS − 2  (27)
L  GS 0 L

This equation is sometimes called the Sah equation [27] and has been used by Shichman
and Hodges [28] as a model for computer simulation. Eq. (27) is only valid when
vGS ≥ VT and vDS ≤ (vGS − VT) (28)
The factor µnCox is often defined as the device-transconductance parameter, given as
µnεox
K' = µnCox = t (29)
ox
Eq. (28) will be examined in more detail in the next chapter, concerning the modeling of
MOS transistors. The operation of the p-channel transistor is essentially the same as that
of the n-channel transistor, except that all voltage and current polarities are reversed.
Allen/Holberg : Chapter 2 : 1/14/01 32

2.4 Passive Components

This section examines the passive components that are compatible with fabrication
steps used to build the MOS device. These passive components include the capacitor and
the resistor.
Capacitors
A good capacitor is often required when designing analog integrated circuits. They
are used as compensation capacitors in amplifier designs, as bandwidth-determining
components in gm/C filters, as charge storage devices in switched-capacitor filters and
digital-to-analog converters, and other places as well. The desired characteristics for
capacitors used in these applications are given below:

• Good matching accuracy

• Low voltage-coefficient
• High ratio of desired capacitance to parasitic capacitance
• High capacitance per unit area

Analog CMOS processes differentiate themselves from purely digital ones by

providing capacitors that meet the above criteria. For such analog processes, there are
basically two types of capacitors made available. One type of capacitor is formed using
one of the available interconnect layer s (metal or polysilicon) on top of crystalline silicon
separated by a dielectric (silicon dioxide layer). Figure 2.4-1(a) shows an example of this
capacitor using polysilicon as the top conducting plate. In order to achieve a low voltage-
coefficient capacitor, the bottom plate must be heavily-doped diffusion (similar to that of
the source and drain). As the process was described in Sec. 2.3, such heavily-doped
diffusion is normally not available underneath polysilicon because the source/drain
implant step occurs after polysilicon is deposited and defined. To solve this problem, an
extra implant step must be included prior to deposition of the polysilicon layer. The
mask-defined implanted region becomes the bottom plate of the capacitor. The
capacitance achieved using this technique is inversely proportional to gate oxide
thickness. Typical values for a 0.8 µm process are given in Table 2.4-1. This capacitor
achieves a high capacitance per unit area and good matching performance, but has a
significant voltage dependent parasitic capacitance to the substrate.
Allen/Holberg : Chapter 2 : 1/14/01 33

Metal
SiO2 Polysilicon top plate
Gate SiO2

FOX FOX

n+ bottom-plate implant
p- substrate

(a)

Polysilicon top plate

Polysilicon bottom plate

FOX

Inter-poly SiO2
p- substrate

(b)

Metal
SiO2 Polysilicon top plate
Gate SiO2

FOX FOX
n- well

p- substrate n+ diffusion

(c)

Figure 2.4-1 MOS capacitors. (a) Polysilicon-oxide-channel. (b) Polysilicon-oxide-polysilicon

(c) Accumulation MOS capacitor.

The second type of capacitor available in analog-taylored processes is that formed by

providing an additional polysilicon layer on top of gate polysilicon (separated by a
dielectric). An example of a double polysilicon capacitor is illustrated in Fig. 2.4-1(b).
The dielectric is formed by a thin silicon-dioxide layer which can only be produced by
Allen/Holberg : Chapter 2 : 1/14/01 34

using several steps beyond the usual single polysilicon process. This capacitor does an
excellent job of meeting the criteria set forth above. In fact, it is the best of all possible
choices for high-performance capacitors. Typical values for a 0.8µm process are given in
Table 2.4-1.
A third type of capacitor is illustrated in Fig. 2.4-1(c). This capacitor is constructed
by putting an n-well underneath an n-channel transistor. It is similar to the capacitor in
Fig2.4-1(a) except that its bottom plate (the n-well) has a much higher resistivity.
Because of this fact, it is not used in circuits where a low voltage coefficient is important.
It is, however, often used when one terminal of the capacitor is connected to ground (or
VSS). It offers a very high capacitance per unit area, it can be matched well, and is
available in all CMOS processes because no unique steps or masks are required.
Quite often, the processing performance required by the digital component of a
mixed-signal integrated circuit, necessitates the use of a process targeted for digital
applications. Such processes do not provide taylored capacitors for analog applications.
Therefore, when a capacitor is needed, it must be derived from two or more of the
interconnect layers. Figure 2.4-2 illustrates symbolically various schemes for making
capacitors in one-, two-, and three-layer metal digital processes. In Fig. 2.4-2(a)
capacitors are constructed vertically using the interlayer oxide as the capacitor dielectric.
The four-layer example achieves the highest ratio of desired capacitance to parasitic
capacitance whereas the two-layer capacitor achieves the lowest. As processes migrate
toward finer line widths and higher speed performance, the oxide between metals
increases while the allowed space between metals decreases. For such processes, same-
layer, horizontal, capacitors can be more efficient than different-layer vertical capacitors.
This is due to the fact that the allowed space between two M1 lines, for example, is less
than the vertical space between M1 and M2 (see Fig. 2.1-6). An example of a same-layer
horizontal capacitor is illustrated in Fig. 2.4-2(b). Compared to polysilicon-oxide-
polysilcon capacitors, these capacitors typically suffer from lower per-unit-area
capacitance and lower ratio of desired capacitance to parasitic capacitance. Matching
accuracy of capacitors implemented like those in Fig 2.4-2 is on the order of 1-2% and
voltage coefficient is low. Typical values for vertical capacitors in a 0.8µm process are
given in Table 2.4-1.
Allen/Holberg : Chapter 2 : 1/14/01 35

M3
M3
T M2 B
M2 T
M1
B M1
Poly

M2 M2 B

T M1 B T M1

Poly

T B

(a)

T B T B M3

M3

M2 M2

M1

M1

(b)

Figure 2.4-2 Various ways to implement capacitors using available interconnect layers illustrated
with a side view. M1, M2, and M3 represent the first, second, and third metal layers respectively.
(a) Vertical parallel plate structures. (b) Horizontal parallel plate structures.

The voltage coefficient of integrated capacitors generally falls within the range of 0
to −200 ppm/V depending upon the structure of the capacitor and, if applicable, the
doping concentration of the capacitor plates [32]. The temperature coefficient of
integrated capacitors is found to be in the range of 20 to 50 ppm/°C. When considering
the ratio of two capacitors on the same substrate, note that the variations on the absolute
value of the capacitor due to temperature tend to cancel. Therefore temperature variations
have little effect on the matching accuracy of capacitors. When capacitors are switched to
different voltages, as in the case of sampled-data circuits, the voltage coefficient can have
a deleterious effect if it is not kept to a minimum.
Allen/Holberg : Chapter 2 : 1/14/01 36

The parasitic capacitors associated with the capacitors of Fig’s. 2.4-1 and 2.4-2 can
give rise to a significant source of error in analog sampled-data circuits. The capacitor
plate with the smallest parasitic associated with it is referred to as the top plate. It is not
necessarily physically the top plate although quite often it is. In contrast, the bottom
plate is that plate having the larger parasitic capacitance associated with it.
Schematically, the top plate is represented by the flat plate in the capacitor symbol while
the curved plate represents the bottom plate. For the capacitors illustrated in Fig. 2.4-1
the parasitic capacitor associated with the top plate of the capacitor itself is due primarily
to interconnect lines leading to the capacitor and the bottom-plate parasitic capacitance is
primarily due to the capacitance between the bottom plate and the substrate. The
capacitors available in a digital process shown in Fig. 2.4-2 have parasitics that are not so
easily generalized. The parasitics are very dependent upon the layout of the device
(layout is discussed in Sec. 2.6).
Figure 2.4-3 shows a general capacitor with its top and bottom plate parasitics. These
parasitic capacitances depend on the capacitor size, layout, and technology, and are
unavoidable.

Cdesired
Top plate
parasitic
Bottom plate
parasitic

Figure 2.4-3 A model for the integrated capacitors showing top and bottom plate parasitics.
Resistors
The other passive component compatible with MOS technology is the resistor. Even
though we shall use circuits consisting of primarily MOS active devices and capacitors,
some applications, such as digital-to-analog conversion, use the resistor. Resistors
compatible with the MOS technology of this section include diffused, polysilicon, and n-
well (or p-well) resistors. Though not as common, metal can be used as a resistor as well.
A diffused resistor is formed using source/drain diffusion and is shown in
Fig. 2.4-4(a). The sheet resistance of such resistors in a non-salicided process is usually
in the range of 50 to 150 Ω/❑ (Ohms per square as explained in Sec 2.6). For a salicide
process, these resistors are in the range of 5 to 15 Ω/❑. The fact that the source/drain
diffusion is needed as a conductor in integrated circuits conflicts with its use as a resistor.
Clearly the goal of a salicide process is to achieve “conductor-like” performance from
source/drain diffusion. In these processes, a salicide block can be used to mask the
silicide film thus allowing for a high-resistance source/drain diffusion where desired.
The diffused resistor is found to have a voltage coefficient of resistance in the 100 to 500
ppm/V range. The parasitic capacitance to ground is also voltage dependent in this type
of resistor.
A polysilicon resistor is shown in Fig. 2.4-4(b). This resistor is surrounded by thick
oxide and has a sheet resistance in the range of 30 to 200 Ω/❑ depending upon doping
levels. For a polysilicide process, the effective resistance of the polysilicon is about 10
Ω/❑.
Allen/Holberg : Chapter 2 : 1/14/01 37

An n-well resistor shown in Fig. 2.4-4(c) is made up of a strip of n-well contacted at

both ends with n+ source/drain diffusion. This type of resistor has a resistance of 1 to 10
kΩ/❑ and a high value for its voltage coefficient. In cases where accuracy is not required,
such as pull-up resistors, or protection resistors, this structure is very useful.
Metal
SiO2 p+

FOX FOX
n- well

p- substrate

(a)

Metal
Polysilicon resistor

FOX

p- substrate

(b)

Metal
n+

FOX FOX FOX

n- well

p- substrate

(c)

Figure 2.4-4 Resistors. (a) Diffused (b) Polysilicon (c) N-well

Allen/Holberg : Chapter 2 : 1/14/01 38

Other types of resistors are possible if the process is altered. The three categories
above represent those most commonly applied with standard MOS technology. Table
2.4-1 summarizes the characteristics of the passive components hitherto discussed.

Table 2.4-1 Approximate Performance Summary of Passive Components in a

0.8µm CMOS Process
Component Range of Matching Temperature Voltage
Type Values Accuracy Coefficient Coefficient
Poly/poly 0.8-1.0 fF/µm2 0.05% 50 ppm/°C 50ppm/V
capacitor
MOS capacitor 2.2-2.7 fF/ µm2 0.05% 50 ppm/°C 50ppm/V
M1-Poly 0.021-0.025 1.5%
capacitor fF/ µm2
M2-M1 0.021-0.025 1.5%
capacitor fF/ µm2
M3-M2 0.021-0.025 1.5%
capacitor fF/ µm2
P+ Diffused 80-150 Ω/❑ 0.4% 1500 ppm/°C 200ppm/V
resistor
N+ Diffused 50-80 Ω/❑ 0.4% 1500 ppm/°C 200ppm/V
resistor
Poly resistor 20-40 Ω/❑ 0.4% 1500 ppm/°C 100ppm/V
N-well resistor 1-2 kΩ/❑ 8000 ppm/°C 10k ppm/V

2.5 Other Considerations of CMOS Technology

In the previous two sections, the active and passive components of the basic CMOS
process have been presented. In this section we wish to consider some other components
that are also available from the basic CMOS process but that are not used as extensively
as the previous components. We will further consider some of the limitations of CMOS
technology, including latch-up, temperature, and noise. This information will become
useful later, when the performance of CMOS circuits is characterized.
So far we have seen that it is possible to make resistors, capacitors, and pn diodes
that are compatible with the basic single-well CMOS fabrication process illustrated in
Fig. 2.3-1. It is also possible to implement a bipolar junction transistor (BJT) that is
compatible with this process, even though the collector terminal is constrained to VDD (or
VSS). Figure 2.5-1 shows how the BJT is implemented for a n-well process. The emitter is
the source or drain diffusion of an p-channel device, the base is the n-well (with a base
width of WB) and the p- substrate is the collector. Because the pn junction between the n-
well and the p - substrate must be reverse biased, the collector must always be connected
to the most negative power-supply voltage, V SS . The BJT will still find many useful
applications even though the collector is constrained. The BJT illustrated in Fig. 2.5-1 is
often called a substrate BJT. The substrate BJT functions like the BJT fabricated in a
process designed for BJTs. The only difference is that the collector is constrained and the
base width is not well controlled, resulting in a wide variation of current gains.
Fig. 2.5-2 shows the minority-carrier concentrations in the BJT. Normally, the base-
emitter (BE) pn junction is forward biased and the collector-base (CB) pn junction is
reverse biased. The forward-biased EB junction causes free electrons to be injected into
the base region. If the base width W B is small, most of these electrons reach the CB
junction and are swept into the collector by the reverse-bias voltage. If the minority-
carrier concentrations are much less than the majority-carrier concentrations, then the
Allen/Holberg : Chapter 2 : 1/14/01 39

collector current can be found by solving for the current in the base region. In terms of
current densities, the collector current density is

Metal
Emitter (p+) Base (n+)

FOX FOX FOX

n- well WB

Collector (p- substrate)

Figure 2.5-1 Substrate BJT available from a bulk CMOS process.

Depletion regions

p n p
Emitter Base Collector

Carrier concentration

ppE
nn(x) ppC
pn(0)
NA npE(0) ND NA
pn(x)
npE ppC
pn(wB)

x
x=0 x=wB

Figure 2.5-2 Minority carrier concentrations for a bipolar junction transistor.

dnp (x) np (0)

JC = −Jn base = −qDn dx = qDn W (1)
B
From Eq. (16) of Sec. 2.2 we can write

np(0) = npo exp  V 

vBE
(2)
t
Allen/Holberg : Chapter 2 : 1/14/01 40

Combining Eqs. (1) and (2) and multiplying by the area of the BE junction A gives the
collector current as
qADnnpo
exp  V  = Is exp  V 
vBE vBE
iC = AJC = (3)
WB t t
where Is is defined as
qADnnpo
Is = (4)
WB
As the holes travel through the base, a small fraction will recombine with electrons
which are the majority carriers in the base. As this occurs, an equal number of electrons
must enter the base from the external base circuit in order to maintain electrical neutrality
in the base region. Also, there will be injection of the electrons from the base to the
emitter due to the forward-biased BE junction. This injection is much smaller than the
hole injection from the emitter because the emitter is more heavily doped than the base.
The injection of electrons into the emitter and the recombination of electrons with holes
in the base both constitute the external base current iB that flows into the base. The ratio
of collector current to base current, iC/iB is defined as βF or the common-emitter current
gain. Thus, the base current is expressed as
iC Is
exp  V 
vBE
iB = = (5)
βF βF t

The emitter current can be found from the base current and the collector current because
the sum of all three currents must equal zero. Although β F has been assumed constant it
varies with iC, having a maximum for moderate currents and falling off from this value
for large or small currents.
In addition to the substrate BJT, it is also possible to have a lateral BJT. Figure 2.3-1
can be used to show how the lateral BJT can be implemented. The emitter could be the
n+ source of the n-channel device, the base the p- substrate, and the collector the n- well.
Although the base is constrained to the substrate potential of the chip, the emitter and
collector can have arbitrary voltages. Unfortunately the lateral BJT is not very useful
because of the large base width. In fact the lateral BJT is considered more as a parasitic
transistor. However, this lateral BJT becomes important in the problem of latch-up of
CMOS circuits which is discussed next [33].
Latch-up in integrated circuits may be defined as a high current state accompanied
by a collapsing or low-voltage condition. Upon application of a radiation transient or
certain electrical excitations, the latched or high current state can be triggered. Latch-up
can be initiated by at least three regenerative mechanisms. They are: (1) the four-layer,
silicon-controlled-rectifier (SCR), regenerative switching action; (2) secondary
breakdown; and (3) sustaining voltage breakdown. Because of the multiple p and n
diffusions present in CMOS, they are susceptible to SCR latch-up.
Fig. 2.5-3(a) shows a cross-section of Fig. 2.3-1 and how the PNPN SCR is formed.
The schematic equivalent of Fig. 2.5-3(a) is given in Fig. 2.5-3(b). Here the SCR action is
clearly illustrated. The resistor RN- is the n-well resistance from the base of the vertical
PNP (Q 2) to VDD. The resistor RP- is the substrate resistance from the base of the lateral
NPN (Q2) to VSS.
Allen/Holberg : Chapter 2 : 1/14/01 41

VDD
S G D=B S G D=A
Substrate tie Well tie

p+ FOX n+ n+ FOX p+ p+ FOX n+

Q2
Q1
RN- n-well

p-substrate RP-
(a)

VDD

RN- Q2
A

Q1
B

RP-

(b)

Figure 2.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS
integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic
bipolar transistors.

Regeneration occurs when three conditions are satisfied. The first condition is that
the loop gain must exceed unity. This condition is stated as
β NPNβPNP ≥ 1 (6)
where βNPN and β PNP are the common-emitter, current-gain ratios of Q2 and Q1,
respectively. The second condition is that both of the base-emitter junctions must become
forward biased. The third condition is that the circuits connected to the emitter must be
capable of sinking and sourcing a current greater than the holding current of the PNPN
device.
To prevent latch-up, several standard precautions are taken. One approach is to keep
the source/drain of the n-channel device as far away from the n-well as possible. This
reduces the value of βNPN and helps to prevent latch-up. Unfortunately, this is very costly
in terms of area. A second approach is to reduce the values of RN- and R P- . Smaller
resistor values are helpful because more current must flow through them in order to
forward bias the base-emitter regions of Q1 and Q2. These resistances can be reduced by
Allen/Holberg : Chapter 2 : 1/14/01 42

surrounding the p-channel devices with a n + guard ring connected to V DD and by

surrounding n-channel transistors with p+ guard rings tied to VSS as shown in Fig. 2.5-4.

p-channel transistor n-channel transistor

n+ guard bars p+ guard bars

VDD VSS

FOX
n-well
p- substrate

Figure 2.5-4 Preventing latch-up using guard bars in an n-well technology

Latch-up can also be prevented by keeping the potential of the source/drain of the p-
channel device [A in Fig. 2.5-3 (b)] from being higher than VDD or the potential of the
source/drain of the n-channel device [B in Fig. 2.5-3 (b)] from going below V SS . By
careful design and layout, latch-up can be avoided in most cases. In the design of various
circuits, particularly those that have high currents, one must use care to avoid circuit
conditions that will initiate latch-up.
Another important consideration of CMOS technology is the electrostatic discharge
protection of the gates of transistors which are externally accessible. To prevent
accidental destruction of the gate oxide, a resistance and two reverse-biased pn junction
diodes are employed to form an input protection circuit. One of the diodes is connected
with the n side to the highest circuit potential (V DD ) and the p side to the gate to be
protected. The other diode is connected with the n side to the gate to be protected and the
p side to the lowest circuit potential (VSS). This is illustrated in Fig. 2.5-5. For an n-well
process, the first diode is usually made by a p+ diffusion into the n- well. The second
diode is made by a n+ diffusion into the substrate. The resistor is connected between the
external contact and the junction between the diodes and the gate to be protected. If a
large voltage is applied to the input, one of the diodes will breakdown depending upon
the polarity of the voltage. If the resistor is large enough, it will limit the breakdown
current so that the diode is not destroyed. This circuit should be used whenever the gates
of a transistor (or transistors) are taken to external circuits.
Allen/Holberg : Chapter 2 : 1/14/01 43

VDD

p+ – n-well diode

Bonding
To internal gates p+ resistor Pad

n+ – substrate diode
VSS
(a)

Metal

n+ FOX p+ FOX
n-well

p-substrate

(b)

Figure 2.5-5 Electrostatic discharge protection circuitry. (a) Electrical equivalent

circuit (b) Implementation in CMOS technology

The temperature dependence of MOS components is an important performance

characteristic in analog circuit design. The temperature behavior of passive components
is usually expressed in terms of a fractional temperature coefficient TCF defined as
1 dX
TCF = X ⋅ dT (7)

where X can be the resistance or capacitance of the passive component. Generally, the
fractional temperature coefficient is multiplied by 106 and expressed in units of parts per
million per °C or ppm/°C. The fractional temperature coefficient of various CMOS
passive components has been given in Table 2.4-1.
The temperature dependence of the MOS device can be found from the expression
for drain current given in Eq. (28) of Sec. 2.3. The primary temperature-dependent
parameters are the mobility µ and the threshold voltage VT. The temperature dependence
of the carrier mobility µ is given as [34],
µ = Kµ T −1.5 (8)
The temperature dependence of the threshold voltage can be approximated by the
following expression [35]
Allen/Holberg : Chapter 2 : 1/14/01 44

VT (T) = VT (T0) − α(T − T0) (9)

where α is approximately 2.3 mV/°C. This expression is valid over the range of 200 to
400 Κ, with α depending on the substrate doping level and the dosages of the implants
used during fabrication. These expressions for the temperature dependence of mobility
and threshold voltage will be used later to determine the temperature performance of
MOS circuits and are valid only for limited ranges of temperature variation about room
temperature. Other modifications are necessary for extreme temperature ranges.
The temperature dependence of the pn junction is also important in this study. For
example, the pn-junction diode can be used to create a reference voltage whose
temperature stability will depend upon the temperature characteristics of the pn-junction
diode. We shall consider the reverse-biased pn-junction diode first. Eq. (24) of Sec. 2.2
shows that when vD < 0, that the diode current is given as
2
−iD ≅ Is = qA 
Dppno Dnnpo qAD ni 3exp −VGo
+ ≅ = KT (10)
 Lp Ln  L N  Vt 
where it has been assumed that one of the terms in the brackets is dominant and that L
and N correspond to the diffusion length and impurity concentration of the dominant
term. Also T is the absolute temperature in Kelvin and V Go is the bandgap voltage of
silicon at 300 Κ (1.205 V). Differentiating Eq. (10) with respect to T results in

dIs 3KT 3 −VGo qKT 3VGo −VGo 3Is Is VGo

= T exp  V  + exp  = + (11)
dT  t  KT 2  Vt  T T Vt
The TCF for the reverse diode current can be expressed as
1 dIs 3 1 VGo
= + (12)
Is dT T T Vt
The reverse diode current is seen to double approximately every 5 °C increase as
illustrated in the following example.
Example 2.5-1 Calculation of the Reverse Diode Current Temperature
Dependence and TCF
Assume that the temperature is 300 Κ (room temperature) and calculate the reverse
diode current change and the TCF for a 5 Κ increase.
The TCF can be calculated from Eq. (12) as

TCF = 0.01 + 0.155 = 0.165

Since the TCF is change per degree, the reverse current will increase by a factor of 1.165
for every degree Κ (or °C) change in temperature. Multiplying by 1.165 five times gives
an increase of approximately 2. This implies that the reverse saturation current will
approximately double for every 5 °C temperature increase. Experimentally, the reverse
current doubles for every 8 °C increase in temperature because the reverse current is in
part leakage current.
The forward biased pn-junction diode current is given by
Allen/Holberg : Chapter 2 : 1/14/01 45

vD
iD ≅ Is exp  V  (13)
 t
Differentiating this expression with respect to temperature and assuming that the diode
voltage is a constant (vD = VD) gives
diD iD dIs 1 VD
dT = Is ⋅ dT − T ⋅ Vt iD (14)

The fractional temperature coefficient for iD results from Eq. (14) as

1 diD 1 dIs VD 3 VGo − VD

 
iD ⋅ dT = Is ⋅ dT − TVt = T +  TVt  (15)

If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to

0.01 + (0.155 − 0.077) = 0.0879. It can be seen that the forward diode current will double
for approximately a 10°C increase in temperature.
The above analysis for the forward-bias pn-junction diode assumed that the diode
voltage vD was held constant. If the forward current is held constant (iD = I D), then the
fractional temperature coefficient of the forward diode voltage can be found. From Eq.
(13) we can solve for vD to get
ID
vD = Vt ln   (16)
 Is 
Differentiating Eq. (16) with respect to temperature gives

dvD vD
= − V  1 ⋅ dIs = vD − 3Vt − VGo = − VGo − vD − 3Vt (17)
dT T t Is dT  T T T  T  T
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltage
at room temperature is approximately −2.3 mV/°C.
Another limitation of CMOS components is noise. Noise is a phenomenon caused by
small fluctuations of the analog signal within the components themselves. Noise results
from the fact that electrical charge is not continuous but the result of quantized behavior
and is associated with the fundamental processes in a semiconductor component. In
essence, noise acts like a random variable and is often treated as one. Our objective is to
introduce the basic concepts concerning noise in CMOS components. More detail can be
found in several excellent references [24,36].
Several sources of noise are important in CMOS components. Shot noise is
associated with the dc current flow across a pn junction. It typically has the form of

i 2 = 2qID ∆f (Amperes2) (18)

where i 2 is the mean-square value of the noise current, q is the charge of an electron, ID is
the average dc current of the pn junction, and ∆f is the bandwidth in hertz. Noise-current
spectral density can be found by dividing i 2 by ∆f. The noise-current spectral density is
denoted as i 2/∆f.
Allen/Holberg : Chapter 2 : 1/14/01 46

Another source of noise, called thermal noise, is due to random thermal motion of
the electron and is independent of the dc current flowing in the component. It generally
has the form of

v 2 = 4kTR ∆f (19)
where k is Boltzmann's constant and R is the resistor or equivalent resistor in which the
thermal noise is occurring.
An important source of noise for MOS components is the flicker noise or the 1/f
noise. This noise is associated with carrier traps in semiconductors which capture and
release carriers in a random manner. The time constants associated with this process give
rise to a noise signal with energy concentrated at low frequency. The typical form of the
1/f noise is given as
Ia 
i 2 = Kf  b ∆f (20)
f 

where Kf is a constant, a is a constant (0.5 to 2), and b is a constant (≅1). The current-
noise spectral density for typical 1/f noise is shown in Fig. 2.5-6. Other sources of noise
exist, such as burst noise and avalanche noise, but are not important in CMOS
components and are not discussed here.

Noise power
spectral density

1/f

log(f)

Figure 2.5-6 1/f noise spectrum.

2.6 Integrated Circuit Layout

The final subject in this chapter concerns the geometrical issues involved in the
design of integrated circuits. A unique aspect of integrated-circuit design is that it
requires understanding of the circuit beyond the schematic. A circuit defined and
functioning properly at the schematic level can fail if it is not correctly designed
physically. Physical design, in the context of integrated circuits, is referred to as layout.
As a designer works through the process of designing a circuit, he must consider all
implications that the physical layout might have on a circuit’s operation. Effects due to
matching of components or parasitic components must be kept in mind. If, for example,
two transistors are intended to exhibit identical performance, their layout must be
identical. A wide-bandwidth amplifier design will not function properly if parasitic
Allen/Holberg : Chapter 2 : 1/14/01 47

capacitances at critical nodes are not minimized through careful layout. To appreciate
these finer issues dealing with physical design, it is important to first develop a basic
understanding of integrated-circuit layout and the rules that govern it.
As described in Sec. 2.1, an integrated circuit is made up of multiple layers, each
defined by a photomask using a photolithographic process. Each photomask is built from
a computer database which describes it geometrically. This database is derived from the
physical layout drawn by a mask designer or by computer (at present, most analog layout
is still performed manually). The layout consists of topological descriptions of all
electrical components that will ultimately be fabricated on the integrated circuit. The
most common components which have been discussed thus far are transistors, resistors,
and capacitors.
Matching Concepts
As will be seen in later chapters, matching performance of two or more components
is very important to overall circuit operation. Since matching is dependent upon layout
topology, it is appropriate to discuss it here.
The rule for making two components electrically equivalent is simply to draw them
as identical units. This is the unit-matching principle. To say that two components are
identical means that both they and their surroundings must be identical. This concept can
be explained in non-electrical terms.
Consider the two square components, A and B, illustrated in Fig. 2.6-1(a). In this
example, these objects could be pieces of metal that are desired after deposition and
etching. They have identical shape in area and perimeter as drawn. However, the
surroundings seen by A and B are different due to the presence of object C. The presence
of object C nearer to object B may cause that object to change in some way different than
A. The solution to this is somehow force the surroundings of both geometries A and B to
be the same. This can never be achieved perfectly! However, matching performance can
normally be improved by at least making the immediate surroundings identical as
illustrated in Fig. 2.6-1(b). This general principle will be applied repeatedly to
components of various types. When it is desired to match components of different size,
optimal matching is achieved when both geometries are made from integer numbers of
units with all units being designed applying the unit-matching principle.
Allen/Holberg : Chapter 2 : 1/14/01 48

C
A B

C
A B

Figure 2.6-1 (a)Illustration of how matching of A and B is disturbed

by the presence of C. (b) Improved matching achieved by matching
surroundings of A and B

When multiple units are being matched using the unit-matching principle, another
issue can arise. Suppose that there is some gradient that causes objects to grow smaller
along some path as illustrated in Fig. 2.6-2(a). By design, component A composed of
units A1 and A2 should be twice the size of unit component B. However, due to the
gradient, component A is less than twice the size of component B. If the gradient is
linear, this situation can be resolved by applying the principle of common-centroid
layout. As illustrated in Fig. 2.6-2(b), component B is placed in the center (the centroid)
between the units A 1 and A 2. Now, any linear gradient will cause A1 to change by an
amount equal and opposite to A 2 such that their average value remains constant with
respect to B. This is easily shown analytically in the following way.
If the linear gradient is described as
y = mx + b (1)

then for Fig. 2.6-2(a) we have

A1 = mx1 + b (2)

A2 = mx2 + b (3)

B = mx3 + b (4)

A1 + A2 m(x1 + x2) + 2b
= (5)
B mx3 + b

This ratio cannot be equal to two because

Allen/Holberg : Chapter 2 : 1/14/01 49

x1 + x2
x3 ≠ (6)
2

However, for the case illustrated in Fig. 2.6-2(b) it easy to show that

x1 + x3
x2 = (7)
2

if x1− x2, and x2 − x3 are equal.

(a) A1 A2 B

(b) A1 B A2

x1 x2 x3

Figure 2.6-2 Components placed in the presence of a gradient,

(a) without common-centroid layout and (b) with common-centroid layout.

The matching principles described thus far should be applied to capacitors when it is
desired to match them. In addition, there are other rules that should be applied when
dealing with capacitors. When laying out a capacitor, the capacitor’s value should be
determined by only one plate to reduce its variability. Consider the dual-plate capacitors
shown in Fig. 2.6-3. In this figure, the electric field lines are illustrated to indicate that
the capacitance between the plates is due to both an area field and fringe field. In Fig.
2.6-3(a) the total capacitance between the two plates will vary if the edges of the top plate
indicated by points A and A' move, or if the edges of the bottom plate indicated by points
B and B' move. On the other hand, the value of the capacitor illustrated in Fig. 2.6-3(b)
is sensitive only to the edge variations of the top plate. Even if the top plate shifts to the
left or to the right by a small amount, the capacitance changes very little. The capacitor in
Fig. 2.6-3(a) is sensitive to movement of both plates and thus will have greater variability
due to process variations that the capacitor in Fig. 2.6-3(b).
Allen/Holberg : Chapter 2 : 1/14/01 50

A A' A A'

B B' B B'
(a) (b)

Figure 2.6-3 Side view of a capacitor made from two plates. The capacitor shown in (a)
will vary in value do to edge variations at points A,A' and B,B'. The capacitor shown in (b)
is not sensitive to edge variations at B,B'. It is only sensitive to edge variations at points A,A'.

The field lines illustrated in Fig. 2.6-3 are helpful to appreciate the fact that the total
capacitance between two plates is due to an area component (the classic parallel plate
capacitor) and a perimeter component (the fringe capacitance). With this in mind,
consider a case where it is desired to ratio two capacitors, C1 and C2 by a precise amount
(e.g., two to one ratio).

Let C1 be defined as

C1 = C1A + C1P (8)

and C2 be defined as

C2 = C2A + C2P (9)

where

CXA is the area capacitance (parallel-plate capacitance)

CXP is the peripheral capacitance (the fringe capacitance)

The ratio of C2 to C1 can be expressed as

C2A 1+C 
2P C
C2 C2A + C2P  2A
C1 = C1A + C1P = (10)
C1A 
1 + 
C1P
C1A
If C1P /C1A equals C2P /C2A then C2/C1 is determined by the ratios of capacitor areas
only. Thus the equations show that maintaining a constant area-to-perimeter ratio
eliminates matching sensitivity due to the perimeter. It should not be a surprise that a
constant area-to-perimeter ratio is achieved when the unit-matching principle is applied!
At this point it is worthwhile to ask what geometry is best at maintaining constant area-
to-perimeter ratio—a square, rectangle, circle, or something else. Referring again to Eq.
(10) it is clear that minimizing the perimeter-to-area ratio is a benefit. It is easy to show
(see problem 29) that a circle achieves the least perimeter for a given area and thus it is
the best choice for minimizing perimeter effects. Moreover, a circle has no corners and
corners experience more etch variation than do sides. For a variety of reasons unrelated
to the technology, circles may be undesirable. A reasonable compromise between a
Allen/Holberg : Chapter 2 : 1/14/01 51

square and a circle is a square with chamfered corners (an octagon) as illustrated in Fig.
2.6-4.

Top plate
of capacitor

Bottom plate
of capacitor

Figure 2.6-4 Illustration of a capacitor using an octagon to approximate a circle

to minimize the ratio of perimeter to area.

Another useful capacitor layout technique uses the Yiannoulos pathi. This method
uses a serpentine structure that can maintain a constant area-to-perimeter ratio. The
beauty of the technique is that you are not limited to integer ratios as is the case when
using the unit-matching principle. An example of this layout technique is given in Fig.
2.6-5. It can be easily shown that this structure maintains a constant area-to-perimeter
ratio (see problem 30)

i
This idea was developed by Aristedes A. Yiannoulos.
Allen/Holberg : Chapter 2 : 1/14/01 52

One unit

Etch compensation

Total area is
12.5 units

Total area is
18 units.

Figure 2.6-5 The Y-path technique for achieving non-integer capacitor ratios
while maintaining constant area-to-perimeter ratio.
MOS Transistor Layout
Figure 2.6-6 illustrates the layout of a single MOS transistor and its associated side
view. Transistors which are used for analog applications are drawn as linear stripes as
opposed to a transistor drawn with a bend in the gate. The dimensions that will be
important later on are the width and length of the transistor as well as the area and
periphery of the drain and source. It is the W/L ratio that is the dominant dimensional
component governing transistor conduction, and the area and periphery of the drain and
source that determine drain and source capacitance on a per-device basis.
Allen/Holberg : Chapter 2 : 1/14/01 53

Metal

FOX FOX

Active area Polysilicon

drain/source gate

Contact L

Cut

Active area
drain/source

Metal 1

Figure 2.6-6 Example layout of an MOS transistor showing

top view and side view at the cut line indicated.

When it is desired to match transistors, the unit-matching principle, and the

common-centroid method should be applied. Once applied, the question arises as to
whether, the drain/source orientation of the transistors should be mirror symmetric or
have the same orientation. In Fig. 2.6-7(a) transistors exhibit mirror symmetry while in
Fig. 2.6-7(b) transistors exhibit identical orientation, or photolithographic invariance
(PLI)i. It is not uncommon for the drain/source implant to be applied at an angle.
Because of its height (its thickness), polysilicon can shadow the implant on one side or
the other causing the gate-source capacitance to differ from the gate-drain capacitance.
By applying the PLI layout method, the effect of the implant angle is matched so that the
two C GS are matched and the two CGD are matched. In order to achieve both common
centroid and PLI layouts, matched transistors must be broken into four units each and laid
out in accordance with Fig. 2.6-7(c).

i
The term “photolithographic invariance” was coined by Eric J. Swanson while at Crystal
Semiconductor.
Allen/Holberg : Chapter 2 : 1/14/01 54

(a) (b)

Metal 2 Metal 1
Via 1

(c)

Metal 2
Via 1

Metal 1

Metal 2
(d)

Figure 2.6-7 Example layout of MOS transistors using (a) mirror symmetry, (b) photolithographic
invariance, and (c) two transistors sharing a common source and laid out to achieve both photolithographic
invariance and common centroid. (d) Compact layout of (c).
Allen/Holberg : Chapter 2 : 1/14/01 55

Resistor Layout
Figure 2.6-8(a) shows the layout of a resistor. The top view is general in that the
resistive component can represent either diffusion (active area) or polysilicon. The side
view is particular to the diffusion case. A well resistor is illustrated in Fig. 2.6-8(b). To
understand the dimensions that are important in accessing the performance of a resistor, it
is necessary to review the relationship for the resistance of a conductive bar.
For a conductive bar of material as shown in Fig. 2.6-9, the resistance R is given as
ρL
R=
A (Ω) (11)

where ρ is resistivity in Ω-cm, and A is a plane perpendicular to the direction of current

flow. In terms of the dimensions given in Fig. 2.6-9, Eq. (11) can be rewritten as
ρL
R = WT (Ω) (12)

Since the nominal values for ρ and T are generally fixed for a given process and material
type, they are grouped together to form a new term ρ s called sheet resistivity. This is
clarified by the following expression
ρ  L L
R = T W = ρ s W (Ω) (13)
 
It is conventional to give ρ s the units of Ω/❑ (read Ohms per square). From the layout
point of view, a resistor has the value determined by the number of squares of resistance
multiplied by ρs.
Allen/Holberg : Chapter 2 : 1/14/01 56

Metal

FOX FOX
Substrate
Active area (diffusion)

Contact Active area or Polysilicon W

Cut

L
Metal 1

(a) Diffusion or polysilicon resistor

Metal

FOX FOX FOX

Substrate
Active area (diffusion) Well diffusion

Active area W
Well diffusion
Contact

Cut

Metal 1
L
(b) Well resistor

Figure 2.6-8 Example layout of (a) diffusion or polysilicon resistor and

(b) Well resistor along with their respective side views at the cut line indicated.
Allen/Holberg : Chapter 2 : 1/14/01 57

Direction of current flow

T W

L Area, A

Figure 2.6-9 Current flow in a conductive bar.

Example 2.6-1 Resistance Calculation

Given a polysilicon resistor like that drawn in Fig. 2.6-8(a) with W=0.8µm and
L=20µm, calculate ρ s (in Ω/❑), the number of squares of resistance, and the resistance
value. Assume that ρ for polysilicon is 9 × 10-4 Ω-cm and polysilicon is 3000 Å thick.
Ignore any contact resistance.
First calculate ρ s.

ρ 9 × 10-4 Ω-cm
ρs = T = = 30 Ω/❑
3000 × 10-8 cm

The number of squares of resistance, N, is

L 20µm
N= W = = 25
0.8µm

giving the total resistance as

R = ρ s × Ν = 30 × 25 = 750 Ω

Returning to Fig. 2.6-8, the resistance of each resistor shown is determined by the
L/W ratio and its respective sheet resistance. One should wonder what the true values of
L and W are since, in reality, the current flow is neither uniform nor unidirectional. It is
convenient to measure L and W as shown and then characterize the total resistance in two
components: the body component of the resistor (the portion along the length, L) and the
contact component. One could choose a different approach as long as devices are
characterized consistently with the measurement technique (this is covered in more detail
in Appendix B on device characterization).
Capacitor Layout
Capacitors can be constructed in a variety of ways depending upon the process as
well as the particular application. Only two detailed capacitor layouts will be shown
here.
Allen/Holberg : Chapter 2 : 1/14/01 58

The double-polysilicon capacitor layout is illustrated in Fig. 2.6-10(a). Notice that

the second polysilicon layer boundary falls completely within the boundaries of the first
polysilicon layer (gate) and the top-plate contact is made at the center of the second
polysilicon geometry. This technique minimizes top-plate parasitic capacitance that
would have been worsened if the top polysilicon had, instead, followed a path outside the
boundary of polysilicon gate and made contact to metal elsewhere.
Purely digital processes do not generally provide double-polysilicon capacitors.
Therefore, precision capacitors are generally made using multiple layers of metal. If only
one layer of metal exists, a metal-polysilicon capacitor can be constructed. For multi-
layer metal processes, polysilicon can still be used as one of the capacitor layers. The
problem with using polysilicon as a capacitor layer in this case is that the polysilicon-to-
substrate capacitance can represent a substantial parasitic capacitance compared to the
desired capacitor. If the additional parasitic capacitance resulting from the use of
polysilicon is not a problem, greater per-unit-area capacitance can be achieved with this
type of capacitor.
An example of a triple-metal capacitor is illustrated in Fig. 2.6-10(b). In this layout,
the top plate of the capacitor is the metal two layer. The bottom plate is made from
metals one and three.
The value of integrated circuit capacitors is approximatelyi
εoxA
C = t = CoxA (14)
ox
where ε ox is the dielectric constant of the silicon dioxide (approximately 3.45 × 10-5
pF/µm), tox is the thickness of the oxide, and A is the area of the capacitor. The value of
the capacitor is seen to depend upon the area A and the oxide thickness tox . There is, in
addition, a fringe capacitance that is a function of the periphery of the capacitor.
Therefore, errors in the ratio accuracy of two capacitors result from an error in either the
ratio of the areas, or the oxide thickness. If the error is caused by a uniform linear
variation in the oxide thickness, then a common centroid geometry can be used to
eliminate its effects [29]. Area related errors result from the inability to precisely define
the dimensions of the capacitor on the integrated circuit. This is due to the error tolerance
associated with making the mask, the nonuniform etching of the material defining the
capacitor plates, and other limitations [30].

i
This is the infinite parallel-plate equation. This expression loses its accuracy as the plate dimensions
approach the dimension separating the plates.
Allen/Holberg : Chapter 2 : 1/14/01 59

Polysilicon 2
Metal

FOX
Substrate

Polysilicon gate

Polysilicon gate
Polysilicon 2

Cut

Metal 1

(a)

Metal 3 Metal 2 Metal 1

FOX
Substrate

Metal 2 Metal 1
Metal 3 Metal 3
Via 2

Via 2
Metal 2
Cut

Via 1

Metal 1

(b)

Figure 2.6-10 Example layout of (a) double-polysilicon capacitor, and (b) triple-level
metal capacitor along with their respective side views at the cut line indicated.
Allen/Holberg : Chapter 2 : 1/14/01 60

The performance of analog sampled-data circuits can be directly related to the

capacitors used in the implementation. From the standpoint of analog sampled-data
applications, one of the most important characteristics of the capacitor is ratio accuracy
[31].
Layout Rules
As the layout of an integrated circuit is being drawn, there are layout rules that must
be observed in order to ensure that the integrated circuit is manufacturable. Layout rules
governing manufacturability arise, in part, from the fact that at each mask step in the
process, features of the next photomask must be aligned to features previously defined on
the integrated circuit. Even when using precision automatic alignment tools, there is still
some error in alignment. In some cases, alignment of two layers is critical to circuit
operation. As a result, alignment tolerances impose a limitation of feature size and
orientation with respect to other layers on the circuit.
Electrical performance requirements also dictate feature size and orientation with
respect to other layers. A good example of this is the allowable distance between
diffusions supporting a given voltage difference. Understanding the rules associated with
electrical performance is most important to the designer if circuits are to be designed that
challenge the limits of the technology. The limits for these rules are constrained by the
process (doping concentration, junction depth, etc.) characterized under a specific set of
conditions.
The following set of design rules are based upon the minimum dimension resolution
λ (lambda, not to be confused with the channel length modulation parameter λ which will
be introduced in Chapter 3). The minimum dimension resolution λ is typically one-half
the minimum geometry allowed by the process technology.
The basic layout levels needed to define a double-metal, bulk, silicon gate CMOS
circuit include well (p - or n- ), active area (AA), polysilicon-gate (poly), second
polysilicon (capacitor top plate), contact, metal-1, via, metal-2, and pad opening. The
symbols for these levels are shown in Fig. 2.6-11(c). Table 2.6-1 gives the simplified
design rules for a polysilicon-gate, bulk CMOS process. Figure 2.6-11 illustrates these
rules.
In most cases design rules are unique to each wafer manufacturer. The design rules
for the particular wafer manufacturer should be obtained before the design is begun and
consulted during the design. This is especially important in the design of state-of-the-art
analog CMOS. However, the principles developed here should remain unaltered while
translated to specific processes.

Table 2.6-1 Design Rules for a Double-Metal, Double-Polysilicon, N-Well, Bulk

CMOS Process.
Minimum Dimension Resolution (λ )
1. N-Well
1A. width .....................................................................................6
1B. spacing (same potential)........................................................8
1C. spacing (different potential) ................................................22
2. Active Area (AA)
2A. width .....................................................................................4
Spacing to Well
2B. AA-n contained in n-Well .....................................................1
Allen/Holberg : Chapter 2 : 1/14/01 61

2C. AA-n external to n-Well......................................................10

2D. AA-p contained in n-Well .....................................................3
2E. AA-p external to n-Well........................................................7
Spacing to other AA (inside or outside well)
2F. AA to AA (p or n) .................................................................3
3. Polysilicon Gate (Capacitor bottom plate)
3A. width......................................................................................2
3B. spacing...................................................................................3
3C. spacing of polysilicon to AA (over field)..............................1
3D. extension of gate beyond AA (transistor width direction) ....2
3E. spacing of gate to edge of AA (transistor length direction) ..4
4. Polysilicon Capacitor top plate
4A. width......................................................................................2
4B. spacing...................................................................................2
4C. spacing to inside of polysilicon gate (bottom plate)..............2
5. Contacts
5A. size ..................................................................................2x2
5B. spacing...................................................................................4
5C. spacing to polysilicon gate ....................................................2
5D. spacing polysilicon contact to AA.........................................2
5E. metal overlap of contact ........................................................1
5F. AA overlap of contact ...........................................................2
5G. polysilicon overlap of contact ...............................................2
5H. capacitor top plate overlap of contact....................................2
6. Metal-1
6A. width......................................................................................3
6B. spacing...................................................................................3
7. Via
7A. size ..................................................................................3x3
7B. spacing...................................................................................4
7C. enclosure by Metal-1.............................................................2
7D. enclosure by Metal-2.............................................................2
8. Metal-2
8A. width......................................................................................4
8B. spacing...................................................................................3
Bonding Pad
8C. spacing to AA......................................................................24
8D. spacing to metal circuitry ....................................................24
8E. spacing to polysilicon gate ..................................................24
9. Passivation Opening (Pad)
9A. bonding-pad opening....................................100µm x 100µm
9B. bonding-pad opening enclosed by Metal-2 ...........................8
9C. bonding-pad opening to pad opening space ........................40

Note: For a P-Well process, exchange p and n in all instances.

2.7 Summary
Allen/Holberg : Chapter 2 : 1/14/01 62

This chapter has introduced CMOS technology from the viewpoint of its use to
implement analog circuits. The basic semiconductor fabrication processes were described
in order to understand the fundamental elements of this technology. The basic fabrication
steps include diffusion, implantation, deposition, etching, and oxide growth. These steps
are implemented by the use of photolithographic methods which limit the processing
steps to certain physical areas of the silicon wafer. The basic processing steps needed to
implement a typical silicon-gate CMOS process were described next.
The pn junction was reviewed following the introduction to CMOS technology
because it plays an important role in all semiconductor devices. This review examined a
step pn junction and developed the physical dimensions, the depletion capacitance, and
the voltage-current characteristics of the pn junction. Next, the MOS transistor was
introduced and characterized with respect to its behavior. It was shown how the channel
between the source and drain is formed and the influence of the gate voltage upon this
channel was discussed. The MOS transistor is physically a very simple component.
Finally, the steps necessary to fabricate the transistor were presented.
A discussion of possible passive components that can be achieved in CMOS
technology followed. These components include only resistors and capacitors. The
absolute accuracy of these components depends on their edge uncertainties and improves
as the components are made physically larger. The relative accuracy of passive
components depends upon type and layout.
The next section discussed further considerations of CMOS technology. These
considerations included: the substrate and lateral BJTs compatible with the CMOS
process; latch-up, which occurs under certain high-current conditions; the temperature
dependence of CMOS components; and the noise sources in these components.
The last section covered the geometrical definition of CMOS devices. This focused
on the physical constraints that insure that the devices will work correctly after
fabrication. This material will lead naturally to the next chapter where circuit models are
developed to be used in analyzing and designing circuits.
Allen/Holberg : Chapter 2 : 1/14/01 63

1B

1A

2E

2B

2A
2F

2C

2D

3C 3A 3E 3D

3B

Figure 2.6-11(a) Illustration of the design rules 1-3 of Table 2.6-1.

Allen/Holberg : Chapter 2 : 1/14/01 64

4C 4B

4A

5C

5A
5B

5D

5E

5F 5G 5H

Figure 2.6-11(b) Illustration of the design rules 4-5 of Table 2.6-1.

Allen/Holberg : Chapter 2 : 1/14/01 65

7A

7B
6B
7C

6A
7D

8A

8B

9B

9A

9C

N-WELL N-AA P-AA

POLYSILICON POLYSILICON METAL-1

CAPACITOR GATE

METAL-2 PASSIVATION CONTACT VIA

Figure 2.6-11(c) Illustration of the design rules 6-9 of Table 2.6-1.

Allen/Holberg : Chapter 2 : 1/14/01 66

PROBLEMS
1. List the five basic MOS fabrication processing steps and give the purpose or
function of each step.
2. What is the difference between positive and negative photoresist and how is
photoresist used?
3. Illustrate the impact on source and drain diffusions of a 7˚ angle off perpendicular
ion implant. Assume that the thickness of polysilicon is 8000 Å and that out
diffusion from point of ion impact is 0.07 µm.
4. Repeat Example 2.2-1 if the applied voltage is -2 V.
5. Develop Eq. (9) of Sec. 2.2 using Eqs. (1), (7), and (8) of the same section.
6. Redevelop Eqs. (7) and (8) pf Sec. 2.2 if the impurity concentration of a pn junction
is given by Fig. 2.2-2 rather than the step junction of Fig. 2.2-1(b).
7. Plot the normalized reverse current, iRA/iR, versus the reverse voltage vR of a silicon
pn diode which has BV = 12 V and n = 6.
8. What is the breakdown voltage of a pn junction with NA = ND = 1016/cm3?
9. What change in vD of a silicon pn diode will cause an increase of 10 (an order of
magnitude) in the forward diode current?
10. Explain in your own words why the magnitude of the threshold voltage in Eq. (19)
of Sec. 2.3 increases as the magnitude of the source-bulk voltage increases (The
source-bulk pn diode remains reversed biased.)
11. If VSB = 2 V, find the value of VT for the n-channel transistor of Ex. 2.3-1.
12. Re-derive Eq. (27) given that VT is not constant in Eq. (22) but rather varies linearly
with v(y) according to the following equation.
VT = VT0 + α | vSB |
13. If the mobility of an electron is 500 cm2/(V⋅s) and the mobility of a hole is 200
cm2/(V⋅s), compare the performance of an n-channel with a p-channel transistor. In
particular, consider the value of the transconductance parameter and speed of the
MOS transistor.
14. What is the function of silicon nitride in the CMOS fabrication process described in
Sec. 2.1?
15. Give typical thicknesses for the field oxide (FOX), thin oxide (TOX), n+ or p + , p-
well, and metal 1 in units of µm.
16. Given the component tolerances in Table 2.4-1, design the simple lowpass filter
illustrated in Fig P2.16 to minimize the variation in pole frequency over all process
variations. Pole frequency should be designed to a nominal value of 1MHz. You
must choose the appropriate capacitor and resistor type. Explain your reasoning.
Calculate the variation of pole frequency over process using the design you have
chosen.
Allen/Holberg : Chapter 2 : 1/14/01 67

vin C vout

Figure P2.16

17. List two sources of error that can make the actual capacitor, fabricated using a
CMOS process, differ from its designed value.
18. What is the purpose of the p+ implantation in the capacitor of Fig. 2.4-1(a)?
19. Using Ex. 2.3-1 as a starting point, calculate the difference in threshold voltage
between two devices whose gate-oxide is different by 5% (i.e., tox = 210 Å).
20. Repeat Ex. 2.3-1 using NA = 7 × 1016 cm-3, gate doping, ND = 1 × 1019 cm-3.
21. Consider the circuit in Fig. P2.21. Resistor R1 is an n-well resistor with a nominal value
of 10 kΩ when the voltage at both terminals is 3 V. The input voltage, vin, is a sine wave
with an amplitude of 2 VPP and a dc component of 3 V. Under these conditions, the value
of R1 is given as

 v + vout 
R1 = Rnom 1 + K in 
  2 
where Rnom is 10K and the coefficient K is the voltage coefficient of an n-well
resistor and has a value of 10K ppm/V. Resistor R2 is an ideal resistor with a value
of 10 kΩ. Derive a time-domain expression for vout. Assume that there are no
frequency dependencies.

R1

4
vin 3
vin R2 vout
2

Figure P2.21

22. Repeat problem 21 using a P+ diffused resistor for R1. Assume that a P+ resistor’s
voltage coefficient is 200 ppm/V. The n-well in which R1 lies, is tied to a 5 volt
supply.
23. Consider problem 22 again but assume that the n-well in which R1 lies is not
connected to a 5 volt supply, but rather is connected as shown in Fig. P2.23.
Allen/Holberg : Chapter 2 : 1/14/01 68

R1

n+

vin R2 vout FOX FOX

Rn-well
p- substrate n-well p+ diffusion

Figure P2.23

24. Assume vD = 0.7 V and find the fractional temperature coefficient of Is and vD.
25. Plot the noise voltage as a function of the frequency if the thermal noise is 100
nV/ Hz and the junction of the 1/f and thermal noise (the 1/f noise corner) is 10,000
Hz.
26. Given the polysilicon resistor in Fig. P2.26 with a resistivity of ρ = 8×10 -4 Ω-cm,
calculate the resistance of the structure. Consider only the resistance between
contact edges. ρ s = 50 Ω/ ❑

Contact
1µm Polysilicon

Cut

Top view 3µm

Metal 1

Metal 8000Å

FOX
Side view
Substrate

Diffusion or polysilicon resistor

Figure P2.26

27. Given that you wish to match two transistors having a W/L of 100µm/0.8µm each.
Sketch the layout of these two transistors to achieve the best possible matching.
28. Assume that the edge variation of the top plate of a capacitor is 0.05µm and that
capacitor top plates are to be laid out as squares. It is desired to match two equal
capacitors to an accuracy of 0.1%. Assume that there is no variation in oxide
thickness. How large would the capacitors have to be to achieve this matching
accuracy?
Allen/Holberg : Chapter 2 : 1/14/01 69

29. Show that a circular geometry minimizes perimeter-to-area ratio for a given area
requirement. In your proof, compare against rectangle and square.
30. Show analytically how the Yiannoulos-path technique illustrated in Fig. 2.6-5
maintains a constant area-to-perimeter ratio with non-integer ratios.
31. Design an optimal layout of a matched pair of transistors whose W/L are 8µm/1µm.
The matching should be photolithographic invariant as well as common centroid.
32. Figure P.32 illustrates various ways to implement the layout of a resistor divider.
Choose the layout that BEST achieves the goal of a 2:1 ratio. Explain why the
other choices are not optimal.
B B

2R

A B A
A
(a) (b)

B B B

A
A A

(c) (d) (e)

B A
2x x (f)

Figure P2.32

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Allen/Holberg : Chapter 2 : 1/14/01 70

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Allen/Holberg : Chapter 2 : 1/14/01 71

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