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SDC File

The document outlines various commands used in SDC (Synopsys Design Constraints) files for defining clock parameters, delays, and uncertainties in digital designs. Key commands include 'create_clock' for defining clock properties, 'create_generated_clock' for generating new clocks, and 'set_clock_uncertainty' for specifying clock skew and jitter. Additional commands address delays for inputs and outputs, as well as latency considerations for clock sources and networks.

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Rathnambiga Unnikrishnan
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59 views2 pages

SDC File

The document outlines various commands used in SDC (Synopsys Design Constraints) files for defining clock parameters, delays, and uncertainties in digital designs. Key commands include 'create_clock' for defining clock properties, 'create_generated_clock' for generating new clocks, and 'set_clock_uncertainty' for specifying clock skew and jitter. Additional commands address delays for inputs and outputs, as well as latency considerations for clock sources and networks.

Uploaded by

Rathnambiga Unnikrishnan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SDC FILE:-

 Create_clock -name clk -period 10 -waveform {0.0 5.0} [get_ports clk]


 Create_clock :- creates a clock object.
 Name :- specifies the name of the clock being created (clk)
 Period :- Specifies the clock period in library time units. This is the minimum time over
which the clock waveform repeats.
 Waveform :- Specifies the rise and fall edge times of the clock waveforms of the clock,
in library time units, over an entire clock period.
 Get_ports:- Means paths started at the port clk

 Create_generated_clock -name ck_clk -divide_by 2 -source [get_ports clk] [drv_pin_port clk]


 Create_generated_clock:- To generate the new clock from existing clock .
 Divide_by divide_factor:- Specifies the frequency division factor. If the divide_factor
value is 2, the generated clock period is twice as long as the master clock period.
 Get_pins:- Creates a collection of pins from the netlist. You can assign these pins to a
variable or pass them into another command.

 Group_path -name WRCK_CORE -from WRCK_CORE -to WRCK_CORE -weight 0.5.


 Groups a set of paths or endpoints for cost function calculations in optimization and
analysis. Design Compiler uses the cost function to direct optimization.
 Set_clock_uncertainty -from [all_clocks] –to [all_clocks] $core_xdomain_uncertainty -setup –
hold
 Specifies the uncertainty (skew) of specified clock networks.
 Uncertainty nothing but clock skew and clock jitter
 Clock skew :-The difference in arrival times of the corresponding edges at the flip-flops
 Clock jitter:- The variation in consecutive edges of a clock signal. Due to the voltage
variations in the IC. There may be some difference in the generation of clock. If may not
be generate the rise edge or fall edge at desire time. This variation of the rise edge and
fall edge delay we call it as clock jitter.
 Set_annotated_delay
 Sets the net or cell delay value between two pins.
 Set_annoted_delay –net :- we are calculate net delays from one pin point to next pin
point using spice simulations because during the multipoint clock tree synthesis have
no of multiple points so prime time not extract delays accurately at that time we need
to calculate net delays using spice simulations those net delays put into the sdc file.

 Set_annoted_delay –cell:- If library do not have accurate cell delays at that time we
need to calculate cell delays using spice simulations and one more reason during the
clock tree synthesis some cells are added those cell delay information not exist in
library.
 Set_annotated_transition :- specifies the transition value at the pins supplied with the
port_pin_list argment. The transition value must be expressed in units consistent with
the technology library used during optimization. For example, if the technology library
specifies transition values in nanoseconds, the transition values must be expressed in
nanoseconds.
 Set_clock_latency
 We have two types of latencies. Clock source latency and clock network latency.
 Clock Source Latency: - Clock source latency is the time it takes for a clock signal to
propagate from its actual ideal waveform origin point to the clock definition point in the
design. It can be used to model off –chip clock latency when the clock generation circuit
is not part of the current design. You can use clock source latency for generated clocks
to model the delay from master –clock to generated –clock definition point.

 Clock network latency :- The clock network latency is the time it takes a clock signal to
propagate from the clock definition point to a register clock pin. The rise and fall
latencies are the latencies for rising and falling transitions at the register clock pin,
respectively. Inversion of the clock wave-form, if present in the clock network, is not
taken into consideration when computing clock network latencies at register clock pins.
Note that this behavior is different than it was in previous releases.

 Set_input_delay:-
 The set_input_delay command sets input path delays on input ports relative to a clock
edge. Unless specified, input ports are assumed to have zero input delay. For inout
(bidirectional) ports, you can specify the path delays for both input and output modes.
 Set_output_delay:-
 The set_output_delay command sets output path delays on output ports relative to a
clock edge. Output ports have no output delay unless specified. For inout
(bidirectional) ports, you can specify the path delays for both input and output modes.

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