Computer Architecture: Input/Output Organisation

Input/Output Subsystem
The I/O subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input-output operations of the
computer system.
Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from the
CPU and are considered to be the part of computer system. These devices are also
called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:
1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well
as, output(from computer to the outside world). Example: Touch screen etc.

Interfaces
Interface is a shared boundary btween two separate components of the computer system which
can be used to attach two or more components to the system for communication purposes.
There are two types of interface:
1. CPU Inteface
2. I/O Interface
Let's understand the I/O Interface in details,

Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with CPU.
In computer system, there are special hardware components between the CPU and peripherals to
control or manage the input-output transfers. These components are called input-output
interface units because they provide communication links between processor bus and
peripherals. They provide a method for transferring information between internal system and
input-output devices.

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three types of
modes which are given below:
1. Programmed I/O
 2. Interrupt Initiated I/O
3. Direct Memory Access

Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program. Each
data item transfer is initiated by the instruction in the program.
Usually the program controls data transfer to and from CPU and peripheral. Transferring data
under programmed I/O requires constant monitoring of the peripherals by the CPU.

Interrupt Initiated I/O

In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is time consuming process because it keeps the processor
busy needlessly.
This problem can be overcome by using interrupt initiated I/O. In this when the interface
determines that the peripheral is ready for data transfer, it generates an interrupt. After receiving
the interrupt signal, the CPU stops the task which it is processing and service the I/O transfer and
then returns back to its previous processing task.

Direct Memory Access

Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA
controller manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards
and sound cards etc. It is also used for intra chip data transfer in multicore processors. In DMA,
CPU would initiate the transfer, do other operations while the transfer is in progress and receive
an interrupt from the DMA controller when the transfer has been completed.
Above figure shows block diagram of DMA
Input-output processor (IOP)::
An input-output processor (IOP) is a processor with direct memory access capability. In this, the
computer system is divided into a memory unit and number of processors.
Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it
handles only the details of I/O processing. The IOP can fetch and execute its own instructions.
These IOP instructions are designed to manage I/O transfers only.
Block Diagram Of I/O Processor
Below is a block diagram of a computer along with various I/O Processors. The memory unit
occupies the central position and can communicate with each processor.
The CPU processes the data required for solving the computational tasks. The IOP provides a
path for transfer of data between peripherals and memory. The CPU assigns the task of initiating
the I/O program.
The IOP operates independent from CPU and transfer data between peripherals and memory.
The communication between the IOP and the devices is similar to the program control method of
transfer. And the communication with the memory is similar to the direct memory access
method.
In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.
The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of
initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU
instructions provide operations to start an I/O transfer. The IOP asks for CPU through interrupt.
Instructions that are read from memory by an IOP are also called commands to distinguish them
from instructions that are read by CPU. Commands are prepared by programmers and are stored
in memory. Command words make the program for IOP. CPU informs the IOP where to find the
commands in memory.
Computer Architecture: Interrupts
Data transfer between the CPU and the peripherals is initiated by the CPU. But the CPU cannot
start the transfer unless the peripheral is ready to communicate with the CPU. When a device is
ready to communicate with the CPU, it generates an interrupt signal. A number of input-output
devices are attached to the computer and each device is able to generate an interrupt request.
The main job of the interrupt system is to identify the source of the interrupt. There is also a
possibility that several devices will request simultaneously for CPU communication. Then, the
interrupt system has to decide which device is to be serviced first.

Priority Interrupt
A priority interrupt is a system which decides the priority at which various devices, which
generates the interrupt signal at the same time, will be serviced by the CPU. The system has
authority to decide which conditions are allowed to interrupt the CPU, while some other interrupt
is being serviced. Generally, devices with high speed transfer such as magnetic disks are given
high priority and slow devices such as keyboards are given low priority.
When two or more devices interrupt the computer simultaneously, the computer services the
device with the higher priority first.
Types of Interrupts:
Following are some different types of interrupts:
Hardware Interrupts
When the signal for the processor is from an external device or hardware then this interrupts is
known as hardware interrupt.
Let us consider an example: when we press any key on our keyboard to do some action, then this
pressing of the key will generate an interrupt signal for the processor to perform certain action.
Such an interrupt can be of two types:
 Maskable Interrupt
The hardware interrupts which can be delayed when a much high priority interrupt has
occurred at the same time.
 Non Maskable Interrupt
The hardware interrupts which cannot be delayed and should be processed by the
processor immediately.

Software Interrupts
The interrupt that is caused by any internal system of the computer system is known as
a software interrupt. It can also be of two types:
 Normal Interrupt
The interrupts that are caused by software instructions are called normal software
interrupts.
 Exception
Unplanned interrupts which are produced during the execution of some program are
called exceptions, such as division by zero.

Daisy Chaining Priority

This way of deciding the interrupt priority consists of serial connection of all the devices which
generates an interrupt signal. The device with the highest priority is placed at the first position
followed by lower priority devices and the device which has lowest priority among all is placed
at the last in the chain.
In daisy chaining system all the devices are connected in a serial form. The interrupt line request
is common to all devices. If any device has interrupt signal in low level state then interrupt line
goes to low level state and enables the interrupt input in the CPU. When there is no interrupt the
interrupt line stays in high level state. The CPU respond to the interrupt by enabling the interrupt
acknowledge line. This signal is received by the device 1 at its PI input. The acknowledge signal
passes to next device through PO output only if device 1 is not requesting an interrupt.
The following figure shows the block diagram for daisy chaining priority system.

Data Communication Processor

A data communication processor is an I/O processor that distributes and collects data from
numerous remote terminals connected through telephone and other communication lines to the
computer. It is a specialized I/O processor designed to communicate with data communication
networks.
Such a communication network consists of variety of devices such as printers, display devices,
digital sensors etc. serving many users at once. The data communication processor
communicates with each terminal through a single pair of wire. It also communicates with CPU
and memory in the same manner as any I/O processor does.

What is Modem?
In a Data Communication Network, the remote terminals are connected to the data
communication processor through telephone lines or other wires. Such telephone lines are
specially designed for voice communication and computers use them to communicate in digital
signals, therefore some conversion is required. These conversions are called modem (modulator-
demodulator).
A modem converts digital signal into audio tones to be transmitted over telephone lines and also
converts audio tones into digital signal for machine use.

Modes Of Transmission
Data can be transmitted between 2 points by three different modes:
Simplex
A simplex line carries information in one direction only. In this mode receiver cannot
communicate with the sender to indicate the occurrence of errors that means only sender can
send data but receiver cannot. For example: Radio and Television Broadcasting.

Half Duplex
In half duplex mode, system is capable of transmitting data in both directions but data can be
transmitted in one direction only at a time. A pair of wires is needed for this mode. For
example: Walkie - Talkie.

Full Duplex
In this mode data can be send and received in both directions simultaneously. In this four wire
link is used. For example: Video Calling, Audio calling etc.

What are Protocols?

The communication lines, modems and other devices used in any transmission are collectively
called a Data Link. The orderly transmission of data in a data link can be accomplished by a
protocol.
A Protocol is a set of rules that are followed by interconnecting devices to ensure that all data is
passed correctly without any error.
Types of Protocols
There are two types of protocols:
Character Oriented Protocol
It is based on the binary code of character set. The code is mostly used in ASCII. It includes
upper case and lower case letters, numerals and variety of special symbols. The characters that
control the transmission is called communication control characters.
Bit Oriented Protocol
It does not use characters in its control field and is independent of any code. It allows the
transmission of serial bit stream of any length without the implication of character boundaries.
RISC and CISC Processors
RISC Processor
It is known as Reduced Instruction Set Computer. It is a type of microprocessor that has a limited
number of instructions. They can execute their instructions very fast because instructions are
very small and simple.
RISC chips require fewer transistors which make them cheaper to design and produce. In RISC,
the instruction set contains simple and basic instructions from which more complex instruction
can be produced. Most instructions complete in one cycle, which allows the processor to handle
many instructions at same time.
In this instructions are register based and data transfer takes place from register to register.
CISC Processor

 It is known as Complex Instruction Set Computer.

 It was first developed by Intel.
 It contains large number of complex instructions.
 In this instructions are not register based.
 Instructions cannot be completed in one machine cycle.
 Data transfer is from memory to memory.
 Micro programmed control unit is found in CISC.
 Also they have variable instruction formats.

Difference Between CISC and RISC

Architectural Complex Instruction Set Reduced Instruction Set
Characterstics Computer(CISC) Computer(RISC)
Instruction size and Large set of instructions with variable Small set of instructions with
format formats (16-64 bits per instruction). fixed format (32 bit).
Data transfer Memory to memory. Register to register.
Most micro coded using control memory
Mostly hardwired without
CPU control (ROM) but modern CISC use hardwired
control memory.
control.
Instruction type Not register based instructions. Register based instructions.
Memory access More memory access. Less memory access.
Clocks Includes multi-clocks. Includes single clock.
Instructions are reduced and
Instruction nature Instructions are complex.
simple.
What is Interleaved Memory?
It is a technique for compensating the relatively slow speed of DRAM(Dynamic RAM). In this
technique, the main memory is divided into memory banks which can be accessed individually
without any dependency on the other.
For example: If we have 4 memory banks(4-way Interleaved memory), with each containing
256 bytes, then, the Block Oriented scheme(no interleaving), will assign virtual address 0 to 255
to the first bank, 256 to 511 to the second bank. But in Interleaved memory, virtual address 0
will be with the first bank, 1 with the second memory bank, 2 with the third bank and 3 with the
fourt, and then 4 with the first memory bank again.
Hence, CPU can access alternate sections immediately without waiting for memory to be cached.
There are multiple memory banks which take turns for supply of data.
Memory interleaving is a technique for increasing memory speed. It is a process that makes the
system more efficient, fast and reliable.
For example: In the above example of 4 memory banks, data with virtual address 0, 1, 2 and 3
can be accessed simultaneously as they reside in spearate memory banks, hence we do not have
to wait for completion of a data fetch, to begin with the next.
An interleaved memory with n banks is said to be n-way interleaved. In an interleaved memory
system, there are still two banks of DRAM but logically the system seems one bank of memory
that is twice as large.
In the interleaved bank representation below with 2 memory banks, the first long word of bank 0
is floowed by that of bank 1, which is followed by the second long word of bank 0, which is
followed by the second long word of bank 1 and so on.
The following figure shows the organization of two physical banks of n long words. All even
long words of logical bank are located in physical bank 0 and all odd long words are located in
physical bank 1.
Types of Interleaving
There are two methods for interleaving a memory:
2-Way Interleaved
Two memory blocks are accessed at same time for writing and reading operations.
4-Way Interleaved
Four memory blocks are accessed at the same time.

Design of Control Unit

Control unit generates timing and control signals for the operations of the computer. The control
unit communicates with ALU and main memory. It also controls the transmission between
processor, memory and the various peripherals. It also instructs the ALU which operation has to
be performed on data.
Control unit can be designed by two methods which are given below:
Hardwired Control Unit
It is implemented with the help of gates, flip flops, decoders etc. in the hardware. The inputs to
control unit are the instruction register, flags, timing signals etc. This organization can be very
complicated if we have to make the control unit large.
If the design has to be modified or changed, all the combinational circuits have to be modified
which is a very difficult task.

Microprogrammed Control Unit

It is implemented by using programming approach. A sequence of micro operations is carried out
by executing a program consisting of micro-instructions. In this organization any modifications
or changes can be done by updating the micro program in the control memory by the
programmer.

Difference between Hardwired Control and Microprogrammed Control

Hardwired Control Microprogrammed Control
Technology is circuit based. Technology is software based.
It is implemented through flip-flops, Microinstructions generate signals to control the
gates, decoders etc. execution of instructions.
Fixed instruction format. Variable instruction format (16-64 bits per instruction).
Instructions are register based. Instructions are not register based.
ROM is not used. ROM is used.
It is used in RISC. It is used in CISC.
Faster decoding. Slower decoding.
Difficult to modify. Easily modified.
Chip area is less. Chip area is large.