Question: }

What is an induction variable, invariant variable, and dead code? Explain with an example. [7M] Here, the statement inside the if block is dead code because the condition x > 10 is
false, so the print statement is never executed.
Answer:
Conclusion:
1. Induction Variable:
An induction variable is a variable that changes in a predictable manner during each  Induction variables help in controlling loop iterations.
iteration of a loop. Typically, it is used as part of the loop counter or index, such as  Invariant variables stay constant during loop execution.
incrementing by 1 or any other constant value in each iteration. It helps in controlling the  Dead code refers to parts of the code that are never executed or have no impact on the
loop flow. program's behavior.

Example: Q. Discuss Global Register Allocation in Code Generation with example. [7M]

for (int i = 0; i < 10; i++) { Answer:

// body of the loop
}
Definition:
Global Register Allocation is the process of assigning a limited number of machine registers to a
In this case, i is an induction variable because it increments by 1 in each iteration of the
large number of variables used in a program, by considering their usage throughout the entire
loop.
program (not just one block).
2. Invariant Variable:
Purpose:
An invariant variable is a variable whose value does not change during the execution of
To minimize memory access (load/store) and increase the efficiency of generated code.
a loop. It is constant within the loop and doesn't get updated or modified by any operation
inside the loop.
Steps in Global Register Allocation:
Example:
1. Construct Control Flow Graph (CFG):
for (int i = 0; i < 10; i++) { Represent the program as basic blocks connected by control flow.
int x = 5; // This is an invariant variable as its value doesn't 2. Compute Live Variables:
change inside the loop Identify which variables are live (used in future) at each point.
// body of the loop 3. Build Interference Graph:
}
Create a graph where nodes are variables. An edge is added if two variables are live at the
same time.
In this example, the variable x is invariant because it always holds the value 5
4. Graph Coloring:
throughout the loop.
Assign registers to variables such that no two connected variables share the same register
(like coloring graph with limited colors = number of registers).
3. Dead Code:
5. Spilling:
Dead code refers to the parts of the program that are never executed or the code that
If there are not enough registers, some variables are stored in memory (called spill).
doesn't affect the program's output. This usually happens when certain conditions or logic
paths are impossible to reach. Dead code is a result of redundant statements that don’t
have any functional impact on the program. Example:
a = b + c;
Example: d = a + e;
f = d + b;
int x = 5;
if (x > 10) {
 Live Variables:
printf("This won't be printed.\n");
 o After a = b + c; → a is used in next line, so it's live. DAG Diagram:
o b is used again in last line, so it's also live after first line.
 Interference Graph: +
/ \
o a interferes with d
+ c
o d interferes with f and b / \
o Variables that interfere can't share registers. a b
 Register Assignment (assume 2 registers R1 and R2):
o a → R1  The lower + node represents a + b
o d → R2  The upper + represents (a + b) + c
o f → memory (spill, if no register available)
✅Step 2: Register Allocation using DAG
Advantages:
 Allocate registers bottom-up
 Reduces memory access  a and b → load into R1 and R2
 Speeds up program execution  a + b → R3 = R1 + R2
 Store result of a + b once and reuse it
Conclusion:  Load c into R4
 (a + b) + c → R5 = R3 + R4
Global register allocation improves code efficiency by smartly assigning registers to variables
across basic blocks using graph coloring techniques. It's better than local allocation which works ✅ Optimized Code (with minimal registers):
block by block.
R1 = a
R2 = b
R3 = R1 + R2 ; t1 = a + b, t2 = a + b
R4 = c
Q. Give an example to show how DAG is used for register allocation. [7M] R5 = R3 + R4 ; t3 = t1 + c

Answer:  Only 5 registers are used

 No need to recompute a + b
DAG (Directed Acyclic Graph) is used in compiler design for register allocation during code  Common sub-expression is reused using DAG
optimization. It helps to identify common sub-expressions and minimize the number of
registers required by reusing values. ✅Advantages:
✅Step-by-step Explanation with Example:  Reduces redundant calculations
 Minimizes number of registers used
Consider the following expression:  Improves performance and memory usage
t1 = a + b
t2 = a + b ✅Conclusion:
t3 = t1 + c
Using DAG in register allocation helps to efficiently handle expressions by eliminating common
✅Step 1: Construct the DAG sub-expressions and assigning minimal registers, which is an important step in compiler
optimization.
 a + b is a common sub-expression
 DAG will contain a single node for a + b Q. Generate code for the following C statements in compiler design:
 t1 and t2 both point to the same node
 Then t3 = (a + b) + c
i) x = f(a) + f(a); main()
{
ii) y = x / 5; int i;
[7M] int a[10];
while(i <= 10)
Answer: a[i] = 0;
}

In compiler design, code generation is the process where the intermediate representation of
source code is translated into target (machine or assembly) code. [7 Marks]

Let’s generate three-address code (TAC) or intermediate code for the given statements. Answer:

To generate code using a code generation algorithm, we convert the high-level C code into
i) x = f(a) + f(a);
Three Address Code (TAC). TAC uses at most three operands and is used as intermediate
code in compilers.
�Important Note:
Since f(a) is a function call and is called twice, the compiler must ensure both calls are
Step-by-step explanation of code:
evaluated separately and their results are added.

Three-Address Code (TAC): 1. i is a variable initialized somewhere before loop (assume initialized to 0).
t1 = call f, a // Call function f with a → store result in t1 2. a[10] is an array.
t2 = call f, a // Call function f again with a → store result in t2 3. The loop runs as long as i <= 10.
t3 = t1 + t2 // Add both results 4. Inside loop: a[i] = 0; and we assume increment i = i + 1; is done for completeness.
x = t3 // Store result in x
Three Address Code (TAC):
ii) y = x / 5; 1. i = 0
L1: if i > 10 goto L2
Three-Address Code (TAC): 2. t1 = i * 4 // Assuming 4-byte integer array
t4 = x / 5 // Divide x by constant 5 3. t2 = &a
y = t4 // Store result in y 4. t3 = t2 + t1 // Address of a[i]
5. *t3 = 0 // a[i] = 0
6. i = i + 1
Final Generated Code: 7. goto L1
L2:
t1 = call f, a
t2 = call f, a Explanation:
t3 = t1 + t2
x = t3
t4 = x / 5  i = 0 → initializes index
y = t4  if i > 10 goto L2 → loop condition check
 t1 = i * 4 → calculates byte offset (assuming 4 bytes per int)
Explanation:  t2 = &a → base address of array
 t3 = t2 + t1 → effective address of a[i]
 t1, t2, etc. are temporary variables.  *t3 = 0 → store value 0 at location
 Each function call is evaluated individually.  i = i + 1 → increment index
 Division and assignment are done step-by-step using intermediate results.  goto L1 → repeat loop
 This is how the code generator in a compiler handles such statements efficiently.
Q. Explain the main issues in code generation. How to handle them? Discuss. [7M]
Q. a) Generate code for the following C program using any code generation
algorithm. Answer:
 In target code generation, the most important step is efficient use of CPU registers. This
involves two main steps:
Main Issues in Code Generation:
1. Register Allocation
1. Input to Code Generator: 2. Register Assignment
o The code generator receives IR from the previous phase.
o It must handle three-address code, syntax tree, or DAG (Directed Acyclic Graph). Let’s understand both in simple terms:
2. Target Program:
o It must generate code for the target machine (like x86, ARM, etc.). 1. Register Allocation:
o The code must be efficient and in proper format.
3. Instruction Selection:  Definition: It decides which variables should be kept in registers.
o Choosing the best machine instructions for each IR statement.  Registers are limited in number, so not all variables can be stored in them.
o Efficient instructions should be selected to reduce execution time.  The goal is to minimize memory access and improve execution speed.
4. Register Allocation:
o Limited number of CPU registers available. Example:
o Temporary values must be stored and reused effectively.
o If not enough registers, use memory (spill). Let’s say we have 3 variables: a, b, c, and only 2 registers are available.
5. Evaluation Order: Register allocation will decide which 2 variables among a, b, c should be kept in registers.
o The order of evaluation affects performance.
o Choose order that reduces number of instructions and register usage. 2. Register Assignment:
6. Handling Variables:
o Variables should be mapped properly to registers or memory.  Definition: It assigns a specific register to each selected variable or temporary.
o Must maintain correct value and scope.
 After allocation, the compiler assigns actual register names (like R0, R1, etc.)
7. Optimization:
o Reduce unnecessary instructions.
Example:
o Apply peephole optimization, constant folding, etc.

If variables a and b are selected for registers, assignment might be:

How to Handle These Issues:
 a → R0
 Efficient IR design to make translation simple.  b → R1
 Use of DAGs or syntax trees to decide instruction selection.
 Graph coloring algorithms for register allocation. Diagrammatic Example:
 Heuristics and cost-based approaches for instruction selection.
 Post-code generation optimization like peephole optimization. Suppose we have an expression:
Conclusion: t1 = a + b
t2 = t1 * c
Proper handling of these issues leads to the generation of optimized, correct, and efficient
target code. A good code generator improves the overall performance of the compiled program. Step 1: Register Allocation
Decide which of a, b, c, t1, t2 go into registers.

Step 2: Register Assignment

Question: Discuss about Register Allocation and Register Assignment in Target Code Assign registers like this:
Generation. [7M]
 a → R0
Answer:  b → R1
  t1 → R2  iis incremented by 1 in every iteration.
 c → R3  So, i is an induction variable.
 t2 → R4
Also,
Final Target Code:
 t1 := 4 * j is a constant multiple of another variable.
R0 = a
 If j is also being incremented linearly (which is common), j can also be an induction
R1 = b
R2 = R0 + R1 variable.
R3 = c
R4 = R2 * R3 ✅ Detection:
Summary: To detect induction variables, we look for:

Term Meaning  Statements like i := i + c or i := i - c, where c is a constant.

 Multiplication with constants like t1 := 4 * j, which are based on induction variables.
Register Allocation Selects which variables to keep in registers
✅ Elimination:
Register Assignment Decides which register to use for each selected variable
We try to replace induction variables with basic ones to reduce calculations.

Question: Example:
Discuss how induction variables can be detected and eliminated from the given If i := i + 1 and j := j + 1, we can eliminate one of them.
intermediate code: We can express i in terms of j or vice versa.
B2: i := i + 1 Let’s say initially:
t1 := 4 * j
t2 := a[t1] i = j = 0 → Then in every loop iteration, both increase by 1.
if t2 < 10 goto B2 So, i = j in every iteration.
Hence, we can remove i and use j directly.
[7M]
✅ Optimized Code (after elimination):
Answer:
B2: j := j + 1
t1 := 4 * j
✅ Induction Variable: t2 := a[t1]
if t2 < 10 goto B2
An induction variable is a variable that is incremented or decremented by a fixed value (usually
in loops). It is mainly used for loop control or index calculations. Now, i is removed → this reduces register usage and improves performance.

✅ Given Intermediate Code: ✅ Conclusion:

B2: i := i + 1
t1 := 4 * j  Induction variables like i := i + 1 can be detected by checking fixed increments.
t2 := a[t1]  If they are linearly related to another variable, they can be eliminated to optimize code.
if t2 < 10 goto B2  This is a standard compiler optimization technique to make code faster and smaller.

Here, Question:
Explain the code generation algorithm in detail with an example. [14M] o Finally, the machine or assembly code is generated and written to an output file
that can be executed by the system.
Answer:
Example:
Code Generation in Compiler Design
Let’s take a simple example to illustrate the process:
Code generation is the final phase in a compiler's translation process, where the intermediate
representation (IR) of the source code is converted into the target machine code or assembly Source Code:
language. This process is crucial because the generated code must be efficient and correct to
execute the program. a = b + c * d;

Steps in Code Generation: Step 1: Intermediate Representation (IR):

1. Intermediate Representation (IR) Generation:  The compiler converts the expression into an IR form that is easier to handle. For
o Before code generation, the compiler generates an intermediate representation example:
(IR) of the source program. This IR is typically in a form that is easier to work  t1 = c * d // temporary variable t1 holds the result of c * d
 t2 = b + t1 // temporary variable t2 holds the result of b + t1
with for further optimization and final code generation.
 a = t2 // assigns the value of t2 to a
2. Translate IR to Target Instructions:
o The IR is translated into the target machine's instruction set, considering registers,
memory, and instructions of the target architecture. Step 2: Translate IR to Target Instructions:
o Each IR instruction is mapped to a machine instruction or assembly language
 Convert the intermediate instructions to machine code instructions, assuming a simple
instruction.
machine with a set of instructions:
3. Register Allocation:
 MUL R1, c, d // multiply c and d, store the result in register R1
o One of the key parts of code generation is deciding where to store values: in
 ADD R2, b, R1 // add b and R1, store the result in R2
registers or memory. Registers are faster, so a good register allocation strategy is  MOV a, R2 // move the value of R2 to the memory location of a
vital.
o Registers are assigned to variables or temporary values generated during
Step 3: Register Allocation:
computation.
4. Instruction Selection:  The compiler assigns registers (R1, R2) to temporary variables and target variables (like
o The compiler chooses specific instructions from the target machine's instruction
a).
set to perform operations such as addition, subtraction, etc.
o Instruction selection is done by mapping the IR operations to corresponding
Step 4: Instruction Scheduling (if needed):
machine instructions.
5. Instruction Scheduling:
 If there are multiple operations that can be done in parallel, the compiler will reorder
o This step involves arranging the machine instructions in a sequence that avoids
instructions to make efficient use of CPU cycles (for example, performing independent
hazards (like data dependencies) and improves execution efficiency.
operations simultaneously).
6. Handling of Expressions:
o Code generation for arithmetic and logical expressions needs to ensure that the
Step 5: Output Generation:
correct operations are performed in the right order, taking operator precedence
and associativity into account.
 Finally, the output assembly code is ready for the machine:
7. Optimization (optional):
 MUL R1, c, d
o Sometimes, the code generation phase includes optimization techniques like
 ADD R2, b, R1
removing redundant operations, minimizing the number of instructions, and using  MOV a, R2
efficient instruction sequences.
8. Output Generation:
Key Concepts in Code Generation:
 1. Register Allocation: The process of assigning variables to registers to optimize  Block 1: a = b + c;
performance.  Block 2: if (a > 10) goto L1;
2. Instruction Selection: Choosing the best instructions based on the IR and the target  Block 3: x = 5;
machine's instruction set.  Block 4: y = x + a; return;
3. Optimization: Minimizing the number of instructions and improving runtime efficiency.
4. Memory Management: Efficiently managing memory to avoid overflow and reduce The flow graph would have these blocks as nodes, with edges representing the control flow
access time. between them. For example, if a > 10, the flow will jump to Block 4 (L1). If not, it will
continue to Block 3.
Question:

a) Discuss basic blocks and flow graphs with an example.

b) Three Address Code (TAC):
b) Generate Three Address Code (TAC) for the following:
1. x=f(a)+f(a)+f(a)x = f(a) + f(a) + f(a)
1. x=f(a)+f(a)+f(a)x = f(a) + f(a) + f(a) TAC:
2. x=f(f(a))x = f(f(a))
3. x=++f(a)x = ++f(a) t1 = f(a)
t2 = f(a)
4. x=f(a)/g(b,c)x = f(a) / g(b, c) t3 = f(a)
x = t1 + t2 + t3

2. x=f(f(a))x = f(f(a))
Answer: TAC:

a) Basic Blocks and Flow Graphs: t1 = f(a)

x = f(t1)

Basic Block:
3. x=++f(a)x = ++f(a)
A basic block is a sequence of consecutive statements in a program that has only one entry point
TAC:
and one exit point. This means there is no branching or jumping within the block. It starts with a
label or a jump instruction and ends with a jump or return instruction. t1 = f(a)
t1 = t1 + 1
Flow Graph: x = t1
A flow graph is a directed graph where nodes represent basic blocks and edges represent control
flow between them. The flow graph helps in visualizing the sequence of execution and 4. x=f(a)/g(b,c)x = f(a) / g(b, c)
dependencies in a program. Each basic block in a program corresponds to a node in the flow TAC:
graph, and edges indicate how the program flow transitions from one block to another.
t1 = f(a)
Example: t2 = g(b, c)
x = t1 / t2
Consider the following program:

1. a = b + c;
2. if (a > 10) goto L1; These TAC representations break down the expressions into simpler three-address code
3. x = 5; instructions where each statement involves at most one operator and two operands. This makes it
4. L1: y = x + a; easier for compilers to optimize and generate machine code.
5. return;

a) Explain the main issues in code generation. [7M]

Here, the basic blocks are:
Answer:  The type and size of the data at that memory location.
 The exact address or offset where the data is stored.
Code generation is a crucial phase of a compiler, where the intermediate code is translated into  The current status of the memory (whether it is being used or free).
machine code or assembly language. The main issues faced during code generation include:
Address descriptors help in generating efficient code for memory access during program
1. Target Architecture: The code generator must handle the specific features of the target execution.
machine, like instruction sets, register usage, and memory addressing modes.
2. Optimization: Efficient use of CPU resources such as registers and memory is necessary iii) Instruction Costs [7M]
to improve the execution time of the generated code. The code should minimize
instruction usage. Answer:
3. Register Allocation: Limited registers in the machine pose challenges in assigning
variables to registers. Overuse of memory or register spilling can degrade performance. Instruction Costs refer to the amount of resources (time, memory, or cycles) required by a
4. Instruction Selection: Mapping high-level operations (like addition, subtraction) to the specific machine instruction to execute. The cost of an instruction varies depending on the
most efficient machine instructions is critical for performance. following factors:
5. Control Flow Generation: Handling loops, jumps, and conditional branches requires
generating the appropriate control flow instructions.  Execution Time: How long the instruction takes to execute on the target machine.
6. Handling of Constants and Variables: Ensuring that constants and variables are  Memory Usage: The amount of memory (registers or main memory) required to execute
correctly mapped to memory locations and registers. the instruction.
7. Error Handling: The code generator must identify and report errors effectively when the  CPU Cycles: The number of clock cycles needed for the instruction to complete its
generated code does not conform to the target machine's constraints. execution.

b) Explain the following terms: In code generation, the goal is to minimize instruction costs to improve program performance,
making sure that fewer and more efficient instructions are used.
i) Register Descriptor [7M]
a) Example to Show How DAG is Used for Register Allocation
Answer:
Directed Acyclic Graph (DAG) is a graph that is used to represent expressions in compiler
A Register Descriptor is a data structure used by a compiler to keep track of the state of optimization, particularly for register allocation. It helps in deciding which variables should be
registers during the code generation phase. It stores information about each register’s current stored in registers and which ones should be stored in memory, improving the efficiency of the
usage, such as: generated code.

 Whether the register is free or currently being used. Example:

 The variable or value assigned to the register.
 The life span of the register in terms of the program execution (when it is needed and Consider a simple expression:
when it can be freed). a = b + c * d

This helps in efficient register allocation and avoids redundant memory accesses. We can construct a DAG for this expression. The DAG is built by representing each operation as
a node, with operands being leaves, and operations being intermediate nodes.
ii) Address Descriptor [7M]
 Nodes b, c, and d are leaves.
Answer:  The operation c * d will have a node, and this result will be fed into the next operation.
 Finally, an addition operation b + (c * d) will be represented in the DAG.
An Address Descriptor is a data structure used by the compiler to maintain information about
memory locations or addresses. It provides details about the variables and constants stored in DAG:
memory, such as:
 The leaf nodes: b, c, d.
  Intermediate node: c * d. a[0] = 0 // Initialize array a[10] with 0s (optional
initialization)
 Final node: b + (c * d). t1 = i // t1 = i
t2 = t1 <= 10 // Check if i <= 10
By using a DAG, the compiler can efficiently determine the dependencies between variables. if t2 goto L1 // If true, enter the loop
Register allocation happens by mapping these DAG nodes into available registers, ensuring that goto L2 // If false, exit loop
each register holds the value of the most critical operations while minimizing memory access.
L1: // Body of the while loop
t3 = 0 // Value to assign to a[i]
b) Code Generation for the Given C Program t4 = i // Current index i
a[t4] = t3 // Store 0 at index i of a
t1 = i + 1 // Increment i
The question asks for code generation for the following C program using any code generation
i = t1 // Update i
algorithm, and yes, TAC (Three-Address Code) is a common intermediate code representation t1 = i // Recalculate t1
used during this phase in the compiler. t2 = t1 <= 10 // Check loop condition
if t2 goto L1 // Continue loop if condition holds
Here is the given C program: goto L2 // Exit loop

L2: // End of loop

main()
{
int i; What is Code Generation in Compiler Design?
int a[10];
while(i <= 10)
Code Generation is the process in a compiler where the intermediate code (such as TAC, AST,
a[i] = 0;
} etc.) is translated into a lower-level language, typically assembly or machine code. During this
phase, the intermediate code instructions are converted into actual instructions for the target
Step-by-Step Code Generation using TAC: CPU.

1. Initialization of variables: TAC (Three-Address Code) is a commonly used intermediate representation that simplifies the
o int i; → i = 0; (initialization) process of generating the final machine code. It has three components:
o int a[10]; → a = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; (array initialization)
2. While loop: 1. Operands: Variables or constants.
o The condition i <= 10 is checked. In TAC, we generate a comparison to check if 2. Operator: Arithmetic or logical operations.
the loop should continue. 3. Result: The output of the operation.
o i = 0 → t1 = i
o i <= 10 → t2 = (t1 <= 10)
In the case of the given C program, TAC helps in breaking down the program into simple
o If t2 is true, execute the body of the loop. Otherwise, exit.
operations that can be easily mapped to the final assembly or machine code.
3. Body of the while loop:
o a[i] = 0; → We store 0 in the ith index of array a.
o t3 = 0 (value to be stored in a[i])
Here is the question along with the answer related to JNTUK:
o t4 = i (current index for the array)
o a[t4] = t3
4. Increment of i: Question:
o After each loop iteration, increment i by 1:
o t1 = i + 1 (i++) a) What are object code forms? Explain.
o i = t1
b) Explain about the Register Allocation and Assignment.
Generated TAC (Three-Address Code):
(OR)
i = 0 // Initialize i to 0
10. a) Explain the issues in the design of a code generator.
b) Explain the code generation algorithm. 3. Instruction Selection: The code generator must choose the appropriate machine
instructions for the operations specified in the high-level code.
Answer: 4. Handling Different Data Types: The code generator needs to handle various data types
(integers, floats, arrays, etc.) and their corresponding machine representations.
a) Object Code Forms: 5. Error Handling: Proper error handling is necessary for generating code that handles
runtime errors or exceptions correctly.
Object code forms refer to the representation of machine code generated by a compiler or
assembler. It is the low-level code that is ready for execution by the machine. Object code forms b) Code Generation Algorithm:
are often in binary format and consist of several key components:
The code generation algorithm is responsible for translating intermediate code (such as three-
1. Text Section: Contains the executable instructions of the program. address code or intermediate representation) into the target machine code. The key steps in the
2. Data Section: Holds initialized and uninitialized global variables. code generation process include:
3. BSS (Block Started by Symbol) Section: Stores uninitialized global variables.
4. Symbol Table: Contains addresses of variables, functions, and constants. 1. Intermediate Code Selection: The first step is to select intermediate code instructions
5. Relocation Information: Allows the linking of different code modules into a single that are closer to the target machine code. For example, simple arithmetic operations or
executable. assignments are selected from the intermediate code.
6. Debugging Information: May include information useful for debugging. 2. Instruction Selection: For each intermediate instruction, select the corresponding
machine instruction from the target architecture's instruction set. This step ensures that
Object code is platform-specific and is generated from the source code written in high-level the target machine’s instructions are used efficiently.
languages like C, Java, or Python. 3. Register Allocation: During this phase, the algorithm decides which registers will be
used to hold intermediate values. It uses techniques like live variable analysis to
b) Register Allocation and Assignment: minimize memory access and improve performance.
4. Code Emission: The final step is emitting the selected machine instructions along with
Register allocation is the process of assigning a limited number of machine registers to variables appropriate register assignments, jumps, and labels.
or intermediate results used in a program. In a computer system, registers are fast storage
locations, and effective register allocation can significantly improve the performance of the code. Example:

Steps in Register Allocation: Intermediate Code:

t1 = a + b
1. Live Variable Analysis: The first step is to determine which variables are live (i.e., they t2 = t1 * c
are used later in the program). d = t2 - e
2. Graph Coloring: A common technique for register allocation. Each variable is
represented as a node, and an edge is drawn between nodes if the variables interfere with Code Generation (x86 Example):
each other (i.e., cannot be assigned to the same register).
3. Spilling: If there are not enough registers, some variables are temporarily stored in MOV R1, a ; Load a into register R1
memory (spilled) instead of registers. MOV R2, b ; Load b into register R2
ADD R1, R2 ; R1 = a + b
MOV R3, c ; Load c into register R3
(OR) 10. a) Issues in the Design of a Code Generator: MUL R1, R3 ; R1 = (a + b) * c
MOV d, R1 ; Store result in d
The design of a code generator has several challenges:

1. Target Machine Dependence: The generated code must be specific to the target
architecture (e.g., x86, ARM), and ensuring compatibility can be complex. Question:
2. Optimization: The generated code must be efficient in terms of both time and space.
Techniques like loop unrolling, instruction scheduling, and register allocation must be
applied carefully.
Generate simple assembly language target code for the following intermediate code statements ; T2 = a * c
using a simple code generator. Assume that the target machine has three registers (R1, R2, R3). LOAD R1, a ; Load a into R1
LOAD R2, c ; Load c into R2
Initially, all registers are empty and no variable is live at the end of all statements. MUL R1, R2 ; R1 = a * c (T2)

Intermediate Code Statements: ; T3 = T1 + b

LOAD R1, T1 ; Load T1 into R1
LOAD R2, b ; Load b into R2
1. T1 = a * b ADD R1, R2 ; R1 = T1 + b (T3)
2. T2 = a * c
3. T3 = T1 + b ; T4 = a + T2
4. T4 = a + T2 LOAD R1, a ; Load a into R1
5. T5 = b + T4 LOAD R2, T2 ; Load T2 into R2
ADD R1, R2 ; R1 = a + T2 (T4)

Answer: ; T5 = b + T4
LOAD R1, T4 ; Load T4 into R1
LOAD R2, b ; Load b into R2
The target machine has three registers, so we need to use them efficiently to generate assembly ADD R2, R1 ; R2 = b + T4 (T5)
code. We assume that the variables a, b, and c are stored in memory, and we'll load them into
registers as needed.
Explanation:
Let's break it down:
 LOAD: Transfers data from memory to a register.
 MUL: Multiplies the contents of two registers.
1. T1 = a * b:
 ADD: Adds the contents of two registers and stores the result in the first register.
o Load a into R1.
o Load b into R2.
This assembly code ensures that the intermediate code is computed efficiently by using the
o Perform the multiplication and store the result in R1.
available registers.
2. T2 = a * c:
o Load a into R1.
o Load c into R2.
Question:
o Perform the multiplication and store the result in R1.
3. T3 = T1 + b: Explain various object code forms used in compilation. [5M]
o Load T1 (stored in R1) and add b (in R2) to it.
o Store the result in R1. Answer:
4. T4 = a + T2:
o Load a into R1. In a compiler, object code refers to the machine code or intermediate code generated after the
o Load T2 (stored in R2).
source code is compiled. The object code forms are used to optimize the code for efficient
o Perform the addition and store the result in R1.
execution. Various forms of object code include:
5. T5 = b + T4:
o Load b into R2.
1. Absolute Code:
o Load T4 (stored in R1).
In this form, the compiler generates a machine code that directly corresponds to memory
o Perform the addition and store the result in R2.
locations. The instructions in the code are mapped directly to physical memory addresses.
This type of code is specific to the system architecture and doesn't allow for
relocatability.
Assembly Code:
Example:
; T1 = a * b A code that accesses a variable using a fixed memory address, such as MOV AX,
LOAD R1, a ; Load a into R1 [0x1234].
LOAD R2, b ; Load b into R2 2. Relocatable Code:
MUL R1, R2 ; R1 = a * b (T1) This form allows the object code to be loaded at different memory locations during
 execution. The generated machine code contains placeholders (like relative addresses) 2. Reduce Memory Access:
which can be adjusted when loaded into memory. This form is commonly used in linkers. Register allocation minimizes the number of memory accesses, thereby reducing the
Example: number of slow memory operations. This can lead to significant performance gains,
A program that accesses a variable at an offset from the base address, such as MOV AX, especially in computationally intensive applications.
[BX + 0x10]. Example:
3. Machine Code: If a loop accesses an array frequently, placing the array index in a register can speed up
This is the final, low-level code that is directly executed by the computer’s CPU. It the loop execution by avoiding repetitive memory fetches.
consists of binary instructions that the processor understands. The compiler generates this 3. Limited Number of Registers:
form when producing the final executable file. The number of registers available is limited. A good register allocation strategy must
Example: decide which variables should be assigned to registers and which ones should remain in
A machine instruction like 01011010 (in binary). memory. Inefficient allocation may lead to excessive memory access or use of slower
4. Intermediate Code: registers.
This is a lower-level, platform-independent representation of the source code, usually Example:
generated after parsing. It is easier to optimize and can later be translated into machine If the register space is overused, the compiler may need to store and reload values from
code for different platforms. memory, leading to a performance hit.
Example: 4. Spilling:
A 3-address code like t1 = a + b. When there are not enough registers, some variables are "spilled" into memory. Spilling
5. Bytecode: occurs when a variable is moved from a register to memory due to the lack of available
Bytecode is a form of intermediate code that is closer to machine code, often used in registers. This can significantly affect the execution speed of a program.
environments like Java. It’s portable and can be interpreted or compiled into machine Example:
code by a virtual machine. If a program needs to store an additional variable but all registers are full, it will store the
Example: variable in memory, resulting in slower access.
A Java program might generate bytecode like aload_0, iconst_5, etc. 5. Optimization Techniques:
Modern compilers use various algorithms for register allocation, such as graph coloring
Question: or greedy approaches, to maximize the use of registers. These techniques attempt to
minimize spills and allocate registers optimally.
Explain how does register allocation techniques affect program performance. [7M] Example:
In a function with many temporary variables, the compiler might use a technique that
reuses registers after they are no longer needed, optimizing performance.
Answer:

Register allocation is a crucial optimization step during compilation that determines which Question:
Explain Peephole Optimization in the context of target assembly language programs with
variables should be stored in the CPU registers rather than in memory. Efficient register
examples.
allocation can greatly improve program performance by reducing memory access time. The
[7M]
performance of a program is directly affected by the number of registers available and how
effectively they are utilized.
Answer:
Key Points:
Peephole Optimization refers to a local optimization technique used in compiler design,
specifically targeting the assembly language generated by compilers. The idea behind peephole
1. Improved Speed:
optimization is to improve a small part of the program, typically a few adjacent instructions, by
Registers are much faster than memory (RAM) in terms of data access speed. By using
replacing them with more efficient or shorter alternatives without changing the overall
registers efficiently, a program can execute faster. If a variable is kept in memory instead
functionality of the code.
of a register, every time it’s accessed, the program will experience slower performance
due to memory latency.
The process involves examining a "window" or "peephole" of a few instructions at a time and
Example:
trying to simplify or improve them. This optimization is often applied during the code generation
If a variable x is stored in a register, the instruction ADD R1, R2, R3 (where R1, R2, and
phase and helps in reducing the size of the generated code and improving its execution speed.
R3 are registers) will execute much faster than if x were stored in memory.
Types of Peephole Optimization: Since dividing by 2 can be efficiently replaced by a right shift operation, we can optimize the
code:
1. Redundant instruction elimination: Removing unnecessary instructions.
2. Common sub-expression elimination: Replacing repeated calculations with a single SHR R1, #1 ; Right shift R1 by 1 (equivalent to dividing by 2)
instruction.
3. Instruction substitution: Replacing a sequence of instructions with a more efficient This optimization reduces the number of instructions and executes faster.
single instruction.
4. Strength reduction: Replacing expensive operations like multiplication or division with Question:
cheaper ones like addition or subtraction.
Explain about next-use, register descriptor, address descriptor data structures used in simple code
Example 1: Redundant Instruction Elimination generation algorithm with an example.
b) Write a simple code generation algorithm with an example.
Consider the following code:
Answer:
MOV R1, R2 ; Copy the value in R2 to R1
MOV R1, R3 ; Copy the value in R3 to R1 a) Next-Use, Register Descriptor, and Address Descriptor Data Structures:

In this case, the first instruction is redundant because the second instruction overwrites the value In the context of simple code generation algorithms, the following data structures are used to
of R1. The optimized version would be: facilitate efficient and optimized generation of machine code.
MOV R1, R3 ; Directly move the value in R3 to R1
1. Next-Use:
o The "next-use" data structure is used to keep track of the next use of a variable or
Here, we have eliminated the first redundant instruction.
operand. It helps in determining the most appropriate location (register or
memory) to store values during code generation.
Example 2: Common Sub-Expression Elimination o It keeps track of how soon a value will be used again, which helps in register
allocation by minimizing register spills and improving the performance of the
Consider the following code sequence: generated code.
o Example:
MOV R1, R2 ; R1 = R2
ADD R1, R3 ; R1 = R1 + R3 If a variable a is used at instruction i+1 and not again until i+5, its next-use will
MOV R4, R1 ; R4 = R1 be recorded as i+5. The compiler can decide to hold it in a register until that
point.
The second instruction (ADD R1, R3) is a common operation where R1 is used and modified. We 2. Register Descriptor:
can optimize this by directly writing: o The register descriptor contains information about the status of registers in the
machine, including whether a register is free or allocated and which variable it
ADD R2, R3 ; R1 = R2 + R3 (and store it directly in R4) holds.
MOV R4, R1 ; R4 = R2 + R3 o It is important for allocating registers to variables during code generation.
o Example:
This reduces the number of instructions and makes the code more efficient. If a register R1 is holding variable a, the register descriptor will indicate R1 -> a.
3. Address Descriptor:
Example 3: Instruction Substitution o The address descriptor stores information about the addresses of variables or
memory locations. It helps the compiler to map variables to physical memory
Consider the following sequence: addresses.
o It plays a vital role in deciding where variables will reside during code generation.
MUL R1, R2 ; Multiply R1 and R2 o Example:
MOV R3, #2 ; Load 2 into R3
DIV R1, R3 ; Divide R1 by R3
If a variable x is stored in memory location 0x1000, the address descriptor will
map x -> 0x1000.
b) Simple Code Generation Algorithm: o Generated Code: R4 = R1 * R5
o Register Descriptor: R4 -> t2, R1 -> t1, R5 -> c
The simple code generation algorithm is used to generate the final target code (machine code or 3. Instruction 3:
assembly code) from an intermediate representation (IR) like three-address code (TAC). The o d = t2 + e
steps of the algorithm typically include register allocation, instruction selection, and instruction o Register Allocation: Allocate R6 for d and R7 for e.
scheduling. o Generated Code: R6 = R4 + R7
o Register Descriptor: R6 -> d, R4 -> t2, R7 -> e
Algorithm:
Final Generated Assembly Code:
1. Input:
oThree-address code (TAC) for a given program. R1 = R2 + R3 ; t1 = a + b
R4 = R1 * R5 ; t2 = t1 * c
oRegister descriptor and address descriptor. R6 = R4 + R7 ; d = t2 + e
2. Process:
o Traverse through the TAC.
Conclusion: In this simple code generation process, the algorithm performs register allocation,
o For each instruction: updates descriptors, and generates the target code based on the intermediate representation. The
 If the instruction involves a variable, check the register descriptor to find a next-use information helps in deciding when to keep a variable in a register or store it in
free register or assign a new register. memory, ensuring efficient code generation.
 If the variable is not available in a register, check the address descriptor
for the memory location.
a) Different Forms of Object Code Used as Target Code in Target Code
 Generate the corresponding machine code instruction.
 Update the register descriptor and address descriptor.
Generation
3. Output:
o Generated assembly or machine code. Object Code Forms are the machine code generated by the compiler after the source code has
been parsed, optimized, and translated into intermediate representations. The target code forms
Example: typically used in target code generation are:

Let’s take a simple example where we have a few intermediate code statements and generate the 1. Absolute Code:
o In absolute code, the machine instructions are generated with fixed memory
corresponding assembly code.
addresses. These are directly mapped to the physical memory addresses.
o Example:
Intermediate Code: o MOV A, 2000 ; Move the value of A into memory location 2000
o ADD B, 3000 ; Add the value of B from memory location 3000
t1 = a + b
t2 = t1 * c
2. Relocatable Code:
d = t2 + e o In relocatable code, the machine code is generated without fixed addresses. The
addresses are placeholders, which are replaced later by a linker when the program
Step-by-Step Code Generation: is loaded into memory.
o Example:
o MOV R1, X ; Move value into register R1
1. Instruction 1: o ADD R2, Y ; Add value from memory address Y into register R2
o t1 = a + b
3. Position-Independent Code (PIC):
o Next-Use Analysis: t1 will be used immediately in the next instruction.
o This form of code does not depend on the actual memory address in which the
o Register Allocation: Allocate a register R1 for t1, R2 for a, and R3 for b.
program is loaded. It is generated in such a way that it can be loaded at any
o Generated Code: R1 = R2 + R3
address in memory.
o Register Descriptor: R1 -> t1, R2 -> a, R3 -> b
o Example:
2. Instruction 2: o MOV R3, [PC + OFFSET] ; Use PC-relative addressing for position
o t2 = t1 * c independence
o Next-Use Analysis: t2 will be used in the next instruction. 4. Byte Code:
o Register Allocation: Allocate R4 for t2 and R5 for c.
 o Byte code is an intermediate code that is closer to machine language, but it is This results in the following graph:
designed to be executed by a virtual machine (such as JVM for Java). It is not
directly executed by the hardware. V1 --- V2
o Example: | |
o 0x60 ; Push constant 0x60 onto stack V3 --- V4
o 0x64 ; Add top two elements of stack
2. Color the Graph:
Advantages of these forms: o Assign R1 to V1, R2 to V2, and R3 to V3.
o V4 can be assigned R1 since it does not interfere with V1.
 Absolute code is fast to execute as it directly uses memory addresses.
 Relocatable code and position-independent code are more flexible, especially for This gives the following register assignment:
linking and running code in different memory spaces.
o V1 → R1
o V2 → R2
o V3 → R3
b) Register Allocation by Graph Coloring o V4 → R1 (Reuse R1)

Register Allocation by Graph Coloring is a technique used to assign variables in a program to Advantages of Graph Coloring:
the available CPU registers efficiently, minimizing the need to use memory for variable storage.
 It allows for efficient register allocation by minimizing the usage of memory.
The basic idea is to represent variables and their interference relationships as a graph, and then
 It is an optimal approach in the sense that it attempts to use as few registers as possible.
apply graph coloring to assign the variables to registers.

Steps involved: a) Different Addressing Modes and Their Role in Improving Performance of
Target Program [7M]
1. Build an Interference Graph:
o Create a graph where each node represents a variable. Addressing modes define how the operands of an instruction are specified. They provide a
o There is an edge between two nodes if their corresponding variables are used at mechanism for specifying operands in various ways. These modes help in making the assembly
the same time (i.e., they interfere with each other and cannot be assigned to the code more flexible and efficient by allowing different methods to access data. Here are the
same register). common addressing modes:
2. Graph Coloring:
o The problem is to color the graph using a limited number of colors (representing 1. Immediate Addressing Mode:
available registers). Each color corresponds to a register, and two connected o Explanation: The operand is specified directly within the instruction.
nodes (variables that interfere) must have different colors (assigned to different o Example: MOV A, #5
registers). In this case, 5 is an immediate value assigned directly to register A.
o The goal is to color the graph using as few colors as possible, corresponding to 2. Register Addressing Mode:
the number of available registers. o Explanation: The operand is located in a register. The instruction specifies the
register.
Example: o Example: MOV A, B
This moves the contents of register B to register A.
Let’s say there are 4 variables (V1, V2, V3, V4) and 3 registers (R1, R2, R3). 3. Direct Addressing Mode:
o Explanation: The effective address of the operand is given directly in the
1. Build the Interference Graph: instruction.
o V1 and V2 interfere (need different registers) o Example: MOV A, 2000
o V2 and V3 interfere The operand is located at memory address 2000.
o V3 and V4 interfere 4. Indirect Addressing Mode:
 o Explanation: The instruction specifies a register or memory location that holds o Explanation: Reducing the overhead of loop control by repeating the body of the
the address of the operand. loop multiple times.
o Example: MOV A, (R1) o Example:
Here, the value in register R1 is treated as the address of the operand to be fetched. 3. for (i = 0; i < 10; i++)
4. sum += arr[i];
5. Indexed Addressing Mode:
o Explanation: The effective address is obtained by adding a constant value
(offset) to the contents of a register. Unrolling the loop:
o Example: MOV A, 100(R1)
sum += arr[0]; sum += arr[1];
The address of the operand is calculated by adding 100 to the contents of register sum += arr[2]; sum += arr[3];
R1. ...
6. Register Indirect Addressing Mode:
o Explanation: The operand's address is found in a register, and the value at that 5. Register Allocation:
address is the operand. o Explanation: Efficiently using CPU registers to store temporary data rather than
o Example: MOV A, [R1] memory, as accessing registers is much faster.
The contents of the address stored in R1 are moved into register A. o Example: When variables are frequently used, allocating them to registers can
speed up the program.
How Addressing Modes Improve Performance: o Optimization: Assigning frequently accessed variables to registers rather than
using memory access.
 Faster Execution: Direct and register addressing modes are faster since they avoid 6. Common Subexpression Elimination (CSE):
memory lookups. o Explanation: Identifying and eliminating redundant calculations by reusing
 Reduced Instruction Size: Immediate and register addressing modes reduce the size of previously computed values.
the instruction since they don’t need extra memory addresses. o Example:
 Memory Access Efficiency: Indirect and indexed addressing modes provide efficient 7. a = b + c;
8. d = b + c;
memory access, making it easier to deal with complex data structures like arrays and
tables.
 Flexibility: Addressing modes make it easier to write flexible programs that can Optimization:
manipulate data in various ways, improving the program's general performance by temp = b + c;
enabling more efficient memory access and calculation. a = temp;
d = temp;

9. Inline Expansion:
b) Different Machine Dependent Code Optimizations with Examples [7M] o Explanation: Replacing a function call with the actual code of the function.
o Example: Replacing small functions with their code can save the overhead of
Machine dependent optimizations refer to techniques used to optimize code based on the function calls.
architecture of the target machine (processor). These optimizations can improve the speed and o Optimization: Instead of calling a small function, the compiler directly inserts the
efficiency of the compiled code, taking advantage of specific hardware features. function's code into the calling location.
10. Constant Folding:
1. Instruction Scheduling: o Explanation: Evaluating constant expressions at compile time rather than at
o Explanation: Rearranging the order of instructions to avoid pipeline stalls and runtime.
hazards. o Example:
o Example: In a pipeline processor, a load instruction might be delayed until the 11. x = 3 + 4;
previous computation finishes, ensuring the CPU remains busy.
o Optimization: Moving independent instructions closer together to utilize the Optimized during compilation:
CPU pipeline fully.
x = 7;
2. Loop Unrolling:
 12. Peephole Optimization: oExample: In the statement int x = "Hello";, semantic analysis detects that a
o Explanation: Optimizing short sequences of instructions (often replacing them string cannot be assigned to an integer.
with more efficient ones). 4. Intermediate Code Generation:
o Example: If an instruction performs an unnecessary move from one register to o In this phase, the compiler generates an intermediate representation (IR) of the
another, it can be eliminated. code, which is platform-independent.
o Optimization: o Example: The assignment x = 5 may be translated to an intermediate form like
13. MOV R1, R2 LOAD 5, STORE x.
14. ADD R3, R1

Machine-Dependent Phases:
Optimized to:

ADD R3, R2
Machine-dependent phases of compilation involve hardware-specific operations, and they are
tailored to generate machine code for a specific target machine.
How Machine Dependent Optimizations Help in Performance:
1. Code Optimization:
o While some optimizations can be machine-independent, many optimization
 Speed: By reducing redundant operations, managing registers efficiently, and reordering
instructions, these optimizations help in making the program run faster. techniques are platform-specific. For example, loop unrolling or instruction
 Reduced Resource Usage: Optimizing memory and register usage reduces the need for scheduling can depend on the target processor.
o Example: A loop that processes large data may be optimized differently on an
expensive memory accesses and function calls, leading to reduced time complexity.
 Better CPU Utilization: Techniques like instruction scheduling make sure the CPU ARM processor vs an Intel processor.
pipeline is fully utilized, reducing idle time and improving overall execution speed. 2. Code Generation:
o This phase converts the intermediate code into machine-specific assembly or
By applying machine-dependent optimizations, compilers can generate code that is finely tuned machine code, depending on the target architecture.
o Example: The intermediate code LOAD 5, STORE x will be translated to
for the target hardware, leading to significant improvements in both performance and efficiency.
assembly instructions like MOV 5, R1 on an Intel processor, but a different
instruction set may be used for an ARM processor.
a) Phases of Compilation: Machine Independent vs Machine Dependent
3. Code Linking and Assembly:
o These steps involve generating final machine code (or assembly code) and linking
Machine-Independent Phases:
it with libraries specific to the target machine.
The machine-independent phases of compilation are those that do not depend on the architecture
of the target machine. These phases work in a high-level manner, abstracting away details of the b) Relocatable Object Code and Cross-Platform Compatibility
hardware.
Relocatable object code is a type of machine code where the address of instructions and data are
1. Lexical Analysis: not fixed. Instead, they can be adjusted or relocated in memory during the linking process. This
o This phase scans the source code and converts it into tokens (keywords, operators,
helps in making the compiled code more flexible and adaptable for different systems.
variables, etc.). It does not depend on the machine architecture.
o Example: In the source code int x = 5;, the lexical analyzer breaks it into
How it helps in Cross-Platform Compatibility:
tokens like int, x, =, 5, and ;.
2. Syntax Analysis: 1. Modular Compilation:
o Relocatable object code allows code to be compiled into separate modules, each
o The syntax analyzer checks the syntactic structure of the program, ensuring the
source code follows grammar rules. It generates a syntax tree. having placeholders for addresses. These modules can be combined and relocated
o Example: The syntax tree for the expression x = 5 could show x as the left
at runtime, making it easier to adapt the code to different platforms.
o Example: A program can be compiled into a relocatable object code on one
operand and 5 as the right operand, with = as the assignment operator.
system, and the same object code can be linked on another system, adjusting
3. Semantic Analysis:
addresses based on the target system’s memory layout.
o It checks for semantic errors, ensuring that the code makes logical sense. For
2. Portability:
example, it ensures type consistency.
 oSince the addresses are not fixed, relocatable object code allows the same Answer: Assembly code acts as the intermediate representation of a program that closely mimics
compiled program to run on different platforms without modification, as long as the behavior of the machine. It is a low-level code that is directly translated into machine code by
the code linking step takes place correctly. an assembler.
o Example: A program compiled on a Windows machine can be executed on a
Linux system, assuming the linking process adapts the code to the new machine's Understanding Program Execution through Assembly Code:
memory model.
3. Linker Adjustments: 1. Instruction Mapping:
o During the linking phase, a linker adjusts the addresses according to the target o Each assembly instruction corresponds to a specific machine instruction, allowing
machine’s architecture. This makes relocatable object code highly useful in us to directly see how a program's high-level operations are executed on the CPU.
situations where the program is to be run on different hardware or OS. 2. Memory and Register Operations:
o Example: If a function is at address 0x100 in one system, it can be relocated to o Assembly code provides insight into how variables are loaded, stored, and
0x200 in another system, without changing the code itself. manipulated in registers and memory. This is useful for understanding how values
are passed, modified, and stored during program execution.
1. (a) How register assignment will be done? Explain in detail. [7M] 3. Control Flow:
o Assembly code makes control flow (loops, conditionals) more transparent by
Answer: Register assignment is the process of mapping variables in a program to a limited showing jump instructions, conditional branches, and the sequence of execution
number of machine registers. It is crucial for optimizing program performance, as registers are steps.
faster to access than memory. 4. Optimization Identification:
o Analyzing assembly code helps in identifying optimization opportunities, like
Steps in Register Assignment: redundant operations or inefficient memory access patterns, thus improving the
program’s performance.
1. Interference Graph Construction: 5. Debugging:
o The first step involves creating an interference graph, where each node represents o Assembly code is useful in debugging programs, especially when working with
a variable and an edge between two nodes represents that the variables interfere low-level operations, as it gives a clear picture of how each instruction affects the
(i.e., they are live at the same time and cannot share the same register). CPU's state.
2. Graph Coloring:
o Register assignment is typically solved using graph coloring, where each node Conclusion: Assembly code helps in understanding how high-level language constructs are
(variable) is assigned a color (register) such that no two adjacent nodes mapped to machine operations, providing a detailed view of the program's execution and
(interfering variables) share the same color (register). behavior.
3. Spilling:
o If there are more variables than available registers, spilling occurs. This means 2. (a) Explain peephole optimization on target assembly language programs with
some variables are temporarily moved to memory and will be loaded into registers examples. [7M]
when needed.
4. Optimizing Register Use: Answer: Peephole optimization is a local optimization technique that inspects a small window
o The compiler may use heuristics or optimizations (like minimal register usage, (or "peephole") of instructions in the assembly code to identify and replace inefficient or
prioritizing frequently used variables) to improve performance. redundant instructions with more efficient ones. This optimization is performed on the generated
5. Final Assignment: target code, typically after the code generation phase.
o After the graph is colored, the register assignments are finalized, and the
corresponding machine code instructions are generated. Examples of Peephole Optimization:

Conclusion: Register assignment is a crucial step in code generation and optimization, ensuring 1. Redundant Instruction Elimination:
that the program runs efficiently within the limited register space. o Example:
o MOV R1, R2
o MOV R2, R1
1. (b) Explain how assembly code as target code helps in understanding program
execution. [7M]
 This can be optimized to just removing both instructions because they are o The code generator must handle errors in the intermediate code (such as type
redundant. mismatches or invalid operations) and report them clearly.
7. Platform Dependencies:
2. Constant Folding: o Code generation must consider platform-specific factors like memory model,
o Example: instruction set, and calling conventions, making it less portable across different
o ADD R1, 5 systems.
o ADD R2, 5
Conclusion: Designing a code generator is challenging because it must balance efficiency,
This can be optimized to: correctness, and platform-specific requirements while generating optimized machine code.
ADD R1, R2, 10

3. Strength Reduction:
o Example: Instead of using expensive multiplication, use addition.
o MUL R1, R2, 4

Can be optimized to:

ADD R1, R1, R1, R1

Conclusion: Peephole optimization reduces unnecessary code and makes the generated assembly
more efficient, improving the overall performance of the program.

2. (b) Discuss various issues in the design of code generator. [7M]

Answer: Designing a code generator involves translating an intermediate representation (IR) of a

program into machine-specific code. There are several challenges faced during this process:

1. Target Machine Architecture:

o The code generator must be tailored to the target architecture (e.g., x86, ARM),
considering its instruction set, addressing modes, and register usage.
2. Efficient Register Allocation:
o Register allocation is a critical issue. Limited registers require intelligent
allocation to minimize the use of memory and optimize execution speed.
3. Instruction Selection:
o The code generator must decide which machine instruction corresponds to the
high-level operations in the IR. This involves choosing the most efficient
instructions.
4. Optimization:
o The code generator should incorporate various optimizations (such as constant
folding, strength reduction) to improve the performance of the generated code.
5. Handling Control Flow:
o Managing jumps, branches, loops, and function calls in assembly code is
complex. Ensuring correct control flow while minimizing jumps is an important
design issue.
6. Error Handling: