SCHOOL OF INDUSTRIAL AND INFORMATION ENGINEERING

MASTER OF SCIENCE IN ELECTRICAL ENGINEERING

Electromagnetic Compatibility B 2024-2025:

Homework 1 2024-2025:

Family name Given name Student ID

1 Calvi Daniele 10808754
2 Cattaneo Alberto 10807490
3 Ravì Antonio 10807995
4 Siddi Luca 10797399
5 Donelli Jacopo 10764809
6 Di Muro Nicholas 10780747

Academic Year 2024 - 2025

SUMMARY

1 PROBLEM NO. 1 .............................................................................................................. 3

1.1 Open circuit case ......................................................................................................... 3

1.1.1 f = 150kHz ......................................................................................................... 4

1.1.2 f = 30MHz .......................................................................................................... 4
1.2 Short circuit case ......................................................................................................... 5

1.2.1 f = 150kHz ......................................................................................................... 6

1.2.2 f = 30MHz .......................................................................................................... 7
2 PROBLEM NO. 2 .............................................................................................................. 8

2.1 DM Test setup ............................................................................................................. 8

2.2 CM Test setup ............................................................................................................. 9

2.3 Analytical expression for ILs .................................................................................... 10

2.3.1 DM ................................................................................................................... 10
2.3.2 CM ................................................................................................................... 12
2.4 Insertion Losses Bode Diagram ................................................................................ 13

2.4.1 DM ................................................................................................................... 13
2.4.2 CM ................................................................................................................... 14
2.5 Spice Prediction Verification .................................................................................... 15

2.5.1 Differential Mode............................................................................................. 15

2.5.2 Common Mode ................................................................................................ 16
3 PROBLEM NO. 3 ............................................................................................................ 17

3.1 CM Test setup ........................................................................................................... 17

3.2 DM Test Setup .......................................................................................................... 19

3.3 Cy and Cx evaluation ................................................................................................ 21

3.4 Including the effects of Lleads ..................................................................................... 22

3.5 Cx as ten capacitors in parallel ................................................................................... 24

4 PROBLEM No. 4 ............................................................................................................. 25

1
4.1 Selection of the Best Filter Topology ....................................................................... 25

4.2 Analytical Expressions for DM and CM Insertion Losses (ILs) ............................... 27

4.3 Calculation of Lg and Cx Values ................................................................................. 31

2
1 PROBLEM NO. 1

In order to illustrate that the LISN shows a 𝟓𝟎𝛀 impedance between phase/neutral and
ground, we have to compute the expression of the equivalent impedance 𝒁 ̂ 𝒆𝒒 in the two cases
of short-circuit and open-circuit representations. Then we will evaluate the value of this
impedance at the ends of CE frequency band (i.e., respectively 𝒇 = 𝟏𝟓𝟎𝒌𝑯𝒛 and 𝒇 =
𝟑𝟎𝑴𝑯𝒛). We are considering Information Technology Equipment, otherwise the frequency
band for conducted emission spans from 𝟗𝒌𝑯𝒛 to 𝟑𝟎𝑴𝑯𝒛.

1.1 Open circuit case

Figure 2.1.1 LISN with open circuit

Figure 1.1.1 LISN open circuit equivalent

The first step to retrieve the equivalent impedance of the LISN is to compute the parallel
between the two resistances of 𝑹𝟏 and 𝑹𝟐 .
𝑅1 𝑅2
𝑅𝑝𝑎𝑟 = 𝑅1 +𝑅2

Then we can easily compute the impedance 𝒁𝟏 by performing the series between 𝑹𝒑𝒂𝒓 and
1
the capacitor 𝑪𝟏 , whose impedance is 𝑍𝐶1 = 𝑗𝜔𝐶1

1 1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟
𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 𝑅𝑝𝑎𝑟 + =
𝑗𝜔𝐶1 𝑗𝜔𝐶1

Furthermore, we can calculate the series impedance between capacitor 𝑪𝟐 , whose impedance
1
is 𝑍𝐶2 = 𝑗𝜔𝐶 and the inductor L which has an impedance equal to 𝑍𝐿 = 𝑗𝜔𝐿.
2

1 −𝜔2 𝐿𝐶2 + 1
𝑍2 = 𝑍𝐶2 + 𝑍𝐿 = + 𝑗𝜔𝐿 =
𝑗𝜔𝐶2 𝑗𝜔𝐶2

The last step is calculating the parallel impedance between 𝒁𝟏 and 𝒁𝟐 , which results in the
equivalent impedance 𝒁 ̂ 𝒆𝒒 searched:

3
 Figure 1.1.2 LISN 𝒁𝟏 and 𝒁𝟐 circuit
equivalent

1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟 −𝜔2 𝐿𝐶2 + 1

∗
𝑗𝜔𝐶1 𝑗𝜔𝐶2
𝑍̂𝑒𝑞 = 𝑍1 ||𝑍2 = =
1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟 −𝜔 2 𝐿𝐶2 + 1
+
𝑗𝜔𝐶1 𝑗𝜔𝐶2

−𝜔2 𝐿𝐶2 + 1 − 𝑗𝜔3 𝐿𝐶1 𝐶2 𝑅𝑝𝑎𝑟 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟

−𝜔 2 𝐶1 𝐶2
= =
𝑗𝜔𝐶2 − 𝜔 2 𝐶1 𝐶2 𝑅𝑝𝑎𝑟 − 𝑗𝜔 3 𝐿𝐶1 𝐶2 + 𝑗𝜔𝐶1
−𝜔 2 𝐶1 𝐶2

−𝜔2 𝐿𝐶2 + 1 − 𝑗𝜔3 𝐿𝐶1 𝐶2 𝑅𝑝𝑎𝑟 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟

=
𝑗𝜔𝐶2 − 𝜔 2 𝐶1 𝐶2 𝑅𝑝𝑎𝑟 − 𝑗𝜔 3 𝐿𝐶1 𝐶2 + 𝑗𝜔𝐶1

Substituting the values of the different components of the LISN, it’s possible to evaluate each
impedance written previously in the two frequencies at the ends of CE frequency band.
1.1.1 f = 150kHz
𝑅𝑝𝑎𝑟 = 47.619 Ω

𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 47.619 − 𝑗10.61 Ω

𝑍2 = 𝑍𝐶2 + 𝑍𝐿 = 𝑗46.063 Ω

𝑍̂𝑒𝑞 = 𝑍1 ||𝑍2 = 28.667 + 𝑗24.719 Ω

To figure out whether the impedance seen by LISN is actually 50Ω we need to consider its
̂ 𝒆𝒒 | = 37.8534 Ω
absolute value: |𝒁

1.1.2 f = 30MHz
𝑅𝑝𝑎𝑟 = 47.619 Ω

𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 47.619 − 𝑗0.053 Ω

4
𝑍2 = 𝑍𝐶2 + 𝑍𝐿 = 𝑗9424.773 Ω

𝑍̂𝑒𝑞 = 𝑍1 ||𝑍2 = 47.6183 + 𝑗0.187 Ω

To figure out whether the impedance seen by LISN is actually 50Ω we need to consider its
̂ 𝒆𝒒 | = 47.6186 Ω
absolute value: |𝒁

̂ 𝒆𝒒 | trend as a function of frequency in the open circuit

Figure 1.1.2.1 Impedance |𝒁
case.

1.2 Short circuit case

Figure 1.2.1 LISN short circuit equivalent

The first step is the same described in Section 1.1 of the open circuit case, where we can
initially find the parallel resistance between 𝑹𝟏 and 𝑹𝟐 .

5
 𝑅1 𝑅2
𝑅𝑝𝑎𝑟 =
𝑅1 + 𝑅2

Then, we proceed in the same way done before by performing the series impedance between
capacitor 𝑪𝟏 and the parallel resistance 𝑹𝒑𝒂𝒓 , obtaining 𝒁𝟏 .

1 1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟
𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 𝑅𝑝𝑎𝑟 + =
𝑗𝜔𝐶1 𝑗𝜔𝐶1

Now, by the fact that the capacitor 𝑪𝟐 is short-circuited in this configuration of the LISN, 𝒁𝟐
is different from before. 𝒁𝟐 in the short circuit configuration corresponds to just the
impedance of the inductor L.

𝑍2 = 𝑍𝐿 = 𝑗𝜔𝐿

̂ 𝒆𝒒 as parallel between 𝒁𝟏 and 𝒁𝟐 .

In the end we can compute 𝒁

1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟
∗ 𝑗𝜔𝐿
̂ 𝒆𝒒 𝑗𝜔𝐶1
𝒁 = 𝑍1 ||𝑍2 = =
1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟
+ 𝑗𝜔𝐿
𝑗𝜔𝐶1

𝑗𝜔𝐿 − 𝜔2 𝐿𝐶1 𝑅𝑝𝑎𝑟

𝑗𝜔𝐶1
= =
1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟 − 𝜔 2 𝐿𝐶1
𝑗𝜔𝐶1

𝑗𝜔𝐿 − 𝜔2 𝐿𝐶1 𝑅𝑝𝑎𝑟

=
1 + 𝑗𝜔𝐶1 𝑅𝑝𝑎𝑟 − 𝜔 2 𝐿𝐶1

To find the value of the impedance seen in the LISN it’s possible to substitute the circuit
parameters and consider the two frequencies, in the same way discussed before.

1.2.1 f = 150kHz
𝑅𝑝𝑎𝑟 = 47.619 Ω

𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 47.619 − 𝑗10.61 Ω

𝑍2 = 𝑍𝐿 = 𝑗47.124 Ω

̂ 𝒆𝒒 = 𝑍1 ||𝑍2 = 29.367 + 𝑗24.605 Ω

𝒁

To figure out whether the impedance seen by LISN is actually 50Ω we need to consider its
̂ 𝒆𝒒 | = 38.3125 Ω
absolute value: |𝒁

6
1.2.2 f = 30MHz
𝑅𝑝𝑎𝑟 = 47.619 Ω

𝑍1 = 𝑅𝑝𝑎𝑟 + 𝑍𝐶1 = 47.619 − 𝑗0.053 Ω

𝑍2 = 𝑍𝐿 = 𝑗9424.778 Ω

̂ 𝒆𝒒 = 𝑍1 ||𝑍2 = 47.6183 + 𝑗0.186 Ω

𝒁
To figure out whether the impedance seen by LISN is actually 50Ω we need to consider its
̂ 𝒆𝒒 | = 47.619 Ω
absolute value: |𝒁

It can be noted that the two cases differ slightly, indeed the main difference is the impedance

̂ 𝒆𝒒 | trend as a function of frequency in the short

Figure 1.2.2.1 Impedance |𝒁
circuit case.
value at 150 kHz, for which the two circuits configuration differ by 0.4 Ω. This is due to the
fact that the main objective of the LISN is to show a constant impedance, whatever is the
measurement set up.
For high frequencies, LISN shows a constant value of nearly 50 Ω.

7
2 PROBLEM NO. 2
The focus of this problem is evaluating the differential and common mode insertion losses
(ILs) of the following circuit, representing a power supply filter:

Figure 2.0.1 Power Supply Filter

The power supply filter is composed of an ideal common-mode choke with 𝐿 = 𝑀 = 15 𝑚𝐻,
a green wire inductor 𝐿𝑤 = 12 𝑚𝐻 and a line-to-line capacitor with 𝐶𝑥 = 48 𝑛𝐹.

2.1 DM Test setup

In the DM insertion loss measurement test setup the green wire terminals are left
unconnected while the phase and the neutral wires are connected each other, as shown in
Figure 2.1.1.

Figure 2.1.1 DM Test setup

8
 Figure 2.1.2 DM Test Setup Equivalent Circuit

The equivalent circuit presented here is derived by analyzing the components that form the
filter in a Differential Mode (DM) Test Setup.
The X-Capacitor 𝑪𝒙 becomes of value 2𝑪𝒙 , the common-mode choke can be considered of
value 𝑳 − 𝑴, but taking into account that the two values of self-inductance and mutual-
inductance are the same, they cancel out resulting in a zero-impedance element (short
circuit).
Lastly, the green-wire inductor 𝑳𝒘 can be entirely neglected in the DM Test Setup, since the
differential mode currents don’t flow through it.
𝑹
The two resistances of 50 Ω are now halved and showed in the circuit as 2𝟎 .

2.2 CM Test setup

In the CM insertion loss measurement test set up the phase and neutral wires are shorted
together and then connected to the test circuit with the green wire, as shown in Figure 2.2.1.

Figure 2.2.1 CM Test setup

9
 Figure 2.2.2 CM Test setup equivalent circuit

The equivalent circuit for the Common Mode (CM) test setup is derived as follows:
The common-mode choke is represented by 𝑳 + 𝑴, while the green-wire inductor has an
equivalent value of 2𝑳𝒘 . The X-Capacitor does not influence the CM equivalent test setup,
since it is shorted.
Additionally, the two resistances are now considered with a doubled value, 2𝑹𝟎 .

2.3 Analytical expression for ILs

The general formula for insertion losses is:
|𝑉𝐿,𝑤𝑜 |
𝐼𝐿𝑑𝐵 = 20𝑙𝑜𝑔10 ( )
|𝑉𝐿,𝑤 |
Where:
• 𝑰𝑳𝒅𝑩 are the insertion losses in decibels
• 𝑽𝑳,𝒘𝒐 is the voltage across the load without the filter
• 𝑽𝑳,𝒘 is the voltage across the load with the filter

2.3.1 DM

Figure 2.3.1.1 General Capacitive filter in test

setup

The general expression of insertion losses for a capacitive filter, like the one in Figure
2.3.1.1, can be derived from the circuit.

10
The first step requires doing the parallel impedance between capacitor 𝑪 and the resistance
representing the load 𝑹𝟎 .
1 𝑅0
𝒁𝒑𝒂𝒓 = || 𝑅0 =
𝑗𝜔𝐶 𝑗𝜔𝐶𝑅0 + 1
̂
Then the voltage 𝑽𝑳,𝒘 can be evaluated.

𝑅0
𝑍𝑝𝑎𝑟 𝑗𝜔𝐶𝑅 0+1 1
̂ 𝑳,𝒘
𝑽 = 𝑉̂𝑠 = 𝑉̂𝑠 = 𝑉̂𝑠 =
𝑅0 + 𝑍𝑝𝑎𝑟 𝑅0 𝑗𝜔𝐶𝑅0 + 1 + 1
𝑅0 + 𝑗𝜔𝐶𝑅 + 1
0
1 1 𝑉̂𝑠 1 𝑉̂𝑠
𝑉̂𝑠 = =
𝑗𝜔𝐶𝑅0 + 2 𝑗𝜔𝐶𝑅0 2 𝑗𝜔𝜏 + 1 2
2 +1

After have computed the expression of voltage on load with the presence of the filter, it is
required to derive the expression for ILs using the general formula, considering that the
̂
𝑉
voltage on load without filter is equal to 𝑉𝐿,𝑤𝑜 = 2𝑠.

𝑉̂𝑠
|
|𝑉𝐿,𝑤𝑜 | 2|
𝑰𝑳𝒅𝑩,𝑫𝑴 = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 (|𝑗𝜔𝜏 + 1|)
|𝑉𝐿,𝑤 | 1 𝑉̂𝑠
|𝑗𝜔𝜏 + 1 2 |
= 20𝑙𝑜𝑔10 (√1 + 𝜔 2 𝜏 2 ) = 10𝑙𝑜𝑔10 (1 + 𝜔2 𝜏 2 )

Where:
• 𝜔 = 2𝜋𝑓
𝐶𝑅
• 𝜏 = 20
• 𝐶 = 2𝐶𝑥 ,
𝑅
• 𝑅𝑛𝑒𝑤 = 20
𝐶 𝑅
• 𝜏 = 𝑥 2𝑛𝑒𝑤
Last three parameters are referred to the DM equivalent circuit, in Figure 2.1.2, recalling that
𝐿 − 𝑀 = 0.

11
2.3.2 CM

Figure 2.3.2.1 General Inductive filter in test setup

Considering then the general expression of insertion losses for an inductive filter, like the one
in Figure 2.3.2.1, its formula can be derived as follows.
The first step requires doing the total impedance of the circuit involving inductor 𝑳 and the
two resistances representing the load and the source impedance, both equal to 𝑹𝟎 .

𝒁𝒕𝒐𝒕 = 𝑅0 + 𝑅0 + 𝑗𝜔𝐿

̂ 𝑳,𝒘 can be evaluated as:

Then 𝑽

𝑅0 𝑅0 𝑅0 𝑉̂𝑠
̂ 𝑳,𝒘 =
𝑽 𝑉̂𝑠 = 𝑉̂𝑠 = =
𝑍𝑡𝑜𝑡 2𝑅0 + 𝑗𝜔𝐿 𝑗𝜔𝐿
𝑅0 + 2 2
1 𝑉̂𝑠 1 𝑉̂𝑠
=
𝑗𝜔𝐿
1 + 2𝑅 2 1 + 𝑗𝜔𝜏 2
0

Approaching the same procedure as before lead us to the evaluation of IL through the use of
the general formula.
𝑉̂𝑠
|
|𝑉𝐿,𝑤𝑜 | 2|
𝑰𝑳𝒅𝑩,𝑪𝑴 = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 (|𝑗𝜔𝜏 + 1|)
|𝑉𝐿,𝑤 | 1 𝑉̂𝑠
|𝑗𝜔𝜏 + 1 2 |
= 20𝑙𝑜𝑔10 (|√1 + 𝜔 2 𝜏 2 |) = 10𝑙𝑜𝑔10 (1 + 𝜔2 𝜏 2 )

Where:
• 𝜔 = 2𝜋𝑓
𝐿
• 𝜏=
2𝑅0
• 𝐿 = 𝐿 + 𝑀 + 𝐿𝑤
• 𝑅𝑛𝑒𝑤 = 2𝑅0
𝐿+𝑀+2𝐿
• 𝜏 = 4𝑅 𝑤
𝑛𝑒𝑤
Last three parameters are referred to the CM equivalent circuit, in Figure 2.2.2.

12
2.4 Insertion Losses Bode Diagram
Plotting the insertion losses of a filter with a Bode diagram is crucial for analyzing its
performance and assessing its effectiveness in attenuating conductive emissions (CE).
From the Bode diagram we can evaluate at which frequency the filter starts working (cut-off
frequency), hence when the filter effectively attenuates noise signals. A good filter should
provide strong attenuation in the stopband (150kHz – 30 MHz) while minimizing loss in the
passband.

2.4.1 DM

Figure 2.4.1.1 Bode Diagram ILs DM Test Setup

This graph represents the Insertion Losses of the Differential Mode (DM) Test Setup
equivalent circuit. The filter is a first-order filter, as it consists of a single component: the X-
Capacitor.
The graph shows a +20 𝑑𝐵/𝑑𝑒𝑐𝑎𝑑𝑒 slope, meaning that the attenuation increases by 20 𝑑𝐵
for every tenfold increase in frequency.
The cut-off frequency is defined for an insertion loss of 3 dB, since:

𝑰𝑳𝒇𝒄𝒖𝒕−𝒐𝒇𝒇 = 10𝑙𝑜𝑔10 (1 + 𝜔2 𝜏 2 ) = 10𝑙𝑜𝑔10 (1 + 1) ≈ 3 𝑑𝐵

1 1
In the case considered, 𝒇𝒄𝒖𝒕−𝒐𝒇𝒇,𝑫𝑴 = 2𝜋𝜏 = 𝐶 𝑅 = 132,629 𝑘𝐻𝑧
𝐷𝑀 2𝜋( 𝑥 𝑛𝑒𝑤 )
2
Thus, the result obtained is coherent with the graph in Figure 2.4.1.1.

13
2.4.2 CM

Figure 2.4.2.1 Bode Diagram ILs CM Test Setup

This graph illustrates the Insertion Losses of the Common Mode (CM) Test Setup equivalent
circuit. The filter in question is a first-order filter, consisting of two inductors in series: the
common-mode choke and the green-wire inductor.
The graph exhibits a +20 𝑑𝐵/𝑑𝑒𝑐𝑎𝑑𝑒 slope, indicating that the attenuation increases by
20 𝑑𝐵 for every tenfold increase in frequency.
The cut-off frequency corresponds, as in the previous case, to an insertion loss of 3 dB.
1 1
In the case considered, 𝒇𝒄𝒖𝒕−𝒐𝒇𝒇,𝑪𝑴 = 2𝜋𝜏 = 𝐿+𝑀+2𝐿𝑤 = 589 𝐻𝑧
𝐶𝑀 2𝜋( )
4𝑅𝑛𝑒𝑤
Thus, the result obtained is coherent with the graph in Figure 2.4.2.1.

14
2.5 Spice Prediction Verification
By implementing the DM and CM equivalent test set-ups in SPICE software, it was possible
to verify the prediction of the cut-off frequencies and the Bode diagram plot for each of the
two circuits.

2.5.1 Differential Mode

Figure 2.5.1.1 SPICE DM equivalent test set-up

For the differential mode, the ILs plotted using SPICE software appears as follows:

Figure 2.5.1.2 DM SPICE Bode plot

Figure 2.5.1.2 shows a result which is consistent with the one analytically evaluated in the
previous points. ILs slope is actually +20 𝑑𝐵/𝑑𝑒𝑐𝑎𝑑𝑒 and the cutoff frequency of the filter
is 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓,𝐷𝑀 ≈ 132 𝑘𝐻𝑧.

Figure 2.5.1.3 Cuf-toff frequency with cursor on SPICE tool

15
2.5.2 Common Mode

Figure 2.5.2.1 SPICE CM equivalent test set-up

The results obtained in paragraph 2.4.2 are confirmed by the use SPICE simulator.
For the common mode, the ILs plotted appears as follows:

Figure 2.5.2.2 CM SPICE Bode plot

Figure 2.5.2.2 shows a result which is consistent with the one analytically evaluated in the
previous points. ILs slope is actually +20 𝑑𝐵/𝑑𝑒𝑐𝑎𝑑𝑒 and the cutoff frequency of the filter
is 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓,𝐶𝑀 ≈ 591 𝐻𝑧.

Figure 2.5.2.3 Cuf-toff frequency with cursor on SPICE tool

16
3 PROBLEM NO. 3
For Problem 3, we examine a circuit different from the one discussed in the previous
sections. Our focus now is on analyzing the insertion losses in the Differential Mode (DM)
and Common Mode (CM) test setups of the following circuit, which consists of only
capacitors

Figure 3.1 Power Supply Filter with only capacitors

The test setup related this kind of filter in Figure 3.1 is designed as:
.
3.1 CM Test setup
In the CM insertion loss measurement test set up the phase and neutral wires are shorted
together and then connected to the test circuit with the green wire, as shown in Figure 3.1.1

Figure 3.1.1 CM Test Setup

Applying KVL and KCL, some simplifications can be performed, resulting in the following
circuit:

17
 Figure 3.1.2 CM Test Setup equivalent circuit

We end up with this circuit because the line-to-line capacitor 𝑪𝒙 is short circuited and thus
does not appear in the equivalent circuit, while the equivalent capacitance of the four parallel
line-to-ground capacitors 𝑪𝒚 is effectively 2𝑪𝒚 .
Additionally, the two resistances are now considered with a doubled value, 2𝑹𝟎 .

To find the expression for 𝐼𝐿𝑑𝐵,𝐶𝑀 , the value of 𝑉𝐿,𝑤 must be derived, from the circuit shown
in Figure 3.1.2, as follows:

𝑅0
𝑗𝜔4𝐶𝑦
1 𝑅0
𝑅0 + 𝑗𝜔4𝐶
(𝑅0 ||4𝐶𝑦 ) 𝑦 1 + 𝑗𝜔4𝐶 𝑦 𝑅0
𝑉𝐿,𝑤 = 𝑉̂𝑠 = 𝑉̂𝑠 = 𝑉̂𝑠
𝑅0 + (𝑅0 ||4𝐶𝑦 ) 𝑅0 𝑅0
𝑅0 + 1 + 𝑗𝜔4𝐶 𝑅
𝑗𝜔4𝐶𝑦 𝑦 0
𝑅0 + 1
𝑅0 + 𝑗𝜔4𝐶
𝑦
𝑅0 1 𝑉̂𝑠
= 𝑉̂𝑠 =
2𝑅0 + 𝑗𝜔4𝐶𝑦 𝑅0 2 1 + 𝑗𝜔2𝐶𝑦 𝑅0 2

̂
𝑉
While the value of 𝑉𝐿,𝑤𝑜 is always 𝑉𝐿,𝑤𝑜 = 2𝑠 .

Now we can evaluate the insertion losses with the general formula introduced in the
paragraph 2.3:

𝑉̂
|𝑉𝐿,𝑤𝑜 | | 2𝑠 |
𝑰𝑳𝒅𝑩,𝑪𝑴 = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 (|𝑗𝜔𝜏 + 1|)
|𝑉𝐿,𝑤 | 1 𝑉̂𝑠
|𝑗𝜔𝜏 + 1 2 |
= 20𝑙𝑜𝑔10 (√1 + 𝜔 2 𝜏 2 ) = 10𝑙𝑜𝑔10 (1 + 𝜔2 𝜏𝐶𝑀 2 )
Where:
• 𝜔 = 2𝜋𝑓
• 𝜏𝐶𝑀 = 2𝐶𝑦 𝑅0

18
Then the cutoff frequency expression can be obtained by taking into account some
simplifications:
2
• 1 ≫ 𝜔2 (2𝐶𝑦 𝑅0 ) ⇒ 𝐼𝐿𝑑𝐵,𝐶𝑀 ≈ 10𝑙𝑜𝑔10 (1) = 0
2 2
• 1 ≪ 𝜔2 (2𝐶𝑦 𝑅0 ) ⇒ 𝐼𝐿𝑑𝐵,𝐶𝑀 ≈ 10𝑙𝑜𝑔10 (𝜔2 (2𝐶𝑦 𝑅0 ) )

Then, the cutoff frequency is:

2 1 1
1 = 𝜔2 (2𝐶𝑦 𝑅0 ) ⇒ 1 = 𝜔𝑐𝑢𝑡−𝑜𝑓𝑓 𝜏𝐶𝑀 ⇒ 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓,𝐶𝑀 = =
2𝜋𝜏𝐶𝑀 4𝜋𝐶𝑦 𝑅0

The cut-off frequency corresponds to an insertion loss of 3 dB.

Figure 3.1.3 Bode diagram of CM insertion losses

3.2 DM Test Setup

In the DM insertion loss measurement test setup the green wire terminals are left
unconnected while the phase and the neutral wires are connected each other, as shown in
Figure 3.2.1.

Figure 3.2.1 DM Test Setup

19
Applying KVL and KCL, some simplifications can be performed, resulting in the following
circuit:

Figure 3.2.2 DM Test Setup equivalent circuit

The circuit here presented is derived considering that the line-to-line capacitor 𝐶𝑥 has, in the
DM equivalent circuit, a value of 2𝐶𝑥 , while for the four line-to-ground capacitors 𝐶𝑦 I have
to consider them first as in series taken as couples and then in parallel each other, obtaining a
capacitance 2𝐶𝑦 .

To find the expression for 𝐼𝐿𝑑𝐵,𝐷𝑀 , the value of 𝑉𝐿,𝑤 must be derived, considering the Figure
3.2.2.

1 1
𝑅 𝑅
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 0 1 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 0
( 1 ) 1
𝑅0
+ 𝑅0 + 𝑅0
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 )
𝑉𝐿,𝑤 = 𝑉̂𝑠 = 𝑉̂𝑠
1 1
𝑅 𝑅
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 0 1 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 0
(𝑅0 + 1 ) 1+ 1
𝑅0
+ 𝑅0 + 𝑅0
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 )
1 1
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 𝑉̂𝑠
= 𝑉̂𝑠 =
1 𝑅0 1 2
𝑅0 + 2
𝑗𝜔(𝐶𝑦 + 𝐶𝑥 ) 2 + 𝑗𝜔(𝐶𝑦 + 𝐶𝑥 )

̂𝑠
𝑉
As usual we consider the value of 𝑉𝐿,𝑤𝑜 = 2

𝑉̂𝑠
|
|𝑉𝐿,𝑤𝑜 | 2|
𝑰𝑳𝒅𝑩,𝑫𝑴 = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 ( ) = 20𝑙𝑜𝑔10 (|𝑗𝜔𝜏 + 1|)
|𝑉𝐿,𝑤 | 1 𝑉̂𝑠
| |
𝑗𝜔𝜏 + 1 2
= 20𝑙𝑜𝑔10 (√1 + 𝜔 2 𝜏 2 ) = 10𝑙𝑜𝑔10 (1 + 𝜔2 𝜏𝐷𝑀 2 )

20
Where:
• 𝜔 = 2𝜋𝑓
(𝐶𝑦 +𝐶𝑥 )𝑅0
• 𝜏𝐷𝑀 = 2
Then the cutoff frequency expression can be obtained by taking into account some
simplifications:
2
(𝐶𝑦 +𝐶𝑥 )𝑅0
• 1 ≫ 𝜔2 ( ) ⇒ 𝐼𝐿𝑑𝐵,𝐶𝑀 ≈ 10𝑙𝑜𝑔10 (1) = 0
2
2 2
(𝐶 +𝐶 𝑥 )𝑅0 (𝐶𝑦 +𝐶𝑥 )𝑅0
•
𝑦
1≪ 𝜔2 ( ) ⇒ 𝐼𝐿𝑑𝐵,𝐶𝑀 ≈ 10𝑙𝑜𝑔10 (𝜔2 ( ) )
2 2

Then, the cutoff frequency is:

2
2
(𝐶𝑦 + 𝐶𝑥 )𝑅0 1 1
1=𝜔 ( ) ⇒ 1 = 𝜔𝑐𝑢𝑡−𝑜𝑓𝑓 𝜏𝐷𝑀 ⇒ 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓,𝐷𝑀 = =
2 2𝜋𝜏𝐷𝑀 𝜋(𝐶𝑦 + 𝐶𝑥 )𝑅0

The cut-off frequency corresponds to an insertion loss of 3 dB.

Figure 3.2.3 Bode diagram of DM insertion losses

3.3 Cy and Cx evaluation

For calculating 𝐶𝑦 and 𝐶𝑥 the following equation system has been defined and solved:

2
𝐼𝐿𝑑𝐵,𝐶𝑀 (2 𝑀𝐻𝑧) = 10𝑙𝑜𝑔10 (1 + 𝜔2 (2𝐶𝑦 𝑅0 ) ) = 5 𝑑𝐵
2
(𝐶𝑦 + 𝐶𝑥 )𝑅0
2
𝐼𝐿𝑑𝐵,𝐷𝑀 (6 𝑀𝐻𝑧) = 10𝑙𝑜𝑔10 (1 + 𝜔 ( ) ) = 20 𝑑𝐵
2
{
2
(1 + 𝜔2 (2𝐶𝑦 𝑅0 ) ) = 100.5
2
(𝐶𝑦 + 𝐶𝑥 )𝑅0
(1 + 𝜔2 ( ) ) = 102
2
{

Resulting values of 𝐶𝑦 and 𝐶𝑥 are:

21
 𝐶𝑦 = 1.17 𝑛𝐹
{
𝐶𝑥 = 9.38 𝑛𝐹

Then we can plot the insertion losses of the two setups, by highlighting that
𝐼𝐿𝑑𝐵,𝐶𝑀 (2 𝑀𝐻𝑧) = 5 𝑑𝐵 and 𝐼𝐿𝑑𝐵,𝐷𝑀 (6 𝑀𝐻𝑧) = 20 𝑑𝐵.

Figure 3.3.1 IL plots for CM and DM configuration

3.4 Including the effects of Lleads

To evaluate the effects due to components leads we need to add in series with each capacitor,
𝐶𝑥 and 𝐶𝑦 , an inductor 𝐿𝑙𝑒𝑎𝑑𝑠 = 16 𝑛𝐹.
To study the behavior of insertion losses, the two circuits in Figure 3.4.1 and Figure 3.4.2 are
studied, representing CM and DM Test Setup.

Figure 3.4.1 CM Test Setup including effects due to components leads

22
 Figure 3.4.2 DM Test Setup including effects due to components leads

The ILs plot resulting from the circuits illustrated before is the following:

Figure 3.4.3 ILs plot of DM (red) and CM (green) Test Setup

Analyzing the CM insertion losses, it can be stated that they present a discontinuity at a
certain frequency. This arises by the fact that there exists a resonance between the line-to-
ground capacitors 𝐶𝑦 and the inductors 𝐿𝑙𝑒𝑎𝑑𝑠 .
The resonance frequency can be easily obtained by considering that this phenomenon occurs
when the total impedance of the capacitor and of the inductor, in series, is zero.
1
𝑓𝑟1 = = 36.784 𝑀𝐻𝑧
2𝜋√𝐶𝑦 𝐿𝑙𝑒𝑎𝑑𝑠
The line-to-line capacitance doesn’t contribute to this phenomenon because it is effectively
short circuited in this configuration.

Regarding the IL of DM Test Setup, we can notice a double discontinuity.

This is since 𝐶𝑥 and 𝐿𝑙𝑒𝑎𝑑𝑠 give rise to one resonance frequency, while 𝐶𝑦 and 𝐿𝑙𝑒𝑎𝑑𝑠 give
rise to another resonance frequency:

23
 1
𝑓𝑟1 = 2𝜋 = 36.784 𝑀𝐻𝑧
√𝐶𝑦 𝐿𝑙𝑒𝑎𝑑𝑠
1
𝑓𝑟2 = = 12.991 𝑀𝐻𝑧
2𝜋√𝐶𝑥 𝐿𝑙𝑒𝑎𝑑𝑠

Observing these results we can conclude that the DM insertion losses are mainly affected by
the presence of components leads, because they exhibit a deviation with respect to the ideal
behavior of the filter at lower frequency (around 23.8 MHz earlier) than the CM insertion
losses and also they present a double discontinuity while for the CM ILs, the discontinuity
occurs at only one specific frequency.

3.5 Cx as ten capacitors in parallel

The circuit obtained by representing the line-to-line capacitance modelled as ten capacitors in
parallel is the following:

Figure 3.5.1 DM Test Setup with ten capacitors in parallel

In this section we deal only with DM Test Setup because in CM Test Setup, the ten
capacitors configuration would be useless because they are short circuited, meaning that no
effective change occurs.

The simulation of the circuit leads us to this result:

Figure 3.5.2 DM Test Setup Insertion Losses when ten Cx capacitors are used

24
Observing Figure 3.5.2 we can state that the ten capacitors displacement is very effective
because the frequency where the resonance occurs between 𝐶𝑥 and 𝐿𝑙𝑒𝑎𝑑𝑠 is shifted further to
the right at
1
𝑓𝑟_𝑛𝑒𝑤 = = 41.082 𝑀𝐻𝑧
2𝜋√𝐶𝑥_𝑛𝑒𝑤 𝐿𝑙𝑒𝑎𝑑𝑠

Consequently, the insertion loss characteristic is linear/ideal up to higher frequencies

compared to the previous case.
Since the bandwidth related to conducted emissions ranges from 150 Hz to 30 MHz, the new
resonance frequency 𝑓𝑟_𝑛𝑒𝑤 falls outside the bandwidth defined by the EMC test limits.

4 PROBLEM NO. 4

4.1 Selection of the Best Filter Topology

The digital product failed the conducted emissions test at two frequency points:

𝒇𝟏 = 𝟏 𝑴𝑯𝒛 (Differential Mode - DM):

1. 𝑉𝐿1 = 10.536 𝑚𝑉 (phase 17°)
2. 𝑉𝐿2 = 10.682 𝑚𝑉 (phase 197°)
The phase difference is 197° − 17° = 180°, hence confirming it as DM noise.

𝒇𝟐 = 𝟏𝟎 𝑴𝑯𝒛 (Common Mode - CM):

1. 𝑉𝐿1 = 13.475 𝑚𝑉 (phase 32°)
2. 𝑉𝐿2 = 13.322 𝑚𝑉 (phase 31°)
The phase difference is 32° − 31° = 1°, hence confirming it as CM noise.

These measures provide critical information regarding the conducted emissions generated by
the digital product under test, specifically at the frequencies where the product has failed. The
voltage measurements, coupled with the phase angle data, allow us to understand the nature
of those emissions.

In a three-conductor system, the currents can be divided into two distinct components, known
as differential mode (DM) and common mode (CM).

Differential Mode (DM):

In differential mode, the currents flow in opposite directions through paired conductors.
Consequently, the polarity of the measured voltages will be opposite. When one voltage
reaches its peak positive value, the other reaches its peak negative value, resulting in a
maximum phase difference of 180 degrees between the two voltages in a balanced system.
This explains why the phase difference between VL1 and VL2, that it’s exactly 180 degrees,
confirms the DM-nature of the emissions at frequency 𝒇𝟏 = 1 𝑀𝐻𝑧.

Common Mode (CM):

In common mode, currents flow in the same direction converging in the ground conductor.
Thus, this time polarities will be the same, hence we can expect a phase difference near or
equal to zero for a balanced system. Again, this explains the CM-nature of the measurement
at 𝒇𝟐 = 10 𝑀𝐻𝑧, given that the phase difference between VL1 and VL2 is only 1 degree.

25
Filter topology:
In the case of Differential Mode emissions, the current flows through the phase conductor
and returns through the neutral conductor. This configuration is ideal for the application of
the properties of a capacitive impedance. Since this type of impedance is inversely
proportional to frequency, placing a capacitor between the phase and neutral conductors can
effectively suppress high-frequency noise. In fact, the capacitor provides a low-impedance
path for the high-frequency noise, thus enabling it to bypass the load.

In the case of Common Mode emissions, the currents flow in the same direction through
both the phase and neutral conductors, with the sum of these currents being returned via the
ground wire. In this case we exploit an inductive impedance by placing an inductor along the
ground wire, since it has a high impedance with high-frequency common-mode currents,
while it permits low-frequency currents to pass. Hence, this impedance presents a
considerable opposition to the flow of high-frequency noise or interference present in
common-mode currents.

Based on said principles, the most effective filter topology employing only an inductor and a
capacitor would be as follows:

Figure 4.1.1 Filter topology

26
4.2 Analytical Expressions for DM and CM Insertion Losses
(ILs)
5
Differential Mode 𝑰𝑳𝑫𝑴 :
Considering the Differential Mode (DM) insertion loss measurement test setup, where the
green wire terminals are left unconnected, and only the phase and neutral wires from the
circuit under test are involved, the circuit configuration is as follows in Figure 4.2.1:

Figure 4.2.1 Differential mode test setup

By applying Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL), the
following equivalent circuit can be derived in Figure 4.2.2:

Figure 4.2.2 Differential mode equivalent circuit

Thus, considering the equivalent circuit the DM Insertion Losses can be derived:

|𝑉̂𝐿𝑊0 |
𝐼𝐿𝐷𝑀 |𝑑𝐵 = 20 log10 ( )
|𝑉̂𝐿𝑊 |
Where 𝑉̂𝐿𝑊0 and 𝑉̂𝐿𝑊 are the measured voltage without and with the filter.
Since the resistances are equal, the first one can be easily obtained through a resistive divider.
𝑉̂𝑆
𝑉̂𝐿𝑊0 =
2
𝑅
To compute the second one, the equivalent parallel impedance 𝑍𝑒𝑞 = 𝑍𝐶𝑥 \\ 20 must be found
𝑅0 1
2 ∙ 𝑗𝜔2𝐶𝑥
𝑍𝑒𝑞 =
𝑅0 1
2 + 𝑗𝜔2𝐶𝑥
And so, the voltage 𝑉̂𝐿𝑊 is computed as:

27
 1
𝑍𝑒𝑞 𝑍𝑒𝑞 𝑍𝑒𝑞 1 1
𝑉̂𝐿𝑊 = 𝑉̂𝑆 = ∙ 𝑉̂𝑆 = 𝑉̂ = 𝑉̂𝑆
𝑅0 𝑅0 1 𝑅0 𝑆 𝑅0 1
𝑍𝑒𝑞 + 2 𝑍𝑒𝑞 + 2 𝑍 1 + 2𝑍
𝑒𝑞 𝑒𝑞 𝑅 2 + 𝑗𝜔2𝐶𝑥
1 + 20 ∙ ( 𝑅 1 )
0
2 ∙ 𝑗𝜔2𝐶𝑥
1 1 1
⇒ 𝑉̂𝐿𝑊 = 𝑉̂𝑆 = 𝑉̂
2 + 𝑗𝜔𝑅0 𝐶𝑋 2 1 + 𝑗𝜔 𝑅0 𝐶𝑥 𝑆
2

Defined the DM-Time constant

𝑅0 𝐶𝑥
𝜏𝐷𝑀 ≜
2
The DM Insertion Loss are computed:
𝑉̂𝑆
|
̂
|𝑉𝐿𝑊0 | 2|
𝐼𝐿𝐷𝑀 |𝑑𝐵 = 20 log10 ( ) = 20 log10 ( ) = 20 log10 (|1 + 𝑗𝜔𝜏𝐷𝑀 |)
|𝑉̂𝐿𝑊 | 1 𝑉̂𝑆
|2 1 + 𝑗𝜔𝜏 |
𝐷𝑀

2 2 )
= 20 log10 (√1 + 𝜔 2 𝜏𝐷𝑀 ) = 10 log10 (1 + 𝜔2 𝜏𝐷𝑀

These computations are based on the assumption that the filter is directly connected between
the product and the load, as we would expect in normal functioning conditions. However, the
compliance test of CE requirements for digital devices requires a setup where the LISN is in
used, as is clearly shown in Figure 4.1.1. Hence, the equivalent circuit of the test setup
changes as it follows in Figure 4.2.3:

Figure 4.2.3 Differential mode equivalent circuit with LISN

With this configuration the time constant also change

𝜏𝐷𝑛𝑒𝑤 = 𝐶𝑥 𝑅0 = 2𝜏𝐷𝑀
So the DM Insertion Loss becomes:
2 𝑛𝑒𝑤 2
𝐼𝐿𝑛𝑒𝑤
𝐷𝑀 |𝑑𝐵 = 10 log10 (1 + 𝜔 𝜏𝐷𝑀 )

At a high enough frequency, we can consider it as:

𝑛𝑒𝑤 2
≃ 10 log10 (𝜔2 𝜏𝐷𝑀 ) = 20 log10 (2𝜔𝜏𝐷𝑀 ) = 20 log10 2 + 20 log10 (𝜔𝜏𝐷𝑀 )
= 6𝑑𝐵 + 𝐼𝐿𝐷𝑀 |𝑑𝐵

28
Common Mode (CM) IL:
Considering the Common Mode (CM) insertion loss measurement test setup, where the
phase and neutral wires are shorted together and connected to the test circuit via the green
wire, the equivalent circuit is as follows:

Figure 4.2.4 Common mode test setup

By applying Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL), the
following equivalent circuit can be derived:

Figure 4.2.5 Common mode equivalent circuit

Starting from this configuration, the CM Insertion Losses can be computed the same as for
the DM, hence we need to derive voltages 𝑉̂𝐿𝑊𝑜 and 𝑉̂𝐿𝑊 .
The first one will be the same as before
𝑉̂𝑆
𝑉̂𝐿𝑊𝑜 =
2
While 𝑉̂𝐿𝑊 is given by:
2𝑅0 2𝑅0
𝑉̂𝐿𝑊 = 𝑉̂𝑆 = 𝑉̂
2𝑅0 + 2𝑅0 + 𝑗𝜔2𝐿𝑔 𝐿𝑔 𝑆
4𝑅0 (1 + 𝑗𝜔 2𝑅 )
0

Defined the CM-Time constant

𝐿𝑔
𝜏𝐶𝑀 ≜
2𝑅0
We derive:
1 𝑉̂𝑆
𝑉̂𝐿𝑊 =
2 1 + 𝑗𝜔𝜏𝐶𝑀
Hence, by the same definition:
𝑉̂𝑆
|
̂
|𝑉𝐿𝑊0 | 2|
𝐼𝐿𝐶𝑀 |𝑑𝐵 = 20 log10 ( ) = 20 log10 ( ) = 20 log10 (|1 + 𝑗𝜔𝜏𝐶𝑀 |)
|𝑉̂𝐿𝑊 | 1 𝑉̂𝑆
|2 1 + 𝑗𝜔𝜏 |
𝐶𝑀
29
 2 )
⇒ 𝐼𝐿𝐶𝑀 |𝑑𝐵 = 10 log10 (1 + 𝜔2 𝜏𝐶𝑀

As in the previous case, this expression is based on the assumption that the filter is connected
to both the source and the load. However, in the context of the compliance test for
Conducted Emissions (CE) requirements for the digital product, the setup involves the use
of the LISN, as shown in Figure 4.2.2. Consequently, the equivalent circuit becomes that
shown in Figure 4.2.6.

Figure 4.2.6 Common mode equivalent circuit with LISN

Hence, a new time constant is obtained

𝑛𝑒𝑤
𝐿𝑔
𝜏𝐶𝑀 = = 2𝜏𝐶𝑀
𝑅0
So the CM Insertion Loss becomes:
2 𝑛𝑒𝑤 2
𝐼𝐿𝑛𝑒𝑤
𝐶𝑀 |𝑑𝐵 = 10 log10 (1 + 𝜔 𝜏𝐶𝑀 )

At a high enough frequency, we can consider it

𝑛𝑒𝑤 2
≃ 10 log10 (𝜔2 𝜏𝐶𝑀 ) = 20 log10 (2𝜔𝜏𝐶𝑀 ) = 20 log10 2 + 20 log10 (𝜔𝜏𝐶𝑀 )
= 6𝑑𝐵 + 𝐼𝐿𝐶𝑀 |𝑑𝐵

30
4.3 Calculation of Lg and Cx Values
Based on the voltage measurements:

𝒇𝟏 = 𝟏 𝑴𝑯𝒛 (Differential Mode - DM):

1. 𝑉𝐿1 = 10.536 𝑚𝑉 (phase 17°)
2. 𝑉𝐿2 = 10.682 𝑚𝑉 (phase 197°)

𝒇𝟐 = 𝟏𝟎 𝑴𝑯𝒛 (Common Mode - CM):

1. 𝑉𝐿1 = 13.475 𝑚𝑉 (phase 32°)
2. 𝑉𝐿2 = 13.322 𝑚𝑉 (phase 31°)

We compute the values of 𝑉̂𝐷𝑀 and 𝑉̂𝐶𝑀 for each case, and compare them to the Conducted
Emission Limits (Quasi-Peak) for class B equipment (EN55022:2006)

FCC Class B Limits (Quasi-Peak):

150 kHz - 500 kHz: [66-56] dBµV
500 kHz - 5 MHz: 56 dBµV
5 MHZ - 30 MHZ: 60 dBµV

𝒇𝟏 = 𝟏 𝑴𝑯𝒛:
Limit = 56 dBµV.

𝑉̂𝐿1 − 𝑉̂𝐿2
𝑉̂𝐷𝑀 = = 10612 µ𝑉 = 80.52 𝑑𝐵𝜇𝑉 → 𝑶𝒗𝒆𝒓 𝒕𝒉𝒆 𝒍𝒊𝒎𝒊𝒕
2
𝑉̂𝐿1 + 𝑉̂𝐿2
̂
{ 𝑉𝐶𝑀 =
2
= 73 µ𝑉 = 37.27 𝑑𝐵𝜇𝑉 → 𝑩𝒆𝒍𝒐𝒘 𝒕𝒉𝒆 𝒍𝒊𝒎𝒊𝒕

Hence, the required attenuation is:

80.52 − 56 = 24.52 𝑑𝐵µ𝑉
Starting from this, the value of the capacitance 𝐶𝑥 can be computed:

2
10𝑙𝑜𝑔10 (1 + ω2 τ𝑛𝑒𝑤 2 2
𝐷𝑀 ) = 24.52 dBµV ⇒ 10𝑙𝑜𝑔10 (1 + ω τ𝐷𝑀 ) + 6𝑑𝐵 = 24.52 dBµV

Thus:

24.52−6 √71.121 𝐶𝑥 𝑅0 8.433

1 + ω2 τ2𝐷𝑀 = 10 10 ⇒ 1 + ω2 τ2𝐷𝑀 = 71.121 ⇒ τ𝐷𝑀 = ⇒ =
ω 2 2𝜋 ∙ 106

8.433 ∙ 2
𝐶𝑥 = = 53.69 𝑛𝐹
50 ∙ 2𝜋 ∙ 106

𝒇𝟐 = 𝟏𝟎 𝑴𝑯𝒛:
Limit = 60 dBµV
𝑉̂𝐿1 − 𝑉̂𝐿2
𝑉̂𝐷𝑀 = = 140 𝜇𝑉 = 42.92 𝑑𝐵𝜇𝑉 → 𝑩𝒆𝒍𝒐𝒘 𝒕𝒉𝒆 𝒍𝒊𝒎𝒊𝒕
2
𝑉̂𝐿1 + 𝑉̂𝐿2
̂
{𝑉𝐶𝑀 =
2
= 13399 𝜇𝑉 = 82.54 𝑑𝐵𝜇𝑉 → 𝑨𝒃𝒐𝒗𝒆 𝒕𝒉𝒆 𝒍𝒊𝒎𝒊𝒕

Hence, the required attenuation is:

31
 82.54 − 60 = 22.54 𝑑𝐵𝜇𝑉

Starting from this, the value of the capacitance 𝐿𝑔 can be computed:

10𝑙𝑜𝑔 10 (1 + ω2 τ2𝐶𝑀 ) = 22.54 dBµV → 10𝑙𝑜𝑔10 (1 + ω2 τ2𝐶𝑀 ) + 6𝑑𝐵 = 22.54 dBµV

Thus:
22.54−6 √45.082 𝐿𝑔 6.714
1 + ω2 τ2𝐶𝑀 = 10 10 → 1 + ω2 τ2𝐷𝑀 = 45.0820 → τ𝐶𝑀 = → =
ω 2𝑅0 2𝜋 ∙ 107
6.714 ∙ 2 ∙ 50
𝐿𝑔 = = 10.69 μ𝐻
2𝜋 ∙ 107

Final Values:
C= 53.69 𝑛𝐹 (DM suppression at 1 MHz).
L=10.69 μ𝐻 (CM suppression at 10 MHz).

32