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SRAM - Basics

Jaydeep P. Kulkarni
[email protected]

Slides are adopted from Prof. Kaushik Roy, Prof. Chris Kim , Prof. Saibal
Mukhopadhyay, and Prof. Jan Rabaey’s slides
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Semiconductor Memory Trends

From [Itoh01]
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 Variation in Process Parameters 9

10000
Source: Intel

# dopant atoms
1000

100

10
1000 500 250 130 65 32
Technology Node (nm)
Line Edge Roughness Random Dopant Fluctuation
(LER) (RDF)

• SRAM Transistors – Minimum geometry

• Inter-die and Intra-die variations

Inter and
• LER, RDF induced device mismatch
Intra-die Variations
 Parametric Failures: Read Failure 10

WL

Voltage
VL
VTRIPRD WL
∆
+∆ VR=‘0’
VREAD
VR=VREAD
PL PR
AXL AXR
VL=‘1’ ∆
-∆
NL NR Time ->
∆
-∆ ∆
+∆
VR

Voltage
BL BR
WL

PRF = P(VREAD > VTRIPRD )

VL

Time ->
Read failure => Flipping of Cell Data while Reading
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Mechanisms of Parametric Failures
BL Access Failure Read Failure
∆MIN VR
Voltage

Voltage
WL
BR

WL VL

Time -> Time ->

Write Failure Hold Failure

VL
Voltage

Voltage VDDH
WL

VR VR VL

Time -> Time ->

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SRAM Bitcell Layouts

Tall-cell
Thin-cell

M. Ishida, IEDM 98
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Tall Cell Layout
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Thin Cell Layout

• 2 Poly-pitch, N-well continuous, Shared Contacts

• WL (Horizontal), BL(Vertical), Lower bitline capacitance
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Upsizing Thin-cell size

Increasing cell area by 2X increase device widths by 4X !

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Trends in Memory Cell Area

From [Itoh01]
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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L 2 K Bit line
Storage cell
AK

Row Decoder
A K1 1 Word line

AL2 1

M.2K

Sense amplifiers / Drivers Amplify swing to

rail-to-rail amplitude

A0
Column decoder Selects appropriate
A K2 1 word

Input-Output
(M bits)
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Hierarchical Memory Architecture

Block 0 Block i Block P 2 1

Row
address

Column
address
Block
address

Global data bus

Control Block selector Global
circuitry amplifier/driver

I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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Memory Architecture: Decoders
M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
wo r d s

A K2 1
N

De c o d e r

SN 2 2
Word N 2 2 Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N
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Hierarchical Decoders
Multi-stage implementation improves performance
•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3
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Dynamic Decoders
Precharge devices GND GND VDD

WL 3
VDD
WL3

WL 2
WL2 VDD

WL1
WL 1
V DD
WL0
WL 0

VDD φ A0 A0 A1 A1
A0 A0 A1 A1 φ

2-input NOR decoder 2-input NAND decoder

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Column Decoder
BL 0 BL 1 BL 2 BL 3

S0
A0
S1

S2

A1 S3
2 - i n p u t NOR d e c o d e r

Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
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Tree based column decoder
BL 0 BL 1 BL 2 BL 3

A0

A0

A1

A1

D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
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Sense Amplifiers
make ∆ V as small
C ×∆ V as possible
t = ----------------
p Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output
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Differential Sense Amplifier

V DD

M3 M4
y Out

bit M1 M2 bit

SE M5
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Differential Sensing ― SRAM
V DD V DD
PC

BL BL V DD V DD
EQ
y M3 M4 2y

WL i
x M1 M2 2x x 2x

SE M5 SE

SE
SRAM cell i

V DD
Diff.
x Sense 2x Output
Amp y

SE
Output
(a) SRAM sensing scheme (b) two stage differential amplifier
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Latch-Based Sense Amplifier
EQ
BL BL
VDD

SE

SE

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
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Decoupled Sense Amplifier

Y. Wang, Intel, ISSCC’07

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Bitline Leakage Compensation - II

• Less transistor count

• Easy to implement in within
column pitch
• No complicated timing
• Calibration after every write

M. Khellah, Intel, VLSI’05

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