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Microprocessor Prem

The document covers key concepts related to microprocessors and microcontrollers, including the 8259 Programmable Interrupt Controller's initialization and operational command words, modes of the 80386 processor, and the floating point pipeline of the Pentium processor. It also discusses Hyper-Threading Technology in Pentium 4, the MESI protocol for cache coherence in multiprocessor systems, and provides a numerical example of interfacing a 4KB RAM with the 8085 microprocessor. Diagrams are suggested for better understanding of the concepts presented.

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5 views5 pages

Microprocessor Prem

The document covers key concepts related to microprocessors and microcontrollers, including the 8259 Programmable Interrupt Controller's initialization and operational command words, modes of the 80386 processor, and the floating point pipeline of the Pentium processor. It also discusses Hyper-Threading Technology in Pentium 4, the MESI protocol for cache coherence in multiprocessor systems, and provides a numerical example of interfacing a 4KB RAM with the 8085 microprocessor. Diagrams are suggested for better understanding of the concepts presented.

Uploaded by

py9502693
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Mystic__prem

Microprocessor & Microcontroller Concepts

1. Initialization Command Words (ICWs) and Operational Command Words (OCWs) of 8259 PIC

The 8259 Programmable Interrupt Controller (PIC) manages hardware interrupts and allows the CPU to

prioritize and handle them efficiently.

Initialization Command Words (ICWs):

Used to initialize the 8259.

ICW1: Sets basic control parameters.

- Bit 0: ICW4 needed

- Bit 1: Single (1 PIC) or Cascade

- Bit 3: Edge or Level triggered

- Bit 4: Must be 1 (signals start of initialization)

ICW2: Sets the interrupt vector address for the first interrupt (usually A7-A3 bits of ISR).

ICW3: Used in cascade mode.

- Master: Indicates which IR lines have slaves.

- Slave: Indicates the ID (IR line) it is connected to on the master.

ICW4: Sets additional modes.

- 8086/88 mode or MCS-80/85

- Auto EOI (End Of Interrupt)

- Buffered mode

Operational Command Words (OCWs):

Used for controlling interrupt operations after initialization.

OCW1: Masking/unmasking interrupts (1 = masked).

OCW2: Used for priority control, End of Interrupt (EOI), etc.

OCW3: Controls the reading of IRR/ISR and special mask modes.


Mystic__prem
Microprocessor & Microcontroller Concepts

Diagram: (For exam, draw ICW/OCW flow or 8259 block diagram with CPU interface)

2. Modes of 80386 & Floating Point Pipeline of Pentium Processor

Real Mode:

- Backward compatible with 8086.

- 20-bit addressing (1 MB memory).

- No protection or multitasking.

- Used during booting.

Protected Mode:

- 32-bit addressing (up to 4 GB memory).

- Supports multitasking, memory protection, and virtual memory.

- Allows use of segment descriptors and privilege levels.

Virtual Mode:

- A sub-mode of protected mode.

- Allows running real-mode applications in a protected environment.

- Used in systems like Windows DOS-box.

Floating Point Pipeline of Pentium:

- Pentium uses a dual-pipeline structure (U and V pipes). For floating point:

- Consists of 8 stages:

1. Decode

2. Address generation

3. Operand fetch

4. Execution (Add, Multiply, Divide stages)

5. Write back

- Uses a Floating Point Unit (FPU) that supports pipelined execution of FP instructions.
Mystic__prem
Microprocessor & Microcontroller Concepts

- Instructions like FADD, FMUL, etc., are executed in pipeline stages for speedup.

3. Hyper-Threading Technology (HTT) in Pentium 4

Hyper-Threading (HT):

- Intel's simultaneous multithreading technology.

- Allows a single physical processor core to appear as two logical processors.

How It Works:

- Each logical processor has its own registers, APIC, and control logic.

- Shares execution engine, caches, buses, etc.

- Executes two threads in parallel to improve CPU utilization.

Benefits in Pentium 4:

- Increased throughput (up to 30% improvement).

- Better performance in multi-threaded applications.

- Efficient CPU resource utilization.

Diagram Suggestion: Show one physical core with two logical processors and shared execution units.

4. MESI Protocol (Modified, Exclusive, Shared, Invalid)

MESI Protocol is used in cache coherence for multiprocessor systems.

Each cache line can be in one of the four states:

1. Modified (M):

- Data is changed (dirty), exists only in this cache.

- Must be written back before another CPU reads it.

2. Exclusive (E):

- Data is clean and exists only in this cache.

- Can be modified without informing others.


Mystic__prem
Microprocessor & Microcontroller Concepts

3. Shared (S):

- Data is clean and may exist in multiple caches.

- No CPU has modified it.

4. Invalid (I):

- Cache line is invalid or outdated.

Purpose: Maintain consistency across multiple caches accessing shared memory.

Diagram Suggestion: A state transition diagram showing MESI states and CPU/memory actions.

5. Numerical on Interfacing (Module 3)

This depends on your syllabus or specific interfacing topic (e.g., 8255 PPI, ADC interfacing, DAC interfacing,

memory interfacing, etc.)

Generic memory interfacing example:

Problem:

Interface a 4KB RAM to 8085 starting at address A000H. Find the address range and control signals.

Solution:

- 4 KB = 2^12, so 12 address lines (A0-A11) connect to RAM.

- Starting address: A000H = 1010 0000 0000 0000

- Ending address: AFFFH = 1010 1111 1111 1111

- Address Range: A000H - AFFFH

- Address decoding uses A12-A15.

- Use decoder to generate chip select when A15-A12 = 1010.


Mystic__prem
Microprocessor & Microcontroller Concepts

Diagram: Show 8085 with Address Bus (A0-A15), Data Bus, control lines, decoder logic, and RAM block.

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