LPE1 Lab Report
LPE1 Lab Report
Question: 2
endmodule
module full_adder(
input A, B, Cin,
output Sum, Cout
);
endmodule
Test Bench:
module four_bit_subtractor_tb;
reg [3:0] A;
reg [3:0] B;
reg Bin;
wire [3:0] Diff;
wire Bout;
full_subtractor uut (
.A(A),
.B(B),
.Bin(Bin),
.Diff(Diff),
.Bout(Bout)
);
initial begin
$finish;
end
endmodule
Output/Simulation Result (Screenshot/SnapShot):
Error