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DEPARTMENT OF AVIONICS ENGINEERING

SUBJECT : FPGA LAB

SUBJECT CODE : 408448

LAB NO : 02
TILTE Introduction to Vivado

SUBMITTED TO Engr. Lal Said Khan

SEMESTER
SECTION
B

Marks
Obtained
Group Member Group Member
1 2
NAME MAHNOOR
REGISTRATION # 220701002
LAB REPORT 2
PERFORMANCE
TOTAL MARKS

DEADLINE: 10-03-2025
DATE OF SUBMISSION: 10-03-2025

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Experiment # 02 Page 1 of 14
FPGA BASED EMBEDDED SYSTEM DESIGN
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Objectives:

To Familiarize yourself with the basic components of an FPGA board.

Introduction

Vivado Design Suite is a comprehensive development environment for FPGA

(FieldProgrammable Gate Array) design and implementation, developed by Xilinx. It is
widely used for creating, analyzing, and implementing FPGA designs on Xilinx FPGA
devices. Vivado supports a range of Xilinx FPGA families, including Artix, Kintex,
Virtex, and Zynq.Vivado supports RTL design entry using languages such as Verilog,
VHDL, or a combination of both.Vivado HLS allows designers to enter and explore
designs using C, C++, or SystemC. It automatically generates RTL code from high-level
descriptions. Vivado IP Integrator is a graphical tool that allows designers to create
complex FPGA designs using pre-designed IP (Intellectual Property) blocks. This speeds
up the design process and promotes reuse.The synthesis step in Vivado transforms the
RTL code into a gate-level netlist. It optimizes the design for the target FPGA device,
balancing performance, area, and power.Vivado's implementation phase involves place
and route, where the tool places the logic elements and routes the interconnections on the
FPGA. It also performs timing analysis to ensure that the design meets the specified
performance requirements.Once the implementation is complete, the bitstream file
generated by Vivado is used to configure the FPGA. This bitstream contains information
about how the logic elements are configured within the FPGA. Vivado provides various
debugging and analysis tools, such as the Vivado Logic Analyzer, to help designers
understand and debug their designs. It allows you to visualize signals in your design and
analyze their behavior.For FPGAs with embedded processors (e.g., Zynq devices),
Vivado supports software development using Xilinx SDK (Software Development Kit).
It enables designers to create and debug software that runs on the embedded ARM
processors within the FPGA.Vivado supports partial reconfiguration, allowing specific
regions of the FPGA to be dynamically reprogrammed without affecting the entire
device. This is useful for implementing flexible and adaptive systems.Vivado HLS
(High-Level Synthesis) allows designers to describe hardware functionality using high-
level programming languages such as C or C++. It automatically generates RTL code,
accelerating the design process.

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Simulation of XOR Gate in Vivado

Creat a project as shown below

Click on next

Assig name and define location of the project

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Tick on RTL Project and tick do not specify spicify source at this time

For simulation puropose you can choose any random settengs. For hardware
implementatation you need to select according to the hardware

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Click on finish

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Add sources

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Add or create design sources:

Define module for XOR gate

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Double click on this

Now define the code for XOR gate function

Run the simulation

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This the the Tcl console

Now go to the force clock to set the clock for each input:

For input A:

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For input B:

This is what window looks like

Now run for 200ns :

Timings diagram

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Tasks
1. Explain the timings digram as shown above.
As the truth table for XOR gate is:
a b c =a xor b
0 0 0
0 1 1
1 0 1
1 1 0

In XOR gate when the inputs are odd or if 1 input is 1 and other is zero then output
occurs.so form timing diagram we see that when the input A is 0 and input B is 1 so
output C is 1.it is shown in the timing diagram. This verifies that the XOR gate was
correctly implemented and simulated.

2. Implement AND, OR ,NOT Gates.

AND GATE:
Code:

Timing diagram:

Analysis:
a b c =a AND b
0 0 0
0 1 0
1 0 0
1 1 1

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Here, the AND gate was designed and simulated. The expected behavior of the AND
gate is that the output remains low (0) unless both inputs are high (1). The timing
diagram correctly represented this behavior, with the output turning high only when
both inputs were simultaneously set to 1. This confirmed the proper working of the
AND gate logic.
OR GATE:
Code:

Timing diagram

Analysis:
a b c =a OR b
0 0 0
0 1 1
1 0 1
1 1 1
Here we have focused on the OR gate implementation, where the output was expected
to be high (1) if at least one of the inputs was high. The waveform analysis supported
this, showing transitions at the correct times, ensuring that the OR gate functioned as
intended. The consistent results with the theoretical truth table indicated that the
simulation was successful.

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NOT gate:
Code:

Timing diagram:

Analysis:
a c= NOT a
0 1
1 0
Here we have focused on the NOT gate, which is the simplest of all logic gates as it
inverts the input signal. The simulation results demonstrated that when the input was
low (0), the output was high (1), and when the input was high (1), the output was low
(0). The timing diagram displayed a perfect inversion of the input signal, confirming
the correct functionality of the NOT gate.

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Conclusion:
From this lab, we have learned:
• How to design and implement basic logic gates (AND, OR, XOR, NOT) using
Verilog in Vivado Design Suite.
• The importance of testbenches and simulation in verifying the functionality
of digital circuits.
• How to analyze timing diagrams to validate gate operations against expected
truth tables.
• The role of FPGA-based digital design in developing and testing
combinational logic circuits efficiently.

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